Solid state drive setting method, computer program product, device and medium

Abstract

The present application provides a solid-state hard disk setting method, computer program product, device and medium, including: performing data read and write test on the communication channel between the main control end and the memory chip of the solid-state hard disk; obtaining the serial port log generated during the data read and write test; parsing the serial port log to obtain test configuration data and corresponding bit flip data; generating a signal quality eye diagram corresponding to the communication channel according to the test configuration data and the bit flip data; determining the target margin offset and target reference voltage corresponding to the communication channel according to the signal quality eye diagram; configuring the communication channel in the solid-state hard disk according to the target margin offset and the target reference voltage. The bit flipping of data on the signal line between the main control end and the memory chip end of the solid-state hard disk is minimized, so as to achieve the purpose of improving the signal quality of the solid-state hard disk under high frequency conditions.

Description

Technical Field

[0001] The present application relates to the field of storage technology, and in particular to a solid state hard disk setting method, a computing program product, a device and a medium. Background Art

[0002] With the update of the Peripheral Component Interconnect Express (PCIE) to version 5.0, the bandwidth has been significantly improved, and the performance of solid-state drive products has been continuously improved in recent years. Not AND Flash (NAND Flash) is a common solid-state drive, and its particle interface rate is getting higher and higher.

[0003] However, high-speed signals will be lost during the transmission process, so how to ensure the integrity and transmission rate of signals under high-speed transmission becomes the primary problem that solid-state drive manufacturers have to face.

[0004] Therefore, there is an urgent need for a method for improving the signal transmission quality in a solid state drive to solve the above technical problems. Summary of the invention

[0005] Based on this, it is necessary to provide a solid state drive setting method, computer program product, device and medium to address the above technical issues.

[0006] In a first aspect, the present application provides a solid state drive configuration method, comprising:

[0007] Perform data read and write tests on the communication channel between the main control end and the memory chip of the solid-state drive;

[0008] Get the serial port log generated during the data reading and writing test process;

[0009] Parse the serial port log to obtain the test configuration data and the corresponding bit flip data;

[0010] Generate a signal quality eye diagram corresponding to the communication channel according to the test configuration data and the bit flip data;

[0011] Determine the target margin offset and target reference voltage corresponding to the communication channel according to the signal quality eye diagram;

[0012] A communication channel within the solid state drive is configured according to a target margin offset and a target reference voltage.

[0013] In some embodiments, performing a data read and write test on a communication channel between a host control terminal and a memory chip of a solid state drive includes:

[0014] Traverse the reference voltage data table and the margin offset data table to generate a test combination value;

[0015] Setting the communication channel according to the test combination value;

[0016] One or more logic areas in the communication channel are traversed, and test data is written into the logic areas to obtain bit flip data corresponding to each logic area, so as to complete the data read and write test of the communication channel.

[0017] In some embodiments, writing test data into the logic regions to obtain bit flip data corresponding to each logic region includes:

[0018] Using the test data as write data, and writing the write data into a test storage page in the logic area;

[0019] Read the test storage page to obtain the read data corresponding to the write data;

[0020] The write data is compared with the read data, and the flip times of each bit in the test data are obtained to generate bit flip data.

[0021] In some embodiments, comparing the write data with the read data, obtaining the flip count of each bit in the test data to generate bit flip data, includes:

[0022] Create a counter that matches the number of bits;

[0023] Traverse the bytes in the read data and write data and compare the bytes bit by bit;

[0024] In response to detecting that the values ​​at the target bit positions are not equal, adding one to the value in the target counter matching the target bit positions;

[0025] After the traversal is completed, the bit flip data is generated according to the flip times of each bit recorded in the counter.

[0026] In some embodiments, after generating the bit-flipped data, the method further comprises:

[0027] Obtaining test configuration data of the current configuration of the communication channel, the test configuration data including a test combination value and a number of a logic area;

[0028] The preset serial port printing function is called to print the test configuration data and the bit flip data matching the logic area into the serial port log according to the first preset format.

[0029] In some embodiments, a method for generating a number of a logical region includes:

[0030] Obtain the target chip select signal number that matches the memory chip to which the logic area belongs and the target communication channel number of the logic area;

[0031] The number of the logic area is generated according to the target communication channel number, the target chip selection signal number and the logic number of the logic area.

[0032] In some embodiments, parsing the serial port log to obtain the test configuration data and the corresponding bit flip data, the method further includes:

[0033] Analyze serial port log line by line;

[0034] Determine whether the current line of the serial port log contains a preset keyword group, the preset keyword group includes a reference voltage keyword, a margin offset keyword, and a flip data keyword;

[0035] In response to detecting whether the current line contains a preset keyword group, determining that the current line is a valid line of the serial port log;

[0036] Read the valid lines of the serial port log to determine the test configuration data and bit flip data.

[0037] In some embodiments, generating a signal quality eye diagram corresponding to a communication channel according to the test configuration data and the bit flip data includes:

[0038] Traversing the first quality eye diagram corresponding to the logical area in the communication channel to generate a signal quality eye diagram corresponding to the communication channel;

[0039] First quality eye diagram generation includes:

[0040] Establish an eye diagram table, wherein the table header is the number of the logic area included in the test configuration data, and the horizontal and vertical axes are the margin offset data value and the reference voltage data value of the test combination value included in the test configuration data;

[0041] The bit flip data is filled into the corresponding cells of the eye diagram table to generate a first quality eye diagram corresponding to the logic area.

[0042] In some embodiments, determining a target margin offset and a target reference voltage corresponding to a communication channel according to a signal quality eye diagram includes:

[0043] Traversing zero-value regions in a plurality of first quality eye diagrams included in a signal quality eye diagram corresponding to a communication channel;

[0044] Get the overlapping area of ​​multiple zero-value areas;

[0045] A target margin offset and a target reference voltage are determined according to a first margin offset data value interval and a first reference voltage data value interval of the overlapped area.

[0046] In some embodiments, determining a target margin offset and a target reference voltage corresponding to a communication channel according to a signal quality eye diagram includes:

[0047] Traversing zero-value regions in a plurality of first quality eye diagrams included in a signal quality eye diagram corresponding to a communication channel;

[0048] Get the first center point cell of multiple zero-value areas;

[0049] Determine a second margin offset data value interval according to a plurality of margin offset data values ​​corresponding to a plurality of first center point cells;

[0050] Determine a second reference voltage data value interval according to a plurality of reference voltage data values ​​corresponding to a plurality of first center point cells;

[0051] A target margin offset and a target reference voltage are determined according to the second margin offset data value interval and the second reference voltage data value interval.

[0052] In some embodiments, determining a target margin offset and a target reference voltage corresponding to a communication channel according to a signal quality eye diagram includes:

[0053] Traversing zero-value regions in a plurality of first quality eye diagrams included in a signal quality eye diagram corresponding to a communication channel;

[0054] Get the second center point cell of the overlapping area of ​​multiple zero-value areas;

[0055] A target margin offset and a target reference voltage are determined according to the corresponding margin offset data value and reference voltage data value of the second center point cell.

[0056] In some embodiments, setting the communication channel according to the test combination value includes:

[0057] Calling a first setting function to set a phase difference control register in a solid state hard disk master control end according to a margin offset data value included in a test combination value;

[0058] The read operation offset of the storage page of one or more logic areas in the communication channel is set according to the set phase difference control register.

[0059] In some embodiments, setting the communication channel according to the test combination value includes:

[0060] Calling a second setting function to set a reference voltage control register in the solid state drive master terminal according to the reference voltage data value included in the test combination value;

[0061] The internal reference voltage of the communication channel is set according to the reference voltage control register after being set.

[0062] In some embodiments, the setting of the margin offset data value in the margin offset data table includes:

[0063] The programmable offset is determined according to a preset formula, where the preset formula is: ,Y represents the programmable offset, X represents the preset value, and F represents the clock period;

[0064] The programmable offset is evenly divided into multiple slices to generate margin offsets.

[0065] In some embodiments, setting the reference voltage data value in the reference voltage data table includes:

[0066] Get the minimum voltage value and the maximum voltage value of the reference voltage range that matches the solid state drive;

[0067] On the basis of the minimum voltage value of the reference voltage range, the minimum voltage value is accumulated according to the least significant bit to obtain a reference voltage value until the maximum voltage value is reached.

[0068] In some embodiments, a method for generating test data includes:

[0069] Get the random number seed according to the preset rules;

[0070] Call the random number generation function and random number seed to generate random numbers;

[0071] Generate test data based on random numbers.

[0072] In some embodiments, obtaining a random number seed according to a preset rule includes:

[0073] Call the time acquisition function to obtain the current system timestamp and generate a random number seed based on the current system timestamp;

[0074] Generate a random number seed based on the random number generated by the hardware random number generator;

[0075] Generates a random number seed based on the current system timestamp and the random number generated by the hardware random number generator.

[0076] In a second aspect, the present application provides a solid state drive configuration system, the system comprising:

[0077] A test module is used to perform data reading and writing tests on the communication channel between the main control terminal and the memory chip of the solid state drive;

[0078] The processing module is used to obtain the serial port log generated during the data reading and writing test process;

[0079] The processing module is also used to parse the serial port log to obtain the test configuration data and the corresponding bit flip data;

[0080] The processing module is further used to generate a signal quality eye diagram corresponding to the communication channel according to the test configuration data and the bit flip data;

[0081] The processing module is further used to determine a target margin offset and a target reference voltage corresponding to the communication channel according to the signal quality eye diagram;

[0082] A setup module is used to configure a communication channel within the solid state drive according to a target margin offset and a target reference voltage.

[0083] In a third aspect, the present application provides a computer program product, which implements the steps of the following method when the computer program is executed by a processor:

[0084] Perform data read and write tests on the communication channel between the main control end and the memory chip of the solid-state drive;

[0085] Get the serial port log generated during the data reading and writing test process;

[0086] Parse the serial port log to obtain the test configuration data and the corresponding bit flip data;

[0087] Generate a signal quality eye diagram corresponding to the communication channel according to the test configuration data and the bit flip data;

[0088] Determine the target margin offset and target reference voltage corresponding to the communication channel according to the signal quality eye diagram;

[0089] A communication channel within the solid state drive is configured according to a target margin offset and a target reference voltage.

[0090] In a fourth aspect, the present application provides an electronic device, the electronic device comprising:

[0091] one or more processors;

[0092] and a memory associated with one or more processors, the memory being used to store program instructions, which, when read and executed by the one or more processors, perform the following operations:

[0093] Perform data read and write tests on the communication channel between the main control end and the memory chip of the solid-state drive;

[0094] Get the serial port log generated during the data reading and writing test process;

[0095] Parse the serial port log to obtain the test configuration data and the corresponding bit flip data;

[0096] Generate a signal quality eye diagram corresponding to the communication channel according to the test configuration data and the bit flip data;

[0097] Determine the target margin offset and target reference voltage corresponding to the communication channel according to the signal quality eye diagram;

[0098] A communication channel within the solid state drive is configured according to a target margin offset and a target reference voltage.

[0099] In a fifth aspect, the present application further provides a computer-readable storage medium, on which a computer program is stored, and the computer program enables a computer to perform the following operations:

[0100] Perform data read and write tests on the communication channel between the main control end and the memory chip of the solid-state drive;

[0101] Get the serial port log generated during the data reading and writing test;

[0102] Parse the serial port log to obtain the test configuration data and the corresponding bit flip data;

[0103] Generate a signal quality eye diagram corresponding to the communication channel according to the test configuration data and the bit flip data;

[0104] Determine the target margin offset and target reference voltage corresponding to the communication channel according to the signal quality eye diagram;

[0105] A communication channel within the solid state drive is configured according to a target margin offset and a target reference voltage.

[0106] The beneficial effects achieved by this application are:

[0107] The present application provides a method, including performing a data read and write test on the communication channel between the main control end and the memory chip of the solid-state hard disk; obtaining the serial port log generated during the data read and write test; parsing the serial port log to obtain the test configuration data and the corresponding bit flip data; generating a signal quality eye diagram corresponding to the communication channel according to the test configuration data and the bit flip data; determining the target margin offset and the target reference voltage corresponding to the communication channel according to the signal quality eye diagram; configuring the communication channel in the solid-state hard disk according to the target margin offset and the target reference voltage. The present application tests the communication channel between the solid-state hard disk control end and the memory chip end from these two dimensions by adjusting the phase difference (i.e., margin offset) and reference voltage between DQS and DQ, obtains the specific information of bit flipping when the test data is written and read, and draws the signal quality eye diagram by parsing the generated log. Further selecting a reasonable DQS and DQ phase difference and reference voltage, the bit flipping of the data on the signal line of the solid-state hard disk main control end and the memory chip end is minimized, so as to achieve the purpose of improving the signal quality of the solid-state hard disk under high frequency conditions. BRIEF DESCRIPTION OF THE DRAWINGS

[0108] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments are briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative work, among which:

[0109] Figure 1 It is a schematic diagram of a solid state hard disk setting method provided in an embodiment of the present application;

[0110] Figure 2 It is a schematic diagram of a data reading and writing test method provided in an embodiment of the present application;

[0111] Figure 3 This is a schematic diagram of a data transmission waveform provided by an embodiment of the present application;

[0112] Figure 4 It is a schematic diagram of a signal quality eye diagram provided in an embodiment of the present application;

[0113] Figure 5 This is a system architecture diagram of a solid state drive configuration provided by an embodiment of the present application;

[0114] Figure 6 It is a structural diagram of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0115] In order to make the purpose, technical solutions and advantages of this application clearer, the technical solutions in the embodiments of this application will be clearly and completely described below in conjunction with the drawings in the embodiments of this application. Obviously, the described embodiments are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0116] It should be understood that in the description of the present application, unless the context clearly requires otherwise, words such as "include", "comprises", and the like in the entire specification and claims should be interpreted as inclusive rather than exclusive or exhaustive; that is, the meaning of "including but not limited to".

[0117] It should also be understood that the terms "first", "second", etc. are only used for descriptive purposes and cannot be understood as indicating or implying relative importance. In addition, in the description of this application, unless otherwise specified, "plurality" means two or more.

[0118] It should be noted that the terms "S1", "S2", etc. are only used for the purpose of describing the steps, and do not specifically refer to the order or sequence, nor are they used to limit the present application. They are only for the convenience of describing the method of the present application, and cannot be understood as indicating the order of the steps. In addition, the technical solutions between the various embodiments can be combined with each other, but they must be based on the ability of ordinary technicians in this field to implement them. When the combination of technical solutions is contradictory or cannot be implemented, it should be considered that such a combination of technical solutions does not exist and is not within the scope of protection required by the present application.

[0119] Embodiment 1

[0120] The embodiment of the present application provides a solid state hard disk setting method, which improves the quality of data signals in the solid state hard disk by setting a communication channel between the solid state hard disk host control terminal and the memory chip, such as Figure 1 As shown, including the following:

[0121] S100, performing a data reading and writing test on the communication channel between the main control end and the memory chip of the solid state drive.

[0122] It is understandable that there are usually multiple communication channels between the SSD host and the memory chip; the method disclosed in this application is set for one or more of the communication channels as required. In this embodiment, one communication channel is used as an example for description.

[0123] In the above step S100, Figure 2 As shown in the figure, the data reading and writing test specifically includes:

[0124] S110 , traverse the preset reference voltage data table and margin offset data table to generate a test combination value.

[0125] In a specific implementation scenario, the generation of the test combination value can be specifically performed by traversing the reference voltage value data value from 4 to 127 through a for loop, and then traversing the margin offset data value from 0 to 255 through a for loop, thereby exhausting the combination of the reference voltage data value and the margin offset data value. Currently, it can also be implemented through other looping methods, and this application does not limit the specific looping method.

[0126] Among them, it can be understood that the above-mentioned reference voltage data table and margin offset data table are data tables pre-defined and stored in a certain medium. The reference voltage data values ​​and margin offset data values ​​in these two data tables are read to test the communication channel in the data reading and writing test, so as to obtain the data signal quality transmitted by the communication channel under different reference voltage and margin offset setting scenarios.

[0127] S120. Setting a communication channel according to the test combination value.

[0128] Specifically, the internal reference voltage of the communication channel is set according to the test combination value, and the read operation offset of the communication channel is set according to the test combination value. The first setting function is called to set the phase difference control register in the solid-state hard disk master terminal according to the margin offset data value contained in the test combination value; the read operation offset of the storage page of one or more logical areas in the communication channel is set according to the phase difference control register after the setting. In this application, the logical area is a logical partition on the solid-state silver hard disk memory chip identified by LUN (Logical Unit Number). It can be understood that the delay of each channel is statically specified using a register. Even if this control specifies 256 slices in a data cycle, the delay tap size of the PDL will limit the actual granularity of the implementation to within about 20ps. Specifically, the second setting function is called to set the reference voltage control register in the solid-state hard disk master terminal according to the reference voltage data value contained in the test combination value; the internal reference voltage of the communication channel is set according to the reference voltage control register after the setting. The first setting function and the second setting function are mainly used to set the bit at the specified position to 1 without changing the state of other bits; the present application does not limit the specific setting function. The present application sets the value of a specific control register by calling the corresponding setting function, and further sets the communication channel. The operation is simple and easy to adjust during the test, which further ensures the efficiency of the test.

[0129] like Figure 3 shows the ideal data transmission waveform. Figure 3 In the output direction shown, the DQ (Data signal) pin is delayed by the PDL (Primary Delay Line) skew to center-align the data. In the input direction, the received edge-aligned DQS (Data strobe signal) is delayed by the PDL to complete the capture of the data. This ideal waveform may require high-speed training to tune out the appropriate non-ideal DQ-DQS skew from the NAND FLASH part.

[0130] The setting of the margin offset data value in the margin offset data table includes: determining the programmable offset according to a preset formula, wherein the preset formula is: ,Y represents the programmable offset, X represents the preset value, and F represents the clock cycle; the programmable offset is evenly divided into multiple slices to generate a margin offset. Specifically, the above X is set to 128 by default; the above clock cycle usually refers to the FIO clock cycle, and the phase difference offset of DQS and DQ is achieved by evenly dividing the clock cycle into 256 offsets.

[0131] The setting of the reference voltage data value in the above reference voltage data table includes obtaining the minimum voltage value and the maximum voltage value of the reference voltage range that matches the solid state drive; based on the minimum voltage value of the reference voltage range, the minimum voltage value is accumulated according to the least significant bit to obtain the reference voltage value until the maximum voltage value is reached. It is worth noting that there is a specific corresponding relationship between the index of the register and the reference voltage data value. When controlling the corresponding reference voltage control register according to the reference voltage data value, it is only necessary to set the reference voltage control register to the corresponding index.

[0132] In a specific implementation scenario, as shown in Table 1, if the reference voltage range corresponding to the solid-state drive is refrange 1 (9.21%~53.81% Vddq), DDR mode, that is, the minimum voltage value is 9.21% Vddq (1.2V), the corresponding register value is 4; then on this basis, the least significant bit is accumulated, and the reference voltage data value corresponding to the register value of 5 is 9.58% Vddq; the reference voltage data value corresponding to the register value of 6 is 9.95% Vddq, and so on, the maximum reference voltage data value is 53.81% Vddq, and its corresponding register value is 127. The figure also shows the setting content of refrange 0, which will not be expanded in this application.

[0133] Table 1

[0134]

[0135] S130, traversing one or more logic areas in the communication channel, writing test data into the logic areas to obtain bit flip data corresponding to each logic area, so as to complete the data read and write test on the communication channel.

[0136] It should be noted that the above method is to obtain the bit flip data of each logical area under each setting of the communication channel after the communication channel is set according to all the combination values ​​generated by traversal.

[0137] In a specific implementation scenario, writing test data into a logic area to obtain bit flip data corresponding to each logic area includes: using the test data as write data and writing the write data into a test storage page in the logic area; reading the test storage page to obtain read data corresponding to the write data; comparing the write data with the read data, obtaining the flip count of each bit in the test data to generate bit flip data. It can be understood that a logic area contains multiple storage blocks, each block contains multiple storage pages; the test storage page is a randomly selected storage page for writing test data.

[0138] The above test data can be a random number or a specified test data input by the user. This application does not limit the specified test data input by the user. When the above test data is a random number, first, obtain the random number seed according to the preset rules; specifically, it can be obtained by calling the time acquisition function, obtaining the current system timestamp and generating a random number seed according to the current system timestamp; it can also be based on the random number generated by the hardware random number generator to generate a random number seed; it can also be based on the current system timestamp and the random number generated by the hardware random number generator. Combined generation of random number seeds; the above random number seed generation method is simple and speeds up the efficiency of data reading and writing tests to a certain extent. Secondly, call the random number generation function and the random number seed to generate random numbers; finally, generate test data based on these random numbers. By generating according to random numbers, the randomness of the test data is ensured, and the robustness of subsequent data reading and writing tests is improved.

[0139] Among them, comparing the write data with the read data, obtaining the number of flips on each bit in the test data to generate bit flip data, includes: establishing a counter that matches the number of bits; traversing the bytes in the read data and the write data, and comparing the bytes bit by bit; in response to detecting that the values ​​on the target bit are not equal, adding one to the value in the target counter that matches the target bit; after the traversal is completed, generating bit flip data according to the number of flips of each bit recorded in the counter. Using the counter, the number of bit flips on each bit is timely counted, the operation is convenient and accurate, and the accuracy of the bit flip data finally generated is improved.

[0140] Take the specific implementation scenario of NAND FLASH with 8 data input and output signal lines DQ[7:0] for explanation: In one cycle of DQ[7:0], data signal DQ0 to data signal DQ7 transmit a total of eight bits of data. For example, the write data is 11010011, and the data carried by write DQ0 to write DQ7 are: write DQ0 can carry "1", write DQ1 can carry "1", write DQ2 can carry "0", write DQ3 can carry "1", write DQ4 can carry "0", write DQ5 can carry "0", write DQ6 can carry "1", and write DQ7 can carry "1". Compare each byte of the write data and the read data in turn. A byte has 8 bits. If the data of the bit i is not equal, the number of bit flips in the counter corresponding to DQi is increased by one.

[0141] Specifically, after generating the bit flip data, the method also includes: obtaining the test configuration data of the current configuration of the communication channel, the test configuration data includes the test combination value and the number of the logic area, wherein the test combination value includes the margin offset data value and the reference voltage data value; calling the preset serial port printing function, and printing the test combination value, the number of the logic area, and the bit flip data matching the logic area to the serial port log according to the first preset format. That is, the corresponding bit flip data needs to be printed out in the end, and the above-mentioned first preset format is as follows: ch4-ce3-lun0, Vref=72, r_dqs=100, dq-pin=0,0,0,0,0,0,0,3, of course, the order can also be reversed, and the specific order is not limited in this application. Among them, ch4-ce3-lun0 is the number of the logic area, and its specific generation method includes: obtaining the target chip select signal number matching the memory chip to which the logic area belongs and the target communication channel number of the logic area; generating the number of the logic area according to the target communication channel number, the target chip select signal number and the logic number of the logic area. CE (Chip Enable) is the enable pin of NAND memory chip, and there are several CEs under each channel; LUN is a component inside the chip; the number of chip select signals CE is related to the capacity of the solid-state drive. Generally, the number of CEs on a 2T solid-state drive is 2, and the number of CEs on a 4T, 8T or 16T solid-state drive is 4. The above ch4-ce3-lun0 means that when the offset reference voltage Vref 72 is on channel 4, CE3, LUN0, and the phase difference between DQ and DQS is 100, the total number of bit flips corresponding to each signal line on DQ0 to DQ7, where DQ7 has 3 bit flips.

[0142] S200, obtaining a serial port log generated during a data reading and writing test process.

[0143] S300, parsing the serial port log to obtain test configuration data and corresponding bit flip data.

[0144] In a specific implementation scenario, after obtaining the serial port log in the data read and write test process, analyze the serial port log line by line; determine whether the current line of the serial port log contains a preset keyword group, the preset keyword group includes a reference voltage keyword, a margin offset keyword, and a flip data keyword; in response to detecting whether the current line contains a preset keyword group, determine that the current line is a valid line of the serial port log; read the valid line of the serial port log to determine the test configuration data and the bit flip data. Among them, the reference voltage keyword is preferably set to "Vref=", the margin offset keyword is preferably set to "r_dqs=", and the flip data keyword is preferably set to "dq-pin=". Of course, it can also be adjusted according to the implementation situation, and this application does not limit this.

[0145] Of course, in order to facilitate later calls, after determining the valid lines of the serial port log, the valid lines of the serial port log can be saved in the dictionary data structure according to the second preset format, and then the test configuration data and the bit flip data are obtained by reading the valid lines of the serial port log in the dictionary data structure. The second preset format is such as: chA-ceB-lunC {vrefX: {dqsY: dq-data0-7}, {dqsY+4: dq-data0-7}...}; wherein, "chA-ceB-lunC" represents the number of the logic area in the test configuration data; "vrefX" represents the reference voltage data value; "dqsY" represents the margin offset data value; "dq-data0-7" represents the bit flip data; the above disclosed second preset format is only for illustration, and can be adaptively modified according to actual conditions in specific scenarios, and this application does not limit this. The preset dictionary data structure is preferably set to EyeInfor (eye information). EyeInfor, as a dictionary format data structure, is usually used to store information related to the "Eye Diagram".

[0146] This application locates valid lines in the serial port log by setting keywords, and further extracts the valid lines into a preset dictionary data structure to facilitate the subsequent generation of signal quality eye diagrams. This is specifically implemented in programming languages ​​such as Python scripts, and this application does not limit this.

[0147] S400: Generate a signal quality eye diagram corresponding to the communication channel according to the test configuration data and the bit flip data.

[0148] Specifically, it includes: traversing the first quality eye diagram corresponding to the logical area in the communication channel to generate a signal quality eye diagram corresponding to the communication channel; the first quality eye diagram generation includes: establishing an eye diagram table, wherein the table header is the number of the logical area contained in the test configuration data, and the horizontal and vertical axes are the margin offset data value and the reference voltage data value of the test combination value contained in the test configuration data, that is, if the horizontal axis is set to the margin offset data value, the vertical axis is set to the reference voltage data value, and if the vertical axis is set to the margin offset data value, the horizontal axis is set to the reference voltage data value; filling the bit flip data into the cell corresponding to the eye diagram table to generate the first quality eye diagram corresponding to the logical area. Figure 4 A first quality eye diagram for a specific scenario is shown.

[0149] S500 : Determine a target margin offset and a target reference voltage corresponding to a communication channel according to a signal quality eye diagram.

[0150] In a specific implementation scenario, the above determination of the target margin offset and target reference voltage corresponding to the communication channel specifically includes: traversing the zero-value areas in multiple first quality eye diagrams included in the signal quality eye diagram corresponding to the communication channel; obtaining the overlapping area of ​​multiple zero-value areas; and determining the target margin offset and target reference voltage according to the first margin offset data value interval and the first reference voltage data value interval of the overlapping area. That is, multiple reference voltage data values ​​and margin offset data values ​​when no bit flip occurs in all tested logic areas in the same communication channel are determined as the first margin offset data value interval and the first reference voltage data value interval, and the target margin offset and the target reference voltage can be arbitrarily selected from the first margin offset data value interval and the first reference voltage data value interval to achieve transmission optimization of the data signal.

[0151] In a specific implementation scenario, the above determination of the target margin offset and target reference voltage corresponding to the communication channel specifically includes: traversing the zero-value areas in the multiple first quality eye diagrams contained in the signal quality eye diagram corresponding to the communication channel; obtaining the first center point cells of the multiple zero-value areas; determining the second margin offset data value interval according to the multiple margin offset data values ​​corresponding to the multiple first center point cells; determining the second reference voltage data value interval according to the multiple reference voltage data values ​​corresponding to the multiple first center point cells; determining the target margin offset and target reference voltage according to the second margin offset data value interval and the second reference voltage data value interval. That is, by summarizing the center points of the first quality eye diagram corresponding to each tested logic area in the same communication channel (that is, the best reference voltage data value and the best margin offset data value in the logic area), the second margin offset data value interval and the second reference voltage data value interval are determined, and numerical values ​​are selected therefrom to determine the target margin offset and target reference voltage; further optimizing the set reference voltage and margin offset.

[0152] In a specific implementation scenario, the above determination of the target margin offset and target reference voltage corresponding to the communication channel specifically includes: traversing the zero-value areas in the multiple first quality eye diagrams contained in the signal quality eye diagram corresponding to the communication channel; obtaining the second center point cell of the overlapping area of ​​the multiple zero-value areas; and determining the target margin offset and target reference voltage according to the margin offset data value and reference voltage data value corresponding to the second center point cell. By first determining the overlapping area of ​​the first quality eye diagram corresponding to each tested logic area in the same communication channel, and then using the margin offset data value and reference voltage data value corresponding to the center point of the overlapping area as the target margin offset and target reference voltage, the optimal setting of the communication channel is determined in all logic areas.

[0153] It is understandable that, in a specific scenario of configuring a solid-state drive, any one of the above three methods of obtaining a target reference voltage and a target margin offset value may be selected to optimize the signal inside the solid-state drive.

[0154] S600: Configure a communication channel in the solid state drive according to a target margin offset and a target reference voltage.

[0155] This application tests the communication channel between the SSD control end and the memory chip end from these two dimensions by adjusting the phase difference (i.e., margin offset) and reference voltage between DQS and DQ, obtains specific information about bit flipping when writing and reading test data, and draws a signal quality eye diagram by analyzing the generated logs. Further selecting a reasonable phase difference between DQS and DQ and reference voltage can minimize the bit flipping of data on the signal line between the SSD main control end and the memory chip end, thereby achieving the purpose of improving the signal quality of the SSD under high frequency conditions.

[0156] Embodiment 2

[0157] Corresponding to the above-mentioned embodiment 1, as Figure 5 The system architecture diagram shown in the figure, the present application also provides a solid state drive setting system, including:

[0158] The test module 510 is used to perform a data read and write test on the communication channel between the main control terminal and the memory chip of the solid state drive;

[0159] Processing module 520, used to obtain the serial port log generated during the data reading and writing test process;

[0160] The processing module 520 is further used to parse the serial port log to obtain the test configuration data and the corresponding bit flip data;

[0161] The processing module 520 is further used to generate a signal quality eye diagram corresponding to the communication channel according to the test configuration data and the bit flip data;

[0162] The processing module 520 is further used to determine a target margin offset and a target reference voltage corresponding to the communication channel according to the signal quality eye diagram;

[0163] The setting module 530 is used to configure the communication channel in the solid state drive according to the target margin offset and the target reference voltage.

[0164] In some embodiments, the test module 510 is also used to: traverse a preset reference voltage data table and a margin offset data table to generate a test combination value; set a communication channel according to the test combination value; traverse one or more logic areas in the communication channel, write test data into the logic area to obtain the bit flip data corresponding to each logic area, so as to complete the data read and write test of the communication channel.

[0165] In some embodiments, the test module 510 is also used to: use the test data as write data, and write the write data into a test storage page within the logic area; read the test storage page to obtain read data corresponding to the write data; compare the write data with the read data, and obtain the number of flips on each bit in the test data to generate bit flip data.

[0166] In some embodiments, the test module 510 is also used to: establish a counter that matches the number of bits; traverse the bytes in the read data and the write data, and compare the bytes bit by bit; in response to detecting that the values ​​on the target bits are not equal, add one to the value in the target counter that matches the target bit; after the traversal is completed, generate bit flip data according to the number of flips of each bit recorded in the counter.

[0167] In some embodiments, the test module 510 is further used to: obtain the test configuration data of the current configuration of the communication channel, the test configuration data including the test combination value and the number of the logic area; call the preset serial port printing function to print the test configuration data and the bit flip data matching the logic area to the serial port log according to the first preset format. The number generation process of the logic area is: obtain the target chip select signal number matching the memory chip to which the logic area belongs and the target communication channel number of the logic area; generate the number of the logic area according to the target communication channel number, the target chip select signal number and the logic number of the logic area.

[0168] In some embodiments, the processing module 520 is also used to: analyze the serial port log line by line; determine whether the current line of the serial port log contains a preset keyword group, the preset keyword group includes a reference voltage keyword, a margin offset keyword and a flip data keyword; in response to detecting whether the current line contains the preset keyword group, determine that the current line is a valid line of the serial port log; read the valid line of the serial port log to determine the test configuration data and the bit flip data.

[0169] In some embodiments, the processing module 520 is also used to: traverse the first quality eye diagram corresponding to the logical area in the communication channel to generate a signal quality eye diagram corresponding to the communication channel; the first quality eye diagram generation includes: establishing an eye diagram table, wherein the table header is the number of the logical area included in the test configuration data, and the horizontal and vertical coordinates are the margin offset data value and the reference voltage data value of the test combination value included in the test configuration data; and fill the bit flip data into the cell corresponding to the eye diagram table to generate the first quality eye diagram corresponding to the logical area.

[0170] In some embodiments, the processing module 520 is also used to: traverse the zero-value areas in multiple first quality eye diagrams included in the signal quality eye diagram corresponding to the communication channel; obtain the overlapping area of ​​multiple zero-value areas; and determine the target margin offset and the target reference voltage based on the first margin offset data value interval and the first reference voltage data value interval of the overlapping area.

[0171] In some embodiments, the processing module 520 is also used to: traverse the zero value areas in multiple first quality eye diagrams included in the signal quality eye diagram corresponding to the communication channel; obtain the first center point cells of the multiple zero value areas; determine the second margin offset data value interval according to the multiple margin offset data values ​​corresponding to the multiple first center point cells; determine the second reference voltage data value interval according to the multiple reference voltage data values ​​corresponding to the multiple first center point cells; determine the target margin offset and the target reference voltage according to the second margin offset data value interval and the second reference voltage data value interval.

[0172] In some embodiments, the processing module 520 is also used to: traverse the zero-value areas in multiple first quality eye diagrams included in the signal quality eye diagram corresponding to the communication channel; obtain the second center point cell of the overlapping area of ​​the multiple zero-value areas; and determine the target margin offset and the target reference voltage according to the corresponding margin offset data value and reference voltage data value of the second center point cell.

[0173] In some embodiments, the test module 510 is further used to: call the first setting function to set the phase difference control register in the solid state drive master terminal according to the margin offset data value included in the test combination value; and set the read operation offset of the storage page of one or more logical areas in the communication channel according to the set phase difference control register. The setting of the margin offset data value in the margin offset data table includes: determining the programmable offset according to a preset formula, wherein the preset formula is: ,Y represents the programmable offset, X represents the preset value, and F represents the clock cycle; the programmable offset is evenly divided into multiple slices to generate the margin offset.

[0174] In some embodiments, the test module 510 is further used to: call the second setting function to set the reference voltage control register in the solid state drive master terminal according to the reference voltage data value included in the test combination value; and set the internal reference voltage of the communication channel according to the reference voltage control register after the setting. The setting of the reference voltage data value in the reference voltage data table includes: obtaining the minimum voltage value and the maximum voltage value of the reference voltage range that matches the solid state drive; based on the minimum voltage value of the reference voltage range, accumulating the minimum voltage value according to the least significant bit to obtain the reference voltage value until the maximum voltage value is reached.

[0175] In some embodiments, the test module 510 is further used to: obtain a random number seed according to a preset rule; call a random number generation function and a random number seed to generate a random number; and generate test data according to the random number.

[0176] In some embodiments, the test module 510 is also used to: call the time acquisition function to obtain the current system timestamp and generate a random number seed based on the current system timestamp; generate a random number seed based on the random number generated by the hardware random number generator; and generate a random number seed based on the current system timestamp and the random number generated by the hardware random number generator.

[0177] Embodiment 3

[0178] Corresponding to the above-mentioned Embodiment 1 and Embodiment 2, the embodiment of the present application further provides a computer program, which implements the steps of the following method when the computer program is executed by a processor:

[0179] Perform data read and write tests on the communication channel between the main control end and the memory chip of the solid-state drive;

[0180] Get the serial port log generated during the data reading and writing test;

[0181] Parse the serial port log to obtain the test configuration data and the corresponding bit flip data;

[0182] Generate a signal quality eye diagram corresponding to the communication channel according to the test configuration data and the bit flip data;

[0183] Determine the target margin offset and target reference voltage corresponding to the communication channel according to the signal quality eye diagram;

[0184] A communication channel within the solid state drive is configured according to a target margin offset and a target reference voltage.

[0185] In some implementation scenarios, when the computer program is executed by a processor, the steps of the following method are also implemented:

[0186] Traverse the preset reference voltage data table and margin offset data table to generate a test combination value;

[0187] Setting the communication channel according to the test combination value;

[0188] One or more logic areas in the communication channel are traversed, and test data is written into the logic areas to obtain bit flip data corresponding to each logic area, so as to complete the data read and write test of the communication channel.

[0189] In some implementation scenarios, when the computer program is executed by a processor, the steps of the following method are also implemented:

[0190] Using the test data as write data, and writing the write data into a test storage page in the logic area;

[0191] Read the test storage page to obtain the read data corresponding to the write data;

[0192] The write data is compared with the read data, and the flip times of each bit in the test data are obtained to generate bit flip data.

[0193] In some implementation scenarios, when the computer program is executed by a processor, the steps of the following method are also implemented:

[0194] Create a counter that matches the number of bits;

[0195] Traverse the bytes in the read data and write data and compare the bytes bit by bit;

[0196] In response to detecting that the values ​​at the target bit positions are not equal, adding one to the value in the target counter matching the target bit positions;

[0197] After the traversal is completed, the bit flip data is generated according to the flip times of each bit recorded in the counter.

[0198] In some implementation scenarios, when the computer program is executed by a processor, the steps of the following method are also implemented:

[0199] Obtaining test configuration data of the current configuration of the communication channel, the test configuration data including a test combination value and a number of a logic area;

[0200] The preset serial port printing function is called to print the test configuration data and the bit flip data matching the logic area into the serial port log according to the first preset format.

[0201] In some implementation scenarios, when the computer program is executed by a processor, the steps of the following method are also implemented:

[0202] Obtain the target chip select signal number that matches the memory chip to which the logic area belongs and the target communication channel number of the logic area;

[0203] The number of the logic area is generated according to the target communication channel number, the target chip selection signal number and the logic number of the logic area.

[0204] In some implementation scenarios, when the computer program is executed by a processor, the steps of the following method are also implemented:

[0205] Analyze serial port log line by line;

[0206] Determine whether the current line of the serial port log contains a preset keyword group, the preset keyword group includes a reference voltage keyword, a margin offset keyword, and a flip data keyword;

[0207] In response to detecting whether the current line contains a preset keyword group, determining that the current line is a valid line of the serial port log;

[0208] Read the valid lines of the serial port log to determine the test configuration data and bit flip data.

[0209] In some implementation scenarios, when the computer program is executed by a processor, the steps of the following method are also implemented:

[0210] Traversing the first quality eye diagram corresponding to the logical area in the communication channel to generate a signal quality eye diagram corresponding to the communication channel;

[0211] First quality eye diagram generation includes:

[0212] Establish an eye diagram table, wherein the table header is the number of the logic area included in the test configuration data, and the horizontal and vertical axes are the margin offset data value and the reference voltage data value of the test combination value included in the test configuration data;

[0213] The bit flip data is filled into the corresponding cells of the eye diagram table to generate a first quality eye diagram corresponding to the logic area.

[0214] In some implementation scenarios, when the computer program is executed by a processor, the steps of the following method are also implemented:

[0215] Traversing zero-value regions in a plurality of first quality eye diagrams included in a signal quality eye diagram corresponding to a communication channel;

[0216] Get the overlapping area of ​​multiple zero-value areas;

[0217] A target margin offset and a target reference voltage are determined according to a first margin offset data value interval and a first reference voltage data value interval of the overlapped area.

[0218] In some implementation scenarios, when the computer program is executed by a processor, the steps of the following method are also implemented:

[0219] Traversing zero-value regions in a plurality of first quality eye diagrams included in a signal quality eye diagram corresponding to a communication channel;

[0220] Get the first center point cell of multiple zero-value areas;

[0221] Determine a second margin offset data value interval according to a plurality of margin offset data values ​​corresponding to a plurality of first center point cells;

[0222] Determine a second reference voltage data value interval according to a plurality of reference voltage data values ​​corresponding to a plurality of first center point cells;

[0223] A target margin offset and a target reference voltage are determined according to the second margin offset data value interval and the second reference voltage data value interval.

[0224] In some implementation scenarios, when the computer program is executed by a processor, the steps of the following method are also implemented:

[0225] Traversing zero-value regions in a plurality of first quality eye diagrams included in a signal quality eye diagram corresponding to a communication channel;

[0226] Get the second center point cell of the overlapping area of ​​multiple zero-value areas;

[0227] A target margin offset and a target reference voltage are determined according to the corresponding margin offset data value and reference voltage data value of the second center point cell.

[0228] In some implementation scenarios, when the computer program is executed by a processor, the steps of the following method are also implemented:

[0229] Calling a first setting function to set a phase difference control register in a solid state hard disk master control end according to a margin offset data value included in a test combination value;

[0230] The read operation offset of the storage page of one or more logic areas in the communication channel is set according to the set phase difference control register.

[0231] In some implementation scenarios, when the computer program is executed by a processor, the steps of the following method are also implemented:

[0232] Calling a second setting function to set a reference voltage control register in the solid state drive master terminal according to the reference voltage data value included in the test combination value;

[0233] The internal reference voltage of the communication channel is set according to the reference voltage control register after being set.

[0234] In some implementation scenarios, when the computer program is executed by a processor, the steps of the following method are also implemented:

[0235] Get the minimum voltage value and the maximum voltage value of the reference voltage range that matches the solid state drive;

[0236] On the basis of the minimum voltage value of the reference voltage range, the minimum voltage value is accumulated according to the least significant bit to obtain a reference voltage value until the maximum voltage value is reached.

[0237] In some implementation scenarios, when the computer program is executed by a processor, the steps of the following method are also implemented:

[0238] The programmable offset is determined according to a preset formula, where the preset formula is: ,Y represents the programmable offset, X represents the preset value, and F represents the clock period;

[0239] The programmable offset is evenly divided into multiple slices to generate margin offsets.

[0240] In some implementation scenarios, when the computer program is executed by a processor, the steps of the following method are also implemented:

[0241] Get the random number seed according to the preset rules;

[0242] Call the random number generation function and random number seed to generate random numbers;

[0243] Generate test data based on random numbers.

[0244] In some implementation scenarios, when the computer program is executed by a processor, the steps of the following method are also implemented:

[0245] Call the time acquisition function to obtain the current system timestamp and generate a random number seed based on the current system timestamp;

[0246] Generate a random number seed based on the random number generated by the hardware random number generator;

[0247] Generates a random number seed based on the current system timestamp and the random number generated by the hardware random number generator.

[0248] Embodiment 4

[0249] Corresponding to all the above embodiments, an embodiment of the present application provides an electronic device, including: one or more processors; and a memory associated with the one or more processors, the memory is used to store program instructions, and when the program instructions are read and executed by the one or more processors, the following operations are performed:

[0250] Perform data read and write tests on the communication channel between the main control end and the memory chip of the solid-state drive;

[0251] Get the serial port log generated during the data reading and writing test;

[0252] Parse the serial port log to obtain the test configuration data and the corresponding bit flip data;

[0253] Generate a signal quality eye diagram corresponding to the communication channel according to the test configuration data and the bit flip data;

[0254] Determine the target margin offset and target reference voltage corresponding to the communication channel according to the signal quality eye diagram;

[0255] A communication channel within the solid state drive is configured according to a target margin offset and a target reference voltage.

[0256] in, Figure 6 The architecture of the electronic device is shown exemplarily, and may include a processor 610, a video display adapter 611, a disk drive 612, an input / output interface 613, a network interface 614, and a memory 620. The processor 610, the video display adapter 611, the disk drive 612, the input / output interface 613, the network interface 614, and the memory 620 may be communicatively connected via a bus 630.

[0257] Among them, the processor 610 can be implemented by a general-purpose CPU (Central Processing Unit), a microprocessor, an application specific integrated circuit (Application Specific Integrated Circuit, ASIC), or one or more circuits, etc., to execute relevant programs to implement the technical solution provided in this application.

[0258] The memory 620 can be implemented in the form of ROM (Read Only Memory, programmable memory), RAM (Random Access Memory, random access memory), static storage device, dynamic storage device, etc. The memory 620 can store an operating system 621 for controlling the execution of the electronic device 600, and a basic input and output system (BIOS) 622 for controlling the low-level operations of the electronic device 600. In addition, a web browser 623, a data storage management system 624, and an icon font processing system 625, etc. can also be stored. The above-mentioned icon font processing system 625 can be an application program that specifically implements the operations of the aforementioned steps in the embodiment of the present application. In short, when the technical solution provided in the present application is implemented by software or firmware, the relevant program code is stored in the memory 620 and is called and executed by the processor 610.

[0259] The input / output interface 613 is used to connect the input / output module to realize information input and output. The input / output module can be configured as a component in the device (not shown in the figure), or it can be externally connected to the device to provide corresponding functions. The input device may include a keyboard, a mouse, a touch screen, a microphone, various sensors, etc., and the output device may include a display, a speaker, a vibrator, an indicator light, etc.

[0260] The network interface 614 is used to connect to a communication module (not shown) to achieve communication interaction between the device and other devices. The communication module can achieve communication through a wired method (such as USB, network cable, etc.) or a wireless method (such as mobile network, WIFI, Bluetooth, etc.).

[0261] The bus 630 comprises a pathway for transmitting information between the various components of the device (eg, the processor 610 , the video display adapter 611 , the disk drive 612 , the input / output interface 613 , the network interface 614 , and the memory 620 ).

[0262] In addition, the electronic device 600 can also obtain information on specific collection conditions from the virtual resource object collection condition information database for use in condition judgment, etc.

[0263] It should be noted that, although the above device only shows a processor 610, a video display adapter 611, a disk drive 612, an input / output interface 613, a network interface 614, a memory 620, a bus 630, etc., in the specific implementation process, the device may also include other components necessary for normal execution. In addition, it can be understood by those skilled in the art that the above device may also only include components necessary for implementing the solution of the present application, and does not necessarily include all the components shown in the figure.

[0264] It can be seen from the description of the above implementation methods that those skilled in the art can clearly understand that the present application can be implemented by means of software plus a necessary general hardware platform. Based on this understanding, the technical solution of the present application can essentially or in other words, the part that contributes to the prior art can be embodied in the form of a software product, which can be stored in a storage medium such as ROM / RAM, a disk, an optical disk, etc., including several instructions for enabling a computer device (which can be a personal computer, a cloud service end, or a network device, etc.) to execute the methods of various embodiments of the present application or certain parts of the embodiments.

[0265] Embodiment 5

[0266] Corresponding to all the above embodiments, the embodiments of the present application further provide a computer-readable storage medium storing a computer program, which enables a computer to perform the following operations:

[0267] Perform data read and write tests on the communication channel between the main control end and the memory chip of the solid-state drive;

[0268] Get the serial port log generated during the data reading and writing test process;

[0269] Parse the serial port log to obtain the test configuration data and the corresponding bit flip data;

[0270] Generate a signal quality eye diagram corresponding to the communication channel according to the test configuration data and the bit flip data;

[0271] Determine the target margin offset and target reference voltage corresponding to the communication channel according to the signal quality eye diagram;

[0272] A communication channel within the solid state drive is configured according to a target margin offset and a target reference voltage.

[0273] Each embodiment in this specification is described in a progressive manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the system or system embodiment, since it is basically similar to the method embodiment, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiment. The system and system embodiments described above are merely schematic, in which the units described as separate components may or may not be physically separated, and the components displayed as units may or may not be physical units, that is, they may be located in one place, or they may be distributed on multiple network units. Some or all of the modules can be selected according to actual needs to achieve the purpose of the scheme of this embodiment. Ordinary technicians in this field can understand and implement it without paying creative labor.

[0274] The above are only preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent substitutions, improvements, etc. made within the spirit and principles of the present application should be included in the protection scope of the present application.

Claims

1. A method for setting a solid state hard disk, characterized in that: The method comprises: Performing data read and write tests on the communication channel between the main control terminal and the memory chip of the solid-state drive, including writing test data into a test storage page in the logic area; Get the serial port log generated during the data reading and writing test; Parsing the serial port log to obtain test configuration data and corresponding bit flip data, wherein the bit flip data is generated according to the flip count of each bit in the test data written in the test storage page; Generate a signal quality eye diagram corresponding to the communication channel according to the test configuration data and the bit flip data; Determining a target margin offset and a target reference voltage corresponding to the communication channel according to the signal quality eye diagram; The communication channel within the solid state drive is configured according to a target margin offset and the target reference voltage.

2. The method according to claim 1, characterized in that The step of writing the test data into the test storage page in the logic area includes: Traverse the preset reference voltage data table and margin offset data table to generate a test combination value; Setting the communication channel according to the test combination value; One or more logic areas in the communication channel are traversed, and test data is written into the test storage pages of the logic areas to obtain bit flip data corresponding to each of the logic areas, so as to complete the data read and write test of the communication channel.

3. The method according to claim 2, characterized in that The generation of the bit flip data includes: Using the test data as write data, and writing the write data into a test storage page in the logic area; Reading the test storage page to obtain read data corresponding to the write data; The write data is compared with the read data, and the flipping times of each bit in the test data are obtained to generate the bit flipping data.

4. The method according to claim 3, characterized in that The comparing the write data with the read data and obtaining the flipping times of each bit in the test data to generate the bit flipping data includes: Create a counter that matches the number of bits; Traversing the bytes in the read data and the write data, and comparing the bytes bit by bit; In response to detecting that the values ​​on the target bit positions are not equal, adding one to the value in the target counter matching the target bit positions; After the traversal is completed, the bit flip data is generated according to the flip times of each bit recorded in the counter.

5. The method according to claim 4, characterized in that After generating the bit flip data, the method further includes: Acquire test configuration data of the current configuration of the communication channel, the test configuration data including a test combination value and a number of a logic area; A preset serial port printing function is called to print the test configuration data and the bit flip data matching the logic area into a serial port log according to a first preset format.

6. The method according to claim 5, characterized in that The method for generating the number of the logic area includes: Obtaining a target chip select signal number matching a memory chip to which the logic area belongs and a target communication channel number of the logic area; The number of the logic area is generated according to the target communication channel number, the target chip select signal number and the logic number of the logic area.

7. The method according to claim 1, characterized in that The method of parsing the serial port log to obtain test configuration data and corresponding bit flip data includes: Analyze the serial port log line by line; Determine whether the current line of the serial port log contains a preset keyword group, wherein the preset keyword group includes a reference voltage keyword, a margin offset keyword, and a flip data keyword; In response to detecting whether the current line contains a preset keyword group, determining that the current line is a valid line of the serial port log; The serial port log valid line is read to determine the test configuration data and the bit flip data.

8. The method according to claim 7, characterized in that The step of generating a signal quality eye diagram corresponding to a communication channel according to the test configuration data and the bit flip data comprises: Traversing a first quality eye diagram corresponding to a logical area in a communication channel to generate a signal quality eye diagram corresponding to the communication channel; The first quality eye diagram generation comprises: Establishing an eye diagram table, wherein the table header is the number of the logic area included in the test configuration data, and the horizontal and vertical axes are the margin offset data value and the reference voltage data value of the test combination value included in the test configuration data; The bit flip data is filled into the cells corresponding to the eye diagram table to generate a first quality eye diagram corresponding to the logic area.

9. The method according to claim 8, characterized in that The step of determining a target margin offset and a target reference voltage corresponding to the communication channel according to the signal quality eye diagram comprises: Traversing zero-value regions in a plurality of first quality eye diagrams included in a signal quality eye diagram corresponding to the communication channel; Obtaining overlapping areas of a plurality of the zero-value areas; A target margin offset and a target reference voltage are determined according to a first margin offset data value interval and a first reference voltage data value interval of the overlapped area.

10. The method according to claim 8, characterized in that The step of determining a target margin offset and a target reference voltage corresponding to the communication channel according to the signal quality eye diagram comprises: Traversing zero-value regions in a plurality of first quality eye diagrams included in a signal quality eye diagram corresponding to the communication channel; Obtaining first center point cells of a plurality of zero-value areas; Determine a second margin offset data value interval according to a plurality of margin offset data values ​​corresponding to a plurality of the first center point cells; Determine a second reference voltage data value interval according to a plurality of reference voltage data values ​​corresponding to a plurality of the first center point cells; A target margin offset and a target reference voltage are determined according to the second margin offset data value interval and the second reference voltage data value interval.

11. The method according to claim 8, characterized in that The step of determining a target margin offset and a target reference voltage corresponding to the communication channel according to the signal quality eye diagram comprises: Traversing zero-value regions in a plurality of first quality eye diagrams included in a signal quality eye diagram corresponding to the communication channel; Obtain a second center point cell of an overlapping area of ​​a plurality of the zero-value areas; A target margin offset and a target reference voltage are determined according to the margin offset data value and the reference voltage data value corresponding to the second center point cell.

12. The method according to claim 2, characterized in that: The step of setting the communication channel according to the test combination value comprises: Calling a first setting function to set a phase difference control register in a solid state hard disk master control end according to a margin offset data value included in the test combination value; The read operation offset of the storage page of one or more logical areas in the communication channel is set according to the set phase difference control register.

13. The method according to claim 2, characterized in that The step of setting the communication channel according to the test combination value comprises: Calling a second setting function to set a reference voltage control register in the solid state hard disk master control end according to the reference voltage data value included in the test combination value; The internal reference voltage of the communication channel is set according to the reference voltage control register after being set.

14. The method according to claim 12, characterized in that The setting of the margin offset data value in the margin offset data table includes: Determine the programmable offset according to a preset formula, wherein the preset formula is: Y=X / 256*F, where Y represents the programmable offset, X represents the preset value, and F represents the clock cycle; The programmable offset is evenly divided into a plurality of slices to generate margin offsets.

15. The method according to claim 13, characterized in that The setting of the reference voltage data value in the reference voltage data table includes: Get the minimum voltage value and the maximum voltage value of the reference voltage range that matches the solid state drive; On the basis of the minimum voltage value in the reference voltage range, the minimum voltage value is accumulated according to the least significant bit to obtain a reference voltage value until a maximum voltage value is reached.

16. The method according to claim 2, characterized in that The method for generating test data comprises: Get the random number seed according to the preset rules; Calling a random number generation function and the random number seed to generate a random number; Generate test data according to the random number.

17. The method according to claim 16, characterized in that The step of obtaining a random number seed according to a preset rule includes: Calling a time acquisition function to obtain a current system timestamp and generate a random number seed according to the current system timestamp; Generate a random number seed based on the random number generated by the hardware random number generator; A random number seed is generated according to the current system timestamp and the random number generated by the hardware random number generator.

18. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 17 are implemented.

19. An electronic device, characterized in that: The electronic device comprises: one or more processors; And a memory associated with the one or more processors, the memory is used to store program instructions, and when the program instructions are read and executed by the one or more processors, the method of any one of claims 1-17 is executed.

20. A computer-readable storage medium, characterized in that: The computer program stores a computer program, wherein the computer program enables a computer to execute the method according to any one of claims 1 to 17.

Images