Chip assembly packaging method

Abstract

The invention relates to a packaging method of a chip assembly. The packaging method of the chip assembly comprises the following steps: cutting a first wafer to form a first chip; bonding the front surface of the first chip with the front surface of a second wafer to form a first semi-finished product; cutting the first semi-finished product, so that the second wafer is cut to form a second chip, and the first chip and the second chip which are bonded with each other form a chip assembly; arranging the chip assembly on a carrier; arranging a first packaging layer on the carrier, wherein the first packaging layer wraps the chip assembly; the first chip and the second chip are stacked and bonded to form the chip assembly, the chip assembly is arranged on the carrier, then the first packaging layer wraps the chip assembly, on the basis that the thickness of the first packaging layer is not affected, more chips are packaged, the density of the packaging structure is improved, and the miniaturization function of the packaging structure is achieved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a packaging method for a chip component. Background Art

[0002] In recent years, terminal consumer electronic products have all been designed to be light, thin, short and small, which has led to the development of chip packaging in the direction of thinness and high density. The packaging structure of multi-chip modules (MCM) has been widely used in electronic devices. The packaging structure of a multi-chip module mainly includes more than two chips to improve the electrical properties and performance of the packaging structure of the multi-chip module. However, in the current packaging structure of a multi-chip module, multiple chips are laid flat in the packaging structure of the multi-chip module in the form of a single-layer chip, and the packaging structure of the multi-chip module has less space for miniaturization. Summary of the invention

[0003] The purpose of the present application is to provide a chip assembly packaging method, which can solve the technical problem in the prior art that multiple chips are laid flat in the form of single-layer chips in the packaging structure of a multi-chip module, and the packaging structure of the multi-chip module has less space for miniaturization.

[0004] In order to solve the above problems, the present application provides a chip component packaging method, which includes: cutting a first wafer to form a first chip; bonding the front side of the first chip to the front side of a second wafer to form a first semi-finished product; cutting the first semi-finished product so that the second wafer is cut to form a second chip, so that the first chip and the second chip bonded to each other form a chip component; arranging the chip component on a carrier, and the carrier has a first direction; arranging a first packaging layer on the carrier, and the first packaging layer covers the chip component; arranging a first substrate on a side of the first packaging layer away from the carrier; patterning the first substrate and the first packaging layer to form a first conductive hole, and the first conductive hole penetrates the first substrate and the first packaging layer along the first direction; preparing a first redistribution layer in the first conductive hole and on a side of the first substrate away from the first packaging layer; preparing solder balls on a side of the first redistribution layer away from the first substrate, and the solder balls are electrically connected to the first redistribution layer.

[0005] In some embodiments, the steps of cutting a first wafer to form a first chip include: setting a first protective film on the front side of the first wafer; thinning the back side of the first wafer; removing the first protective film; setting a second protective film on the back side of the first wafer; and cutting the first wafer to form a first chip.

[0006] In some embodiments, the step of bonding the front side of a first chip to the front side of a second wafer to form a first semi-finished product includes: setting a third protective film on the front side of the second wafer; thinning the back side of the second wafer; removing the third protective film; and bonding the front side of the first chip to the front side of the second wafer to form a first semi-finished product.

[0007] In some embodiments, the first wafer includes a first main body portion and a first conductive portion arranged on one side of the first main body portion, and the second wafer includes a second main body portion and a second conductive portion arranged on one side of the second main body portion; the step of bonding the front side of the first chip to the front side of a second wafer to form a first semi-finished product includes: bonding the first conductive portion of the first chip to the second conductive portion of the second wafer to form a first semi-finished product.

[0008] In some embodiments, the front side of the first chip is bonded to the front side of the second wafer by at least one of thermocompression welding, ultrasonic welding, laser welding, conductive adhesive welding and micro welding to form a first semi-finished product.

[0009] In some embodiments, the step of cutting the first semi-finished product so that the second wafer is cut to form a second chip, and the first chip and the second chip bonded to each other form a chip assembly includes: setting a fourth protective film on the back side of the second wafer; cutting the second wafer of the first semi-finished product so that the second wafer is cut to form a second chip, and the first chip and the second chip bonded to each other form a chip assembly.

[0010] In some embodiments, the step of placing the chip assembly on a carrier includes: placing an adhesive layer on the carrier and attaching the chip assembly to the adhesive layer; before the step of preparing solder balls on the side of the first redistribution layer away from the first substrate, the step also includes: removing the carrier and the adhesive layer.

[0011] In some embodiments, the step of patterning the first substrate and the first packaging layer to form the first conductive via includes: patterning the first substrate and the first packaging layer by a laser process to form the first conductive via.

[0012] In some embodiments, before the step of preparing solder balls on the side of the first redistribution layer away from the first substrate, the step also includes: preparing at least one sub-packaging structure on the side of the first substrate away from the first packaging layer, the sub-packaging structure covering the first redistribution layer; the step of preparing at least one sub-packaging structure on the side of the first substrate away from the first packaging layer includes: preparing a sub-packaging layer on the side of the first substrate away from the first packaging layer, the sub-packaging layer covering the first redistribution layer; preparing a sub-substrate on the side of the sub-packaging layer away from the first substrate; patterning the sub-substrate and the sub-packaging layer to form sub-conductive holes, the sub-conductive holes passing through the sub-substrate and the sub-packaging layer along a first direction; preparing a sub-redistribution layer in the sub-conductive holes and on the side of the sub-substrate away from the sub-packaging layer, the sub-redistribution layer closest to the first substrate is electrically connected to the first redistribution layer; preparing solder balls on the side of the sub-redistribution layer away from the sub-substrate, the solder balls are electrically connected to the sub-redistribution layer farthest from the first substrate.

[0013] In some embodiments, the step of preparing at least one sub-package structure on the side of the first substrate away from the first packaging layer also includes: arranging the chip component on the side of the first substrate away from the first packaging layer and / or on the side of the sub-substrate away from the sub-package layer, and the sub-package layer covers the chip component.

[0014] The present application uses a first chip to bond with a second wafer, and then cuts the first semi-finished product so that the second wafer is cut to form a second chip, so that the first chip and the second chip bonded to each other form a chip assembly, and then the chip assembly is set on a carrier, and a first packaging layer is set on the carrier, and the first packaging layer covers the chip assembly. By stacking and bonding the first chip and the second chip to form a chip assembly and then setting it on the carrier, and then using the first packaging layer to cover the chip assembly, more chips can be packaged without affecting the thickness of the first packaging layer, thereby improving the density of the packaging structure and realizing the function of miniaturization of the packaging structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0015] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the drawings required for use in the description of the embodiments will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For those skilled in the art, other drawings can be obtained based on these drawings without creative work.

[0016] Figure 1 is a flow chart of a chip assembly packaging method according to an embodiment of the present application;

[0017] Figure 2a-2f is a schematic structural diagram of cutting a first wafer to form a first chip in an embodiment of the present application;

[0018] Figure 3a-3dIt is a structural schematic diagram of bonding a front side of a first chip to a front side of a second wafer to form a first semi-finished product in an embodiment of the present application;

[0019] Figure 4a-4c is a schematic structural diagram of cutting the first semi-finished product in an embodiment of the present application;

[0020] Figure 5 is a schematic structural diagram of an embodiment of the present application in which a chip component is disposed on a carrier;

[0021] Figure 6 is a structural schematic diagram of an embodiment of the present application in which a first packaging layer is arranged on a carrier;

[0022] Figure 7 is a schematic structural diagram of an embodiment of the present application in which a first substrate is disposed on a first packaging layer;

[0023] Figure 8 It is a structural schematic diagram of the embodiment of the present application in which the first substrate and the first packaging layer are patterned to form a first conductive hole;

[0024] Fig. 9 It is a structural schematic diagram of preparing a first redistribution layer in the first conductive hole and on the side of the first substrate away from the first packaging layer in an embodiment of the present application;

[0025] Fig.10 is a schematic diagram of the structure of the embodiment of the present application in which the carrier and the adhesive layer are removed;

[0026] Fig.11 is a schematic diagram of a structure in which solder balls are prepared on a side of the first redistribution layer away from the first substrate in an embodiment of the present application;

[0027] Figure 12a-12e is a structural schematic diagram of an embodiment of the present application in which a layer of sub-encapsulation structure is prepared on a side of the first substrate away from the first encapsulation layer;

[0028] Fig.13 This embodiment of the application is Fig.12e Schematic diagram of the structure without the carrier and glue layer on the foundation;

[0029] Fig.14 This embodiment of the application is Fig.13 A schematic diagram of a structure in which solder balls are prepared on a side of a sub-rewiring layer away from a sub-substrate;

[0030] Fig.15 is a structural schematic diagram of a three-layer sub-encapsulation structure prepared on a side of the first substrate away from the first encapsulation layer in an embodiment of the present application;

[0031] Fig.16 This embodiment of the application is Fig.15 Schematic diagram of the structure without the carrier and glue layer on the foundation;

[0032] Fig.17 This embodiment of the application is Fig.16 A schematic diagram of a structure for preparing solder balls on a side of a sub-rewiring layer away from a sub-substrate.

[0033] Description of reference numerals:

[0034] 1. First wafer; 2. First protective film; 3. Second protective film; 4. First chip; 5. Second wafer; 6. Third protective film; 7. First semi-finished product; 8. Fourth protective film; 9. Chip assembly; 10. Second chip; 11. First packaging layer; 12. Carrier; 13. Glue layer; 14. First substrate; 15. First conductive via; 16. First redistribution layer; 17. Solder ball; 18. Sub-packaging structure; 110. First main body; 120. First conductive part; 510. Second main body; 520. Second conductive part; 1810. Sub-packaging layer; 1820. Sub-substrate; 1830. Sub-conductive via; 1840. Sub-redistribution layer. DETAILED DESCRIPTION

[0035] The preferred embodiments of the present invention are described in detail below in conjunction with the drawings in the specification, so as to fully introduce the technical content of the present invention to those skilled in the art, to illustrate that the present invention can be implemented, to make the technical content disclosed in the present invention clearer, and to make it easier for those skilled in the art to understand how to implement the present invention. However, the present invention can be embodied through many different forms of embodiments, and the protection scope of the present invention is not limited to the embodiments mentioned in the text, and the description of the embodiments below is not intended to limit the scope of the present invention.

[0036] The directional terms mentioned in the present invention, such as "up", "down", "front", "back", "left", "right", "inside", "outside", "side", etc., are only directions in the drawings. The directional terms used in this article are used to explain and illustrate the present invention, rather than to limit the scope of protection of the present invention.

[0037] In the drawings, components with the same structure are represented by the same numerical numerals, and components with similar structures or functions are represented by similar numerical numerals. In addition, for ease of understanding and description, the size and thickness of each component shown in the drawings are arbitrarily shown, and the present invention does not limit the size and thickness of each component.

[0038] See also Figure 1 , Figure 11 is a flow chart of a chip assembly packaging method of an embodiment of the present application. The chip assembly packaging method includes: step 101, cutting a first wafer 1 to form a first chip 4; step 102, bonding the front side of the first chip 4 to the front side of a second wafer 5 to form a first semi-finished product 7; step 103, cutting the first semi-finished product 7 so that the second wafer 5 is cut to form a second chip 10, so that the first chip 4 and the second chip 10 bonded to each other form a chip assembly 9; step 104, placing the chip assembly 9 on a carrier 12, the carrier 12 having a first direction M; step 105, placing the chip assembly 9 on the carrier 12 A first packaging layer 11 is arranged on the chip assembly 9; step 106, a first substrate is arranged on a side of the first packaging layer away from the carrier; step 107, the first substrate and the first packaging layer are patterned to form a first conductive hole, the first conductive hole penetrates the first substrate and the first packaging layer along a first direction; step 108, a first redistribution layer is prepared in the first conductive hole and on a side of the first substrate away from the first packaging layer; step 109, a solder ball is prepared on a side of the first redistribution layer away from the first substrate, and the solder ball is electrically connected to the first redistribution layer.

[0039] See also Figure 2a In some embodiments, step 101 includes: providing a first protective film 2 on the front side of the first wafer 1. Specifically, the first wafer 1 includes a first main body 110 and a first conductive part 120 provided on one side of the first main body 110. The first protective film 2 covers the side of the first conductive part 120 away from the first main body 110. That is, the front side of the first wafer 1 refers to the surface of the first conductive part 120 away from the first main body 110, and the back side of the first wafer 1 refers to the surface of the first main body 110 away from the first conductive part 120.

[0040] See also Figure 2b In some embodiments, step 101 includes: thinning the back side of the first wafer 1. Specifically, the surface of the first main body 110 away from the first conductive part 120 may be ground to reduce the thickness of the first main body 110, thereby reducing the overall thickness of the first wafer 1.

[0041] See also Figure 2c In some embodiments, step 101 includes: removing the first protective film 2 .

[0042] See also Figure 2d In some embodiments, step 101 includes: disposing a second protective film 3 on the back side of the first wafer 1 . That is, the second protective film 3 covers the surface of the first main body 110 away from the first conductive part 120 .

[0043] See also Figure 2eIn some embodiments, step 101 includes: cutting the first wafer 1 to form a first chip 4. Specifically, the first wafer 1 may be cut by a cutting process such as laser cutting to form a plurality of first chips 4. Figure 2f shown.

[0044] See also Figure 2f The first chip 4 includes a first main body portion 110 and at least two first conductive portions 120 disposed on one side of the first main body portion 110 .

[0045] See also Figure 3a In some embodiments, step 102 includes: providing a third protective film 6 on the front side of the second wafer 5. Specifically, the second wafer 5 includes a second main body 510 and a second conductive part 520 provided on one side of the second main body 510. The third protective film 6 covers the side of the second conductive part 520 away from the second main body 510. That is, the front side of the second wafer 5 refers to the surface of the second conductive part 520 away from the second main body 510, and the back side of the second wafer 5 refers to the surface of the second main body 510 away from the second conductive part 520.

[0046] See also Figure 3b In some embodiments, step 102 includes: thinning the back side of the second wafer 5. Specifically, the surface of the second main body 510 away from the second conductive part 520 may be ground to reduce the thickness of the second main body 510, thereby reducing the overall thickness of the second wafer 5.

[0047] See also Figure 3c , in some embodiments, step 102 includes: removing the third protective film 6;

[0048] See also Figure 3d In some embodiments, step 102 includes: bonding the front surface of the first chip 4 to the front surface of the second wafer 5 to form a first semi-finished product 7. Specifically, the first conductive portion 120 of the first chip 4 is bonded to the second conductive portion 520 of the second wafer 5 to form the first semi-finished product 7.

[0049] In some embodiments, the front side of the first chip 4 is bonded to the front side of the second wafer 5 by at least one of hot pressing welding, ultrasonic welding, laser welding, conductive adhesive welding and micro welding to form the first semi-finished product 7 .

[0050] See also Figure 4a In some embodiments, step 103 includes: disposing a fourth protective film 8 on the back side of the second wafer 5. That is, the fourth protective film 8 covers the surface of the second main body 510 away from the second conductive part 520.

[0051] See also Figure 4bIn some embodiments, step 103 includes: cutting the second wafer 5 of the first semi-finished product 7, the second wafer 5 is cut to form a second chip 10, and the first chip 4 and the second chip 10 bonded to each other form a chip assembly 9. Specifically, the second wafer 5 can be cut by a cutting process such as laser cutting to form a plurality of second chips 10, and the second chip 10 and the first chip 4 are combined to form a chip assembly 9.

[0052] See also Figure 4c In some embodiments, the chip assembly 9 includes a first chip 4 and a second chip 10 stacked along a first direction M. The first chip 4 and the second chip 10 are bonded to each other, and the second chip 10 and the first chip 4 are combined to form the chip assembly 9.

[0053] See also Figure 5 In some embodiments, step 104 includes: providing a glue layer 13 on a carrier 12, and attaching the chip assembly 9 to the glue layer 13. In some embodiments, the glue layer 13 can be a double-sided adhesive. Specifically, the glue layer 13 is attached to the surface of one side of the carrier 12.

[0054] See also Figure 6 In some embodiments, step 105 includes: preparing a first packaging layer 11 on a side of the adhesive layer 13 away from the carrier 12 , wherein the first packaging layer 11 covers the chip component 9 .

[0055] Through the above scheme, the present application stacks and bonds the first chip 4 and the second chip 10 to form a chip assembly 9, which is then set on a carrier 12, and then uses the first packaging layer 11 to cover the chip assembly 9. Without affecting the thickness of the first packaging layer 11, more chips are packaged, the density of the packaging structure is improved, and the function of miniaturization of the packaging structure is realized.

[0056] See also Figure 7 In some embodiments, step 106 includes: disposing a first substrate 14 on a side of the first packaging layer 11 away from the carrier 12. In this embodiment, the material of the first substrate 14 is polyimide (PI for short).

[0057] See also Figure 8 In some embodiments, step 107 includes: patterning the first substrate 14 and the first packaging layer 11 to form a first conductive via 15, and the first conductive via 15 penetrates the first substrate 14 and the first packaging layer 11 along the first direction M. In some embodiments, the first conductive via 15 is formed by patterning the first substrate 14 and the first packaging layer 11 through a laser process, and one end of the first conductive via 15 close to the carrier 12 abuts against the surface of the second conductive portion 520 away from the second main body 510.

[0058] See also Fig. 9 In some embodiments, step 108 includes: preparing a first redistribution layer 16 in the first conductive hole 15 and on a side of the first substrate 14 away from the first packaging layer 11. In some embodiments, the first redistribution layer 16 is made by a spraying process, and the material of the first redistribution layer 16 is copper. In other embodiments, the first redistribution layer 16 can also be made by other processes and other conductive materials according to actual conditions and needs.

[0059] See also Fig.10 In some embodiments, the chip assembly packaging method further includes: removing the carrier 12 and the glue layer 13 .

[0060] See also Fig.11 In some embodiments, step 109 includes: preparing solder balls 17 on a side of the first redistribution layer 16 away from the first substrate 14 , wherein the solder balls 17 are electrically connected to the first redistribution layer 16 .

[0061] See also Figure 12a-12e In some embodiments, before step 109, the process further includes: preparing a sub-package structure 18 on a side of the first substrate 14 away from the first package layer 11, wherein the sub-package structure 18 covers the first redistribution layer 16. Specifically, between step 108 and the step of removing the carrier 12 and the adhesive layer 13, a sub-package structure 18 is prepared on a side of the first substrate 14 away from the first package layer 11, wherein the sub-package structure 18 covers the first redistribution layer 16.

[0062] See also Fig.12a In some embodiments, the step of preparing at least one sub-package structure 18 on the side of the first substrate 14 away from the first package layer 11 includes: arranging the chip component 9 on the side of the first substrate 14 away from the first package layer 11. In this embodiment, the chip component 9 is arranged on the side of the first substrate 14 away from the first package layer 11. In other embodiments, the chip component 9 may not be arranged on the side of the first substrate 14 away from the first package layer 11 according to actual needs.

[0063] See also Figure 12b In some embodiments, the step of preparing at least one sub-package structure 18 on the side of the first substrate 14 away from the first package layer 11 further includes: preparing a sub-package layer 1810 on the side of the first substrate 14 away from the first package layer 11, and the sub-package layer 1810 covers the first redistribution layer 16 and the chip component 9. In this embodiment, the first chip 4 and the second chip 10 are stacked and bonded to form a chip component 9, which is then arranged on the first substrate 14, and then the chip component 9 is covered with the sub-package layer 1810. On the basis of not affecting the thickness of the sub-package layer 1810, more chips are packaged, the density of the package structure is improved, and the function of miniaturization of the package structure is realized.

[0064] See also Fig.12c In some embodiments, the step of preparing at least one sub-encapsulation structure 18 on the side of the first substrate 14 away from the first encapsulation layer 11 further includes: preparing a sub-substrate 1820 on the side of the sub-encapsulation layer 1810 away from the first substrate 14. In this embodiment, the material of the sub-substrate 1820 is polyimide (PI for short).

[0065] See also Fig.12d In some embodiments, the step of preparing at least one sub-encapsulation structure 18 on the side of the first substrate 14 away from the first encapsulation layer 11 further includes: patterning the sub-substrate 1820 and the sub-encapsulation layer 1810 to form a sub-conductive hole 1830, and the sub-conductive hole 1830 penetrates the sub-substrate 1820 and the sub-encapsulation layer 1810 along the first direction M. In some embodiments, the sub-conductive hole 1830 is formed by patterning the sub-substrate 1820 and the sub-encapsulation layer 1810 through a laser process, and one end of a part of the sub-conductive hole 1830 close to the first substrate 14 abuts against the surface of the second conductive part 520 on the first substrate 14 away from the second main body 510, and one end of a part of the sub-conductive hole 1830 close to the first substrate 14 abuts against the surface of the first redistribution layer 16 on the side away from the first substrate 14.

[0066] See also Fig.12e In some embodiments, the step of preparing at least one sub-packaging structure 18 on the side of the first substrate 14 away from the first packaging layer 11 also includes: preparing a sub-rewiring layer 1840 in the sub-conductive hole 1830 and on the side of the sub-substrate 1820 away from the sub-packaging layer 1810, and the sub-rewiring layer 1840 is electrically connected to the first rewiring layer 16.

[0067] See also Fig.13 In some embodiments, Fig.12e The carrier and the glue layer 13 are removed on the basis of.

[0068] See also Fig.14 In some embodiments, Fig.13 On the basis of this, solder balls 17 are prepared on a side of the sub-redistribution layer 1840 away from the sub-substrate 1820 , and the solder balls 17 are electrically connected to the sub-redistribution layer 1840 .

[0069] See also Fig.15In some embodiments, before the step of preparing solder balls 17 on the side of the first redistribution layer 16 away from the first substrate 14, the method further includes: preparing a three-layer sub-encapsulation structure 18 on the side of the first substrate 14 away from the first packaging layer 11, and the sub-encapsulation structure 18 covers the first redistribution layer 16. Specifically, between the step of preparing the first redistribution layer 16 in the first conductive hole 15 and on the side of the first substrate 14 away from the first packaging layer 11 and the step of removing the carrier 12 and the glue layer 13, a three-layer sub-encapsulation structure 18 is prepared on the side of the first substrate 14 away from the first packaging layer 11, and the sub-encapsulation structure 18 covers the first redistribution layer 16. The sub-redistribution layer 1840 closest to the first substrate 14 is electrically connected to the first redistribution layer 16. In this embodiment, the bottommost sub-redistribution layer 1840 is electrically connected to the first redistribution layer 16.

[0070] See also Fig.15 In this embodiment, the chip component 9 is disposed on the side of the first substrate 14 away from the first packaging layer 11, and is disposed on the side of the sub-substrate 1820 away from the sub-packaging layer 1810. Specifically, the chip component 9 is disposed on the side of the first substrate 14 away from the first packaging layer 11 and on the side of each sub-substrate 1820 away from the sub-packaging layer 1810. In other embodiments, the chip component 9 may be disposed on the first substrate 14 or on part of the sub-substrates 1820 according to actual conditions, or the chip component 9 may not be disposed on the first substrate 14 and any sub-substrate 1820.

[0071] See also Fig.16 In some embodiments, Fig.15 The carrier and the glue layer 13 are removed on the basis of.

[0072] See also Fig.17 In some embodiments, Fig.16 On the basis of the above, solder balls 17 are prepared on the side of the sub-redistribution layer 1840 farthest from the first substrate 14 away from the sub-substrate 1820, and the solder balls 17 are electrically connected to the sub-redistribution layer 1840 farthest from the first substrate 14. In this embodiment, the solder balls 17 are electrically connected to the sub-redistribution layer 1840 at the top of the first substrate 14.

[0073] In some embodiments, the packaging method of the chip assembly includes: setting a first protective film 2 on the front side of the first wafer 1, thinning the back side of the first wafer 1, removing the first protective film 2, setting a second protective film 3 on the back side of the first wafer 1, and cutting the first wafer 1 to form a first chip 4; setting a third protective film 6 on the front side of the second wafer 5, thinning the back side of the second wafer 5, removing the third protective film 6, bonding the front side of the first chip 4 to the front side of the second wafer 5 to form a first semi-finished product 7, and The fourth protective film 8 is arranged on the back of the first semi-finished product 7, the second wafer 5 is cut to form a second chip 10, and the first chip 4 and the second chip 10 bonded to each other form a chip assembly 9; an adhesive layer 13 is arranged on a carrier 12, and the chip assembly 9 is attached to the adhesive layer 13; a first packaging layer 11 is prepared on a side of the adhesive layer 13 away from the carrier 12, and the first packaging layer 11 covers the chip assembly 9; a first substrate 14 is arranged on a side of the first packaging layer 11 away from the carrier 12; the first substrate 14 and the first packaging layer 11 are connected to each other. The packaging layer 11 is patterned to form a first conductive hole 15; a first redistribution layer 16 is prepared in the first conductive hole 15 and on a side of the first substrate 14 away from the first packaging layer 11; the chip component 9 is arranged on a side of the first substrate 14 away from the first packaging layer 11; a sub-packaging layer 1810 is prepared on a side of the first substrate 14 away from the first packaging layer 11, and the sub-packaging layer 1810 covers the first redistribution layer 16 and the chip component 9; a sub-substrate 1820 is prepared on a side of the sub-packaging layer 1810 away from the first substrate 14; and the sub-substrate 1 820 and the sub-packaging layer 1810 are patterned to form a sub-conductive hole 1830; a sub-rewiring layer 1840 is prepared in the sub-conductive hole 1830 and on the side of the sub-substrate 1820 away from the sub-packaging layer 1810, and a sub-packaging layer 1810, a sub-substrate 1820, a sub-conductive hole 1830, and a sub-rewiring layer 1840 are combined to form a sub-packaging structure 18; the carrier 12 and the adhesive layer 13 are removed; and a solder ball 17 is prepared on the side of the sub-rewiring layer 1840 farthest from the first substrate 14 and away from the sub-substrate 1820.

[0074] The above is a detailed introduction to a chip component packaging method provided by the present application. Specific examples are used in this article to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the core idea of ​​the present application. At the same time, for technical personnel in this field, according to the idea of ​​the present application, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present application.

Claims

1. A chip assembly (9) packaging method, characterized in that: The packaging method of the chip component (9) comprises: Cutting a first wafer (1) to form a first chip (4); Bonding the front side of the first chip (4) to the front side of a second wafer (5) to form a first semi-finished product (7); cutting the first semi-finished product (7) so that the second wafer (5) is cut into second chips (10), and the first chip (4) and the second chip (10) bonded to each other form a chip assembly (9); The chip component (9) is arranged on a carrier (12), wherein the carrier (12) has a first direction (M); A first packaging layer (11) is arranged on the carrier (12), wherein the first packaging layer (11) covers the chip component (9); A first substrate (14) is arranged on a side of the first packaging layer (11) away from the carrier (12); The first substrate (14) and the first packaging layer (11) are patterned to form a first conductive hole (15), wherein the first conductive hole (15) penetrates the first substrate (14) and the first packaging layer (11) along the first direction (M); Preparing a first redistribution layer (16) in the first conductive hole (15) and on a side of the first substrate (14) away from the first packaging layer (11); A solder ball (17) is prepared on a side of the first redistribution layer (16) away from the first substrate (14), and the solder ball (17) is electrically connected to the first redistribution layer (16).

2. The packaging method of the chip assembly (9) according to claim 1, characterized in that: The step of cutting a first wafer (1) to form a first chip (4) comprises: Providing a first protective film (2) on the front surface of the first wafer (1); Performing a thinning process on the back side of the first wafer (1); removing the first protective film (2); Arranging a second protective film (3) on the back side of the first wafer (1); The first wafer (1) is cut into pieces to form the first chips (4).

3. The packaging method of the chip assembly (9) according to claim 1, characterized in that: The step of bonding the front surface of the first chip (4) to the front surface of a second wafer (5) to form a first semi-finished product (7) comprises: Arranging a third protective film (6) on the front surface of the second wafer (5); Performing a thinning process on the back side of the second wafer (5); removing the third protective film (6); The front side of the first chip (4) is bonded to the front side of the second wafer (5) to form the first semi-finished product (7).

4. The packaging method of the chip assembly (9) according to claim 1, characterized in that: The first wafer (1) comprises a first main body portion (110) and a first conductive portion (120) arranged on one side of the first main body portion (110); the second wafer (5) comprises a second main body portion (510) and a second conductive portion (520) arranged on one side of the second main body portion (510); The step of bonding the front surface of the first chip (4) to the front surface of a second wafer (5) to form a first semi-finished product (7) comprises: The first conductive portion (120) of the first chip (4) and the second conductive portion (520) of the second wafer (5) are bonded to form a first semi-finished product (7).

5. The chip assembly (9) packaging method according to claim 1, characterized in that: The front side of the first chip (4) and the front side of the second wafer (5) are bonded to form a first semi-finished product (7) by using at least one of hot pressing welding, ultrasonic welding, laser welding, conductive adhesive welding and micro welding.

6. The chip assembly (9) packaging method according to claim 1, characterized in that: The step of cutting the first semi-finished product (7) so that the second wafer (5) is cut into a second chip (10), and the first chip (4) and the second chip (10) bonded to each other form a chip assembly (9) comprises: Arranging a fourth protective film (8) on the back side of the second wafer (5); The second wafer (5) of the first semi-finished product (7) is cut to form the second chip (10). The first chip (4) and the second chip (10) bonded to each other form the chip assembly (9).

7. The chip assembly (9) packaging method according to claim 1, characterized in that: The step of arranging the chip component (9) on a carrier (12) comprises: arranging an adhesive layer (13) on the carrier (12), and attaching the chip component (9) to the adhesive layer (13); Before the step of preparing solder balls (17) on the side of the first redistribution layer (16) away from the first substrate (14), the step further includes: removing the carrier (12) and the glue layer (13).

8. The chip assembly (9) packaging method according to claim 1, characterized in that: The step of patterning the first substrate (14) and the first packaging layer (11) to form a first conductive hole (15) comprises: The first substrate (14) and the first packaging layer (11) are patterned by laser processing to form a first conductive hole (15).

9. The chip assembly (9) packaging method according to claim 1, characterized in that: Before the step of preparing solder balls (17) on the side of the first redistribution layer (16) away from the first substrate (14), the method further comprises: preparing at least one sub-encapsulation structure (18) on the side of the first substrate (14) away from the first encapsulation layer (11), wherein the sub-encapsulation structure (18) covers the first redistribution layer (16); The step of preparing at least one sub-encapsulation structure (18) on a side of the first substrate (14) away from the first encapsulation layer (11) comprises: A sub-encapsulation layer (1810) is prepared on a side of the first substrate (14) away from the first encapsulation layer (11), wherein the sub-encapsulation layer (1810) covers the first redistribution layer (16); Preparing a sub-substrate (1820) on a side of the sub-encapsulation layer (1810) away from the first substrate (14); The sub-substrate (1820) and the sub-packaging layer (1810) are patterned to form a sub-conductive hole (1830), wherein the sub-conductive hole (1830) penetrates the sub-substrate (1820) and the sub-packaging layer (1810) along the first direction (M); A sub-redistribution layer (1840) is prepared in the sub-conductive hole (1830) and on a side of the sub-substrate (1820) away from the sub-packaging layer (1810), and the sub-redistribution layer (1840) closest to the first substrate (14) is electrically connected to the first redistribution layer (16); The solder ball (17) is prepared on the side of the sub-redistribution layer (1840) away from the sub-substrate (1820), and the solder ball (17) is electrically connected to the sub-redistribution layer (1840) farthest from the first substrate (14).

10. The chip assembly (9) packaging method according to claim 9, characterized in that: The step of preparing at least one sub-encapsulation structure (18) on a side of the first substrate (14) away from the first encapsulation layer (11) further comprises: The chip component (9) is arranged on a side of the first substrate (14) away from the first packaging layer (11) and / or on a side of the sub-substrate (1820) away from the sub-packaging layer (1810), and the sub-packaging layer (1810) covers the chip component (9).

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