A method for manufacturing a nano-silicon through hole and a chip packaging structure
By fabricating deep holes on wafers and forming cavities using CVD chemical vapor deposition, and then combining this with IC process to fabricate metal layers to connect IC devices, the incompatibility between through-silicon vias (TSVs) and IC processes is solved, achieving high-density interconnection and improved integration.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Patents(China)
- Current Assignee / Owner
- PEKING UNIV
- Filing Date
- 2024-11-07
- Publication Date
- 2026-07-24
AI Technical Summary
Existing technologies struggle to make through-silicon via (TSV) processes compatible with IC processes, making it impossible to achieve high-density interconnects on the same wafer.
By fabricating deep holes on wafers and using CVD chemical vapor deposition to partially fill them to form cavities, metal layers are fabricated using IC processes to connect IC devices, and then metal materials are filled to form nano-silicon through-hole structures.
It achieves compatibility between through-silicon vias (TSVs) and IC processes, improves the interconnect density and flexibility of wafer packaging, adapts to nano-TSV processing, and enhances the integration and performance of integrated circuits.
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Figure CN119400754B_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and in particular to a method for fabricating nano-silicon through-holes and a chip packaging structure. Background Technology
[0002] Through-silicon via (TSV) technology is an important advanced semiconductor packaging technology that allows direct electrical connections between silicon wafers via vertical vias. This enables integrated circuits to achieve higher integration and smaller sizes, meeting the ever-increasing demands for performance and power consumption. Currently, a common method for TSV packaging is to fabricate the TSV on a separate wafer and then connect it to a wafer containing logic or memory structures via bonding.
[0003] As the size of through-silicon vias (TSVs) continues to shrink, the via size is becoming increasingly similar to the device size, increasing the demand for interconnects. However, current technologies still struggle to achieve compatibility between TSV processes and IC processes and implement them on the same wafer. Summary of the Invention
[0004] In view of the above problems, this application provides a method for fabricating nano-silicon through-holes and a chip packaging structure to overcome or at least partially solve the above problems.
[0005] A first aspect of this application provides a method for preparing nano-silicon through-holes, the method comprising: Obtain a first wafer and determine a first surface of the first wafer, wherein the first surface is the surface on the first wafer on which the IC process is to be performed; A first deep hole is formed on the first surface of the first wafer by etching; By controlling the deposition conditions of CVD chemical vapor deposition, the first deep hole is partially filled with a dielectric layer material to obtain a second deep hole with a cavity. An IC process is performed on the first surface to fabricate an IC device layer; Using a first metal material, a first metal layer is prepared on the surface of the IC device layer, so that the first metal layer and the IC device in the IC device layer are metal connected, and the first metal layer covers the second deep hole; Thinning is performed from the second surface of the first wafer until the cavity of the second deep hole is exposed; The first metallic material is used to fill the second deep hole to obtain a nano-silicon through-hole structure.
[0006] In one possible implementation, filling the second deep hole with the first metallic material to obtain a nano-silicon through-hole structure includes: The dielectric layer material in the second deep hole is etched until the first metal layer is exposed. The cavity of the second deep hole is filled with the first metal material to obtain the nano-silicon through-hole structure.
[0007] In one possible implementation, the method further includes: Using the first metal material, a second metal layer is prepared on the second surface, such that the second metal layer is connected to the first metal layer through the nano-silicon through-hole structure.
[0008] In one possible implementation, the process of forming a first deep hole on a first surface of the first wafer by etching includes: Determine the position of each IC device on the first surface of the first wafer in the IC process to be executed; The position of the first deep hole is determined with the goal of ensuring that the position of the first deep hole does not overlap with the position of each IC device; The first deep hole is etched on the first surface of the first wafer according to its location.
[0009] In one possible implementation, the first metallic material is one or more of copper, tungsten, ruthenium, and aluminum.
[0010] In one possible implementation, the diameter of the nano-silicon through-hole structure is 100 nm-1 μm, and the depth is 1 μm-10 μm.
[0011] In one possible implementation, the depth of the first deep hole is 2-3 μm.
[0012] In one possible implementation, the dielectric layer material is silicon oxide or silicon nitride.
[0013] In one possible implementation, the deposition conditions for the CVD chemical vapor deposition include: the concentration of the CVD feed gas and the reaction temperature.
[0014] The second aspect of this application also provides a chip packaging structure, the chip packaging structure including a first wafer, the first wafer including a nano-silicon via structure, the nano-silicon via structure being prepared by the nano-silicon via preparation method described in the first aspect of this application.
[0015] This application provides a method for fabricating nano-silicon through-holes (TSHs). The method includes: obtaining a first wafer; determining a first surface of the first wafer, wherein the first surface is the surface on the first wafer to be processed by an IC process; fabricating a first deep hole on the first surface of the first wafer by etching; partially filling the first deep hole with a cavity by controlling the deposition conditions of CVD (Chemical Vapor Deposition) using a dielectric layer material; performing an IC process on the first surface to fabricate an IC device layer; fabricating a first metal layer on the surface of the IC device layer using a first metal material, thereby achieving a metal connection between the first metal layer and the IC device in the IC device layer, wherein the first metal layer covers the second deep hole; thinning from a second surface of the first wafer until the cavity of the second deep hole is exposed; and filling the second deep hole with the first metal material to obtain a nano-silicon through-hole structure.
[0016] The nano-silicon via fabrication method provided in this application utilizes CVD (chemical vapor deposition) to partially fill a first deep hole obtained through etching, forming a cavity, and then occupying space within the deep hole (fabricating a second deep hole with a cavity). Based on this, an IC process is performed to fabricate a first metal layer, which connects the IC device in the IC device layer to the deep hole. The deep hole is then filled to obtain the nano-silicon via structure. This method adapts the fabrication of silicon vias and IC devices to the same wafer, improving the interconnect density and flexibility of wafer packaging. Attached Figure Description
[0017] To more clearly illustrate the technical solutions of the embodiments of this application, the drawings used in the description of the embodiments of this application will be briefly introduced below. Obviously, the drawings described below are only some embodiments of this application. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0018] Figure 1 This is a flowchart illustrating the steps of a method for preparing nano-silicon through-holes provided in an embodiment of this application; Figure 2 This is a schematic diagram of the structure of the first deep hole formed by a nano-silicon through-hole preparation method provided in the embodiments of this application; Figure 3 This is a schematic diagram of the structure of the second deep hole formed by a nano-silicon through-hole preparation method provided in the embodiments of this application; Figure 4 This is a schematic diagram of the structure of an IC device layer formed by a nano-silicon through-hole fabrication method provided in this application embodiment; Figure 5This is a schematic diagram of the structure of the first metal layer formed by a method for preparing nano-silicon through-holes provided in this application embodiment; Figure 6 This is a schematic diagram of the thinned structure formed by a method for preparing nano-silicon through-holes provided in this application embodiment; Figure 7 This is a schematic diagram of the etched structure formed by a method for preparing nano-silicon through-holes provided in this application embodiment; Figure 8 This is a schematic diagram of a nano-silicon through-hole structure formed by a method for preparing nano-silicon through-holes provided in this application embodiment; Figure 9 This is a schematic diagram of a chip packaging structure formed by a nano-silicon through-hole fabrication method provided in an embodiment of this application; Figure 10 This is a schematic diagram of the structure of a nano-silicon through-hole fabrication device provided in an embodiment of this application; Figure description: First wafer 100, first deep hole 101, second deep hole of cavity 102, IC device layer 103, first metal layer 104, nano-silicon through-hole structure 105, second metal layer 106. Detailed Implementation
[0019] Exemplary embodiments of this application will now be described in more detail with reference to the accompanying drawings. While exemplary embodiments of this application are shown in the drawings, it should be understood that this application may be implemented in various forms and should not be limited to the embodiments set forth herein. Rather, these embodiments are provided to enable a more thorough understanding of this application and to fully convey the scope of this application to those skilled in the art.
[0020] Nano-Through-Silicon-Via (nTSV) are nanoscale through-holes that penetrate a silicon wafer and are filled with metal. NTSV technology is an important advanced semiconductor packaging technology that allows direct electrical connections between silicon wafers via vertical through-holes. It drives the development of integrated circuits towards higher integration and smaller sizes, meeting the ever-increasing demands for performance and power consumption.
[0021] Through-silicon vias (TSVs) are widely used in advanced packaging, but their apertures are typically between tens and hundreds of micrometers, resulting in low density. Furthermore, a common approach to TSV packaging is to fabricate them on a separate wafer and then connect them to a wafer containing logic or memory structures via bonding.
[0022] The small size of nano-sized through-silicon vias (TSVs) offers a density advantage, enabling higher interconnect density per unit area and thus greater practical value. Furthermore, as TSV sizes shrink to sub-micrometer scales, the via size and device size become increasingly similar, allowing nano-sized TSVs to connect to structures as small as several devices, significantly improving interconnect density and flexibility. However, current technologies still struggle to achieve compatibility between TSV fabrication processes and IC fabrication on the same wafer.
[0023] In view of the above problems, this application proposes a method for fabricating nano-silicon vias and a chip packaging structure to achieve compatibility between the via fabrication process and IC process and to realize them on the same wafer. The method for fabricating nano-silicon vias provided in this application will be described in detail below with reference to the accompanying drawings and through some embodiments and application scenarios.
[0024] The first aspect of this application provides a method for preparing nano-silicon through-holes, referring to... Figure 1 , Figure 1 A flowchart illustrating the steps of a method for preparing nano-silicon through-holes provided in this application embodiment is shown below. Figure 1 As shown, the method includes: Step S101: Obtain the first wafer and determine the first surface of the first wafer, wherein the first surface is the surface on the first wafer on which the IC process is to be performed.
[0025] In this embodiment, the first wafer can be a bare silicon wafer. The first wafer has two surfaces, namely a first surface and a second surface, with the first surface being the surface on the first wafer to be processed by IC technology. IC technology refers to the process of processing the first wafer through multiple steps to embed one or more IC devices inside or on the surface of the wafer, achieving electrical connection in subsequent packaging or in the bonding stack structure formed by multiple wafers. Different application scenarios involve different IC technologies and IC devices; therefore, this embodiment does not specifically limit the IC technology.
[0026] Step S102: A first deep hole is formed on the first surface of the first wafer by etching.
[0027] Reference Figure 2 , Figure 2 A schematic diagram of the structure of the first deep hole formed by a method for preparing nano-silicon through-holes is shown, as follows. Figure 2 As shown, according to the required size of the through-silicon via (TSV), a first deep hole 101 is formed on the first surface of the first wafer 100 by etching. Figure 2As shown, the height of the first deep hole can be determined according to actual needs, but it must not be the same as the thickness of the wafer, i.e., it cannot become a through-hole structure. The location of the first deep hole 101 (i.e., the final location of the required through-silicon via) can be determined according to actual application requirements. Since IC processing is required on the first surface in subsequent steps, the impact on subsequent IC processes must be fully considered when determining the location of the first deep hole 101; for example, the location of the first deep hole should not occupy the space of the IC device.
[0028] In one possible implementation, the depth of the first deep hole is 2-3 μm. The diameter of the first deep hole can be 100 nm-1 μm.
[0029] In one possible implementation, step S102, which involves etching to create a first deep hole on a first surface of the first wafer, includes: Step S1021: Determine the position of each IC device in the IC process to be executed on the first surface of the first wafer.
[0030] Step S1022: Determine the position of the first deep hole with the goal of ensuring that the position of the first deep hole does not overlap with the position of each IC device.
[0031] Step S1023: Etch the first deep hole on the first surface of the first wafer according to the position of the first deep hole.
[0032] In this embodiment, based on the IC process to be executed (i.e., the IC process to be executed in step S104), the positions occupied by each IC device involved on the first surface are determined, such as the position of the chip, the position of the metal PAD, etc. With the goal of ensuring that the position of the first deep hole does not overlap with the positions of each IC device, the position of the first deep hole is determined from the empty first surface, and then etching is performed to obtain the first deep hole.
[0033] Step S103: By controlling the deposition conditions of CVD chemical vapor deposition, the first deep hole is partially filled with a dielectric layer material to obtain a second deep hole with a cavity.
[0034] Specifically, refer to Figure 3 , Figure 3 A schematic diagram of the structure of a second deep pore formed by a method for preparing nano-silicon through-holes is shown, as follows. Figure 3 As shown, in this embodiment, chemical vapor deposition is used to deposit a dielectric layer material into the first deep hole. Because the pore size of the first deep hole is relatively small relative to its height, the rapid deposition rate causes the opening of the deep hole to be filled before the interior of the first deep hole, resulting in incomplete filling of the interior of the first deep hole, forming a layer as shown in the diagram. Figure 3The second deep hole 102 with a cavity is shown. Then, excess dielectric layer material on the first surface is removed by oxygen plasma etching, leaving the first surface as a smooth plane.
[0035] In one possible implementation, the dielectric layer material is silicon oxide or silicon nitride.
[0036] In one possible implementation, the deposition conditions for the CVD chemical vapor deposition include: the concentration of the CVD feed gas and the reaction temperature.
[0037] Specifically, incomplete filling of the first deep hole can be achieved by controlling the concentration and temperature of the raw material gas during vapor deposition. Increasing the raw material gas concentration or decreasing the temperature promotes the deposition of the dielectric layer material at the opening of the first deep hole. In practical applications of CVD deposition, different processes use different raw material gases, and their concentrations and reaction temperatures vary significantly. Therefore, this embodiment does not limit the specific range of raw material gas concentration and reaction temperature. For example, using the PECVD method with tetraethyl orthosilicate (TEOS) as the raw material, a 300 nm thick layer of general-weight silicon dioxide is deposited at a reaction temperature between 250°C and 400°C, with a raw material gas volume ratio (i.e., raw material gas concentration) of TEOS:oxygen = 1:5-1:10. It should be noted that actual process parameters still need to be adjusted based on the desired film quality, deposition rate, and the equipment itself. Therefore, the data provided in the above example can only be used as a "typical" reference.
[0038] Step S104: Perform IC process on the first surface to prepare IC device layer.
[0039] In this application embodiment, no specific IC process scheme is limited. The IC process may include embedding the chip in an etched buried trench, or using a dual damascene wiring process to fabricate one or more metal interconnect structures, etc. (Refer to...) Figure 4 , Figure 4 A schematic diagram of the structure of an IC device layer formed by a nano-silicon through-hole fabrication method is shown, as follows. Figure 4 As shown, different IC processes result in different final structures. These structures can include IC devices embedded in the first wafer (e.g., chips, metal interconnect structures), or IC devices and related dielectric materials fixed on the first surface of the first wafer. In this embodiment, they can be uniformly represented as a single hierarchical structure, namely IC device layer 103. For example... Figure 4 As shown, during the IC process, the structure of the second deep hole is not affected, so that the surface of the final IC device layer and the surface of the second deep hole are on the same horizontal plane.
[0040] Step S105: Using a first metal material, a first metal layer is prepared on the surface of the IC device layer, so that the first metal layer and the IC device in the IC device layer are metal connected, and the first metal layer covers the second deep hole.
[0041] In this embodiment, the first metal layer is used to realize the metal connection between some IC devices in the IC device layer and the second deep hole. The first metal layer may include metal interconnect structures of different shapes. The specific structure and fabrication method of the first metal layer will vary with IC processes and are designed according to actual process requirements. This embodiment does not limit these aspects. (Refer to...) Figure 5 , Figure 5 A schematic diagram of the structure of the first metal layer formed by a method for fabricating nano-silicon through-holes is shown, as follows. Figure 5 As shown, the first metal layer may contain metal structures connecting IC devices within the IC device layer, or it may contain related dielectric materials that serve a fixing or filling function, or it may contain metal structures connected to the second deep hole. The connection between the first metal layer and the second deep hole does not disrupt the original structure of the second deep hole; it means that the metal components in the first metal layer cover the second deep hole, i.e., the original opening of the first deep hole. In the embodiments of this application, it can be uniformly represented as a hierarchical structure located above the IC device layer, namely the first metal layer 104.
[0042] In one possible implementation, the first metallic material is one or more of copper, tungsten, ruthenium, and aluminum.
[0043] Step S106: Thinning is performed from the second surface of the first wafer until the cavity of the second deep hole is exposed.
[0044] In this embodiment, a multi-step thinning method can be used to thin the surface of the first wafer away from the first surface (i.e., the second surface), exposing the cavity of the second deep hole. The thinning process generally employs a multi-step thinning method (mechanical thinning-CMP-dry etching) to achieve the desired silicon layer thickness. (Refer to...) Figure 6 , Figure 6 A schematic diagram of a thinned structure formed by a method for fabricating nano-silicon through-holes is shown, as follows. Figure 6 As shown, the back side (i.e., the second surface) of the first wafer is thinned until the cavity of the second deep via is exposed. Alternatively, the thinning thickness is calculated based on the required height of the through-silicon via (TSV), such that the height of the remaining second deep via after thinning is the same as the final required height of the TSV.
[0045] Step S107: Using the first metal material, fill the second deep hole to obtain a nano-silicon through-hole structure.
[0046] In one possible implementation, step S107, which involves filling the second deep hole with the first metal material to obtain a nano-silicon through-hole structure, includes: Step S1071: Etch the dielectric layer material in the second deep hole until the first metal layer is exposed.
[0047] Specifically, refer to Figure 7 , Figure 7 A schematic diagram of the etched structure formed by a method for fabricating nano-silicon through-holes is shown, as follows. Figure 7 As shown, after the thinning process in step S106, since the other end of the second deep hole is still deposited with dielectric layer material, the dielectric layer material in the second deep hole is etched in step S1071 until the bottom first metal layer is exposed.
[0048] Step S1072: Fill the cavity of the second deep hole with the first metal material to obtain the nano-silicon through-hole structure.
[0049] Specifically, refer to Figure 8 , Figure 8 A schematic diagram of a nano-silicon through-hole structure formed by a method for preparing nano-silicon through-holes is shown, as follows. Figure 8 As shown, after etching, the second deep hole is filled by metal deposition to form a nano-silicon through-hole structure 105, and the silicon through-hole is metal-connected to the first metal layer. This allows the nano-silicon through-hole structure to achieve metal connection with related IC devices in the IC device through the metal components in the first metal layer. The first metal material is the same as the metal material used to prepare the first metal layer. The first metal material is one or more of copper, tungsten, ruthenium, and aluminum.
[0050] In one possible implementation, the diameter of the nano-silicon through-hole structure is 100 nm-1 μm, and the depth is 1 μm-10 μm. Correspondingly, the diameter of the first and second deep holes in steps S102-S106 is 100 nm-1 μm. Since the depth of the second deep hole (i.e., the height of the deep hole) is reduced to some extent when thinning is performed from the second surface in step S106, the depth of the first and second deep holes in steps S102-S105 will slightly exceed 1 μm-10 μm. Further, the depth of the nano-silicon through-hole structure is 2-3 μm.
[0051] In one possible implementation, the method further includes: Step S108: Using the first metal material, a second metal layer is prepared on the second surface, such that the second metal layer and the first metal layer are connected through the nano-silicon through-hole structure.
[0052] In this embodiment, after filling the vias with metal to obtain a nano-silicon via structure, excess first metal material on the second surface can be removed to keep the second surface smooth. Then, a second metal layer is prepared on the second surface, allowing the upper surface (the first metal layer on the first surface) and the lower surface (the second metal layer on the second surface) of the first wafer to be connected through the obtained nano-silicon via structure, forming a through-hole connection channel from the front metal layer to the back metal layer of the silicon wafer. When preparing the second metal layer, the same first metal material as the first metal layer and the nano-silicon via structure can be used; this first metal material can be one or more of copper, tungsten, ruthenium, and aluminum.
[0053] In the embodiments of this application, the second metal layer may include metal interconnect structures of different shapes. The specific structure and fabrication method of the second metal layer are designed according to actual process requirements and are not limited in the embodiments of this application. (Refer to...) Figure 9 , Figure 9 A schematic diagram of a chip packaging structure formed by a nano-silicon through-hole fabrication method is shown, as follows. Figure 9 As shown, a back metal layer, namely the second metal layer 106, is formed on the back side of the first wafer. The connection between the second metal layer 106 and the nano-through-silicon via (TSV) structure 105 does not disrupt the original structure of the TSV; rather, the metal components in the second metal layer cover the TSV 106. In the embodiments of this application, it can be uniformly represented as a hierarchical structure located on the second surface of the first wafer, namely the second metal layer 106, which completes the TSV fabrication from the front metal layer to the back metal layer.
[0054] The nano-silicon via (TSV) fabrication method provided in this application utilizes CVD (chemical vapor deposition) to partially fill a first deep hole obtained through etching, forming a cavity, and then occupying space within the deep hole (fabricating a second deep hole with a cavity). Based on this, an IC process is performed to fabricate a first metal layer, which connects the IC device in the IC device layer to the deep hole. The deep hole is then filled to obtain the nano-silicon via structure. This achieves the adaptation of TSV fabrication and IC device fabrication onto the same wafer, improving the interconnect density and flexibility of wafer packaging. This application provides a nano-silicon via fabrication method compatible with nano-IC device manufacturing on the same silicon wafer, offering a highly adaptable solution for achieving high-density vertical interconnects. Furthermore, the method for leaving holes in the nano-silicon via structure does not require high-precision photolithographic alignment.
[0055] A second aspect of this application also provides a chip packaging structure, the chip packaging structure including a first wafer, the first wafer including a nano-silicon via structure, the nano-silicon via structure being prepared by the nano-silicon via preparation method described in the first aspect.
[0056] Specifically, the chip packaging structure is as follows: Figure 9 As shown, the chip packaging structure includes: a first wafer 100, an IC device layer 103, a first metal layer 104, a nano-silicon via structure 105, and a second metal layer 106. The first metal layer 104 and the second metal layer 106 are connected via the nano-silicon via structure 105. The IC devices in the IC device layer 103 are connected to the metal devices in the first metal layer 104, and the metal devices in the first metal layer 104 are connected to the nano-silicon via structure 105. The specific structure of the IC device layer is determined by the specific IC process, and this embodiment does not limit the structure of the IC device layer. For example, the IC device layer may include multiple chips embedded in buried trenches, metal pads connected to the chips, and dielectric layer materials that provide fixation and filling. Correspondingly, this embodiment does not limit the specific structures of the first and second metal layers, as long as the first and second metal layers include metal interconnect structures connected to the nano-silicon via structure.
[0057] A third aspect of this application provides a through-silicon via (TSV) fabrication apparatus for performing the steps of the nano-TSV fabrication method provided in the first aspect, with reference to... Figure 10 , Figure 10 A schematic diagram of a through-silicon via (TSV) fabrication apparatus is shown, as follows: Figure 10 As shown, the device includes: A wafer acquisition module is used to acquire a first wafer and determine a first surface of the first wafer, wherein the first surface is the surface on the first wafer to be processed by an IC process; An etching module is used to form a first deep hole on a first surface of the first wafer by etching. The first filling module is used to partially fill the first deep hole with a cavity by controlling the deposition conditions of CVD chemical vapor deposition and using a dielectric layer material. An IC process execution module is used to perform IC processes on the first surface to fabricate an IC device layer; The first metal layer fabrication module is used to fabricate a first metal layer on the surface of the IC device layer using a first metal material, so that the first metal layer and the IC device in the IC device layer are connected by metal, and the first metal layer covers the second deep hole. A thinning module is used to thin from the second surface of the first wafer until the cavity of the second deep hole is exposed; The second filling module is used to fill the second deep hole with the first metal material to obtain a nano-silicon through-hole structure.
[0058] In one possible implementation, the second filling module includes: The first etching submodule is used to etch the dielectric layer material in the second deep hole until the first metal layer is exposed; The filling submodule is used to fill the cavity of the second deep hole with the first metal material to obtain the nano-silicon through-hole structure.
[0059] In one possible implementation, the device further includes: The second metal layer preparation module is used to prepare a second metal layer on the second surface using the first metal material, so that the second metal layer is connected to the first metal layer through the nano-silicon through-hole structure.
[0060] In one possible implementation, the etching module includes: The IC device location determination submodule is used to determine the position of each IC device on the first surface of the first wafer in the IC process to be executed. The first deep hole position determination submodule is used to determine the position of the first deep hole with the goal of ensuring that the position of the first deep hole does not overlap with the position of each IC device; The second etching submodule is used to etch the first deep hole on the first surface of the first wafer according to the position of the first deep hole.
[0061] In one possible implementation, the first metallic material is one or more of copper, tungsten, ruthenium, and aluminum.
[0062] In one possible implementation, the diameter of the nano-silicon through-hole structure is 100 nm-1 μm, and the depth is 1 μm-10 μm.
[0063] In one possible implementation, the depth of the first deep hole is 2-3 μm.
[0064] In one possible implementation, the dielectric layer material is silicon oxide or silicon nitride.
[0065] In one possible implementation, the deposition conditions for the CVD chemical vapor deposition include: the concentration of the CVD feed gas and the reaction temperature.
[0066] The various embodiments in this specification are described in a progressive manner, with each embodiment focusing on the differences from other embodiments. The same or similar parts between the various embodiments can be referred to each other.
[0067] This application describes embodiments with reference to flowchart illustrations and / or block diagrams of methods, apparatuses, electronic devices, and computer program products according to embodiments of this application. It should be understood that each block of the flowchart illustrations and / or block diagrams, and combinations of blocks in the flowchart illustrations and / or block diagrams, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, special-purpose computer, embedded processor, or other programmable data processing terminal device to produce a machine, such that the instructions, which execute via the processor of the computer or other programmable data processing terminal device, generate instructions for implementing the flowchart... Figure 1 One or more processes and / or boxes Figure 1 A device that provides the functions specified in one or more boxes.
[0068] These computer program instructions may also be stored in a computer-readable storage medium that can direct a computer or other programmable data processing terminal device to operate in a particular manner, such that the instructions stored in the computer-readable storage medium produce an article of manufacture including instruction means, which are implemented in a process Figure 1 One or more processes and / or boxes Figure 1 The function specified in one or more boxes.
[0069] These computer program instructions can also be loaded onto a computer or other programmable data processing terminal equipment, causing a series of operational steps to be performed on the computer or other programmable terminal equipment to produce a computer-implemented process, thereby providing instructions that execute on the computer or other programmable terminal equipment for implementing the process. Figure 1 One or more processes and / or boxes Figure 1 The steps of the function specified in one or more boxes.
[0070] Although preferred embodiments of the present application have been described, those skilled in the art, upon learning the basic inventive concept, can make other changes and modifications to these embodiments. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments as well as all changes and modifications falling within the scope of the embodiments of the present application.
[0071] Finally, it should be noted that in this document, relational terms such as "first" and "second" are used only to distinguish one entity or operation from another, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Furthermore, the terms "comprising," "including," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or terminal device that comprises a list of elements includes not only those elements but also other elements not expressly listed, or elements inherent to such a process, method, article, or terminal device. Without further limitations, an element defined by the phrase "comprising one..." does not exclude the presence of other identical elements in the process, method, article, or terminal device that includes said element.
[0072] The above provides a detailed description of a method for fabricating nano-silicon through-holes and a chip packaging structure provided in this application. Specific examples have been used to illustrate the principles and implementation methods of this application. The descriptions of the above embodiments are only for the purpose of helping to understand the method and core ideas of this application. At the same time, for those skilled in the art, there will be changes in the specific implementation methods and application scope based on the ideas of this application. Therefore, the content of this specification should not be construed as a limitation of this application.
Claims
1. A method for preparing nano-silicon through-holes, characterized in that, The method includes: Obtain a first wafer and determine a first surface of the first wafer, wherein the first surface is the surface on the first wafer on which the IC process is to be performed; A first deep hole is formed on the first surface of the first wafer by etching. The height of the first deep hole cannot be the same as the thickness of the first wafer, and the first deep hole cannot be converted into a through-hole structure. The depth of the first deep hole is 2-3 μm, and the diameter of the first deep hole is 100 nm-1 μm. By controlling the deposition conditions of CVD (Chemical Vapor Deposition), a dielectric layer material is used to partially fill the first deep hole, resulting in a second deep hole with a cavity. This partial filling of the first deep hole by the dielectric layer material includes: controlling the concentration and temperature of the raw material gas during vapor deposition; increasing the raw material gas concentration or decreasing the temperature to promote the accumulation of the dielectric layer material at the opening of the first deep hole; and ensuring that the opening of the first deep hole is filled before the interior, thus leaving the interior incompletely filled. An IC process is performed on the first surface to prepare an IC device layer; during the IC process, the structure of the second deep hole is not affected, so that the surface of the final prepared IC device layer and the surface of the second deep hole are on the same horizontal plane. A first metal layer is prepared on the surface of the IC device layer using a first metal material, so that the first metal layer and the IC device in the IC device layer are metal connected, and the first metal layer covers the second deep hole; the metal components in the first metal layer cover the second deep hole. Thinning is performed from the second surface of the first wafer until the cavity of the second deep hole is exposed; the height of the remaining second deep hole after thinning is the same as the final required height of the through silicon via; Using the first metal material, the second deep hole is filled to obtain a nano-silicon through-hole structure, which enables metal connection between the nano-silicon through-hole structure and the relevant IC device in the IC device layer through the metal components in the first metal layer; the diameter of the nano-silicon through-hole structure is 100nm-1um, and the depth is 1um-10um; filling the second deep hole with the first metal material to obtain the nano-silicon through-hole structure includes: etching the dielectric layer material in the second deep hole until the first metal layer is exposed; and filling the cavity of the second deep hole with the first metal material to obtain the nano-silicon through-hole structure; Using the first metal material, a second metal layer is prepared on the second surface to complete the through-silicon via (TSV) fabrication from the second metal layer to the first metal layer, so that the second metal layer and the first metal layer are connected through the nano-TSV structure, forming a connection channel through the silicon wafer from the first metal layer to the second metal layer; the connection channel through the silicon wafer from the first metal layer to the second metal layer is a vertical through-hole through the silicon wafer, so as to realize the direct electrical connection between the silicon wafer and other silicon wafers through the vertical through-hole; the metal components in the second metal layer cover the TSV below.
2. The method for preparing nano-silicon through-holes according to claim 1, characterized in that, The process of forming a first deep hole on a first surface of the first wafer by etching includes: Determine the position of each IC device on the first surface of the first wafer in the IC process to be executed; The position of the first deep hole is determined with the goal of ensuring that the position of the first deep hole does not overlap with the position of each IC device; The first deep hole is etched on the first surface of the first wafer according to its location.
3. The method for preparing nano-silicon through-holes according to claim 1, characterized in that, The first metallic material is one or more of copper, tungsten, ruthenium, and aluminum.
4. The method for preparing nano-silicon through-holes according to claim 1, characterized in that, The dielectric layer material is silicon oxide or silicon nitride.
5. A chip packaging structure, characterized in that, The chip packaging structure includes a first wafer, the first wafer including a nano-silicon through-hole structure, the nano-silicon through-hole structure being prepared by the nano-silicon through-hole preparation method according to any one of claims 1-4.