Interface heat dissipation material preform, preparation method thereof and multi-chip packaging structure

Abstract

The present application provides an interface heat dissipation material preform, a preparation method thereof, and a multi-chip packaging structure. The interface heat dissipation material preform, a preparation method thereof, and a multi-chip packaging structure provided by the present application form multiple chip fixing areas on the second surface, and at least two of the multiple chip fixing areas have different thicknesses. In this way, the interface heat dissipation material preform can simultaneously support at least two chips of different thicknesses, adapting to different chip requirements, thereby simplifying the packaging process, reducing assembly time, improving production flexibility, and increasing production efficiency. In addition, the standardized design of the interface heat dissipation material preform helps ensure the consistency and repeatability of each multi-chip package, which can reduce variability in the production process.

Description

Technical Field

[0001] The present application relates to the field of chip packaging technology, and in particular to an interface heat dissipation material preform, a preparation method thereof, and a multi-chip packaging structure. Background Art

[0002] In multi-chip packaging, chip heights vary due to varying design requirements. This leads to uneven distances between the top of the chip and the bottom of the heat sink. This necessitates the use of multiple preforms of thermal interface material to accommodate these varying chip heights. This multi-chip packaging requires multiple pick-and-place processes, resulting in a long production cycle. Summary of the Invention

[0003] In view of this, the present application provides an interface heat dissipation material preform, a preparation method thereof and a multi-chip packaging structure, which are used to simultaneously package chips of different thicknesses using a piece of interface heat dissipation material preform, so as to improve the efficiency of chip packaging and shorten the chip packaging cycle.

[0004] Specifically, this application is implemented through the following technical solutions:

[0005] In a first aspect, the present application provides an interface heat dissipation material preform, which is used for a multi-chip packaging structure. The multi-chip packaging structure includes a plurality of chips, and the plurality of chips include at least two chips of different thicknesses. The interface heat dissipation material preform has a first surface and a second surface that are arranged in back-to-back relationship.

[0006] The first surface is a plane and is used for bonding the heat dissipation cover in the multi-chip packaging structure;

[0007] A plurality of chip fixing areas matching the plurality of chips are formed on the second surface, each chip fixing area being used to fix a chip matching the chip fixing area; a total thickness of each chip fixing area and the chip to be fixed on the chip fixing area is equal to a specified value, and at least two of the plurality of chip fixing areas have different thicknesses, so that the at least two chips of different thicknesses can be simultaneously fixed by the interface heat dissipation material preform.

[0008] A second aspect of the present application provides a method for preparing an interface heat dissipation material preform, the method being used to prepare the interface heat dissipation material preform provided in the first aspect of the present application; the method comprising:

[0009] Prepare an initial piece of interface heat dissipation material; wherein the initial piece of interface heat dissipation material has a first surface and a second surface disposed back to back;

[0010] A plurality of chip fixing regions are formed on the second surface; wherein at least two of the plurality of chip fixing regions have different thicknesses, and a total thickness of each chip fixing region and a chip to be fixed thereon is equal to a specified value.

[0011] The third aspect of the present application provides a multi-chip packaging structure, which includes a substrate, a plurality of chips, an interface heat dissipation material preform as provided in the first aspect of the present application, and a heat dissipation cover; wherein,

[0012] The plurality of chips are fixed on the substrate; the plurality of chips include at least two chips with different thicknesses;

[0013] The interface heat dissipation material preform has a plurality of chip fixing regions matching the plurality of chips, and the interface heat dissipation material preform is fixed to the plurality of chips in a manner such that each chip fixing region is directly opposite to the chip it matches; wherein the total thickness of each chip fixing region and the chip it matches is equal to a specified value;

[0014] The heat dissipation cover is fixed on the first surface of the interface heat dissipation material preform in a manner of covering the plurality of chips, and a surrounding portion of the heat dissipation cover protruding downward is in contact with the base.

[0015] The interface heat dissipation material preform, its preparation method and multi-chip packaging structure provided by the present application form multiple chip fixing areas on the second surface, and make the thickness of at least two chip fixing areas of the multiple chip fixing areas different. In this way, the interface heat dissipation material preform can simultaneously support at least two chips of different thicknesses, and can adapt to different chip requirements to simplify the packaging process, reduce assembly time, improve production flexibility and improve generation efficiency; in addition, the standardized design of the interface heat dissipation material preform helps to ensure the consistency and repeatability of each multi-chip package, which can reduce the variability in the production process. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] Figure 1 This is a schematic diagram of Example 1 of the interface heat dissipation material preform provided in this application;

[0017] Figure 2 for Figure 1 A schematic diagram of a multi-chip package structure where the interface heat dissipation material preform is located;

[0018] Figure 3 This is a schematic diagram of Example 2 of the interface heat dissipation material preform provided in this application;

[0019] Figure 4 for Figure 3A schematic diagram of a multi-chip package structure where the interface heat dissipation material preform is located;

[0020] Figure 5 This is a schematic diagram of Example 3 of the interface heat dissipation material preform provided in this application;

[0021] Figure 6 for Figure 5 A bottom view of the multi-chip package structure where the interface heat dissipation material preform is located;

[0022] Figure 7 This is a schematic diagram of a fourth embodiment of the interface heat dissipation material preform provided in this application;

[0023] Figure 8 A schematic diagram of an interface heat dissipation material preform is provided for the present application as an exemplary embodiment;

[0024] Figure 9 This is a schematic diagram of Example 5 of the interface heat dissipation material preform provided in this application;

[0025] Figure 10 This is a flow chart of Example 1 of the method for preparing the interface heat dissipation material preform provided in this application;

[0026] Figure 11 This is a schematic diagram illustrating the implementation principle of preparing a preform of an interface heat dissipation material according to an exemplary embodiment of the present application.

[0027] Description of reference numerals:

[0028] 11: first surface;

[0029] 12: second surface;

[0030] 121: chip fixing area;

[0031] 122: Division;

[0032] 123: Melting starting point control unit. DETAILED DESCRIPTION

[0033] Exemplary embodiments are described in detail herein, with examples illustrated in the accompanying drawings. When the following description refers to the drawings, identical numerals in different drawings represent identical or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all embodiments consistent with this application.

[0034] The terms used in this application are for the purpose of describing specific embodiments only and are not intended to limit this application. The singular forms "a," "the," and "the" used in this application are also intended to include the plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0035] It should be understood that although the terms first, second, third, etc. may be used in this application to describe various information, such information should not be limited to these terms. These terms are only used to distinguish information of the same type from each other. For example, without departing from the scope of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the word "if" as used herein may be interpreted as "at the time of" or "when" or "in response to determining".

[0036] Specific embodiments are given below to introduce the technical solutions of the present application in detail.

[0037] Figure 1 This is a schematic diagram of Example 1 of the interface heat dissipation material preform provided in this application. Figure 2 for Figure 1 The schematic diagram of the multi-chip package structure where the interface heat dissipation material preform is located is shown. Please also refer to Figure 1 and Figure 2 The interface heat dissipation material preform provided in this embodiment is used for a multi-chip packaging structure, wherein the multi-chip packaging structure includes a plurality of chips, and the plurality of chips include chips of at least two different thicknesses; the interface heat dissipation material preform has a first surface 11 and a second surface 12 disposed in back-to-back relation; wherein,

[0038] The first surface 11 is a plane and is used for bonding the heat dissipation cover in the multi-chip packaging structure;

[0039] A plurality of chip fixing areas 121 matching the plurality of chips are formed on the second surface 12, and each chip fixing area 121 is used to fix a chip matching the chip fixing area 121; the total thickness of each chip fixing area 121 and the chip to be fixed on the chip fixing area 121 is equal to a specified value, and the thicknesses of at least two chip fixing areas 121 among the plurality of chip fixing areas 121 are different, so that the at least two chips of different thicknesses can be simultaneously fixed by the interface heat dissipation material preform.

[0040] Specifically, the multi-chip package structure includes multiple chips. Due to different designs, the thickness of the multiple chips may be different, that is, the multiple chips include at least two chips with different thicknesses. Figure 2In the example shown, the multi-chip package structure includes three chips, and the thicknesses of the three chips are different. That is, the multi-chip package structure includes chips of three different thicknesses.

[0041] For further information, please refer to Figure 1 and Figure 2 The interface heat dissipation material preform provided in this embodiment has a first surface 11 and a second surface 12, which are arranged back to back; wherein the first surface 11 is a plane and is used to bond with the heat dissipation cover in the multi-chip packaging structure, and the second surface 12 is composed of multiple planes of different heights, and the multiple uneven planes constitute multiple chip fixing areas 121. For example, in Figure 1 In the example shown, the second plane 12 has three uneven surfaces, which constitute three chip fixing areas 121 .

[0042] It should be noted that the bonding method between the first surface 11 and the heat dissipation cover is set according to actual needs and is not limited in this embodiment. For example, the bonding method between the first surface 11 and the heat dissipation cover can be thermal adhesive bonding, welding, etc. Furthermore, the number of chip fixing areas 121 included on the second surface 12 matches the number of chips included in the multi-chip package structure, and each chip fixing area 121 is used to fix the chip that matches the chip fixing area 121. It should be noted that if the sum of the thickness of a chip fixing area 121 and the thickness of a chip (i.e., the total thickness) is equal to a specified value, the chip fixing area 121 matches the chip.

[0043] Please refer to Figure 2 ,exist Figure 2 In the example shown, the multi-chip package structure includes three chips. For the convenience of explanation, the three chips are respectively marked as the first chip, the second chip and the third chip in order from left to right. Figure 1 and Figure 2 The interface heat dissipation material preform provided in this embodiment includes three chip fixing areas 121. For the convenience of distinction, the three chip fixing areas 121 are respectively recorded as a first chip fixing area, a second chip fixing area and a third chip fixing area.

[0044] Reference Figure 2The total thickness of the first chip and the first chip fixing region is equal to a specified value, the first chip and the first chip fixing region match, and the first chip fixing region is used to fix the first chip. Similarly, the total thickness of the second chip and the second chip fixing region is equal to a specified value, the second chip and the second chip fixing region match, and the second chip fixing region is used to fix the second chip. Similarly, the total thickness of the third chip and the third chip fixing region is equal to a specified value, the third chip and the third chip fixing region match, and the third chip fixing region is used to fix the third chip. The interface heat dissipation material preform includes three chip fixing regions 121 of different thicknesses, capable of simultaneously fixing three chips of different thicknesses.

[0045] It should be noted that the specified value is set according to actual needs and is not limited in this embodiment.

[0046] Optionally, in a possible implementation, the interface heat dissipation material preform may be made of any one of the following materials: indium, tin, silver, indium alloy, tin alloy, silver alloy, graphite, graphene, and composite materials.

[0047] Furthermore, in another possible implementation, the interface heat dissipation material preform is a preform having an external polymer coating or an external flux coating.

[0048] Specifically, the external polymer coating and the external flux coating can provide additional mechanical strength and wear resistance for the interface heat dissipation material preform, protect it from chemical corrosion, ensure the heat dissipation performance of the interface heat dissipation material preform, and promote welding to make the welding stronger.

[0049] Optionally, in a possible implementation, the thickness difference between any two chip fixing regions with different thicknesses is between 20 μm and 700 μm.

[0050] or,

[0051] The thickness difference between any two chip fixing regions with different thicknesses is less than or equal to 80% B; wherein B is the thickness value of the chip fixing region with the largest thickness among the plurality of chip fixing regions.

[0052] For details, see the above description, for example, Figure 1In the example shown, the thickness of the first chip-mounting region is 200μm, the thickness of the second chip-mounting region is 130μm, and the thickness of the third chip-mounting region is 170μm. Of these three chip-mounting regions 121, the first chip-mounting region 121 is the thickest, with a thickness of 200μm. That is, B is equal to 200μm. In this case, 80% of B is equal to 160μm. Furthermore, the thickness difference between the first and second chip-mounting regions is 70μm, the thickness difference between the first and third chip-mounting regions is 30μm, and the thickness difference between the second and third chip-mounting regions is 40μm. In other words, among these three chip-mounting regions 121, the thickness difference between any two chip-mounting regions 121 with different thicknesses ranges from 20μm to 700μm; alternatively, the thickness difference between any two chip-mounting regions 121 with different thicknesses is less than or equal to 80% of B (160μm).

[0053] Two specific embodiments are given below to illustrate in detail the interface heat dissipation material preform provided by the present application.

[0054] Figure 3 This is a schematic diagram of the second embodiment of the interface heat dissipation material preform provided in this application. Figure 4 for Figure 3 Schematic diagram of a multi-chip package structure in which an interface heat dissipation material preform is located.

[0055] Please refer to Figure 4 ,exist Figure 4 In the example shown, the multi-chip package structure includes three chips. For the convenience of explanation, the three chips are respectively marked as the first chip, the second chip and the third chip in order from left to right. Figure 3 and Figure 4 The interface heat dissipation material preform provided in this embodiment includes three chip fixing areas 121. For the convenience of distinction, the three chip fixing areas 121 are respectively recorded as a first chip fixing area, a second chip fixing area and a third chip fixing area.

[0056] Furthermore, the total thickness of the first chip and the first chip fixing area is equal to a specified value, the first chip and the first chip fixing area match, and the first chip fixing area is used to fix the first chip; similarly, the total thickness of the second chip and the second chip fixing area is equal to the specified value, the second chip and the second chip fixing area match, and the second chip fixing area is used to fix the second chip; similarly, the total thickness of the third chip and the third chip fixing area is equal to the specified value, the third chip and the third chip fixing area match, and the third chip fixing area is used to fix the third chip.

[0057] Please continue to refer to Figure 3 and Figure 4 In this embodiment, the first chip and the third chip have the same thickness, and the second chip has a thickness greater than that of the first chip. Furthermore, the first chip fixing region and the third chip fixing region have the same thickness, and the second chip fixing region has a thickness less than that of the first chip fixing region.

[0058] In other words, the interface heat dissipation material preform includes two chip fixing areas 121 with different thicknesses, and can simultaneously fix two types of chips with different thicknesses.

[0059] Further, Figure 5 Schematic diagram of the third embodiment of the interface heat dissipation material preform provided in this application ( Figure 5 Shown is a bottom view of the interface heat dissipation material preform). Figure 6 for Figure 5 The partial schematic diagram of the multi-chip package structure where the interface heat dissipation material preform is located is shown. Please also refer to Figure 5 and Figure 6 ,exist Figure 6 In the example shown, the multi-chip packaging structure includes four chips, namely chip A, chip B, chip C and chip D; further, the thickness of chip A and chip D is the same, and the thickness of chip A, chip B and chip C are different, that is, the multi-chip packaging structure includes chips of three different thicknesses.

[0060] For further information, please refer to Figure 5 The interface heat dissipation material preform provided in this embodiment includes four chip fixing areas 121, which are: chip fixing area A, chip fixing area B, chip fixing area C and chip fixing area D; among them, the chip fixing area A and the chip fixing area D have the same thickness, and the chip fixing area A, chip fixing area B and chip fixing area C have different thicknesses.

[0061] Furthermore, the total thickness of chip A and chip fixing area A is equal to the specified value, chip A and chip fixing area A match, and chip fixing area A is used to fix chip A; similarly, the total thickness of chip B and chip fixing area B is equal to the specified value, chip B and chip fixing area B match, and chip fixing area B is used to fix chip B; similarly, the total thickness of chip C and chip fixing area C is equal to the specified value, chip C and chip fixing area C match, and chip fixing area C is used to fix chip C; similarly, the total thickness of chip D and chip fixing area D is equal to the specified value, chip D and chip fixing area D match, and chip fixing area D is used to fix chip D.

[0062] With reference to the foregoing description, it can be understood that the interface heat dissipation material preform includes four chip fixing areas 121 , which can simultaneously fix three types of chips of different thicknesses.

[0063] The interface heat dissipation material preform provided in this embodiment forms multiple chip fixing areas on the second surface, and the thickness of at least two chip fixing areas among the multiple chip fixing areas are different. In this way, the interface heat dissipation material preform can simultaneously support at least two chips of different thicknesses and can adapt to different chip requirements to simplify the packaging process, reduce assembly time, improve production flexibility, and improve production efficiency. In addition, the standardized design of the interface heat dissipation material preform helps to ensure the consistency and repeatability of each multi-chip package, which can reduce variability in the production process.

[0064] Specifically, Figure 7 For the schematic diagram of the fourth embodiment of the interface heat dissipation material preform provided in this application, please refer to Figure 7 Based on the above embodiment, the interface heat dissipation material preform provided in this embodiment has a dividing portion 122 at the junction of two adjacent chip fixing areas. The dividing portion 122 divides the two adjacent chip fixing areas 121, so that during the reflow soldering process, the melting starting point of the interface heat dissipation material preform is controlled by the dividing portion 122, and the melted interface heat dissipation material is divided by the dividing portion 122; wherein, the dividing portion 122 includes at least one of the following forms of dividing portions: a groove, a sink, a through-hole array, and a blind hole array.

[0065] Specifically, a dividing portion 122 is formed at the junction of two adjacent chip mounting areas 121. The dividing portion 122 includes at least one of the following types of dividing portions: a groove, a sunken groove, a through-hole array, or a blind-hole array. Thus, during the reflow process, in addition to forming a melting starting point around the exterior of the interface heat dissipation material preform, the groove, sunken groove, through-hole, or blind-hole structures can effectively guide the distribution of heat within the interface heat dissipation material preform, thereby forming a melting starting point at the dividing portion 122. This allows the interface heat dissipation material preform to melt simultaneously from both the exterior and interior, accelerating the melting rate of the interface heat dissipation material preform.

[0066] Furthermore, the dividing portion 122 can also divide the adjacent chip fixing areas 121, thereby dividing the melted interface heat dissipation material to ensure its reasonable distribution during the reflow process and prevent the melted interface heat dissipation material from flowing into the chip.

[0067] Optional, Figure 8 A schematic diagram of an interface heat dissipation material preform is provided for the present application as an exemplary embodiment. Figure 8 Figures A to E in the figure show different forms of segmentation. Figure 8 , understandably, Figure 8The interface heat dissipation material preform shown includes three chip fixing areas 121. For the sake of convenience, the three chip fixing areas 121 are respectively recorded as a first chip fixing area, a second chip fixing area and a third chip fixing area in order from left to right, wherein the first chip fixing area and the second chip fixing area are two adjacent chip fixing areas, and the second chip fixing area and the third chip fixing area are two adjacent chip fixing areas.

[0068] Taking the first chip fixing area and the second chip fixing area as an example, the boundary between the two adjacent chip fixing areas may include the first boundary where the first chip fixing area is close to the second chip fixing area, and / or the second boundary where the second chip fixing area is close to the first chip fixing area. Therefore, the dividing portion 122 may be set at the first boundary and / or the second boundary. For example, Figure 8 In FIG. A of FIG. 1 , for the first chip mounting region and the second chip mounting region, the dividing portion 122 is provided at the first boundary of the first chip mounting region. Figure 8 In FIG. B, for the first chip fixing region and the second chip fixing region, the dividing portion 122 is provided at the second boundary of the second chip fixing region. Figure 8 In FIG. C, for the first chip mounting region and the second chip mounting region, the dividing portion 122 is provided at both a first boundary on the first chip mounting region and a second boundary on the second chip mounting region.

[0069] It should be noted that the dividing portion 122 includes at least one of the following types of dividing portions: a groove, a sink, a through hole array, and a blind hole array.

[0070] For example, in Figure 8 In FIG. A, FIG. B and FIG. E, each segmentation portion 122 includes a segmentation portion of a certain type. Further, for example, in Figure 8 In Figures C and D of , each segmentation contains multiple types of segmentations. For example, Figure 8 In FIG. C, two types of dividing parts 122 are provided at the junction of the first chip fixing area and the second chip fixing area, and at the junction of the second chip fixing area and the third chip fixing area. Figure 8 In Figure D, two types of dividing parts 122 are provided at the junction of the first chip fixing area and the second chip fixing area, namely a through-hole array and a groove; three types of dividing parts 122 are provided at the junction of the second chip fixing area and the third chip fixing area, namely a through-hole array, a groove and a sink.

[0071] For further information, please refer to Figure 8In Figures D and E, optionally, in one possible implementation, the length direction of the dividing portion 122 is parallel to the boundary line of the two adjacent chip fixing areas 121, or the angle between the length direction of the dividing portion 122 and the boundary line of the two adjacent chip fixing areas 121 is less than 90°.

[0072] As described above, it can be understood that the dividing portion 1 at the junction of two adjacent chip mounting areas 121 can be any one of a groove, a sunken groove, a through-hole array, or a blind-hole array, or a combination of any two or more of these. This is not limited in this embodiment. For example, in one embodiment, the dividing portion 122 is in the form of a groove; in another embodiment, the dividing portion 122 is in the form of a combination of a groove, a through-hole array, and a blind-hole array.

[0073] It should be noted that when the dividing portion 122 is in the form of a through hole array or a blind hole array, the number of through holes or blind holes is set according to actual needs and is not limited in this embodiment.

[0074] Optionally, in a possible implementation, when the dividing portion 122 is a groove or a through-hole array, the groove is arranged along the direction of arrangement of the two adjacent chip fixing regions 121 ( Figure 8 The width in the left-right direction (as shown) or the diameter of each through hole in the through hole array is greater than or equal to 20 μm and less than or equal to the distance between the two adjacent chip fixing areas 121 .

[0075] It should be noted that the spacing between two adjacent chip fixing regions 121 refers to the distance between the positions where the two chip fixing regions 121 actually fix the chips (the positions covered by the chips) in the above arrangement direction.

[0076] In other words, when the dividing portion 122 is in the form of a groove, the width of the groove along the arrangement direction of the two adjacent chip fixing areas 121 is within the range of 20 μm and the spacing between the two adjacent chip fixing areas 121, that is, the width of the groove is at least 20 μm and at most the spacing between the two adjacent chip fixing areas 121; similarly, when the dividing portion 122 is in the form of a through-hole array, the diameter of each through-hole in the through-hole array is within the range of 20 μm and the spacing between the two adjacent chip fixing areas 121, that is, the diameter of the through-hole is at least 20 μm and at most the spacing between the two adjacent chip fixing areas 121.

[0077] Optionally, in another possible implementation, when the dividing portion 122 is a groove or a blind hole array, the width of the groove along the arrangement direction of the two adjacent chip fixing areas 121 or the diameter of each blind hole in the blind hole array is greater than or equal to 10 μm and less than or equal to 2 times the spacing between the two adjacent chip fixing areas 121.

[0078] Furthermore, when the dividing portion 122 is in the form of a groove, the width of the groove along the arrangement direction of the adjacent chip fixing areas 121 is within the range of 10 μm and twice the spacing between the two adjacent chip fixing areas 121, that is, the width of the groove is at least 10 μm and at most twice the spacing between the two adjacent chip fixing areas 121; similarly, when the dividing portion 122 is in the form of a blind hole array, the diameter of each blind hole in the blind hole array is within the range of 10 μm and twice the spacing between the two adjacent chip fixing areas 121, that is, the width of the groove is at least 10 μm and at most twice the spacing between the two adjacent chip fixing areas 121.

[0079] Optionally, in another possible implementation, when the dividing portion 122 is a groove or a blind hole array, the depth of the groove or the depth of each blind hole in the blind hole array is between 5%A and 95%A; wherein A is the thickness value of the interface heat dissipation material preform at the location of the groove or the blind hole array.

[0080] Preferably, in one embodiment, the depth of the sink or the depth of each blind hole in the blind hole array is between 30%A and 60%A.

[0081] Furthermore, when the dividing portion 122 is in the form of a sunken groove or blind hole array, the depth of the blind holes in the sunken groove or blind hole array is within 5% to 95% of the thickness of the interface heat dissipation material preform at the location of the sunken groove or blind hole array. That is, the minimum depth of the blind holes in the sunken groove or blind hole array is 5% of the thickness at the location of the sunken groove or blind hole array, and the maximum depth of the blind holes in the sunken groove or blind hole array is 95% of the thickness at the location of the sunken groove or blind hole array. The depth of the blind holes in the sunken groove or blind hole array is preferably 30% to 60% of the thickness at the location of the sunken groove or blind hole array.

[0082] The interface heat dissipation material preform provided in this embodiment has a dividing portion disposed at the junction of two adjacent chip fixing regions, and the dividing portion divides the two adjacent chip fixing regions. Thus, firstly, during the reflow process, in addition to forming a melting starting point around the exterior of the interface heat dissipation material preform, a melting starting point can also be formed at the location of the dividing portion, thereby simultaneously melting the interface heat dissipation material preform from both the exterior and interior, accelerating the melting speed of the interface heat dissipation material preform. Secondly, the dividing portion can also divide the melted interface heat dissipation material, ensuring its proper distribution during the reflow process and preventing the melted interface heat dissipation material from flowing into the chip.

[0083] Figure 9 For the schematic diagram of the fifth embodiment of the interface heat dissipation material preform provided in this application, please refer to Figure 9 Based on the above embodiment, the interface heat dissipation material preform provided in this embodiment has a melting starting point control part 123 inside each chip fixing area 121, so that the melting starting point can be controlled by the melting starting point control part 123 during the reflow process; wherein, the melting starting point control part 123 includes at least one of the following forms of control parts: a sink or a blind hole.

[0084] For further information, please refer to Figure 9 Each chip-mounting region has a melting starting point control portion 123 within it. During the reflow process, the melting starting point control portion 123, in the form of a sink or blind via, can control the melting starting point within the chip-mounting region 121. This allows the chip-mounting region 121 to simultaneously begin melting from the outside, from the partition 122 between two adjacent chip-mounting regions 121, and from the melting starting point control portion 123 within each chip-mounting region 121 during the reflow process, accelerating the melting of the interface heat dissipation material preform.

[0085] Furthermore, the melting starting point control portion 123 can be in the form of a sink or a blind hole. The form of the melting starting point control portion 123 within each chip fixing region can be the same or different. Furthermore, the size, depth, number, and form of the melting starting point control portion 123 within each chip fixing region are determined based on actual needs and are not limited in this embodiment. For example, in one embodiment, a chip fixing region has two melting starting point control portions, one of which is in the form of a sink and the other is in the form of a blind hole.

[0086] The interface heat dissipation material preform provided in this embodiment is provided with a melting starting point control portion inside each chip fixing area in the interface heat dissipation material preform. In this way, the melting starting point can be controlled by the melting starting point control portion during the reflow process, so that the interface heat dissipation material preform can start to melt simultaneously from the outside, the dividing portion between two adjacent chip fixing areas, and the melting starting point control portion inside each chip fixing area, thereby accelerating the melting speed of the interface heat dissipation material preform.

[0087] Corresponding to the aforementioned embodiment of an interface heat dissipation material preform, the present application also provides a method for preparing an interface heat dissipation material preform. Figure 10 This is a flow chart of Example 1 of the method for preparing the interface heat dissipation material preform provided in this application. Figure 10 The method for preparing the interface heat dissipation material preform provided in this embodiment is used to prepare any interface heat dissipation material preform provided in the first aspect of this application; the preparation method comprises:

[0088] S101, preparing an initial piece of interface heat dissipation material; wherein, the initial piece of interface heat dissipation material has a first surface and a second surface disposed back to back.

[0089] S102. Form a plurality of chip fixing regions on the second surface; wherein at least two of the plurality of chip fixing regions have different thicknesses, and a total thickness of each chip fixing region and a chip to be fixed thereto is equal to a specified value.

[0090] In a specific implementation, for example, in a possible implementation, a plurality of chip fixing areas may be formed on the second surface by mechanical processing.

[0091] Optionally, in a possible implementation, the second surface may be embossed using a micro-embossing mold; wherein the micro-embossing mold has a pattern matching the multiple chip fixing regions, so as to form multiple chip fixing regions on the second surface.

[0092] Optionally, in a possible implementation, the step of imprinting the second surface using a micro-imprinting mold includes:

[0093] During the stamping process, the initial interface heat dissipation material is heated to soften the initial interface heat dissipation material; wherein the heating temperature is less than or equal to 85%°C; and C is the melting temperature of the initial interface heat dissipation material.

[0094] Optionally, in a possible implementation, heating the initial piece of interface heat dissipation material during the stamping process includes:

[0095] During the heating process, an inert gas is used to form a protective environment to prevent the initial part of the interface heat dissipation material from being oxidized.

[0096] Specifically, Figure 11 This is a schematic diagram showing the principle of preparing a preform of an interface heat dissipation material according to an exemplary embodiment of the present application. Figure 11 , the second surface may be embossed using a micro-embossing mold; wherein the micro-embossing mold has a pattern matching the multiple chip fixing areas to form multiple chip fixing areas on the second surface.

[0097] See also Figure 11 The micro-imprinting mold includes an upper mold and a lower mold. The lower mold has a pattern that matches multiple chip fixing areas. During imprinting, the upper mold contacts the first surface of the interface heat dissipation material initial piece, and the lower mold contacts the second surface. In this way, multiple chip fixing areas that meet the requirements can be imprinted on the second surface. In addition, referring to the previous description, when imprinting the second surface, the interface heat dissipation material initial piece can be heated in an inert gas environment to soften the interface heat dissipation material initial piece and prevent it from oxidizing. Furthermore, the temperature for heating the interface heat dissipation material initial piece needs to be less than or equal to 85% of the melting temperature of the interface heat dissipation material initial piece, that is, the maximum heating temperature is 85% of the melting temperature of the interface heat dissipation material initial piece.

[0098] Optionally, the micro-embossing mold may be a linear pressing mold or a roller mold, which is not limited in this embodiment.

[0099] The method provided in this embodiment provides a method for preparing an interface heat dissipation material preform. Through this method, interface heat dissipation material preforms with different thicknesses can be prepared, so that multiple chips of different thicknesses can be simultaneously packaged through a piece of interface heat dissipation material preform, thereby improving the efficiency of chip packaging and shortening the chip packaging cycle.

[0100] Optionally, after forming a plurality of chip fixing areas on the second surface, the preparation method further includes:

[0101] A dividing portion is formed at the junction of two adjacent chip fixing areas; wherein the dividing portion divides the two adjacent chip fixing areas, so that in the reflow soldering process, the melting starting point of the interface heat dissipation material preform is controlled by the dividing portion, and the melted interface heat dissipation material is divided by the dividing portion; the dividing portion includes at least one of the following forms of dividing portions: a groove, a sink, a through-hole array, and a blind hole array.

[0102] The preparation method of the interface heat dissipation material preform provided in this embodiment forms a dividing portion at the junction of two adjacent chip fixing areas. During the reflow soldering process, the melting starting point of the interface heat dissipation material preform can be controlled by the dividing portion, so that the interface heat dissipation material preform can be melted simultaneously from the outside of the interface heat dissipation material preform and the junction of two adjacent chip fixing areas to accelerate the melting speed of the interface heat dissipation material preform; further, the dividing portion can also divide the melted interface heat dissipation material to ensure its reasonable distribution during the reflow soldering process and prevent the melted interface heat dissipation material from flowing into the chip.

[0103] Optionally, after forming a plurality of chip fixing areas on the second surface, the preparation method further includes:

[0104] A melting starting point control portion is formed inside each chip fixing area to control the melting starting point during the reflow process; wherein the melting starting point control portion includes at least one of the following forms of control portions: a sink or a blind hole.

[0105] In a specific implementation, the dividing portion or the melting starting point control portion is formed by a micro-embossing mold or a cutting mold.

[0106] Please continue to refer to Figure 1 and Figure 3 The present application also provides a multi-chip packaging structure, which includes a substrate, a plurality of chips, an interface heat dissipation material preform as provided in the first aspect of the present application, and a heat dissipation cover; wherein,

[0107] The plurality of chips are fixed on the substrate; the plurality of chips include at least two chips with different thicknesses;

[0108] The interface heat dissipation material preform has a plurality of chip fixing regions matching the plurality of chips, and the interface heat dissipation material preform is fixed to the plurality of chips in a manner such that each chip fixing region is directly opposite to the chip it matches; wherein the total thickness of each chip fixing region and the chip it matches is equal to a specified value;

[0109] The heat dissipation cover is fixed on the first surface of the interface heat dissipation material preform in a manner of covering the plurality of chips, and a surrounding portion of the heat dissipation cover protruding downward is in contact with the base.

[0110] The multi-chip packaging structure provided in this embodiment can package multiple chips with different thicknesses at the same time according to different design requirements, reducing the chip packaging picking and placement process, thereby improving packaging efficiency and shortening the production cycle.

[0111] The present application also provides a use of the interface heat dissipation material preform provided in the first aspect of the present application, wherein the interface heat dissipation material preform is used in the field of multi-chip packaging.

[0112] The above description is only a preferred embodiment of the present application and is not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principles of the present application shall be included in the scope of protection of the present application.

Claims

1. An interface heat dissipation material preform, characterized in that: The interface heat dissipation material preform is used for a multi-chip packaging structure, wherein the multi-chip packaging structure includes a plurality of chips, and the plurality of chips include at least two chips of different thicknesses; the interface heat dissipation material preform has a first surface and a second surface that are arranged in back-to-back relationship; wherein, The first surface is a plane and is used for bonding the heat dissipation cover in the multi-chip packaging structure; A plurality of chip fixing regions matching the plurality of chips are formed on the second surface, each chip fixing region being used to fix a chip matching the chip fixing region; a total thickness of each chip fixing region and the chip to be fixed thereto is equal to a specified value, and at least two of the plurality of chip fixing regions have different thicknesses, so that the at least two chips of different thicknesses can be simultaneously fixed by the interface heat dissipation material preform; The junction of two adjacent chip fixing areas has a dividing portion, and the dividing portion divides the two adjacent chip fixing areas, so that during the reflow process, the melting starting point of the interface heat dissipation material preform is controlled by the dividing portion, and the melted interface heat dissipation material is divided by the dividing portion; wherein the dividing portion includes at least one of the following types of dividing portions: a groove, a through hole array, and a blind hole array; Each chip fixing area has a melting starting point control portion inside, so as to control the melting starting point during the reflow process; wherein the melting starting point control portion includes at least one of the following control portions: a sink or a blind hole; When the dividing portion is a groove or a through-hole array, the width of the groove along the arrangement direction of the two adjacent chip fixing regions or the diameter of each through-hole in the through-hole array is greater than or equal to 20 μm and less than or equal to the distance between the two adjacent chip fixing regions; When the dividing portion is a blind hole array, the diameter of each blind hole in the blind hole array is greater than or equal to 10 μm and less than or equal to twice the distance between two adjacent chip fixing regions.

2. The interface heat dissipation material preform according to claim 1, characterized in that: When the dividing portion is a blind hole array, the depth of each blind hole in the blind hole array is 5%A to 95%A; wherein A is the thickness value of the interface heat dissipation material preform at the location of the blind hole array.

3. The interface heat dissipation material preform according to claim 1, characterized in that: The depth of each blind hole in the blind hole array is between 30%A and 60%A; wherein A is the thickness value of the interface heat dissipation material preform at the location of the blind hole array.

4. The interface heat dissipation material preform according to claim 1, characterized in that: The length direction of the dividing portion is parallel to a boundary line of the two adjacent chip fixing regions, or an angle between the length direction of the dividing portion and a boundary line of the two adjacent chip fixing regions is less than 90°.

5. The interface heat dissipation material preform according to claim 1, characterized in that: The interface heat dissipation material preform is made of any one of the following materials: indium, tin, silver, indium alloy, tin alloy, silver alloy, graphite, graphene and composite material.

6. The interface heat dissipation material preform according to claim 1, characterized in that: The interface heat dissipation material preform is a preform with an external polymer coating or an external flux coating.

7. The interface heat dissipation material preform according to claim 1, characterized in that: The thickness difference between any two chip fixing areas with different thicknesses is between 20 μm and 700 μm; or, The thickness difference between any two chip fixing regions with different thicknesses is less than or equal to 80% B; wherein B is the thickness value of the chip fixing region with the largest thickness among the plurality of chip fixing regions.

8. A method for preparing a preform of an interface heat dissipation material, characterized in that: The preparation method is used to prepare the interface heat dissipation material preform according to any one of claims 1 to 7; the preparation method comprises: Prepare an initial piece of interface heat dissipation material; wherein the initial piece of interface heat dissipation material has a first surface and a second surface disposed back to back; forming a plurality of chip fixing regions on the second surface; wherein at least two of the plurality of chip fixing regions have different thicknesses, and a total thickness of each chip fixing region and a chip to be fixed thereto is equal to a specified value; After forming a plurality of chip fixing areas on the second surface, the preparation method further includes: A dividing portion is formed at the junction of two adjacent chip fixing areas; wherein the dividing portion divides the two adjacent chip fixing areas so that during the reflow process, the dividing portion controls the melting starting point of the interface heat dissipation material preform and divides the melted interface heat dissipation material; the dividing portion includes at least one of the following types of dividing portions: a groove, a through-hole array, and a blind hole array; A melting starting point control portion is formed inside each chip fixing area so as to control the melting starting point during the reflow process; wherein the melting starting point control portion includes at least one of the following control portions: a sink or a blind hole; When the dividing portion is a groove or a through-hole array, the width of the groove along the arrangement direction of the two adjacent chip fixing regions or the diameter of each through-hole in the through-hole array is greater than or equal to 20 μm and less than or equal to the distance between the two adjacent chip fixing regions; When the dividing portion is a blind hole array, the diameter of each blind hole in the blind hole array is greater than or equal to 10 μm and less than or equal to twice the distance between two adjacent chip fixing regions.

9. The preparation method according to claim 8, characterized in that The forming of a plurality of chip fixing areas on the second surface comprises: The second surface is imprinted using a micro-imprinting mold, wherein the micro-imprinting mold has a pattern matching the plurality of chip-fixing regions, so as to form a plurality of chip-fixing regions on the second surface.

10. The preparation method according to claim 9, characterized in that The method of imprinting the second surface with a micro-imprinting mold comprises: During the stamping process, the initial interface heat dissipation material is heated to soften the initial interface heat dissipation material; wherein the heating temperature is less than or equal to 85%°C; and C is the melting temperature of the initial interface heat dissipation material.

11. The preparation method according to claim 10, characterized in that: The step of heating the initial piece of the interface heat dissipation material during the stamping process includes: During the heating process, an inert gas is used to form a protective environment to prevent the initial part of the interface heat dissipation material from being oxidized.

12. The preparation method according to claim 8, characterized in that The dividing portion or the melting starting point control portion is formed by a micro-embossing mold or a cutting mold.

13. A multi-chip packaging structure, characterized in that: The multi-chip packaging structure comprises a substrate, a plurality of chips, an interface heat dissipation material preform according to any one of claims 1 to 7, and a heat dissipation cover; wherein, The plurality of chips are fixed on the substrate; the plurality of chips include at least two chips with different thicknesses; The interface heat dissipation material preform has a plurality of chip fixing regions matching the plurality of chips, and the interface heat dissipation material preform is fixed to the plurality of chips in a manner such that each chip fixing region is directly opposite to the chip it matches; wherein the total thickness of each chip fixing region and the chip it matches is equal to a specified value; The heat dissipation cover is fixed on the first surface of the interface heat dissipation material preform in a manner of covering the plurality of chips, and a surrounding portion of the heat dissipation cover protruding downward is in contact with the base.

14. Use of the interface heat dissipation material preform according to any one of claims 1 to 7, characterized in that: The interface heat dissipation material preform is used in the field of multi-chip packaging.

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