Driving circuit and vertical cavity surface emitting laser system

Abstract

The present invention provides a drive circuit, wherein the output end of a bias current control subcircuit is connected to the output end of an output drive subcircuit and a driven element; the output drive subcircuit includes a differential pair module circuit, wherein the source of a PMOS transistor is connected to a power supply, and the drain is connected to load resistors RL1 and RL2, forming a junction; the end of load resistor RL2 closest to the driven element serves as the output end of the output drive subcircuit and is connected to one end of load resistor Rf; the end of load resistor Rf remote from load resistor RL2 is connected to the first input end of a first operational amplifier; the end of load resistor RL1 closest to the PMOS transistor is connected to one end of load resistor Rref; the end of load resistor Rref remote from load resistor RL1 is connected to the second input end of the first operational amplifier and to a first current source; the output end of the first operational amplifier is connected to the gate of the PMOS transistor. The present invention provides an optimized drive circuit capable of achieving higher-speed optical communication applications.

Description

Technical Field

[0001] The present invention relates to the field of circuit technology, and in particular to a driving circuit and a vertical cavity surface emitting laser system. Background Art

[0002] In modern optical communication systems, vertical-cavity surface-emitting laser (VCSEL) drivers are widely used due to their excellent performance, including low power consumption, high bandwidth, small size, low cost, and easy integration. Due to cost and component structure constraints, VCSEL drivers typically use DC-coupled common-cathode VCSEL lasers. VCSEL optical power requirements vary in different application environments, resulting in significant variations in driver bias current requirements. In high-speed communications, limited by the driver's operating voltage and power consumption, a bias current of 4-8 mA is typically used. Higher operating currents mean higher VCSEL operating voltages, which reduces the power supply voltage margin and necessitates bias circuit design. Existing solutions include increasing the driver voltage to ensure voltage margin and circuit performance. However, this introduces a new power supply, increases circuit complexity, and increases power consumption. This results in high impedance seen from the output node, mismatching the VCSEL, and signal reflections, which can degrade signal quality in high-speed applications. Furthermore, the current source needs to carry a large current, resulting in large transistor sizes and significant parasitic capacitance, which compromises high-frequency performance. Currently, there is no simple and effective solution to these shortcomings. Summary of the Invention

[0003] The purpose of the present invention is to provide a drive circuit and a vertical cavity surface emitting laser system, which realize higher-speed optical communication applications through the optimized design of the bias current control subcircuit, the modulation current control subcircuit and the output drive subcircuit.

[0004] To achieve the above-mentioned objectives, the present invention provides a driving circuit, comprising a bias current control subcircuit and an output driving subcircuit; the bias current control subcircuit input end is connected to a power supply, and the bias current control subcircuit output end is connected to the output end of the output driving subcircuit and the driven element; the output driving subcircuit comprises a differential pair module circuit, the differential pair module circuit comprises a load resistor RL1 and a load resistor RL2, a PMOS transistor is provided between the power supply of the differential pair module circuit and the load resistors RL1 and RL2, the source of the PMOS transistor is connected to the power supply of the differential pair module circuit, and the drain of the PMOS transistor is connected to the load resistors RL1 and RL2. and form an intersection; the end of the load resistor RL2 close to the driven element is the output end of the output drive sub-circuit, the end of the load resistor RL2 close to the driven element is also connected to one end of a load resistor Rf, and the end of the load resistor Rf away from the load resistor RL2 is connected to the first input end of the first operational amplifier; the end of the load resistor RL1 close to the PMOS transistor is also connected to one end of a load resistor Rref, the end of the load resistor Rref away from the load resistor RL1 is connected to the second input end of the first operational amplifier, and the end of the load resistor Rref away from the load resistor RL1 is connected to the first current source; the output end of the first operational amplifier is connected to the gate of the PMOS transistor.

[0005] Optionally, the bias current control subcircuit includes a current mirror module circuit.

[0006] Optionally, the current mirror module circuit includes a cascade structure circuit.

[0007] Optionally, the differential pair module circuit also includes a second current source, a transistor Q1, and a transistor Q2; one end of the second current source is grounded, and the end of the second current source away from the ground direction is connected to the emitter of the transistor Q1, and the end of the second current source away from the ground direction is connected to the emitter of the transistor Q2; the collector of the transistor Q1 is connected to the end of the load resistor RL1 away from the PMOS transistor, and the collector of the transistor Q2 is connected to the end of the load resistor RL2 away from the PMOS transistor.

[0008] Optionally, a transistor Q3 is provided between the transistor Q1 and the load resistor RL1, and a transistor Q4 is provided between the transistor Q2 and the load resistor RL2; the collector of the transistor Q3 is connected to the end of the load resistor RL1 away from the PMOS transistor, and the emitter of the transistor Q3 is connected to the collector of the transistor Q1; the collector of the transistor Q4 is connected to the end of the load resistor RL2 away from the PMOS transistor, and the emitter of the transistor Q4 is connected to the collector of the transistor Q2.

[0009] Optionally, it also includes a transistor Q5, a transistor Q6 and a third current source; one end of the third current source is grounded, and the end of the third current source away from the ground direction is connected to the emitter of the transistor Q5, and the end of the third current source away from the ground direction is connected to the emitter of the transistor Q6; the collector of the transistor Q5 is connected to the end of the load resistor RL1 away from the PMOS transistor and is connected to the collector of the transistor Q1; the collector of the transistor Q6 is connected to the end of the load resistor RL2 away from the PMOS transistor and is connected to the collector of the transistor Q2.

[0010] Optionally, the first current source includes a second operational amplifier, a transistor QB1 and an emitter resistor RE2, and the second current source includes a third operational amplifier, a transistor QB2 and an emitter resistor RE3; one end of the emitter resistor RE2 is grounded, and the end of the emitter resistor RE2 away from the ground direction is connected to the emitter of the transistor QB1 and the reverse input terminal of the second operational amplifier; one end of the emitter resistor RE3 is grounded, and the end of the emitter resistor RE3 away from the ground direction is connected to the emitter of the transistor QB2 and the reverse input terminal of the third operational amplifier; the collector of the transistor QB1 is connected to the end of the load resistor Rref away from the load resistor RL1, and the base of the transistor QB1 is connected to the output terminal of the second operational amplifier; the collector of the transistor QB2 is connected to the emitter of the transistor Q1 and to the emitter of the transistor Q2, and the base of the transistor QB2 is connected to the output terminal of the third operational amplifier; the positive input terminals of the second operational amplifier and the third operational amplifier are connected to the first temperature-compensated current source.

[0011] Optionally, it further includes a transistor Q5, a transistor Q6 and a third current source; one end of the third current source is grounded, and the end of the third current source away from the ground direction is connected to the emitter of the transistor Q5, and the end of the third current source away from the ground direction is connected to the emitter of the transistor Q5; the collector of the transistor Q5 is connected to the end of the load resistor RL1 away from the PMOS transistor and to the collector of the transistor Q1; the collector of the transistor Q6 is connected to the end of the load resistor RL2 away from the PMOS transistor and to the collector of the transistor Q2; the third current source includes a fourth operational amplifier, a transistor QB3 and an emitter resistor RE4; the first current source also includes a fifth operational amplifier, a transistor QB4 and an emitter resistor RE5; one end of the emitter resistor RE4 The end of the emitter resistor RE4 is grounded, and the end away from the ground is connected to the emitter of the transistor QB2 and the inverting input terminal of the fourth operational amplifier; one end of the emitter resistor RE5 is grounded, and the end away from the ground is connected to the emitter of the transistor QB4 and the inverting input terminal of the fifth operational amplifier; the collector of the transistor QB3 is connected to the emitter of the transistor Q5 and the emitter of the transistor Q6, and the base of the transistor QB3 is connected to the output terminal of the fourth operational amplifier; the collector of the transistor QB4 is connected to the end of the load resistor Rref away from the load resistor RL1, and the base of the transistor QB4 is connected to the output terminal of the fifth operational amplifier; the positive input terminals of the fourth operational amplifier and the fifth operational amplifier are connected to a second temperature-compensated current source.

[0012] Optionally, several inductors are also included, and the inductors are used to weaken the parasitic capacitance in the circuit.

[0013] The present invention further provides a vertical cavity surface emitting laser system, comprising any one of the driving circuits described above, wherein the driven element is a vertical cavity surface emitting laser.

[0014] The vertical cavity surface emitting laser system provided by the present invention has the following beneficial effects:

[0015] The present invention provides a driving circuit, comprising a bias current control subcircuit and an output driving subcircuit; the bias current control subcircuit input end is connected to a power supply, the bias current control subcircuit output end is connected to the output end of the output driving subcircuit and the driven element; the output driving subcircuit comprises a differential pair module circuit, the differential pair module circuit comprises a load resistor RL1 and a load resistor RL2, a PMOS transistor is provided between the power supply of the differential pair module circuit and the load resistor RL1 and the load resistor RL2, the source of the PMOS transistor is connected to the power supply of the differential pair module circuit, and the drain of the PMOS transistor is connected to the load resistor RL1 and the load resistor RL2 to form a An intersection point; the end of the load resistor RL2 near the driven element serves as the output end of the output driver subcircuit; the end of the load resistor RL2 near the driven element is also connected to one end of a load resistor Rf; the end of the load resistor Rf away from the load resistor RL2 is connected to the first input end of the first operational amplifier; the end of the load resistor RL1 near the PMOS transistor is also connected to one end of a load resistor Rref; the end of the load resistor Rref away from the load resistor RL1 is connected to the second input end of the first operational amplifier; the end of the load resistor Rref away from the load resistor RL1 is connected to a first current source; the output end of the first operational amplifier is connected to the gate of the PMOS transistor. With this arrangement, the present invention simultaneously uses a resistive load and the bias current control subcircuit to modulate the drive current. This solution has the advantage of effectively achieving output impedance matching through the resistive load, which can reduce the size of the current mirror load tube of the bias current control subcircuit, thereby reducing the driver stage load, which is beneficial to improving the circuit bandwidth and achieving greater gain-bandwidth performance. The modulation current control circuit is implemented using a feedback loop formed by an operational amplifier. This circuit works in conjunction with the output stage to form a current clamp circuit to ensure the stability of the output DC current, so that the modulation current and bias current can be adjusted separately, and it is ensured that the bias current does not flow into the output stage, causing the bias current to be inconsistent with expectations.

[0016] A vertical cavity surface emitting laser system includes a drive circuit as described in any of the above, wherein the driven element is a vertical cavity surface emitting laser. Since the vertical cavity surface emitting laser system includes the drive circuit, the vertical cavity surface emitting laser system simultaneously uses a resistive load and the bias current control subcircuit to modulate the drive current. The advantage of this solution is that the resistive load effectively achieves output impedance matching, which can reduce the size of the current mirror load tube of the bias current control subcircuit, thereby reducing the driver stage load, which is beneficial to improving the circuit bandwidth and achieving greater gain bandwidth performance. The modulation current control circuit is implemented using a feedback loop composed of an op amp. This circuit works in conjunction with the output stage to form a current clamp circuit to ensure the stability of the output DC current, so that the modulation current and bias current can be adjusted separately, and it is ensured that the bias current does not flow into the output stage, causing the bias current to be inconsistent with expectations. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 A schematic diagram of the circuit principle of a vertical cavity surface emitting laser driver provided by an embodiment of the prior art.

[0018] Figure 2 A schematic diagram of the circuit principle of a driving circuit provided by the first embodiment of the present invention.

[0019] Figure 3 This is a schematic diagram of the circuit principle of the bias current control sub-circuit of the driving circuit provided by the first embodiment of the present invention.

[0020] Figure 4 A schematic diagram of the circuit principle of a bias current control sub-circuit of a driving circuit provided by a second embodiment of the present invention.

[0021] Figure 5 This is a schematic diagram of the circuit principle of the output driving sub-circuit of the driving circuit provided by the first embodiment of the present invention.

[0022] Figure 6 This is a schematic diagram of the circuit principle of the output driving sub-circuit of the driving circuit provided by the second embodiment of the present invention.

[0023] Figure 7 This is a schematic circuit diagram of the output drive sub-circuit of the drive circuit provided in the third embodiment of the present invention.

[0024] Figure 8 This is a schematic diagram of the circuit principles of the first current source and the second current source of the driving circuit provided by an embodiment of the present invention.

[0025] Figure 9 This is a schematic diagram of the circuit principles of the first current source, the second current source, and the third current source of the driving circuit provided in one embodiment of the present invention.

[0026] Figure 10 A schematic diagram of the circuit principle of a driving circuit provided in a second embodiment of the present invention.

[0027] The accompanying drawings are denoted as follows:

[0028] 01-bias current control subcircuit; 011-bias current control subcircuit current source;

[0029] 02-output driver subcircuit; 020-intersection point; 021-second current source;

[0030] 03-modulation current control subcircuit; 031-first current source;

[0031] driven element;

[0032] 041-third current source;

[0033] 051-a compensation current source unit with a temperature coefficient in the first temperature-compensated current source; 052-a compensation current source unit without a temperature coefficient in the first temperature-compensated current source;

[0034] 061-compensation current source unit with a temperature coefficient in the second temperature-compensated current source; 062-compensation current source unit without a temperature coefficient in the second temperature-compensated current source;

[0035] 100-Inductor. DETAILED DESCRIPTION

[0036] To make the objects, advantages, and features of the present invention more clearly apparent, the present invention is further described below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the drawings are all in a very simplified form and are not drawn to scale. They are only used to conveniently and clearly assist in illustrating the purposes of the embodiments of the present invention. In addition, the structures shown in the drawings are often part of the actual structure. In particular, different drawings may need to illustrate different focuses and sometimes use different scales.

[0037] It should be understood that when an element or layer is referred to as being "on" or "connected to" another element or layer, it may be directly on or connected to the other element or layer, or may include intervening elements or layers. Conversely, when an element is referred to as being "directly on" or "directly connected to" another element or layer, intervening elements or layers are not included. Although terms such as first, second, and third may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, or part from another. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, or part discussed below may be represented as a second element, component, region, layer, or part. Spatially relative terms such as "under," "below," "below," "above," "above," and the like may be used herein for convenience of description to describe the relationship between an element or feature shown in a figure and other elements or features. It should be understood that, in addition to the orientations shown in the figures, spatial relationship terms are intended to also include different orientations of devices in use and operation. For example, if the device in the drawings is flipped, then, the elements or features described as "under...", "below," or "below" will be oriented to be "on" other elements or features. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial descriptors used herein are interpreted accordingly. The purpose of the terms used herein is only to describe specific embodiments and is not intended to be limiting of the present invention. When used herein, the singular forms "one," "an," and "said / the" are also intended to include plural forms unless the context clearly indicates otherwise. It should also be understood that the term "comprising" is used to determine the inclusion of features, steps, operations, elements, and / or parts, but does not exclude the inclusion or addition of one or more other features, steps, operations, elements, parts, and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0038] Please refer to Figure 1 , Figure 1 A schematic diagram of a circuit principle of a vertical cavity surface emitting laser driver provided in an embodiment of the prior art. In the prior art, the voltage margin and circuit performance are guaranteed by raising the driving stage voltage, but a new power supply is introduced to increase the circuit complexity and power consumption. For example, the solution Figure 1 Using a PMOS transistor current source as a DC bias load results in high impedance seen from the output node, which is mismatched with the VCSEL and can cause signal reflections, degrading signal quality in high-speed applications. Furthermore, the current source needs to flow a large current, which results in a large transistor size and generates large parasitic capacitance, thus affecting high-frequency performance.

[0039] The purpose of the present invention is to provide a drive circuit and a vertical cavity surface emitting laser system, which realize higher-speed optical communication applications through the optimized design of the bias current control subcircuit, the modulation current control subcircuit and the output drive subcircuit.

[0040] Please refer to Figure 2 , Figure 2 Schematic diagram of the circuit principle of the driving circuit provided by the first embodiment of the present invention. Figure 2 As shown, in order to achieve the above-mentioned purpose, the present invention provides a driving circuit, including a bias current control subcircuit 01 and an output driving subcircuit 02;

[0041] The input end of the bias current control sub-circuit 01 is connected to the power supply VCC, and the output end of the bias current control sub-circuit 01 is connected to the output end of the output drive sub-circuit 02 and the driven element 10;

[0042] The output driver sub-circuit 02 includes a differential pair module circuit, which includes a load resistor RL1 and a load resistor RL2. A PMOS transistor MP1 is provided between a power supply of the differential pair module circuit and the load resistors RL1 and RL2. The source of the PMOS transistor MP1 is connected to the power supply of the differential pair module circuit, and the drain of the PMOS transistor MP1 is connected to the load resistors RL1 and RL2 to form a junction 020.

[0043] The end of the load resistor RL2 close to the driven element 10 is the output end of the output driver sub-circuit 02. The end of the load resistor RL2 close to the driven element 10 is also connected to one end of a load resistor Rf. The end of the load resistor Rf away from the load resistor RL2 is connected to the first input end of the first operational amplifier OP1 (in Figure 2 In the embodiment shown, the first input terminal is a reverse input terminal);

[0044] The end of the load resistor RL1 close to the PMOS transistor MP1 is also connected to one end of a load resistor Rref, and the end of the load resistor Rref away from the load resistor RL1 is connected to the second input terminal of the first operational amplifier OP1 (in Figure 2 In the embodiment shown, the second input terminal is a positive input terminal), the end of the load resistor Rref away from the load resistor RL1 is connected to the first current source O31;

[0045] The output terminal of the first operational amplifier OP1 is connected to the gate of the PMOS transistor MP1.

[0046] It should be understood that the driving circuit should also include a capacitor Cf and a capacitor Cvdd. One end of the capacitor Cf is grounded, and the end of the capacitor Cf away from the ground is connected to the first input terminal of the first operational amplifier OP1 (in Figure 2 In the illustrated embodiment, the first input terminal is an inverting input terminal and is connected to an end of the load resistor Rf away from the load resistor RL2. One end of the capacitor Cvdd is grounded, and an end of the capacitor Cvdd away from ground is connected to an end of the load resistor RL2 near the drain of the PMOS transistor MP1, an end of the load resistor RL1 near the drain of the PMOS transistor MP1, the drain of the PMOS transistor MP1, and an end of the load resistor Rref away from the first current source O31.

[0047] With this arrangement, the present invention simultaneously uses a resistive load and the bias current control subcircuit 01 to modulate the drive current. This solution has the advantage of effectively achieving output impedance matching through the resistive load, which can reduce the size of the current mirror load tube of the bias current control subcircuit, thereby reducing the driver stage load, which is beneficial for improving circuit bandwidth and achieving greater gain-bandwidth performance. The modulation current control subcircuit 03, implemented using a feedback loop formed by an op amp, cooperates with the output stage to form a current clamp circuit to ensure stable output DC current, making the modulation current and bias current separately adjustable, and ensuring that the bias current does not flow into the output stage, causing the bias current to be inconsistent with expectations. Specifically, by setting a proportional relationship between the load resistor Rref and the load resistor RL2, the voltages applied to the positive and negative input terminals of the first op amp OP1 can be made consistent, thereby configuring the first op amp OP1 to output the desired target value level. This solution requires low-frequency signals at both ends of the op amp, so a large RC filter is needed to obtain the DC voltage of the output node. The common-mode end of the resistor, serving as the power supply for the driver stage, requires a large capacitor to ensure that this node is an ideal high-frequency signal ground. When the chip power supply voltage is limited, a PMOS transistor is used as a voltage-stabilized power transistor, making this node a high-impedance node. Therefore, attention should be paid to the zero-pole position of the loop to maintain loop stability during design. Furthermore, the first op amp OP1 is used to control the PMOS transistor MP1, ultimately achieving the required target voltage at the intersection point 020. This ensures that the bias current does not flow into the output stage, causing the bias current to differ from the expected value. This reduces the bias circuit requirements and can reduce the size requirements of the PMOS current mirror in the bias circuit by approximately half, equivalently reducing the parasitic capacitance by half. This can effectively expand the bandwidth while maintaining equal current in the two branches of the differential pair module circuit.

[0048] For example, the driven element 10 is a VCSEL, with load resistances RL1 = RL2 = RL, and reference load resistance Rref = RL*K. The DC value vfb of the VCSEL anode voltage VO is obtained through Rf and Cf, where vfb = VO. Assuming the voltage at the intersection 020 is RVDD, the current of the first current source 031 is Imod_ref, the current of the second current source 021 is Imod_tail, and Imod_tail = 2K*Imod_ref, and the current source 011 of the bias current control subcircuit is Ibias. In static operating point analysis, it can be found that the voltage vref applied to the load resistor Rref is vref = RVDD - Rref * Imod_ref, and vfb = RVDD - RL2 * I(RL2). By clamping vref = vfb through the first operational amplifier OP1, I(RL2) = K * imod_ref can be achieved. Because Q2's output equivalent resistance is much larger than the VCSEL's internal resistance, the Ibias current primarily flows into the VCSEL. Consequently, Q2's collector current, IC(Q2), = Ibias + I(RL1) – Ibias(VCSEL) ≈ I(RL2) = K*imod_ref. When the base currents of Q1 and Q2 are much smaller than their collector currents, IC(Q1) ≈ Imod_tail – IC(Q2) = IC(Q2). This ensures current balance in the output stage, ensuring consistent amplification gains for high and low input voltages, thereby maintaining the output eye diagram's rising and falling edge performance. The RVDD voltage is determined by the set operating current: RVDD = VO + V(RL2) = VCC – VDS(MP1). VCC is the power supply voltage. Therefore, sufficient VCC voltage is required to ensure proper operation of MP1 in all operating scenarios. Cvdd should be connected to the aforementioned intersection 020 to ensure that this is an ideal differential-mode signal ground node capable of absorbing high-frequency jitter signals. For a VCSEL with an equivalent internal resistance of Rv, this structure can achieve a VCSEL modulation current amplitude of IMOD = RL / (RL+Rv)*Imod_tail = 2*K*RL / (RL+Rv)*Imod_ref. Therefore, IMOD is independent of the bias current control subcircuit current source 011. Adjusting imod_ref through digital configuration allows IMOD to be adjustable.

[0049] For details, please refer to Figure 3 , Figure 3 This is a schematic diagram of the circuit principle of the bias current control sub-circuit of the driving circuit provided by the first embodiment of the present invention. Figure 3 As shown, the bias current control sub-circuit 01 includes a current mirror module circuit. For further information, please refer to Figure 4 , Figure 4This is a schematic diagram of the circuit principle of the bias current control sub-circuit of the driving circuit provided by the second embodiment of the present invention. Figure 4 As shown, the bias current control subcircuit of the drive circuit provided in the second embodiment differs from the bias current control subcircuit of the drive circuit provided in the first embodiment in that the current mirror module circuit includes a cascade structure circuit. Both the current mirror module circuit and the cascade structure circuit can be configured with reference to existing technologies and will not be described in detail here.

[0050] For further information, please refer to Figure 5 , Figure 5 This is a schematic diagram of the circuit principle of the output drive sub-circuit of the drive circuit provided by the first embodiment of the present invention. Figure 5 As shown, the differential pair module circuit also includes a second current source 021, a transistor Q1, and a transistor Q2. One end of the second current source 021 is grounded, and the end of the second current source 021 away from the ground is connected to the emitter of the transistor Q1. The end of the second current source 021 away from the ground is connected to the emitter of the transistor Q2. The collector of the transistor Q1 is connected to the end of the load resistor RL1 away from the PMOS transistor MP1, and the collector of the transistor Q2 is connected to the end of the load resistor RL2 away from the PMOS transistor MP1. With this configuration, the differential pair module circuit essentially forms a CML (Current Mode Logic) structure, which has better gain-bandwidth performance and is easier to control output load matching.

[0051] There are many optimization solutions for the CML structure, for example, please refer to Figure 6 , Figure 6 This is a schematic diagram of the circuit principle of the output drive sub-circuit of the drive circuit provided by the second embodiment of the present invention. Figure 6 As shown, the output driver subcircuit of the driver circuit provided in the second embodiment differs from the output driver subcircuit of the driver circuit provided in the first embodiment in that a transistor Q3 is provided between the transistor Q1 and the load resistor RL1, and a transistor Q4 is provided between the transistor Q2 and the load resistor RL2; the collector of the transistor Q3 is connected to the end of the load resistor RL1 away from the PMOS transistor, and the emitter of the transistor Q3 is connected to the collector of the transistor Q1; the collector of the transistor Q4 is connected to the end of the load resistor RL2 away from the PMOS transistor MP1, and the emitter of the transistor Q4 is connected to the collector of the transistor Q2. This arrangement essentially adds a cascade stage to the CML structure, resulting in advantages such as higher output impedance and output isolation.

[0052] For further information, please refer to Figure 7 , Figure 7 Schematic diagram of the circuit principle of the output drive sub-circuit of the drive circuit provided by the third embodiment of the present invention. Figure 7 As shown, the output driver subcircuit of the driver circuit provided by the third embodiment differs from the output driver subcircuit of the driver circuit provided by the second embodiment and the first embodiment in that it further includes a transistor Q5, a transistor Q6, and a third current source; one end of the third current source is grounded, and the end of the third current source away from the ground is connected to the emitter of the transistor Q5, and the end of the third current source away from the ground is connected to the emitter of the transistor Q6; the collector of the transistor Q5 is connected to the end of the load resistor RL1 away from the PMOS transistor MP1 and to the collector of the transistor Q1; the collector of the transistor Q6 is connected to the end of the load resistor RL2 away from the PMOS transistor and to the collector of the transistor Q2. This configuration essentially constitutes an FFE structure. By adjusting the polarity, delay, and amplitude of the second signal, a stronger equalization function can be achieved, bandwidth expansion can be achieved, and nonlinear characteristics of driven elements such as VCSELs can be compensated, thereby ensuring the performance of the VCSEL output signal.

[0053] For further information, please refer to Figure 8 , Figure 8 Schematic diagram of the circuit principle of the first current source and the second current source of the driving circuit provided by one embodiment of the present invention. Figure 8As shown, the first current source includes a second operational amplifier OP2, a transistor QB1, and an emitter resistor RE2, and the second current source includes a third operational amplifier OP3, a transistor QB2, and an emitter resistor RE3; one end of the emitter resistor RE2 is grounded, and the end of the emitter resistor RE2 away from the ground is connected to the emitter of the transistor QB1 and the inverting input terminal of the second operational amplifier OP2; one end of the emitter resistor RE3 is grounded, and the end of the emitter resistor RE3 away from the ground is connected to the emitter of the transistor QB2 and the inverting input terminal of the third operational amplifier; the collector of the transistor QB1 is connected to the end of the load resistor Rref away from the load resistor RL1, and the base of the transistor QB1 is connected to the output terminal of the second operational amplifier OP2; the collector of the transistor QB2 is connected to the emitter of the transistor Q1 and the emitter of the transistor Q2, and the base of the transistor QB2 is connected to the output terminal of the third operational amplifier OP3; the positive input terminals of the second operational amplifier and the third operational amplifier OP3 are connected to the first temperature-compensated current source. The first temperature-compensated current source includes a compensation current source unit 051 with a temperature coefficient and a compensation current source unit 052 without a temperature coefficient. The configuration of the two enables temperature compensation for the entire circuit. The current ratio between the first and second current sources can be achieved by configuring the resistance values ​​of emitter resistors RE1, RE2, and RE3, thereby serving the first operational amplifier OP1.

[0054] For further information, please refer to Figure 9 , Figure 9 Schematic diagram of the circuit principle of the first current source, the second current source and the third current source of the driving circuit provided by an embodiment of the present invention. Figure 9As shown, it also includes a transistor Q5, a transistor Q6 and a third current source; one end of the third current source is grounded, and the end of the third current source away from the ground direction is connected to the emitter of the transistor Q5, and the end of the third current source away from the ground direction is connected to the emitter of the transistor Q5; the collector of the transistor Q5 is connected to the end of the load resistor RL1 away from the PMOS transistor and to the collector of the transistor Q1; the collector of the transistor Q6 is connected to the end of the load resistor RL2 away from the PMOS transistor and to the collector of the transistor Q2; the third current source includes a fourth operational amplifier, a transistor QB3 and an emitter resistor RE4; the first current source also includes a fifth operational amplifier, a transistor QB4 and an emitter resistor RE5; one end of the emitter resistor RE4 The first terminal of the circuit is connected to ground, and the end of the emitter resistor RE4 away from ground is connected to the emitter of the transistor QB2 and the inverting input terminal of the fourth operational amplifier. The first terminal of the emitter resistor RE5 is grounded, and the end of the emitter resistor RE5 away from ground is connected to the emitter of the transistor QB4 and the inverting input terminal of the fifth operational amplifier. The collector of the transistor QB3 is connected to the emitter of the transistor Q5 and the emitter of the transistor Q6, and the base of the transistor QB3 is connected to the output terminal of the fourth operational amplifier. The collector of the transistor QB4 is connected to the end of the load resistor Rref away from the load resistor RL1, and the base of the transistor QB4 is connected to the output terminal of the fifth operational amplifier. The positive input terminals of the fourth operational amplifier and the fifth operational amplifier are connected to a second temperature-compensated current source. The second temperature-compensated current source includes a compensation current source unit 061 with a temperature coefficient and a compensation current source unit 062 without a temperature coefficient. By configuring the two, temperature compensation of the entire circuit can be achieved. Figure 9 The illustrated embodiment is particularly suitable for adapting a CML structure with an FFE structure, essentially proportionally increasing the post-tap tail current.

[0055] The principle of temperature compensation is as follows: Ibias = k1*(a*Iptat1+(1-a)*Iflat1), Imod_ref = k2*(a*Iptat2+(1-a)*Iflat2), where Iptat is the current that is positively correlated with temperature, and Iflat is the current that is independent of temperature. a is the proportion of the positive temperature coefficient current to the reference current. Using digital registers to control the values ​​of a, k1, and k2 ensures stable VCSEL emission at different temperatures.

[0056] For further information, please refer to Figure 10 , Figure 10 FIG. 1 is a schematic diagram of the circuit principle of the driving circuit provided by the second embodiment of the present invention. Figure 10As shown, it also includes several inductors 100, which are used to weaken the parasitic capacitance in the circuit. Figure 10 In the embodiment of the second driving circuit, the CML structure may include both a cascade structure and an FFE structure, which will not be described in detail here.

[0057] It should be noted that all the transistors described in this application may be NPN transistors or NMOS transistors.

[0058] The present invention also provides a vertical cavity surface emitting laser system, comprising a driving circuit as described in any of the above, wherein the driven element 10 is a vertical cavity surface emitting laser. Because the vertical cavity surface emitting laser system includes the driving circuit, the vertical cavity surface emitting laser system simultaneously uses a resistive load and the bias current control subcircuit to modulate the driving current. The advantage of this solution is that the resistive load effectively achieves output impedance matching, which can reduce the size of the current mirror load tube of the bias current control subcircuit, thereby reducing the driver stage load, which is beneficial for improving the circuit bandwidth and achieving greater gain-bandwidth performance. The modulation current control circuit is implemented using a feedback loop composed of an operational amplifier. This circuit works in conjunction with the output stage to form a current clamp circuit to ensure the stability of the output DC current. The modulation current and bias current are separately adjustable, so that the bias current is viewed from the output end of the output driver subcircuit as a high-impedance environment, ensuring that the bias current does not flow into the output stage, causing the bias current to be inconsistent with the expected value.

[0059] It should also be noted that although the present invention has been disclosed above with reference to preferred embodiments, the above embodiments are not intended to limit the present invention. For any person skilled in the art, without departing from the scope of the technical solution of the present invention, the technical content disclosed above can be used to make many possible changes and modifications to the technical solution of the present invention, or to modify it into an equivalent embodiment with equivalent changes. Therefore, any simple modification, equivalent change, and modification made to the above embodiments based on the technical essence of the present invention without departing from the content of the technical solution of the present invention still fall within the scope of protection of the technical solution of the present invention.

[0060] It should also be understood that, unless otherwise specified or indicated, the terms "first", "second", "third", etc. in the specification are only used to distinguish the various components, elements, steps, etc. in the specification, and are not used to indicate the logical relationship or sequential relationship between the various components, elements, steps, etc.

[0061] It should also be recognized that the terms described herein are used only to describe specific embodiments and are not intended to limit the scope of the invention. It should be noted that the singular forms "a" and "an" used herein and in the appended claims include plural references unless the context clearly indicates otherwise. For example, a reference to "a step" or "a device" means a reference to one or more steps or devices, and may include secondary steps as well as secondary devices. All conjunctions used should be understood in their broadest sense. Also, the word "or" should be understood to have the definition of a logical "or" rather than a logical "exclusive or" unless the context clearly indicates otherwise. In addition, implementation of embodiments of the present invention may include performing selected tasks manually, automatically, or in combination.

Claims

1. A driving circuit, characterized in that: including a bias current control subcircuit and an output drive subcircuit; The input end of the bias current control subcircuit is connected to a power supply, and the output end of the bias current control subcircuit is connected to the output end of the output drive subcircuit and a driven element; The output driver sub-circuit includes a differential pair module circuit, which includes a load resistor RL1, a load resistor RL2, a second current source, a transistor Q1, and a transistor Q2. A PMOS transistor is provided between a power supply of the differential pair module circuit and the load resistors RL1 and RL2. The source of the PMOS transistor is connected to the power supply of the differential pair module circuit, and the drain of the PMOS transistor is connected to the load resistors RL1 and RL2 to form a junction. One end of the second current source is grounded, and an end of the second current source away from the ground direction is connected to the emitter of the transistor Q1 and the emitter of the transistor Q2. The collector of the transistor Q1 is connected to an end of the load resistor RL1 away from the PMOS transistor, and the collector of the transistor Q2 is connected to an end of the load resistor RL2 away from the PMOS transistor. A transistor Q3 is provided between the transistor Q1 and the load resistor RL1, a transistor Q4 is provided between the transistor Q2 and the load resistor RL2, the collector of the transistor Q3 is connected to the end of the load resistor RL1 away from the PMOS transistor, the emitter of the transistor Q3 is connected to the collector of the transistor Q1, the base of the transistor Q3 is connected to the voltage VB, the collector of the transistor Q4 is connected to the end of the load resistor RL2 away from the PMOS transistor, the emitter of the transistor Q4 is connected to the collector of the transistor Q2, and the base of the transistor Q4 is connected to the voltage VB; The end of the load resistor RL2 close to the driven element is the output end of the output driver sub-circuit, the end of the load resistor RL2 close to the driven element is also connected to one end of a load resistor Rf, and the end of the load resistor Rf away from the load resistor RL2 is connected to the first input end of the first operational amplifier; One end of the load resistor RL1 close to the PMOS transistor is further connected to one end of a load resistor Rref, one end of the load resistor Rref away from the load resistor RL1 is connected to the second input terminal of the first operational amplifier, and one end of the load resistor Rref away from the load resistor RL1 is connected to a first current source; The output terminal of the first operational amplifier is connected to the gate of the PMOS transistor.

2. The driving circuit according to claim 1, wherein: The bias current control subcircuit includes a current mirror module circuit.

3. The driving circuit according to claim 2, wherein: The current mirror module circuit includes a cascade structure circuit.

4. The driving circuit according to claim 1, wherein: Also includes a transistor Q5, a transistor Q6 and a third current source; One end of the third current source is grounded, and one end of the third current source away from the ground is connected to the emitter of the transistor Q5 and the emitter of the transistor Q6; The collector of the transistor Q5 is connected to the end of the load resistor RL1 away from the PMOS transistor and is also connected to the collector of the transistor Q1; The collector of the transistor Q6 is connected to the end of the load resistor RL2 away from the PMOS transistor and is also connected to the collector of the transistor Q2 .

5. The driving circuit according to claim 1, wherein: The first current source includes a second operational amplifier, a transistor QB1 and an emitter resistor RE2, and the second current source includes a third operational amplifier, a transistor QB2 and an emitter resistor RE3; One end of the emitter resistor RE2 is grounded, and the end of the emitter resistor RE2 away from the ground is connected to the emitter of the transistor QB1 and the inverting input terminal of the second operational amplifier; One end of the emitter resistor RE3 is grounded, and the end of the emitter resistor RE3 away from the ground is connected to the emitter of the transistor QB2 and the inverting input terminal of the third operational amplifier; The collector of the transistor QB1 is connected to the end of the load resistor Rref away from the load resistor RL1, and the base of the transistor QB1 is connected to the output end of the second operational amplifier; The collector of the transistor QB2 is connected to the emitter of the transistor Q1 and the emitter of the transistor Q2, and the base of the transistor QB2 is connected to the output terminal of the third operational amplifier; The positive input terminals of the second operational amplifier and the third operational amplifier are connected to a first temperature compensation current source.

6. The driving circuit according to claim 5, wherein: Also includes a transistor Q5, a transistor Q6 and a third current source; One end of the third current source is grounded, and one end of the third current source away from the ground direction is connected to the emitter of the transistor Q5 and is also connected to the emitter of the transistor Q5; The collector of the transistor Q5 is connected to the end of the load resistor RL1 away from the PMOS transistor and is also connected to the collector of the transistor Q1; The collector of the transistor Q6 is connected to the end of the load resistor RL2 away from the PMOS transistor and is also connected to the collector of the transistor Q2; The third current source includes a fourth operational amplifier, a transistor QB3 and an emitter resistor RE4; The first current source further includes a fifth operational amplifier, a transistor QB4 and an emitter resistor RE5; One end of the emitter resistor RE4 is grounded, and the end of the emitter resistor RE4 away from the ground is connected to the emitter of the transistor QB3 and the inverting input terminal of the fourth operational amplifier; One end of the emitter resistor RE5 is grounded, and the end of the emitter resistor RE5 away from the ground is connected to the emitter of the transistor QB4 and the inverting input terminal of the fifth operational amplifier; The collector of the transistor QB3 is connected to the emitter of the transistor Q5 and the emitter of the transistor Q6, and the base of the transistor QB3 is connected to the output terminal of the fourth operational amplifier; The collector of the transistor QB4 is connected to the end of the load resistor Rref away from the load resistor RL1, and the base of the transistor QB4 is connected to the output end of the fifth operational amplifier; The positive input terminals of the fourth operational amplifier and the fifth operational amplifier are connected to a second temperature compensation current source.

7. The driving circuit according to claim 1, wherein: The device also includes several inductors, which are used to weaken the parasitic capacitance in the circuit.

8. A vertical cavity surface emitting laser system, characterized in that: The driving circuit comprises the driving circuit according to any one of claims 1 to 7, wherein the driven element is a vertical cavity surface emitting laser.

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