Power supply chip and control method thereof

Abstract

The embodiment of the invention provides a power supply chip and a control method thereof. The power supply chip comprises a control module, a first output module and a second output module, the control module is configured to judge the working mode of the power supply chip according to signals of the first control signal end and the second control signal end, generate control signals and provide the control signals to the first output module and the second output module; the first output module is electrically connected with the control module, and the first output module is configured to output a first power supply voltage in response to a control signal and a signal of a first power supply signal end; the second output module is electrically connected with the control module, and the second output module is configured to output a second power supply voltage in response to the control signal and a signal of a second power supply signal end; therefore, the manufacturing cost is saved, the manufacturing period is shortened, the function stability is improved, the application range is wide, and the method can be applied to most of circuit design scenes at present.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a power chip and a control method thereof. Background Art

[0002] With the continuous development of electronic technology, power chips play a vital role in various electronic devices. In the hardware circuit design process of current electronic devices, power chips need to be configured according to the circuit design.

[0003] For example, in a circuit that requires more voltage values, many power chips are needed to build a power conversion circuit. The use of multiple power chips will increase the material cost and occupy more board area of ​​the printed circuit board (PCB). In a circuit that requires a large current, if a large current power chip is selected, the price of the large current power chip is generally more expensive. If multiple small current power chips are connected in parallel to share the current, while increasing the materials, it also has higher requirements for the stability of the current sharing of the peripheral circuit. In the circuit design that requires power backup, two single-channel power chips are still needed and the power backup is achieved through the peripheral circuit design, which increases the difficulty of circuit design and the peripheral materials. The above examples will all cause the problem of increased material cost and increased circuit design difficulty. At the same time, with the increase in the use of materials, the circuit failure rate will theoretically increase significantly, posing a hidden danger to product safety. Summary of the invention

[0004] The power chip provided in the embodiment of the present invention comprises: a control module, a first output module and a second output module;

[0005] The control module is configured to determine the working mode of the power chip according to the signals at the first control signal terminal and the second control signal terminal, and generate a control signal to provide to the first output module and the second output module;

[0006] The first output module is electrically connected to the control module, and the first output module is configured to output a first power supply voltage in response to the control signal and a signal at a first power supply signal terminal;

[0007] The second output module is electrically connected to the control module, and the second output module is configured to output a second power supply voltage in response to the control signal and a signal at a second power supply signal terminal.

[0008] In some possible implementations, the working modes include: a first working mode;

[0009] In the first working mode, the control module controls the first output module and the second output module to work independently of each other, the first output module outputs the first power supply voltage through the first output terminal, and the second output module outputs the second power supply voltage through the second output terminal.

[0010] In some possible implementations, when the signal at the first control signal end and the signal at the second control signal end are both first level signals, and at least one of the signal at the first power signal end and the signal at the second power signal end is a first level signal, the control module determines that it is in the first operating mode.

[0011] In some possible implementations, the working modes include: a second working mode;

[0012] In the second working mode, the control module controls the first output module to output the first power supply voltage through the third output terminal and the second output module to output the second power supply voltage through the third output terminal.

[0013] In some possible implementations, when the signal at the first control signal end, the signal at the first power signal end, and the signal at the second power signal end are all first level signals, and the signal at the second control signal end is a second level signal, the control module determines that it is in the second operating mode.

[0014] In some possible implementations, the working modes include: a third working mode;

[0015] In the third working mode, the control module controls the first output module to output the first power supply voltage through the third output terminal or the second output module to output the second power supply voltage through the third output terminal.

[0016] In some possible implementations, the first output module works preferentially, and the second output module works as an alternative. When the first power signal terminal is damaged, the second output module outputs the second power voltage through the third output terminal.

[0017] In some possible implementations, when the signal at the first power signal end and the signal at the second power signal end are both first level signals, and the signal at the first control signal end and the signal at the second control signal end are second level signals, the control module determines that it is in the third operating mode.

[0018] The control method of the power chip provided by the embodiment of the present invention includes: the power chip includes: a control module, a first output module and a second output module;

[0019] Loading signals to the first control signal terminal, the second control signal terminal, the first power signal terminal, and the second power signal terminal;

[0020] The control module determines the working mode of the power chip according to the signals at the first control signal terminal and the second control signal terminal, and provides the control signal to the first output module and the second output module;

[0021] The first output module outputs a first power supply voltage in response to the control signal and a signal at the first power supply signal terminal; the second output module outputs a second power supply voltage in response to the control signal and a signal at the second power supply signal terminal.

[0022] In some possible implementations, the working mode includes: a first working mode, a second working mode, and a third working mode;

[0023] In the first working mode, the control module controls the first output module and the second output module to work independently of each other, the first output module outputs the first power supply voltage through the first output terminal, and the second output module outputs the second power supply voltage through the second output terminal;

[0024] In the second working mode, the control module controls the first output module to output the first power supply voltage through the third output terminal and the second output module to output the second power supply voltage through the third output terminal;

[0025] In the third working mode, the control module controls the first output module to output the first power supply voltage through the third output terminal or the second output module to output the second power supply voltage through the third output terminal. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 Some structural schematic diagrams of power chips provided by embodiments of the present invention;

[0027] Figure 2 Other structural schematic diagrams of power chips provided by embodiments of the present invention;

[0028] Figure 3 Some further structural schematic diagrams of the power chip provided by the embodiments of the present invention;

[0029] Figure 4 Some further structural schematic diagrams of the power chip provided by the embodiments of the present invention;

[0030] Figure 5 Some further structural schematic diagrams of the power chip provided by the embodiments of the present invention;

[0031] Figure 6Some structural schematic diagrams of the power supply chip provided by the embodiment of the present invention applied in the circuit;

[0032] Figure 7 Other structural schematic diagrams of the power chip provided by the embodiment of the present invention applied in the circuit;

[0033] Figure 8 Some further structural schematic diagrams of the power supply chip provided by the embodiment of the present invention applied in the circuit;

[0034] Fig. 9 Some schematic diagrams of processes provided for embodiments of the present invention;

[0035] Fig.10 Some other flow charts provided for embodiments of the present invention. DETAILED DESCRIPTION

[0036] In order to make the purpose, technical solution and advantages of the embodiment of the present invention clearer, the technical solution of the embodiment of the present invention will be clearly and completely described below in conjunction with the drawings of the embodiment of the present invention. Obviously, the described embodiment is a part of the embodiment of the present invention, not all of the embodiments. And in the absence of conflict, the embodiments of the present invention and the features in the embodiments can be combined with each other. Based on the described embodiments of the present invention, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present invention.

[0037] Unless otherwise defined, the technical or scientific terms used in the present invention shall have the usual meanings understood by persons with ordinary skills in the field to which the present invention belongs. The words "first", "second" and similar words used in the present invention do not indicate any order, quantity or importance, but are only used to distinguish different components. Words such as "include" or "comprise" and the like mean that the elements or objects appearing before the word include the elements or objects listed after the word and their equivalents, without excluding other elements or objects. Words such as "connect" or "connected" and the like are not limited to physical or mechanical connections, but may include electrical connections, whether direct or indirect.

[0038] It should be noted that the sizes and shapes of the figures in the accompanying drawings do not reflect the actual proportions, but are only intended to illustrate the content of the present invention. The same or similar reference numerals throughout represent the same or similar elements or elements with the same or similar functions.

[0039] With the continuous development of electronic technology, power chips play a vital role in various electronic devices. In the current hardware circuit design process of electronic devices, it is necessary to configure power chips according to the circuit design. Among them, there are more and more optional manufacturers and models of power chips, but the advantages of most power chips are still mostly reflected in the price, and there is still not much innovation and breakthrough in terms of function.

[0040] In the prior art, in circuits that require more voltage values, many power chips are often still used to build power conversion circuits. In circuit designs that require large currents, it is still necessary to use expensive high-current power chips, or to use multiple small-current power chips in parallel to share the current. In addition, in the fields of aviation, rail transit, coal, etc., in order to ensure the reliability of data network transmission, the requirements for circuit design are high, and power backup scenarios are required. Generally, two single-channel power chips are required. Power backup is achieved by designing the peripheral circuit of the power chip to ensure the safety and stability of product functions.

[0041] In view of the above phenomenon, it can be found that the current general method has some disadvantages, for example: in the circuit that requires more voltage values, many power chips are needed to build the power conversion circuit. The use of multiple power chips will increase the material cost and occupy more board area of ​​the printed circuit board (PCB); in the circuit that requires large current, if a large current power chip is selected, the price of the large current power chip is generally more expensive, and if multiple small current power chips are connected in parallel to share the current, while increasing the materials, it also has higher requirements for the stability of the current sharing of the peripheral circuit; in the circuit design that requires power backup, two single-channel power chips are still needed and the power backup is achieved through the peripheral circuit design, which increases the difficulty of circuit design and the peripheral materials. In the above examples, there will be problems of increased material cost and increased difficulty of circuit design. At the same time, with the increase in the use of materials, the circuit failure rate will theoretically increase significantly, bringing hidden dangers to product safety.

[0042] Therefore, in order to solve the above problems, the present invention provides a power chip that can realize the above required functions, reduce material costs and reduce the difficulty of circuit design, solve the disadvantages of using the above general method, and ensure the safety and reliability of the product.

[0043] An embodiment of the present invention provides a power chip, such as Figure 1 As shown, it includes: a control module 100, a first output module 200 and a second output module 300;

[0044] The control module 100 is configured to determine the working mode of the power chip 01 according to the signals of the first control signal terminal CTRL1 and the second control signal terminal CTRL2, and generate a control signal to provide to the first output module 200 and the second output module 300;

[0045] The first output module 200 is electrically connected to the control module 100, and the first output module 200 is configured to output a first power supply voltage in response to a control signal and a signal of a first power supply signal terminal VIN1;

[0046] The second output module 300 is electrically connected to the control module 100 , and is configured to output a second power supply voltage in response to the control signal and the signal at the second power supply signal terminal VIN2 .

[0047] The present invention implements a control module to determine the working mode of the power chip according to the signals of the first control signal terminal and the second control signal terminal, and through the mutual cooperation of the control module, the first output module and the second output module, the power chip can realize multiple working modes, thereby adapting to circuits with different design requirements, such as circuits that require more voltage values, circuits that require large currents, and circuits that require power backup, and saves manufacturing costs and cycles and improves functional stability;

[0048] Moreover, the power chip in the present invention has a high degree of integration and can meet the needs of many circuits without the need for peripheral circuit cooperation. It has a wide range of applications and can be used in most current circuit design scenarios.

[0049] It should be noted that the control module 100 also monitors the internal and external states of the power chip in real time. If an emergency occurs, a corresponding instruction is immediately issued to change the output state of the power chip.

[0050] In the embodiment of the present invention, Figure 2 and Figure 3 As shown, the control module 100 specifically includes: a core logic control unit 110 (CORE Control Logic), a pulse width modulation unit 120 (Pulse Width Modulation, PWM) and a temperature protection unit 130 (Thermal Shut down);

[0051] The core logic control unit 110 is used to control the operation of the entire power chip 01 , and is responsible for monitoring and directing the working state and working mode of the entire power chip 01 .

[0052] The pulse width modulation unit 120 is used to control the output voltage and current, that is, to control the average value of the output signal by adjusting the pulse width (ie, the duration of the high level of the pulse).

[0053] The temperature protection unit 130 is used to automatically cut off the output of the power chip 01 when it determines that the operating temperature of the power chip 01 exceeds the set threshold, and wait for the temperature of the power chip 01 to drop to a safe range before resuming operation of the power chip 01, so as to prevent the power chip 01 from overheating and causing safety hazards.

[0054] In the embodiment of the present invention, Figure 2 and Figure 4 As shown, the first output module 200 specifically includes: a logic control unit 210 (Control Logic), a current limiting protection unit 220 (HS MOSFET Current limit), an enable logic unit 230 (Enable Logic), a bootstrap capacitor charging unit 240 (Boot Charge), an undervoltage lockout unit 250 (Boot UnderVoltage Lock Out, Boot UVLO), a current balancing control unit 260 (Current Balance), an oscillator and phase-locked loop combination unit 270 (Os cillator With PLL) and a pulse width modulation unit 280 (Pulse Width Modulation, PWM);

[0055] The logic control unit 210 is controlled by the core logic control unit 110. When receiving the control signal (eg Figure 2 After Control_1 in the control, the first output module 200 is controlled to enter a preset working mode, and the working state of the first output module 200 is monitored in real time.

[0056] The current limiting protection unit 220 is used to accurately control the current of the transistor in the logic control unit 210 to protect the logic control unit 210 and prevent the logic control unit 210 from being damaged.

[0057] The enable logic unit 230 is used to control the activation or deactivation of the control logic control unit 210, that is, the enable logic unit 230 can determine whether the control logic control unit 210 starts to execute work. Among them, the enable logic unit 230 is controlled by the core logic control unit 110. When the core logic control unit 110 outputs an enable control signal (for example, Figure 2 When the EN_1 in the signal source is on, the logic unit 230 starts to work. The enable logic unit 230 is also electrically connected to the first reference voltage signal terminal VREF and the second reference voltage signal terminal VCC.

[0058] The bootstrap capacitor charging unit 240 is used to charge the bootstrap capacitor in the first output module 200, while ensuring the stability and reliability of the first output module 200. The bootstrap capacitor charging unit 240 is electrically connected to the second reference voltage signal terminal VCC.

[0059] The undervoltage lockout unit 250 is used to monitor the power supply voltage of the first output module 200, and when the power supply voltage drops below a preset threshold, take appropriate measures (such as shutting down the first output module 200 or putting the first output module 200 into a standby state) to prevent the first output module 200 from running at a low voltage and possibly causing functional abnormality or damage.

[0060] The current sharing control unit 260 is used to control and balance the current values ​​output by the first output module 200 and the second output module 300 when the first output module 200 and the second output module 300 enter a common working mode, so as to prevent one of the first output module 200 and the second output module 300 from stopping working due to excessive workload due to excessive error in the current values ​​output by the first output module 200 and the second output module 300.

[0061] The oscillator and phase-locked loop combination unit 270 is used to output a stable clock signal CLK with a fixed frequency, so as to provide it to the core logic control unit 110 .

[0062] The pulse width modulation unit 280 is used to control the output voltage and current, that is, to control the average value of the output signal by adjusting the pulse width (that is, the duration of the high level of the pulse).

[0063] Exemplarily, the first output module 200 also includes: a gain compensation unit, a bias current unit, a reference Vref unit, an output stage MOS, an error amplifier, etc., wherein the gain compensation unit is used to adjust the gain of the circuit in the first output module 200 to compensate for the gain drop that may occur during the power conversion process. This is crucial to maintaining the stability and accuracy of the output voltage. The bias current unit provides the necessary bias current for other units in the circuit in the first output module 200 to ensure their normal operation. The magnitude and stability of the bias current directly affect the performance of the circuit in the first output module 200. The reference Vref unit provides a stable reference voltage for the circuit in the first output module 200, which is the reference for the operation of other parts of the circuit. The stability and accuracy of the reference voltage have a great influence on the performance of the circuit in the entire first output module 200. The output stage MOS, as an electronic switch, can control the on and off of the current and plays a key role in the power conversion process. By adjusting the gate voltage, the current can be established or cut off in its channel. The error amplifier is used to ensure the output constant current or constant voltage, sample the feedback voltage, and generate an error signal to adjust the working state of the circuit in the first output module 200. Of course, the first output module 200 may also include other working units, which are not specifically limited here.

[0064] The first output module 200 provides the control module 100 with the first power detection signal VIN1_DECT, and the control module 100 can detect and determine the signal of the first power signal terminal VIN1. The first output module 200 also includes: a first drive signal terminal BOOT1, a first enable signal terminal EN1, a first switching frequency configuration signal terminal RT / CLK1, a first output voltage configuration signal terminal FB1, a first loop compensation signal terminal COMP1, a first power output signal terminal SW1 and a ground terminal GND.

[0065] In the embodiment of the present invention, Figure 2 and Figure 5 As shown, the second output module 300 specifically includes: a logic control unit 310 (Control Logic), a current limiting protection unit 320 (HS MOSFET Current limit), an enable logic unit 330 (Enable Logic), a bootstrap capacitor charging unit 340 (Boot Charge), an undervoltage lockout unit 350 (Boot UnderVoltage Lock Out, Boot UVLO), an oscillator and phase-locked loop combination unit 370 (Os cillator With PLL) and a pulse width modulation unit 380 (Pulse Width Modulation, PWM);

[0066] The logic control unit 310 is controlled by the core logic control unit 110. When receiving the control signal (eg Figure 2 After Control_2 in the control, the second output module 300 is controlled to enter a preset working mode, and the working state of the second output module 300 is monitored in real time.

[0067] The current limiting protection unit 320 is used to accurately control the current of the transistor in the logic control unit 310 to protect the logic control unit 310 and prevent the logic control unit 310 from being damaged.

[0068] The enable logic unit 330 is used to control the activation or deactivation of the control logic control unit 310, that is, the enable logic unit 330 can determine whether the control logic control unit 310 starts to execute work. Among them, the enable logic unit 330 is controlled by the core logic control unit 110. When the core logic control unit 110 outputs an enable control signal (for example, Figure 2 When EN_2 in the enable logic unit 330 is enabled, the logic unit 330 starts to work. The enable logic unit 330 is also electrically connected to the first reference voltage signal terminal VREF and the second reference voltage signal terminal VCC.

[0069] The bootstrap capacitor charging unit 340 is used to charge the bootstrap capacitor in the second output module 300, while ensuring the stability and reliability of the second output module 300. The bootstrap capacitor charging unit 340 is electrically connected to the second reference voltage signal terminal VCC.

[0070] The undervoltage lockout unit 350 is used to monitor the power supply voltage of the second output module 300, and when the power supply voltage drops below a preset threshold, take appropriate measures (such as shutting down the second output module 300 or putting the second output module 300 into a standby state) to prevent the second output module 300 from operating at a low voltage and possibly causing malfunction or damage.

[0071] The oscillator and phase-locked loop combination unit 270 is used to output a stable clock signal CLK with a fixed frequency, so as to provide it to the core logic control unit 110 .

[0072] The pulse width modulation unit 380 is used to control the output voltage and current, that is, to control the average value of the output signal by adjusting the pulse width (that is, the duration of the high level of the pulse).

[0073] Exemplarily, the second output module 300 also includes: a gain compensation unit, a bias current unit, a reference Vref unit, an output stage MOS, an error amplifier, etc., wherein the gain compensation unit is used to adjust the gain of the circuit in the second output module 300 to compensate for the gain drop that may occur during the power conversion process. This is crucial to maintaining the stability and accuracy of the output voltage. The bias current unit provides the necessary bias current for other units in the circuit in the second output module 300 to ensure their normal operation. The magnitude and stability of the bias current directly affect the performance of the circuit in the second output module 300. The reference Vref unit provides a stable reference voltage for the circuit in the second output module 300, which is the reference for the operation of other parts of the circuit. The stability and accuracy of the reference voltage have a great influence on the performance of the circuit in the entire second output module 300. The output stage MOS, as an electronic switch, can control the on and off of the current and plays a key role in the power conversion process. By adjusting the gate voltage, the current can be established or cut off in its channel. The error amplifier is used to ensure the output constant current or constant voltage, sample the feedback voltage, and generate an error signal to adjust the working state of the circuit in the second output module 300. Of course, the second output module 300 may also include other working units, which are not specifically limited here.

[0074] The second output module 300 provides the control module 100 with a second power detection signal VIN2_DECT, and the control module 100 can detect and determine the signal of the second power signal terminal VIN2. The second output module 300 also includes: a second drive signal terminal BOOT2, a second enable signal terminal EN2, a second switching frequency configuration signal terminal RT / CLK2, a second output voltage configuration signal terminal FB2, a second loop compensation signal terminal COMP2, a second power output signal terminal SW2, and a ground terminal GND.

[0075] The truth table of the working mode of the power chip provided by the embodiment of the present invention is shown in Table 1.

[0076]

[0077]

[0078] Table 1

[0079] It should be noted that "1" and "0" represent the level values ​​of the signal, "1" represents that the signal is a high level signal, that is, the first level signal in the embodiment of the present invention is a high level signal, and "0" represents that the signal is a low level signal, that is, the second level signal in the embodiment of the present invention is a low level signal.

[0080] In an embodiment of the present invention, the working mode includes: a first working mode; in the first working mode, the control module controls the first output module and the second output module to operate independently of each other, the first output module outputs the first power supply voltage through the first output terminal, and the second output module outputs the second power supply voltage through the second output terminal.

[0081] In an embodiment of the present invention, when the signal at the first control signal end and the signal at the second control signal end are both first level signals, and at least one of the signal at the first power signal end and the signal at the second power signal end is a first level signal, the control module determines that it is in the first operating mode.

[0082] For example, when the circuit design requires more voltage values, that is, the circuit design requires the first working mode in the power chip, the structural diagram of the power chip 01 applied to the circuit is as follows: Figure 6 shown.

[0083] For example, Figure 6 As shown, the circuit specifically includes:

[0084] The power chip 01; wherein the signal terminals in the power chip 01 are respectively led out through pins, that is, the first drive signal terminal BOOT1 is led out through the first pin 1, the first power signal terminal VIN1 is led out through the second pin 2, the first enable signal terminal EN1 is led out through the third pin 3, the first switching frequency configuration signal terminal RT / CLK1 is led out through the fourth pin 4, the first output voltage configuration signal terminal FB1 is led out through the fifth pin 5, the first loop compensation signal terminal COMP1 is led out through the sixth pin 6, the first power output signal terminal SW1 is led out through the eighth pin 8, the first control signal terminal CTRL1 is led out through the ninth pin 9, the second control signal terminal CTRL2 is led out through the tenth pin 10, and the second drive signal terminal BOOT2 is led out through the eleventh pin 1 1, a second power signal terminal VIN2 is led out through a twelfth pin 12, a second enable signal terminal EN2 is led out through a thirteenth pin 13, a second switching frequency configuration signal terminal RT / CLK2 is led out through a fourteenth pin 14, a second output voltage configuration signal terminal FB2 is led out through a fifteenth pin 15, a second loop compensation signal terminal COMP2 is led out through a sixteenth pin 16, a second power output signal terminal SW2 is led out through an eighteenth pin 18, a plurality of ground terminals GND are respectively led out through a seventh pin 7, a seventeenth pin 17, a nineteenth pin 19, a twentieth pin 20, a twenty-first pin 21, a twenty-second pin 22, a twenty-third pin 23, and a twenty-fourth pin 24, and a heat dissipation signal terminal TP1 is led out through a twenty-fifth pin 25.

[0085] The pins and functions of the power chip provided by the embodiment of the present invention are shown in Table 2.

[0086]

[0087] Table 2

[0088] For example, Figure 6 As shown, the first drive signal terminal BOOT1 is electrically connected to the first pin 1, and the first pin 1 is electrically connected to the eighth pin 8 through a 0.1uF bootstrap capacitor C1. The second drive signal terminal BOOT2 is electrically connected to the eleventh pin 11, and the eleventh pin 11 is electrically connected to the eighteenth pin 18 through a 0.1uF bootstrap capacitor C7.

[0089] For example, Figure 6 As shown, the circuit specifically also includes:

[0090] A second capacitor C2, wherein a first electrode of the second capacitor C2 is electrically connected to the first power signal terminal VIN1, and a second electrode of the second capacitor C2 is electrically connected to the ground terminal GND;

[0091] A first resistor R1, a first electrode of the first resistor R1 is electrically connected to the first power signal terminal VIN1, and a second electrode of the first resistor R1 is electrically connected to the third pin 3;

[0092] A second resistor R2, wherein a first electrode of the second resistor R2 is electrically connected to the third pin 3, and a second electrode of the second resistor R2 is electrically connected to a first electrode of a fourth resistor R4;

[0093] a fourth resistor R4, wherein a first electrode of the fourth resistor R4 is electrically connected to the ground terminal GND, and a second electrode of the fourth resistor R4 is electrically connected to the fourth pin 4;

[0094] A bootstrap capacitor C1, a first electrode of the bootstrap capacitor C1 is electrically connected to the first pin 1, and a second electrode of the bootstrap capacitor C1 is electrically connected to the eighth pin 8;

[0095] A first inductor L1, a first electrode of the first inductor L1 is electrically connected to the eighth pin 8, and a second electrode of the first inductor L1 is electrically connected to the first output terminal VOUT1;

[0096] a diode D1, wherein a first electrode of the diode D1 is electrically connected to the eighth pin 8, and a second electrode of the diode D1 is electrically connected to the seventh pin 7;

[0097] A third capacitor C3, a first electrode of the third capacitor C3 is electrically connected to the first output terminal VOUT1, and a second electrode of the third capacitor C3 is electrically connected to the seventh pin 7;

[0098] a fourth capacitor C4, wherein a first electrode of the fourth capacitor C4 is electrically connected to the first output terminal VOUT1, and a second electrode of the fourth capacitor C4 is electrically connected to the seventh pin 7;

[0099] a fifth capacitor C5, wherein a first electrode of the fifth capacitor C5 is electrically connected to the first output terminal VOUT1, and a second electrode of the fifth capacitor C5 is electrically connected to the seventh pin 7;

[0100] a sixth capacitor C6, wherein a first electrode of the sixth capacitor C6 is electrically connected to the first output terminal VOUT1, and a second electrode of the sixth capacitor C6 is electrically connected to the seventh pin 7;

[0101] a third resistor R3, wherein a first electrode of the third resistor R3 is electrically connected to the first output terminal VOUT1, and a second electrode of the third resistor R3 is electrically connected to the fifth pin 5;

[0102] a fifth resistor R5, wherein a first electrode of the fifth resistor R5 is electrically connected to the fifth pin 5, and a second electrode of the fifth resistor R5 is electrically connected to the ground terminal GND;

[0103] a sixth resistor R6, wherein a first electrode of the sixth resistor R6 is electrically connected to the sixth pin 6, and a second electrode of the sixth resistor R6 is electrically connected to a first electrode of a fourteenth capacitor C14;

[0104] a fourteenth capacitor C14, wherein a second electrode of the fourteenth capacitor C14 is electrically connected to the ground terminal GND;

[0105] a ninth capacitor C9, wherein a first electrode of the ninth capacitor C9 is electrically connected to the sixth pin 6, and a second electrode of the ninth capacitor C9 is electrically connected to the ground terminal GND;

[0106] an eighth capacitor C8, wherein a first electrode of the eighth capacitor C8 is electrically connected to the second power signal terminal VIN2, and a second electrode of the eighth capacitor C8 is electrically connected to the ground terminal GND;

[0107] a seventh resistor R7, wherein a first electrode of the seventh resistor R7 is electrically connected to the second power signal terminal VIN2, and a second electrode of the seventh resistor R7 is electrically connected to the thirteenth pin 13;

[0108] a ninth resistor R9, wherein a first electrode of the ninth resistor R9 is electrically connected to the thirteenth pin 13, and a second electrode of the ninth resistor R9 is electrically connected to a first electrode of the tenth resistor R10;

[0109] a tenth resistor R10, wherein a first electrode of the tenth resistor R10 is electrically connected to the ground terminal GND, and a second electrode of the tenth resistor R10 is electrically connected to the fourteenth pin 14;

[0110] A bootstrap capacitor C7, a first electrode of the bootstrap capacitor C7 is electrically connected to the eleventh pin 11, and a second electrode of the bootstrap capacitor C7 is electrically connected to the eighteenth pin 18;

[0111] a second inductor L2, wherein a first electrode of the second inductor L2 is electrically connected to the eighteenth pin 18, and a second electrode of the second inductor L2 is electrically connected to the second output terminal VOUT2;

[0112] a diode D2, wherein a first electrode of the diode D2 is electrically connected to the eighteenth pin 18, and a second electrode of the diode D2 is electrically connected to the seventeenth pin 17;

[0113] a tenth capacitor C10, wherein a first electrode of the tenth capacitor C10 is electrically connected to the second output terminal VOUT2, and a second electrode of the tenth capacitor C10 is electrically connected to the seventeenth pin 17;

[0114] an eleventh capacitor C11, a first electrode of the eleventh capacitor C11 is electrically connected to the second output terminal VOUT2, and a second electrode of the eleventh capacitor C11 is electrically connected to the seventeenth pin 17;

[0115] a twelfth capacitor C12, wherein a first electrode of the twelfth capacitor C12 is electrically connected to the second output terminal VOUT2, and a second electrode of the twelfth capacitor C12 is electrically connected to the seventeenth pin 17;

[0116] a thirteenth capacitor C13, wherein a first electrode of the thirteenth capacitor C13 is electrically connected to the second output terminal VOUT2, and a second electrode of the thirteenth capacitor C13 is electrically connected to the seventeenth pin 17;

[0117] an eighth resistor R8, wherein a first electrode of the eighth resistor R8 is electrically connected to the second output terminal VOUT2, and a second electrode of the eighth resistor R8 is electrically connected to the fifteenth pin 15;

[0118] a twelfth resistor R12, wherein a first electrode of the twelfth resistor R12 is electrically connected to the fifteenth pin 15, and a second electrode of the twelfth resistor R12 is electrically connected to the ground terminal GND;

[0119] an eleventh resistor R11, a first electrode of the eleventh resistor R11 is electrically connected to the sixteenth pin 16, and a second electrode of the eleventh resistor R11 is electrically connected to a first electrode of the sixteenth capacitor C16;

[0120] a sixteenth capacitor C16, a second electrode of the sixteenth capacitor C16 being electrically connected to the ground terminal GND;

[0121] A fifteenth capacitor C15, a first electrode of the fifteenth capacitor C15 is electrically connected to the sixteenth pin 16, and a second electrode of the fifteenth capacitor C15 is electrically connected to the ground terminal GND;

[0122] a thirteenth resistor R13, wherein a first electrode of the thirteenth resistor R13 is electrically connected to the first power signal terminal VIN1, and a second electrode of the thirteenth resistor R13 is electrically connected to the ninth pin 9;

[0123] A fourteenth resistor R14, a first electrode of the fourteenth resistor R14 is electrically connected to the second power signal terminal VIN2, and a second electrode of the fourteenth resistor R14 is electrically connected to the tenth pin 10;

[0124] A seventeenth capacitor C17, a first electrode of the seventeenth capacitor C17 is electrically connected to the first power signal terminal VIN1, and a second electrode of the seventeenth capacitor C17 is electrically connected to the ground terminal GND;

[0125] An eighteenth capacitor C18 , wherein a first electrode of the eighteenth capacitor C18 is electrically connected to the second power signal terminal VIN2 , and a second electrode of the eighteenth capacitor C18 is electrically connected to the ground terminal GND.

[0126] For example, as shown in Table 1 and Figure 6 As shown, when the signal of the first control signal terminal CTRL1 and the signal of the second control signal terminal CTRL2 are both first level signals, that is, the voltage values ​​of the signal of the first control signal terminal CTRL1 and the signal of the second control signal terminal CTRL2 are both "1", and when the signal of the first power signal terminal VIN1 and the signal of the second power signal terminal VIN2 are both first level signals, that is, the voltage values ​​of the signal of the first power signal terminal VIN1 and the signal of the second power signal terminal VIN2 are both "1", the control module in the power chip 01 determines that the power chip 01 is in the first working mode according to the detected signal of the first control signal terminal CTRL1 and the signal of the second control signal terminal CTRL2, and detects that the input of the signal of the first power signal terminal VIN1 and the signal of the second power signal terminal VIN2 are also normal, then the control module controls the first output module and the second output module to work independently of each other, so as to control the first output module to output the first power supply voltage through the first output terminal VOUT1, and control the second output module to output the second power supply voltage through the second output terminal VOUT2.

[0127] For example, as shown in Table 1 and Figure 6 As shown, when the signal of the first control signal terminal CTRL1 and the signal of the second control signal terminal CTRL2 are both first level signals, that is, the voltage values ​​of the signal of the first control signal terminal CTRL1 and the signal of the second control signal terminal CTRL2 are both "1", and when the signal of the first power signal terminal VIN1 is a first level signal and the signal of the second power signal terminal VIN2 is a second level signal, that is, the voltage value of the signal of the first power signal terminal VIN1 is "1" and the voltage value of the signal of the second power signal terminal VIN2 is "0", the control module in the power chip 01 determines that the power chip 01 is in the first working mode according to the detected signal of the first control signal terminal CTRL1 and the signal of the second control signal terminal CTRL2, and detects that the input of the signal of the first power signal terminal VIN1 is also normal, then the control module controls the first output module to work independently, thereby controlling the first output module to output the first power voltage through the first output terminal VOUT1.

[0128] For example, as shown in Table 1 and Figure 6 As shown, when the signal of the first control signal terminal CTRL1 and the signal of the second control signal terminal CTRL2 are both first level signals, that is, the voltage values ​​of the signal of the first control signal terminal CTRL1 and the signal of the second control signal terminal CTRL2 are both "1", and when the signal of the first power signal terminal VIN1 is a second level signal and the signal of the second power signal terminal VIN2 is a first level signal, that is, the voltage value of the signal of the first power signal terminal VIN1 is "0" and the voltage value of the signal of the second power signal terminal VIN2 is "1", the control module in the power chip 01 determines that the power chip 01 is in the first working mode according to the detected signal of the first control signal terminal CTRL1 and the signal of the second control signal terminal CTRL2, and detects that the input of the signal of the second power signal terminal VIN2 is also normal, then the control module controls the second output module to work independently, thereby controlling the second output module to output the second power voltage through the second output terminal VOUT2.

[0129] Through the above embodiments, the power chip in the embodiments of the present invention solves the problem in the prior art that a large number of power chips are needed to build a power conversion circuit in a circuit design that requires more voltage values. The single power chip in the present invention can output multiple voltage values, thereby reducing material costs and saving printed circuit board layout area, improving space utilization, and facilitating circuit integration.

[0130] In an embodiment of the present invention, the working mode includes: a second working mode; in the second working mode, the control module controls the first output module to output the first power supply voltage through the third output terminal and the second output module to output the second power supply voltage through the third output terminal.

[0131] In an embodiment of the present invention, when the signal at the first control signal end, the signal at the first power signal end and the signal at the second power signal end are all first level signals and the signal at the second control signal end is a second level signal, the control module determines that it is in the second working mode.

[0132] For example, when the circuit design requires a large current, that is, the circuit design requires the second working mode in the power chip, the structural diagram of the power chip 01 applied to the circuit is as follows: Figure 7 shown.

[0133] For example, Figure 7 As shown, the first drive signal terminal BOOT1 is electrically connected to the first pin 1, and the first pin 1 is electrically connected to the eighth pin 8 through a 0.1uF bootstrap capacitor C19. The second drive signal terminal BOOT2 is electrically connected to the eleventh pin 11, and the eleventh pin 11 is electrically connected to the eighteenth pin 18 through a 0.1uF bootstrap capacitor C19.

[0134] For example, Figure 7 As shown, the circuit specifically includes:

[0135] A twenty-fourth capacitor C24, a first electrode of the twenty-fourth capacitor C24 is electrically connected to the first power signal terminal VIN1, and a second electrode of the twenty-fourth capacitor C24 is electrically connected to the ground terminal GND;

[0136] A sixteenth resistor R16, a first electrode of the sixteenth resistor R16 is electrically connected to the first power signal terminal VIN1, and a second electrode of the sixteenth resistor R16 is electrically connected to the third pin 3;

[0137] a nineteenth resistor R19, wherein a first electrode of the nineteenth resistor R19 is electrically connected to the third pin 3, and a second electrode of the nineteenth resistor R19 is electrically connected to a first electrode of a twentieth resistor R20;

[0138] a twentieth resistor R20, wherein a first electrode of the twentieth resistor R20 is electrically connected to the ground terminal GND, and a second electrode of the twentieth resistor R20 is electrically connected to the fourth pin 4;

[0139] A bootstrap capacitor C19, a first electrode of the bootstrap capacitor C19 is electrically connected to the first pin 1, and a second electrode of the bootstrap capacitor C19 is electrically connected to the eighth pin 8;

[0140] a third inductor L3, wherein a first electrode of the third inductor L3 is electrically connected to the eighth pin 8, and a second electrode of the third inductor L3 is electrically connected to the third output terminal VOUT3;

[0141] a diode D3, wherein a first electrode of the diode D3 is electrically connected to the eighth pin 8, and a second electrode of the diode D3 is electrically connected to the seventh pin 7;

[0142] A twentieth capacitor C20, a first electrode of the twentieth capacitor C20 is electrically connected to the third output terminal VOUT3, and a second electrode of the twentieth capacitor C20 is electrically connected to the seventh pin 7;

[0143] A twenty-first capacitor C21, a first electrode of the twenty-first capacitor C21 is electrically connected to the third output terminal VOUT3, and a second electrode of the twenty-first capacitor C21 is electrically connected to the seventh pin 7;

[0144] A twenty-second capacitor C22, a first electrode of the twenty-second capacitor C22 is electrically connected to the third output terminal VOUT3, and a second electrode of the twenty-second capacitor C22 is electrically connected to the seventh pin 7;

[0145] A twenty-third capacitor C23, a first electrode of the twenty-third capacitor C23 is electrically connected to the third output terminal VOUT3, and a second electrode of the twenty-third capacitor C23 is electrically connected to the seventh pin 7;

[0146] a fifteenth resistor R15, wherein a first electrode of the fifteenth resistor R15 is electrically connected to the third output terminal VOUT3, and a second electrode of the fifteenth resistor R15 is electrically connected to the fifth pin 5;

[0147] a seventeenth resistor R17, wherein a first electrode of the seventeenth resistor R17 is electrically connected to the fifth pin 5, and a second electrode of the seventeenth resistor R17 is electrically connected to the ground terminal GND;

[0148] an eighteenth resistor R18, a first electrode of the eighteenth resistor R18 is electrically connected to the sixth pin 6, and a second electrode of the eighteenth resistor R18 is electrically connected to a first electrode of a twenty-sixth capacitor C26;

[0149] A twenty-sixth capacitor C26, a second electrode of the twenty-sixth capacitor C26 is electrically connected to the ground terminal GND;

[0150] A twenty-fifth capacitor C25, a first electrode of the twenty-fifth capacitor C25 is electrically connected to the sixth pin 6, and a second electrode of the twenty-fifth capacitor C25 is electrically connected to the ground terminal GND;

[0151] The eleventh pin 11 is electrically connected to the first pin 1, the twelfth pin 12 is electrically connected to the second pin 2, the thirteenth pin 13 is electrically connected to the third pin 3, the fourteenth pin 14 is electrically connected to the fourth pin 4, the eighteenth pin 18 is electrically connected to the eighth pin 8, the fifteenth pin 15 is electrically connected to the fifth pin 5, and the sixteenth pin 16 is electrically connected to the sixth pin 6;

[0152] A twenty-first resistor R21, a first electrode of the twenty-first resistor R21 is electrically connected to the first power signal terminal VIN1, and a second electrode of the twenty-first resistor R21 is electrically connected to the ninth pin 9;

[0153] A twenty-second resistor R22, a first electrode of the twenty-second resistor R22 is electrically connected to the ground terminal GND, and a second electrode of the twenty-second resistor R22 is electrically connected to the tenth pin 10;

[0154] A twenty-seventh capacitor C27 , a first electrode of the twenty-seventh capacitor C27 is electrically connected to the first power signal terminal VIN1 , and a second electrode of the twenty-seventh capacitor C27 is electrically connected to the ground terminal GND.

[0155] For example, as shown in Table 1 and Figure 7As shown, when the signal of the first control signal terminal CTRL1 is a first level signal and the signal of the second control signal terminal CTRL2 is a second level signal, that is, the voltage value of the signal of the first control signal terminal CTRL1 is "1" and the voltage value of the signal of the second control signal terminal CTRL2 is "0", and, when the signal of the first power signal terminal VIN1 and the signal of the second power signal terminal VIN2 are both first level signals, that is, the voltage values ​​of the signal of the first power signal terminal VIN1 and the signal of the second power signal terminal VIN2 are both "1", the control module in the power chip 01 determines that the power chip 01 is in the second working mode according to the detected signal of the first control signal terminal CTRL1 and the signal of the second control signal terminal CTRL2, and detects that the input of the signal of the first power signal terminal VIN1 and the signal of the second power signal terminal VIN2 are also normal, then the control module controls the first output module and the second output module to work together, so as to control the first output module to output the first power supply voltage through the third output terminal VOUT3 and control the second output module to output the second power supply voltage through the third output terminal VOUT3. That is, the first power supply voltage and the second power supply voltage are both output through the third output terminal VOUT3, wherein the specific values ​​of the first power supply voltage and the second power supply voltage are controlled within a small error by the current sharing control unit in the power supply chip 01, and the maximum current output value of the power supply chip 01 is the sum of the maximum current output values ​​of the first output module and the second output module working independently.

[0156] Through the above embodiments, the power chip in the embodiments of the present invention solves the problem in the prior art that in large-current circuit design, expensive large-current power chips need to be used or multiple power chips need to be connected in parallel for power supply. Now, a single power chip in the present invention can achieve large-current output, which saves costs and greatly reduces the difficulty of circuit design, thereby improving product safety and reliability.

[0157] In an embodiment of the present invention, the working mode includes: a third working mode; in the third working mode, the control module controls the first output module to output the first power supply voltage through the third output terminal or the second output module to output the second power supply voltage through the third output terminal.

[0158] In the embodiment of the present invention, the first output module works preferentially, and the second output module works as an alternative. When the first power signal terminal is damaged, the second output module outputs the second power voltage through the third output terminal.

[0159] In an embodiment of the present invention, when the signal at the first power signal terminal and the signal at the second power signal terminal are both first level signals, and the signal at the first control signal terminal and the signal at the second control signal terminal are both second level signals, the control module determines that it is in the third working mode.

[0160] For example, when the circuit design requires power backup, that is, the circuit design requires the third working mode in the power chip, the structural diagram of the power chip 01 applied to the circuit is as follows: Figure 8 shown.

[0161] For example, Figure 8 As shown, the first drive signal terminal BOOT1 is electrically connected to the first pin 1, and the first pin 1 is electrically connected to the eighth pin 8 through a 0.1uF bootstrap capacitor C28. The second drive signal terminal BOOT2 is electrically connected to the eleventh pin 11, and the eleventh pin 11 is electrically connected to the eighteenth pin 18 through a 0.1uF bootstrap capacitor C34.

[0162] For example, Figure 8 As shown, the circuit specifically includes:

[0163] A twenty-ninth capacitor C29, a first electrode of the twenty-ninth capacitor C29 is electrically connected to the first power signal terminal VIN1, and a second electrode of the twenty-ninth capacitor C29 is electrically connected to the ground terminal GND;

[0164] A twenty-third resistor R23, a first electrode of the twenty-third resistor R23 is electrically connected to the first power signal terminal VIN1, and a second electrode of the twenty-third resistor R23 is electrically connected to the third pin 3;

[0165] A twenty-fifth resistor R25, a first electrode of the twenty-fifth resistor R25 is electrically connected to the third pin 3, and a second electrode of the twenty-fifth resistor R25 is electrically connected to a first electrode of a twenty-sixth resistor R26;

[0166] A twenty-sixth resistor R26, a first electrode of the twenty-sixth resistor R26 is electrically connected to the ground terminal GND, and a second electrode of the twenty-sixth resistor R26 is electrically connected to the fourth pin 4;

[0167] A bootstrap capacitor C28, a first electrode of the bootstrap capacitor C28 is electrically connected to the first pin 1, and a second electrode of the bootstrap capacitor C28 is electrically connected to the eighth pin 8;

[0168] a fourth inductor L4, wherein a first electrode of the fourth inductor L4 is electrically connected to the eighth pin 8, and a second electrode of the fourth inductor L4 is electrically connected to the third output terminal VOUT3;

[0169] a diode D4, wherein a first electrode of the diode D4 is electrically connected to the eighth pin 8, and a second electrode of the diode D4 is electrically connected to the seventh pin 7;

[0170] a 30th capacitor C30, a first electrode of the 30th capacitor C30 is electrically connected to the third output terminal VOUT3, and a second electrode of the 30th capacitor C30 is electrically connected to the seventh pin 7;

[0171] A thirty-first capacitor C31, a first electrode of the thirty-first capacitor C31 is electrically connected to the third output terminal VOUT3, and a second electrode of the thirty-first capacitor C31 is electrically connected to the seventh pin 7;

[0172] A thirty-second capacitor C32, a first electrode of the thirty-second capacitor C32 is electrically connected to the third output terminal VOUT3, and a second electrode of the thirty-second capacitor C32 is electrically connected to the seventh pin 7;

[0173] A thirty-third capacitor C33, a first electrode of the thirty-third capacitor C33 is electrically connected to the third output terminal VOUT3, and a second electrode of the thirty-third capacitor C33 is electrically connected to the seventh pin 7;

[0174] A twenty-fourth resistor R24, a first electrode of the twenty-fourth resistor R24 ​​is electrically connected to the third output terminal VOUT3, and a second electrode of the twenty-fourth resistor R24 ​​is electrically connected to the fifth pin 5;

[0175] A twenty-seventh resistor R27, wherein a first electrode of the twenty-seventh resistor R27 is electrically connected to the fifth pin 5, and a second electrode of the twenty-seventh resistor R27 is electrically connected to the ground terminal GND;

[0176] A twenty-eighth resistor R28, a first electrode of the twenty-eighth resistor R28 is electrically connected to the sixth pin 6, and a second electrode of the twenty-eighth resistor R28 is electrically connected to a first electrode of the thirty-seventh capacitor C37;

[0177] A thirty-seventh capacitor C37, a second electrode of the thirty-seventh capacitor C37 is electrically connected to the ground terminal GND;

[0178] A thirty-fifth capacitor C35, a first electrode of the thirty-fifth capacitor C35 is electrically connected to the sixth pin 6, and a second electrode of the thirty-fifth capacitor C35 is electrically connected to the ground terminal GND;

[0179] A thirty-sixth capacitor C36, a first electrode of the thirty-sixth capacitor C36 is electrically connected to the second power signal terminal VIN2, and a second electrode of the thirty-sixth capacitor C36 is electrically connected to the ground terminal GND;

[0180] A twenty-ninth resistor R29, a first electrode of the twenty-ninth resistor R29 is electrically connected to the second power signal terminal VIN2, and a second electrode of the twenty-ninth resistor R29 is electrically connected to the thirteenth pin 13;

[0181] a 30th resistor R30, wherein a first electrode of the 30th resistor R30 is electrically connected to the 13th pin 13, and a second electrode of the 30th resistor R30 is electrically connected to a first electrode of a 31st resistor R31;

[0182] A thirty-first resistor R31, a first electrode of the thirty-first resistor R31 is electrically connected to the ground terminal GND, and a second electrode of the thirty-first resistor R31 is electrically connected to the fourteenth pin 14;

[0183] A bootstrap capacitor C34, a first electrode of the bootstrap capacitor C34 is electrically connected to the eleventh pin 11, and a second electrode of the bootstrap capacitor C34 is electrically connected to the eighteenth pin 18;

[0184] The eighteenth pin 18 is electrically connected to the eighth pin 8 , the fifteenth pin 15 is electrically connected to the fifth pin 5 , and the sixteenth pin 16 is electrically connected to the sixth pin 6 ;

[0185] A thirty-second resistor R32, wherein a first electrode of the thirty-second resistor R32 is electrically connected to the ninth pin 9, and a second electrode of the thirty-second resistor R32 is electrically connected to the ground terminal GND;

[0186] A thirty-third resistor R33 , a first electrode of the thirty-third resistor R33 is electrically connected to the tenth pin 10 , and a second electrode of the thirty-second resistor R32 is electrically connected to the ground terminal GND.

[0187] For example, as shown in Table 1 and Figure 8 As shown, when the signal of the first control signal terminal CTRL1 and the signal of the second control signal terminal CTRL2 are both second level signals, that is, the voltage values ​​of the signal of the first control signal terminal CTRL1 and the signal of the second control signal terminal CTRL2 are both "0", and when the signal of the first power signal terminal VIN1 and the signal of the second power signal terminal VIN2 are both first level signals, that is, the voltage values ​​of the signal of the first power signal terminal VIN1 and the signal of the second power signal terminal VIN2 are both "1", the control module in the power chip 01 determines that the power chip 01 is in the third working mode according to the detected signal of the first control signal terminal CTRL1 and the signal of the second control signal terminal CTRL2, and detects that the input of the signal of the first power signal terminal VIN1 and the signal of the second power signal terminal VIN2 are also normal, then the control module controls the first output module or the second output module to work, that is, controls the first output module to output the first power voltage through the third output terminal VOUT3; but when the control module determines that the first power signal terminal is damaged, that is, the first output module cannot work normally, then controls the second output module to replace the first output module, and controls the second output module to output the second power voltage through the third output terminal VOUT3.

[0188] Through the above embodiments, the power chip in the embodiments of the present invention solves the problem in the prior art that in the circuit design requiring power backup, two single-channel power chips are still needed to achieve power backup through peripheral circuit design. By using the power chip in the present invention, the material cost is reduced and the difficulty of circuit design is reduced, and the switching efficiency of the backup power supply is greatly improved, thereby ensuring the safety and reliability of the product.

[0189] In summary, the design of the power chip in the embodiment of the present invention has the characteristics of wide application range, flexible application scenarios, powerful functions, high stability, etc. Specifically, in the hardware circuit design, it saves the number of materials used, saves development and debugging time, reduces the risks brought by the independent design of peripheral circuits under different circumstances, shortens the product development cycle and greatly improves the safety and stability of the product.

[0190] Based on the same inventive concept, an embodiment of the present invention further provides a control method for a power chip, wherein the power chip comprises: a control module, a first output module and a second output module;

[0191] like Fig. 9 As shown, the control method includes:

[0192] S100, applying a signal to a first control signal terminal, a second control signal terminal, a first power signal terminal, and a second power signal terminal;

[0193] S200, the control module determines the working mode of the power chip according to the signals at the first control signal terminal and the second control signal terminal, and provides the control signal to the first output module and the second output module;

[0194] S300, the first output module outputs a first power supply voltage in response to a control signal and a signal at a first power supply signal terminal; the second output module outputs a second power supply voltage in response to a control signal and a signal at a second power supply signal terminal.

[0195] In the embodiment of the present invention, the working mode includes: a first working mode, a second working mode and a third working mode;

[0196] In the first working mode, the control module controls the first output module and the second output module to work independently of each other, the first output module outputs the first power supply voltage through the first output terminal, and the second output module outputs the second power supply voltage through the second output terminal;

[0197] In the second working mode, the control module controls the first output module to output the first power supply voltage through the third output terminal and the second output module to output the second power supply voltage through the third output terminal;

[0198] In the third working mode, the control module controls the first output module to output the first power supply voltage through the third output terminal or the second output module to output the second power supply voltage through the third output terminal.

[0199] Exemplary, combined Fig.10 The specific control method of the power chip includes:

[0200] S10, the first power signal terminal and the second power signal terminal are loaded with signals, and the control module works;

[0201] S20, the control module determines the working mode of the power chip according to the signals of the first control signal terminal and the second control signal terminal;

[0202] S30, when CTRL1=1, CTRL2=1, VIN1=1, VIN2=1 or CTRL1=1, CTRL2=1, VIN1=1, VIN2=0 or CTRL1=1, CTRL2=1, VIN1=0, VIN2=1;

[0203] S31, in a first working mode, the control module controls the first output module and the second output module to work independently of each other, the first output module outputs a first power supply voltage through a first output terminal, and the second output module outputs a second power supply voltage through a second output terminal;

[0204] S40, when CTRL1=1, CTRL2=0, VIN1=1, VIN2=1;

[0205] S41, second working mode, the control module controls the first output module to output the first power supply voltage through the third output terminal and the second output module to output the second power supply voltage through the third output terminal;

[0206] S50, when CTRL1=0, CTRL2=0, VIN1=1, VIN2=1;

[0207] S51, in a third working mode, the control module controls the first output module to output the first power supply voltage through the third output terminal;

[0208] S52: When the first power signal terminal is damaged, the control module controls the second output module to output the second power voltage through the third output terminal;

[0209] S60, does not conform to the preset working mode;

[0210] S61, the control module controls the first output module and the second output module to stand by, and the control module waits for the next working instruction.

[0211] Those skilled in the art will appreciate that embodiments of the present invention may be provided as methods, systems, or computer program products. Therefore, the present invention may take the form of a complete hardware embodiment, a complete software embodiment, or an embodiment combining software and hardware. Moreover, the present invention may take the form of a computer program product implemented on one or more computer-usable storage media (including but not limited to disk storage, CD-ROM, optical storage, etc.) containing computer-usable program code.

[0212] The present invention is described with reference to flowcharts and / or block diagrams of methods, devices (systems), and computer program products according to embodiments of the present invention. It should be understood that each process and / or block in the flowchart and / or block diagram, as well as the combination of processes and / or blocks in the flowchart and / or block diagram, can be implemented by computer program instructions. These computer program instructions can be provided to a processor of a general-purpose computer, a special-purpose computer, an embedded processor, or other programmable data processing device to produce a machine, so that the instructions executed by the processor of the computer or other programmable data processing device generate instructions for implementing the processes in the flowchart and / or block diagram. Figure 1 A process or multiple processes and / or boxes Figure 1 A device that provides the functions specified in a block or multiple blocks.

[0213] These computer program instructions may also be stored in a computer-readable memory capable of directing a computer or other programmable data processing device to operate in a specific manner, so that the instructions stored in the computer-readable memory produce an article of manufacture comprising an instruction device, which implements the process Figure 1 A process or multiple processes and / or boxes Figure 1 A function specified in one or more boxes.

[0214] These computer program instructions can also be loaded onto a computer or other programmable data processing device so that a series of operating steps are executed on the computer or other programmable device to produce a computer-implemented process, thereby providing instructions for implementing the process. Figure 1 A process or multiple processes and / or boxes Figure 1 A step that specifies a function in one or more boxes.

[0215] Although the preferred embodiments of the present invention have been described, those skilled in the art may make other changes and modifications to these embodiments once they have learned the basic creative concept. Therefore, the appended claims are intended to be interpreted as including the preferred embodiments and all changes and modifications that fall within the scope of the present invention.

[0216] Obviously, those skilled in the art can make various changes and modifications to the embodiments of the present invention without departing from the spirit and scope of the embodiments of the present invention. Thus, if these modifications and variations of the embodiments of the present invention fall within the scope of the claims of the present invention and their equivalents, the present invention is also intended to include these modifications and variations.

Claims

1. A power chip, characterized in that: include: A control module, a first output module and a second output module; The control module is configured to determine the working mode of the power chip according to the signals at the first control signal terminal and the second control signal terminal, and generate a control signal to provide to the first output module and the second output module; The first output module is electrically connected to the control module, and the first output module is configured to output a first power supply voltage in response to the control signal and a signal at a first power supply signal terminal; The second output module is electrically connected to the control module, and the second output module is configured to output a second power supply voltage in response to the control signal and a signal at a second power supply signal terminal.

2. The power chip according to claim 1, characterized in that: The working modes include: a first working mode; In the first working mode, the control module controls the first output module and the second output module to work independently of each other, the first output module outputs the first power supply voltage through the first output terminal, and the second output module outputs the second power supply voltage through the second output terminal.

3. The power chip according to claim 2, characterized in that: When the signal at the first control signal end and the signal at the second control signal end are both first level signals, and at least one of the signal at the first power signal end and the signal at the second power signal end is a first level signal, the control module determines that it is in the first working mode.

4. The power chip according to claim 1, characterized in that: The working modes include: a second working mode; In the second working mode, the control module controls the first output module to output the first power supply voltage through the third output terminal and the second output module to output the second power supply voltage through the third output terminal.

5. The power chip according to claim 4, characterized in that: When the signal at the first control signal end, the signal at the first power signal end and the signal at the second power signal end are all first level signals and the signal at the second control signal end is a second level signal, the control module determines that it is in the second working mode.

6. The power chip according to claim 1, characterized in that: The working modes include: a third working mode; In the third working mode, the control module controls the first output module to output the first power supply voltage through the third output terminal or the second output module to output the second power supply voltage through the third output terminal.

7. The power chip according to claim 6, characterized in that: The first output module works preferentially, and the second output module works as an alternative. When the first power signal terminal is damaged, the second output module outputs the second power voltage through the third output terminal.

8. The power chip according to claim 6, characterized in that: When the signal at the first power signal terminal and the signal at the second power signal terminal are both first level signals, and the signal at the first control signal terminal and the signal at the second control signal terminal are second level signals, the control module determines that it is in the third working mode.

9. A control method for a power chip according to any one of claims 1 to 8, characterized in that: include: The power chip includes: a control module, a first output module and a second output module; Loading signals to the first control signal terminal, the second control signal terminal, the first power signal terminal, and the second power signal terminal; The control module determines the working mode of the power chip according to the signals at the first control signal terminal and the second control signal terminal, and provides the control signal to the first output module and the second output module; The first output module outputs a first power supply voltage in response to the control signal and a signal at the first power supply signal terminal; the second output module outputs a second power supply voltage in response to the control signal and a signal at the second power supply signal terminal.

10. The control method according to claim 9, characterized in that: The working modes include: a first working mode, a second working mode and a third working mode; In the first working mode, the control module controls the first output module and the second output module to work independently of each other, the first output module outputs the first power supply voltage through the first output terminal, and the second output module outputs the second power supply voltage through the second output terminal; In the second working mode, the control module controls the first output module to output the first power supply voltage through the third output terminal and the second output module to output the second power supply voltage through the third output terminal; In the third working mode, the control module controls the first output module to output the first power supply voltage through the third output terminal or the second output module to output the second power supply voltage through the third output terminal.

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