BCI Optimization Circuit, Optimization Method and Transceiver in LIN Bus

Abstract

The present application provides a BCI optimization circuit, an optimization method and a transceiver in a LIN bus, which are applied to the technical field of LIN transceivers. Among them, the LIN bus is respectively connected to a pull-up path and a pull-down path; the gate of the field-effect transistor in the pull-down path is connected to a gate control module; the gate control module controls the energy coupled to the gate of the field-effect transistor so that the optimization circuit has anti-interference ability. When the LIN bus is at a low level or a high level, the gate control module in the present application controls the energy coupled to the gate of the field-effect transistor, so that the optimization circuit has anti-interference ability, and the rising edge and the falling edge have little difference compared with the case without interference. Moreover, when the LIN transceiver is working and is interfered by BCI, it can still communicate normally without generating communication error codes, thereby improving the reliability and robustness of LIN communication.

Description

Technical Field

[0001] The present application relates to the technical field of LIN transceivers, and particularly to a BCI optimization circuit, an optimization method and a transceiver in a LIN bus. Background Art

[0002] A LIN (Local Interconnect Network) transceiver is a device based on a low-cost serial communication protocol of UART / SCI (Universal Asynchronous Receiver-Transmitter / Serial Communication Interface). A LIN transceiver usually consists of two parts: a transmitter and a receiver. The transmitter is responsible for converting data into an electrical signal and sending it to the receiver through the LIN bus; while the receiver is responsible for receiving the data and converting it into a format that can be read by a computer.

[0003] However, when the LIN transceiver is working, it is easily interfered by BCI (Bulk Current Injection), resulting in difficult normal communication, easy generation of communication error codes, and poor reliability of LIN communication.

[0004] Based on this, a new technical solution is needed. Summary of the Invention

[0005] In view of this, the present application provides a BCI optimization circuit, an optimization method and a transceiver in a LIN bus.

[0006] The present application provides the following technical solutions:

[0007] According to a BCI optimization circuit in a LIN bus provided by the present application, it includes a pull-up path and a pull-down path respectively connected to the LIN bus; the pull-up path is used to pull up the LIN bus to a high-level state, and the pull-down path is used to pull down the LIN bus to a low-level state;

[0008] The pull-down path includes a field effect transistor, and the gate of the field effect transistor is connected to a gate control module; the gate control module controls the energy coupled to the gate of the field effect transistor, so that the optimization circuit has anti-interference ability.

[0009] Preferably, the gate control module includes a current source, a switch and a control resistor;

[0010] One end of the current source is connected to the pull-up path; the other end of the current source is connected to one end of the switch; the other end of the switch is respectively connected to one end of the control resistor and the gate of the field effect transistor;

[0011] The other end of the control resistor is connected to the source electrode of the field effect transistor, and the other end of the control resistor is grounded.

[0012] Preferably, the pull-down path further includes a pull-down diode;

[0013] The positive electrode of the pull-down diode is connected to the LIN bus, and the negative electrode of the pull-down diode is connected to the drain electrode of the field effect transistor.

[0014] Preferably, the pull-up path includes a pull-up diode and a pull-up resistor;

[0015] The positive electrode of the pull-up diode is connected to one end of the current source; the negative electrode of the pull-up diode is connected to one end of the pull-up resistor, and the other end of the pull-up resistor is connected to the LIN bus.

[0016] Preferably, the control resistor is less than the equivalent impedance of the parasitic capacitance C GD between the gate and the drain of the field effect transistor, and the equivalent impedance of the control resistor and the parasitic capacitance C GD differs by more than n times, where n is greater than 5;

[0017] The product of the current source current and the control resistor is greater than the threshold turn-on voltage V TH of the field effect transistor, so as to enable the normal opening and closing of the LIN bus;

[0018] The product of the current source current and the control resistor is less than or equal to the maximum gate withstand voltage of the field effect transistor to ensure the gate withstand voltage of the field effect transistor.

[0019] Preferably, when the switch is closed, the gate voltage of the field effect transistor is the product of the current source current and the control resistor, turning on the field effect transistor to pull the LIN bus to the low level state, and at the same time controlling the energy coupled to the gate of the field effect transistor according to the control resistor to maintain the low level state of the LIN bus.

[0020] Preferably, when the switch is opened, the gate voltage of the field effect transistor is 0, turning off the field effect transistor to pull the LIN bus to the high level state, and controlling the energy coupled to the gate of the field effect transistor according to the control resistor to maintain the high level state of the LIN bus.

[0021] Preferably, the field effect transistor is an N-channel field effect transistor.

[0022] According to an optimization method provided by the present application, applying the BCI optimization circuit in any of the above-mentioned LIN buses includes: the gate control module controls the energy coupled to the gate of the field effect transistor, so that the optimization circuit has anti-interference ability and maintains the level state of the LIN bus.

[0023] A transceiver provided by the present application includes a transmitter, a receiver, a LIN bus, and the BCI optimization circuit in any one of the above-mentioned LIN buses; the transmitter is connected to the receiver through the LIN bus.

[0024] Compared with the prior art, the beneficial effects that can be achieved by at least one of the above technical solutions adopted in the present application at least include:

[0025] When the LIN bus is at a low level or a high level, the gate control module controls the energy coupled to the gate of the field-effect transistor, so that the optimization circuit has anti-interference ability, and the rising edge and the falling edge have little difference compared with the case without interference; moreover, when the LIN transceiver is interfered by BCI during operation, it can still communicate normally without generating communication error codes, thereby improving the reliability and robustness of LIN communication. Description of the Drawings

[0026] In order to more clearly illustrate the technical solutions of the embodiments of the present application, the drawings required for use in the embodiments will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can be obtained based on these drawings.

[0027] Figure 1 It is a schematic diagram of the BCI optimization design circuit of the LIN bus of the present application. Detailed Embodiments

[0028] The embodiments of the present application will be described in detail below with reference to the drawings.

[0029] The following specific examples illustrate the implementation manners of the present application. Those skilled in the art can easily understand other advantages and effects of the present application from the content disclosed in this specification. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. The present application can also be implemented or applied through other different specific implementation manners, and various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present application. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present application without creative efforts belong to the scope of protection of the present application.

[0030] It should be noted that the following description relates to various aspects of embodiments within the scope of the appended claims. It will be apparent that the aspects described herein can be embodied in a wide variety of forms, and any specific structure and / or function described herein is illustrative only. Based on this application, those skilled in the art should understand that one aspect described herein can be implemented independently of any other aspect, and two or more of these aspects can be combined in various ways. For example, any number and aspects set forth herein can be used to implement an apparatus and / or practice a method. Additionally, this apparatus and / or method can be implemented using other structures and / or functionality in addition to one or more of the aspects set forth herein.

[0031] It should also be noted that the diagrams provided in the following embodiments only illustrate the basic concept of this application schematically. Only the components related to this application are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in its actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0032] In addition, in the following description, specific details are provided to facilitate a thorough understanding of the examples. However, those skilled in the art will understand that these examples can be practiced without these specific details.

[0033] The following describes the technical solutions provided by the embodiments of this application in conjunction with the accompanying drawings.

[0034] An embodiment of this specification proposes a BCI optimization circuit in a LIN bus, as Figure 1 shown, including a pull-up path and a pull-down path respectively connected to the LIN bus; the pull-up path is used to pull up the LIN bus to a high-level state, and the pull-down path is used to pull down the LIN bus to a low-level state.

[0035] The pull-down path includes a field-effect transistor, and the gate of the field-effect transistor is connected to a gate control module; the gate control module controls the energy coupled to the gate of the field-effect transistor to enable the optimization circuit to have anti-interference ability.

[0036] In one embodiment, as Figure 1 shown, the gate control module includes a current source, a switch, and a control resistor; one end of the current source is connected to the pull-up path; the other end of the current source is connected to one end of the switch; the other end of the switch is respectively connected to one end of the control resistor and the gate of the field-effect transistor; the other end of the control resistor is connected to the source of the field-effect transistor, and the other end of the control resistor is grounded.

[0037] In one embodiment, as Figure 1 shown, the pull-down path further includes a pull-down diode; the positive electrode of the pull-down diode is connected to the LIN bus, and the negative electrode of the pull-down diode is connected to the drain of the field-effect transistor.

[0038] In one embodiment, as Figure 1 shown, the pull-up path includes a pull-up diode and a pull-up resistor; the positive electrode of the pull-up diode is connected to one end of the current source; the negative electrode of the pull-up diode is connected to one end of the pull-up resistor, and the other end of the pull-up resistor is connected to the LIN bus.

[0039] In one embodiment, the control resistor is less than the equivalent impedance of the parasitic capacitance C GD between the gate and the drain of the field-effect transistor, and the control resistor and the equivalent impedance of the parasitic capacitance C GD differ by more than n times, where n is greater than 5, and preferably n is equal to 10.

[0040] The product of the current source current and the control resistor is greater than the threshold turn-on voltage V TH of the field-effect transistor, so as to enable the normal opening and closing of the LIN bus; the product of the current source current and the control resistor is less than or equal to the maximum gate withstand voltage of the field-effect transistor to ensure the gate withstand voltage of the field-effect transistor.

[0041] In one embodiment, when the switch is closed, the gate voltage of the field-effect transistor is the product of the current source current and the control resistor, turning on the field-effect transistor to pull the LIN bus down to the low level state, and at the same time controlling the energy coupled to the gate of the field-effect transistor according to the control resistor to maintain the LIN bus at the low level state.

[0042] In one embodiment, when the switch is open, the gate voltage of the field-effect transistor is 0, turning off the field-effect transistor to pull the LIN bus up to the high level state, and controlling the energy coupled to the gate of the field-effect transistor according to the control resistor to maintain the LIN bus at the high level state.

[0043] In one embodiment, as Figure 1 shown, the field-effect transistor is an N-channel field-effect transistor.

[0044] As Figure 1 shown, it is the optimized design circuit of the LIN bus BCI of the present application. Among them, D1 and R1 constitute the internal pull-up path of the LIN bus; D2 and NM1 constitute the pull-down control path of the LIN bus, and the current source I1, the switch K2 and the resistor R2 constitute the gate control circuit of the NM1 power transistor. Figure 1 Here, D1 represents the pull-up diode; R1 represents the pull-up resistor; D2 represents the pull-down diode; I1 represents the current source; K2 represents the switch; R2 represents the control resistor; NM1 represents the N-channel field-effect transistor; VBAT represents the power supply voltage.

[0045] When K1 is closed, the gate voltage of NM1 is I1 * R2, turning on the NM1 transistor, thereby pulling down the LIN bus. At this time, if there is BCI interference energy injected into the bus, due to the relatively large current I1 and small resistance R2, R2 should be much smaller than the parasitic capacitance C between the gate and drain of NM1 GD of the equivalent impedance, for example, more than 10 times different. After designing the resistor R2 according to the equivalent impedance of the parasitic capacitance C GD , then design the magnitude of the current source I1. Considering the normal opening and closing of the LIN bus, I1 * R2 should be greater than the threshold opening voltage V of NM1 TH . But at the same time, considering the gate breakdown voltage problem of the NM1 transistor, I1 * R2 should be less than or equal to the maximum gate breakdown voltage of the NM1 transistor. R2 being much smaller than the parasitic capacitance C between the gate and drain of NM1 GD of the equivalent impedance can ensure that the energy coupled to the gate of NM1 is small, thus making it difficult to interfere with the current low - level state of the LIN bus.

[0046] When K1 is open, the gate voltage of NM1 is 0, turning off the NM1 transistor, thereby pulling up the LIN bus to the VBAT power supply. At this time, if there is BCI anti - interference energy injected, due to the small resistance R2, it is difficult for the gate voltages of all NM1s to be coupled together to mis - turn on NM1, thus making it difficult to interfere with the current high - level state of the LIN bus.

[0047] Therefore, the relatively large current source I1 and small resistor R2 make it difficult for BCI interference to be coupled into the internal circuit whether the LIN bus is at a high level or a low level, thus causing misoperation, and ultimately achieving the purpose of enhancing the BCI anti - interference ability of the system.

[0048] This embodiment of the specification also discloses an optimization method, applying the BCI optimization circuit in the LIN bus of any one of the above - mentioned embodiments, including: a gate control module controls the energy coupled to the gate of the field - effect transistor, enabling the optimization circuit to have anti - interference ability and maintaining the level state of the LIN bus.

[0049] This embodiment of the specification also discloses a transceiver, including a transmitter, a receiver, a LIN bus, and the BCI optimization circuit in the LIN bus of any one of claims 1 - 8; the transmitter is connected to the receiver through the LIN bus.

[0050] This application is about a LIN bus BCI optimization circuit and method, which can still communicate normally without generating communication error codes when the LIN transceiver is interfered by BCI, thus ensuring the reliability and robustness of LIN communication. This application features strong anti-BCI interference ability, high integration, simple circuit structure and high reliability. For example, it has strong anti-EMI (Electromagnetic Interference) interference ability. This application can have a strong anti-interference ability of its control circuit whether the LIN bus is at a low level or a high level, so that it will not be misflipped, and the rising edge and falling edge are not much different from those without interference.

[0051] In this specification, for the same or similar parts among the various embodiments, reference can be made to each other. Each embodiment focuses on the differences from other embodiments. In particular, for the embodiments described later, the description is relatively simple, and for the relevant parts, reference can be made to the partial description of the foregoing embodiments.

[0052] The above is only the specific implementation manner of this application, but the protection scope of this application is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by this application should be covered by the protection scope of this application. Therefore, the protection scope of this application should be subject to the protection scope of the claims.

Claims

1. A BCI optimization circuit in a LIN bus, characterized in that: It includes a pull-up path and a pull-down path respectively connected to the LIN bus; the pull-up path is used to pull the LIN bus up to a high level state, and the pull-down path is used to pull the LIN bus down to a low level state; The pull-down path includes a field effect tube, and the gate of the field effect tube is connected to a gate control module; the gate control module controls the energy coupled to the gate of the field effect tube so that the optimized circuit has anti-interference capability; The gate control module includes a current source, a switch and a control resistor; One end of the current source is connected to the pull-up path; the other end of the current source is connected to one end of the switch; the other end of the switch is respectively connected to one end of the control resistor and the gate of the field effect tube; The other end of the control resistor is connected to the source of the field effect transistor, and the other end of the control resistor is grounded; The control resistor is smaller than the parasitic capacitance C between the gate and drain of the field effect tube. GD The equivalent impedance of the control resistor and the parasitic capacitance C GD The equivalent impedance of the resistors differs by more than n times, where n is greater than 5; The current source current multiplied by the control resistance is greater than the threshold turn-on voltage V of the field effect tube TH , so that the LIN bus can be opened and closed normally; The current source current multiplied by the control resistance is less than or equal to the maximum gate withstand voltage of the field effect tube to ensure the gate withstand voltage of the field effect tube; When the switch is closed, the gate voltage of the field effect tube is the current source current multiplied by the control resistance, the field effect tube is turned on, the LIN bus is pulled down to a low level state, and the energy coupled to the gate of the field effect tube is controlled according to the control resistance to keep the LIN bus in a low level state; When the switch is disconnected, the gate voltage of the field effect tube is 0, the field effect tube is turned off, the LIN bus is pulled up to a high level state, and the energy coupled to the gate of the field effect tube is controlled according to the control resistor to maintain the high level state of the LIN bus.

2. The BCI optimization circuit in the LIN bus according to claim 1, characterized in that: The pull-down path also includes a pull-down diode; The anode of the pull-down diode is connected to the LIN bus, and the cathode of the pull-down diode is connected to the drain of the field effect transistor.

3. The BCI optimization circuit in the LIN bus according to claim 1, characterized in that: The pull-up path includes a pull-up diode and a pull-up resistor; The anode of the pull-up diode is connected to one end of the current source; the cathode of the pull-up diode is connected to one end of the pull-up resistor, and the other end of the pull-up resistor is connected to the LIN bus.

4. The BCI optimization circuit in the LIN bus according to any one of claims 1 to 3, characterized in that: The field effect transistor is an N-channel field effect transistor.

5. An optimization method, characterized in that: The BCI optimization circuit in the LIN bus according to any one of claims 1 to 4 includes: a gate control module controls the energy coupled to the gate of the field effect transistor, so that the optimization circuit has anti-interference ability and maintains the level state of the LIN bus.

6. A transceiver, characterized in that: The invention comprises a transmitter, a receiver, a LIN bus and a BCI optimization circuit in the LIN bus as described in any one of claims 1 to 4; the transmitter is connected to the receiver via the LIN bus.

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