Link performance measurement algorithm of TWAMP-Light model based on FPGA
By implementing the link performance measurement algorithm of the TWAMP-Light model on FPGA, the problem of lack of effective performance statistics tools in traditional IP networks is solved, and accurate measurement and optimization of network link performance is achieved.
Patent Information
- Application Number
- CN202411516036.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-10-29
- Publication Date
- 2025-02-07
AI Technical Summary
In traditional IP networks, effective, lightweight, and universal OAM performance statistics tools are lacking, making it difficult to fully understand and measure network performance, especially in large network environments.
The link performance measurement algorithm based on FPGA is adopted. Through the collaboration between the Sender and the Responder, the test-request and Test-response packets carry link information and timestamps to calculate the link delay. , packet loss rate and jitter.
It realizes effective measurement of network link performance, provides accurate data of delay, packet loss rate and jitter, helping network administrators to make timely adjustments and optimizations to meet business needs.
Smart Images
Figure CN119402387A_ABST
Abstract
Description
Technical Field
[0001] The present invention relates to the field of data communication technology, and in particular to a link performance measurement algorithm of a TWAMP-Light model based on FPGA. Background Art
[0002] With the rapid development of network technology and the deepening of related applications, as well as the increasing demands that come with it, the network is carrying more and more services, such as videos, games, and especially in large-scale network environments, such as mobile networks and data centers, which have put forward higher and higher requirements for network performance (packet loss, latency, etc.). At the same time, the detection of network link performance is becoming more and more important.
[0003] Therefore, enterprise networks need standard-based, effective performance monitoring tools to fully understand the network's latency, jitter, and packet loss, so that the network can be adjusted and optimized in a timely manner based on the test results to meet business needs.
[0004] In traditional IP networks, using standard protocols to measure IP network performance has always been a challenge, and the corresponding IP network performance statistics have always lacked effective, lightweight, and universal OAM performance statistics tools. In order to solve this problem, the IETF IPPM (IP performance monitoring) working group proposed a series of protocols to solve this problem. TWAMP is an IP network OAM performance statistics tool proposed by the working group, and TWAMP technology was developed in this context.
[0005] TWAMP gives large enterprise network operators the flexibility to choose solutions that give them a comprehensive view of network performance through interoperability between all devices deployed in the network. TWAMP measures core and edge IP performance through cooperation between routers and switches in the network. Any two endpoints can interoperate, thus reducing the need for managers to deploy systems that use closed proprietary protocols to measure performance. Summary of the invention
[0006] The purpose of the present invention is to provide a link performance measurement algorithm of the TWAMP-Light model based on FPGA. In the text of the present invention, the Sender end fills the link information to be tested (five-tuple, etc.) configured by the upper layer into the RAM of the corresponding sequence number, fills in the corresponding field according to the message format through the packet sending module, and sends it according to the set period or number. After receiving the Test-request message, the Responder end records the timestamp of the packet receiving moment, and extracts information such as the sequence number and timestamp. Then, according to the reflected message format, the receiving timestamp T2, the sending timestamp T3, and the Sender end sending timestamp T1 are filled in, and the extracted sequence number is brought, which is used for the Sender end to calculate the performance of different links and reflected to the Sender end. After the Sender end receives the reflected Test-response message, the packet receiving module will record the receiving timestamp after receiving the packet, and will extract the four timestamps of this measurement cycle according to the format, calculate the delay and number of the corresponding link (used to calculate the packet loss rate), and store it in the RAM of the corresponding link. Read the stored delay of the last test and calculate the jitter. Also read all delays to calculate the average delay and average jitter.
[0007] In order to achieve the above-mentioned object of the invention, the technical solution of the present invention is:
[0008] According to one aspect of the present invention, a link performance measurement algorithm of a TWAMP-Light model based on FPGA is provided, and the method includes:
[0009] The Test-request message carrying the measurement link information is sent from the Sender end. After receiving the message, the Responder end parses and extracts the corresponding information, records the receiving time, and then re-fills it into the Test-response message and sends it. The Sender end receives and latches the time value information, extracts all time values, and calculates the link quality.
[0010] Step 1: The sender obtains the five-tuple information through the upper-layer configuration, stores it in the RAM of the corresponding sequence number, fills in the corresponding fields according to the message format through the packet sending module, and sends it regularly and quantitatively according to the set period or number.
[0011] Step 2: After receiving the Test-request message, the Responder extracts information such as the sequence number and timestamp, and records the timestamp of the packet receiving time.
[0012] Step 3: The Responder fills in the receiving timestamp T2, sending timestamp T3, and sender sending timestamp T1 according to the reflected message format, and also adds the extracted sequence number for the Sender to calculate the performance of different links.
[0013] Step 4: After the sender receives the reflected Test-response message, the packet receiving module will record the receiving timestamp after receiving the packet, and extract all timestamps according to the format.
[0014] Step 5: The sender calculates the delay and number of the corresponding link (used to calculate the packet loss rate) according to the extracted Sequence Number and all four timestamps, and stores them in the RAM of the corresponding link.
[0015] Step 6: The sender needs to read the stored delay from the last test and calculate the jitter. It also needs to read all delays to calculate the average delay and average jitter.
[0016] According to another aspect of the present invention, a link performance measurement algorithm of a TWAMP-Light model based on FPGA is provided, and the module includes:
[0017] The sending cycle generation module is used to generate the time cycle pulses required for configuration sending, trigger the packet sending enable, and also supports sending packets by the number of packets.
[0018] The timestamp maintenance module is used to generate internal time information and calculate path delay. It is usually maintained by the 125M or 250M clock of synchronous Ethernet.
[0019] The Test-request message generation module is used to generate a Test-request message according to a format when a packet pulse is generated, and carry a sending timestamp T1.
[0020] The Test-request message receiving module is used to latch the receiving timestamp T2 when receiving the Test-request message, and extract the information carried in the message, including the Sequency number and the sending timestamp T1.
[0021] The Test-response message sending module is used to reply after receiving the Test-request message. When sending, it latches the sending timestamp T3, and at the same time puts the timestamp extracted and latched by the receiving module into the message and sends it out.
[0022] The test-response message receiving module is used to receive the reflected test-response message, latch the receiving timestamp T4, and extract the three timestamps and sequence number contained in the message.
[0023] The delay and jitter calculation and storage module calculates the delay of each test cycle according to the formula, then calculates the jitter based on the delay, stores the delay and jitter of all cycles, and calculates the average value. It also counts the number of sent and received packets and calculates the packet loss rate.
[0024] As mentioned above, in step 1, the FPGA needs all the information of the upper layer configuration link measurement, including the test cycle, the number of tests, the test sequence number, the five-tuple information, etc. This information will be stored in the FPGA's RAM, and the RAM depth is the maximum number of TWAMPs that need to be supported simultaneously. When the generated period pulse is 1, the FPGA will poll all the stored RAMs. If the address with a period match and a non-zero number of transmissions is found, the transmission enable will be turned on, the transmission timestamp will be latched, and the information stored in the corresponding address of the RAM will be sent to the packet sending module.
[0025] In steps 2 and 3, the FPGA will latch the receiving timestamp and the information contained in the message, including the sequence number, when receiving the packet. Because the test messages are sent sequentially, they do not need to be stored in RAM. Then the Test-response packet sending module will construct a new Test-response message through the information latched by the packet receiving module, and latch the sending time and reflect it to the Sender end.
[0026] In step 4, the FPGA processing is similar to step 2. After the sender receives the reflected message, it latches the receiving timestamp and extracts the sequence number and all timestamp information according to the format.
[0027] In steps 5 and 6, the FPGA needs to calculate the delay of the corresponding serial number and store the delay value in the RAM corresponding to the serial number. Read the last delay value, calculate the jitter, and store all jitter values in the RAM corresponding to the serial number. The calculation of average delay and jitter will also read all delay values and jitter values in a polling manner and calculate the average value respectively. At the same time, count when receiving the message, calculate the number of sent and received packets in the corresponding period, and calculate the packet loss rate.
[0028] The beneficial effect of the present invention is to provide a link performance measurement algorithm of the TWAMP-Light model based on FPGA. The sender end fills the link information to be tested (five-tuple, etc.) configured by the upper layer into the RAM of the corresponding sequence number, fills in the corresponding field according to the message format through the packet sending module, and sends it according to the set period or number. After receiving the Test-request message, the responder end records the timestamp of the packet receiving time, and extracts the sequence number and timestamp information at the same time. Then, according to the reflected message format, the receiving timestamp T2, the sending timestamp T3, and the sender end sending timestamp T1 are filled in, and the extracted sequence number is brought, which is used for the sender end to calculate the performance of different links and reflected to the sender end. After the sender end receives the reflected Test-response message, the packet receiving module will record the receiving timestamp after receiving the packet, and will extract the four timestamps of the current measurement cycle according to the format, calculate the delay and number of the corresponding link (used to calculate the packet loss rate), and store it in the RAM of the corresponding link. Read the stored delay of the last test and calculate the jitter. It is also necessary to read out all delays to calculate the average delay and average jitter. BRIEF DESCRIPTION OF THE DRAWINGS
[0029] Figure 1 A flowchart of the algorithm steps provided by an embodiment of the present invention.
[0030] Figure 2 A module flow chart provided for an embodiment of the present invention.
[0031] Figure 3 A flow chart of a sending module provided in an embodiment of the present invention.
[0032] Figure 4 A reflection message flow chart provided for an embodiment of the present invention.
[0033] Figure 5 A flow chart of calculating link quality provided by an embodiment of the present invention. DETAILED DESCRIPTION
[0034] According to one aspect of an embodiment of the present invention, a method for link performance measurement algorithm of TWAMP-Light model based on FPGA is provided, such as Figure 1 As shown, the method includes:
[0035] When the link information (quintuple) configured by the upper layer is configured into the RAM of the FPGA:
[0036] Step S101, the sender end fills the link information to be tested (five-tuple, etc.) configured by the upper layer into the RAM of the corresponding sequence number, fills in the corresponding fields according to the message format through the packet sending module, and sends it regularly and quantitatively according to the set period or number.
[0037] Step S102, after receiving the Test-request message, the Responder records the timestamp of the packet receiving time, and extracts information such as the sequence number and timestamp.
[0038] Step S103, according to the reflection message format, fill in the receiving timestamp T2, sending timestamp T3, and sender sending timestamp T1, and carry the extracted sequence number for the sender to calculate the performance of different links and reflect it to the sender.
[0039] Step S104, after the sender receives the reflected Test-response message, the packet receiving module will record the receiving timestamp after receiving the packet, and will extract four timestamps of the current measurement cycle according to the format.
[0040] Step S105, calculating the delay and number of the corresponding links (for calculating the packet loss rate), and storing them in the RAM of the corresponding links.
[0041] Step S106, read the stored delay of the last test and calculate the jitter, and then read out all delays to calculate the average delay and average jitter.
[0042] According to another aspect of an embodiment of the present invention, a module of a link performance measurement algorithm of a TWAMP-Light model based on FPGA is provided, such as Figure 2 As shown, the module includes:
[0043] The sending cycle generation module is used to generate the time cycle pulses required for configuration sending, trigger the packet sending enable, and also supports sending packets by the number of packets.
[0044] The timestamp maintenance module is used to generate internal time information and calculate path delay. It is usually maintained by the 125M or 250M clock of synchronous Ethernet.
[0045] The Test-request message generation module is used to generate a Test-request message according to a format when a packet pulse is generated, and carry a sending timestamp T1.
[0046] The Test-request message receiving module is used to latch the receiving timestamp T2 when receiving the Test-request message, and extract the information carried in the message, including the Sequency number and the sending timestamp T1.
[0047] The Test-response message sending module is used to reply after receiving the Test-request message. When sending, it latches the sending timestamp T3, and at the same time puts the timestamp extracted and latched by the receiving module into the message and sends it out.
[0048] The test-response message receiving module is used to receive the reflected test-response message, latch the receiving timestamp T4, and extract the three timestamps and sequence number contained in the message.
[0049] The delay and jitter calculation and storage module calculates the delay of each test cycle according to the formula, then calculates the jitter based on the delay, stores the delay and jitter of all cycles, and calculates the average value. It also counts the number of sent and received packets and calculates the packet loss rate.
[0050] To further understand the steps and processes of message forwarding, timestamp transmission, delay calculation, etc. provided in the embodiment of the present invention, the following will describe in detail.
[0051] In steps S101 and S102, the FPGA needs all the information of the upper layer configuration link measurement, including the test cycle, the number of tests, the test sequence number, the five-tuple information, etc. This information will be stored in the FPGA's RAM, and the RAM depth is the maximum number of TWAMPs that need to be supported simultaneously. When the generated period pulse is 1, the FPGA will poll all the stored RAMs. If the address with a period match and a non-zero number of transmissions is found, the transmission enable will be turned on, the transmission timestamp will be latched, and the information stored in the corresponding address of the RAM will be sent to the packet sending module.
[0052] The sending module process is as follows Figure 3 As shown:
[0053] Step S401, write link measurement information including a five-tuple.
[0054] Step S402, generating a supported clock cycle pulse.
[0055] Step S403: When the pulse cycle arrives, poll the stored RAM.
[0056] Step S404: The matched link that needs to be sent is connected to the packet sending module to latch the sending time.
[0057] In step S103, the FPGA will latch the receiving timestamp and the information in the message including the sequence number when receiving the packet. Because the test message is sent sequentially, it does not need to be stored in the RAM. Then the Test-response packet sending module will construct a new Test-response message through the information latched by the packet receiving module, and latch the sending time and reflect it to the Sender end.
[0058] In step S104, the FPGA processing is similar to step 2. After the sender receives the reflected message, it latches the receiving timestamp and extracts the sequence number and all timestamp information according to the format.
[0059] The reflection message process is as follows Figure 4 As shown:
[0060] Step S401, receiving a message, extracting information, and latching a time value.
[0061] Step S402, fill in information, latch time value, and reflect message.
[0062] In steps S105 and S106, the FPGA needs to calculate the delay of the corresponding serial number and store the delay value in the RAM corresponding to the serial number. Read the last delay value, calculate the jitter, and store all jitter values in the RAM corresponding to the serial number. The calculation of average delay and jitter will also read all delay values and jitter values in a polling manner, and calculate the average value respectively. At the same time, count when receiving the message, calculate the number of sent and received packets in the corresponding period, and calculate the packet loss rate.
[0063] The link quality calculation process is as follows: Figure 5 As shown:
[0064] Step S501, after receiving the message, get all 4 timestamps, calculate the delay according to the formula, and store it in the RAM corresponding to the sequence number.
[0065] Step S502, reading the delay of the previous cycle and calculating the jitter.
[0066] Step S503: poll and read all delays and jitters in the RAM, and calculate the average delay and jitter.
Claims
1. A link performance measurement algorithm based on the TWAMP-Light model of FPGA, characterized in that: The method comprises: The Sender sends the corresponding Test-request message through the upper layer configuration. After receiving the message, the Responder adds the timestamp and other information to the corresponding position and reflects it back. After receiving and parsing the reflected message, the Sender can calculate the link performance based on a series of algorithms. Step 1: The sender obtains the five-tuple information through the upper layer configuration, stores it in the RAM of the corresponding sequence number, fills in the corresponding fields according to the message format through the packet sending module, and sends it regularly and quantitatively according to the set period or number; Step 2: After receiving the Test-request message, the Responder extracts information such as the sequence number and timestamp, and records the timestamp of the packet receiving time; Step 3: The Responder fills in the receiving timestamp T2, sending timestamp T3, and sender sending timestamp T1 according to the reflected message format, and also adds the extracted sequence number for the Sender to calculate the performance of different links. Step 4: After the sender receives the reflected Test-response message, the packet receiving module will record the receiving timestamp after receiving the packet, and extract all timestamps according to the format; Step 5: The sender calculates the delay and number of the corresponding link (used to calculate the packet loss rate) according to the extracted SequenceNumber and all four timestamps, and stores them in the RAM of the corresponding link; Step 6: The sender needs to read the stored delay from the last test and calculate the jitter; it also needs to read all delays to calculate the average delay and average jitter.
2. According to claim 1, a link performance measurement algorithm of the TWAMP-Light model based on FPGA is characterized in that: The modules include: The sending cycle generation module is used to generate the pulses of each time period required for configuration sending, trigger the packet sending enable, and also supports sending packets by the number of packets; Timestamp maintenance module, used to generate internal time information and calculate path delay; usually uses synchronous Ethernet 125M or 250M clock maintenance; The Test-request message generation module is used to generate a Test-request message according to the format when the packet pulse is generated, and carry a sending timestamp T1; A Test-request message receiving module is used to latch the receiving timestamp T2 when receiving the Test-request message, and extract the information carried by the message, including the Sequency number and the sending timestamp T1; The Test-response message sending module is used to reply after receiving the Test-request message; when sending, it latches the sending timestamp T3, and at the same time puts the timestamp extracted and latched by the receiving module into the message and sends it out; Test-response message receiving module, used to receive the reflected Test-response message, latch the receiving timestamp T4, and extract the three timestamps and Sequence number contained in the message; The delay and jitter calculation and storage module calculates the delay of each test cycle according to the formula, and then calculates the jitter based on the delay, stores the delay and jitter of all cycles, and calculates the average value; counts the number of sent and received packets, and calculates the packet loss rate.
3. According to the link performance measurement algorithm of the FPGA-based TWAMP-Light model according to claim 1, it is characterized in that: In step 1, the FPGA needs the upper layer to configure all the information of the link measurement, including the test cycle, the number of tests, the test sequence number, the five-tuple information, etc. This information will be stored in the FPGA's RAM. The RAM depth is the maximum number of TWAMPs that need to be supported simultaneously. When the generated periodic pulse is 1, FPGA will poll all the RAMs stored. If an address with a period match and a non-zero number of transmissions is found, the transmission enable will be turned on, the transmission timestamp will be latched, and the information stored in the corresponding address of RAM will be sent to the packet sending module. In steps 2 and 3, the FPGA will latch the receiving timestamp and information contained in the message including the sequnencenumber when receiving the packet. Because the test messages are sent sequentially, they do not need to be stored in the RAM. Then the Test-response packet sending module will construct a new Test-response message through the information latched by the packet receiving module, and latch the sending time at the same time, and reflect it to the Sender end; In step 4, the FPGA processing is similar to step 2. After the sender receives the reflected message, it latches the receiving timestamp and extracts the sequence number and all timestamp information according to the format. In steps 5 and 6, the FPGA needs to calculate the delay of the corresponding serial number, store the delay value in the RAM corresponding to the serial number, read the last delay value, calculate the jitter, and store all jitter values in the RAM corresponding to the serial number. The calculation of the average delay and jitter will also be carried out in a polling manner. All delay values and jitter values are read out, and the average values are calculated respectively. At the same time, count when receiving the message, calculate the number of sent and received packets in the corresponding period, and calculate the packet loss rate.