Projection image correction system and projection image correction method

Abstract

The invention discloses a projection image correction system and a projection image correction method, and relates to the technical field of projection image correction. The projected image correction system includes a state control circuit and a data output circuit. The state control circuit issues a read request to the first memory to obtain first pixel information when the read request corresponding to the interpolation operation is not sent to the first memory, stores the first pixel information to the second memory, and counts the number of times the read request is sent to the first memory to generate a first count value. The data output circuit counts according to the write-in completion signal to generate a second count value, and when the second count value is the same as the first count value, obtains a plurality of pieces of second pixel information required by the interpolation operation from the second memory to the interpolation device so as to execute the interpolation operation. The write completion signal indicates that the first pixel information has been stored in the second memory, and the plurality of second pixel information includes the first pixel information.

Description

Technical Field

[0001] The present invention relates to the technical field of projection image correction, and in particular to a projection image correction system and a projection image correction method. Background Art

[0002] The projected image displayed by the projector usually has distortion (e.g., trapezoidal distortion). In order to correct the above-mentioned projected image, the projection image correction system can usually obtain the neighboring pixel information of the distorted image area to perform interpolation operations, thereby correcting the distorted image area. In the prior art, the control mechanism of the line buffer or the general high-speed memory is used to implement the data access mechanism of the projection image correction system. In the setting method of the line buffer, a large storage space and hardware cost are required to temporarily store the pixel information for the correction image; and in the setting method of the general high-speed memory, a cache line in the high-speed memory can only be read / written once in one cycle, and the next read / write request can only be processed after processing one read / write request, causing the projection image correction system to spend a lot of time on data access, making the overall processing efficiency significantly poor. Summary of the invention

[0003] In some embodiments, one of the purposes of the present application is to provide a projection image correction system and a projection image correction method having a high-speed memory mechanism capable of continuously receiving and sending read requests, so as to improve the deficiencies of the prior art.

[0004] In some embodiments, the projection image correction system includes a state control circuit and a data output circuit. The state control circuit sends the at least one read request to a first memory when the at least one read request corresponding to an interpolation operation has not been sent to the first memory, so as to obtain at least one first pixel information from the first memory, store the at least one first pixel information to a second memory, and count the number of times the at least one read request is sent to the first memory to generate a first count value. The data output circuit counts according to at least one write completion signal to generate a second count value, and obtains a plurality of second pixel information to be used in the interpolation operation from the second memory to an interpolation device when the second count value is the same as the first count value, so that the interpolation device performs the interpolation operation according to the plurality of second pixel information. The at least one write completion signal indicates that the at least one first pixel information has been stored in the second memory, and the plurality of second pixel information includes the at least one first pixel information.

[0005] In some embodiments, a projection image correction method performed by a projection image correction system includes the following operations: issuing at least one read request corresponding to an interpolation operation to a first memory when the at least one read request has not been sent to the first memory to obtain at least one first pixel information from the first memory, and storing the at least one first pixel information to a second memory in the projection image correction system; counting the number of times the at least one read request is sent to the first memory to generate a first count value; counting according to at least one write completion signal to generate a second count value; and obtaining a plurality of second pixel information to be used in the interpolation operation from the second memory to an interpolation device when the second count value is the same as the first count value, so that the interpolation device performs the interpolation operation according to the plurality of second pixel information, wherein the at least one write completion signal indicates that the at least one first pixel information has been stored in the second memory, and the plurality of second pixel information includes the at least one first pixel information.

[0006] The features, implementation and effects of the present application are described in detail below with reference to the accompanying drawings. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Figure 1 A schematic diagram of a projection image correction system drawn according to some embodiments of the present application;

[0008] Figure 2 According to some embodiments of the present application, Figure 1 A schematic diagram of a memory in FIG.

[0009] Figure 3 According to some embodiments of the present application, Figure 1 A schematic diagram of a state control circuit;

[0010] Figure 4 According to some embodiments of the present application, Figure 1 A schematic diagram of the reordering operation of the data sorting circuit;

[0011] Figure 5 According to some embodiments of the present application, Figure 1 A schematic diagram of a data output circuit;

[0012] Fig. 6A According to some embodiments of the present application, Figure 1 A flowchart of a first part of the operation of the projection image correction system performing an interpolation operation;

[0013] Figure 6B According to some embodiments of the present application, Figure 1 A flowchart of a second part of the operation of the projection image correction system performing the interpolation operation;

[0014] Figure 7 According to some embodiments of the present application, Figure 1 A timing diagram of a projection image correction system executing multiple read requests; and

[0015] Figure 8 This is a schematic diagram of a projection image correction method drawn according to some embodiments of the present application.

[0016] 100: Projection image correction system;

[0017] 101: Projection keystone correction device;

[0018] 102: interpolation device;

[0019] 103: memory;

[0020] 110: address decoding circuit;

[0021] 120: memory;

[0022] 122, 124, 126, 128: storage repository;

[0023] 130: confirm the circuit;

[0024] 140: data sorting circuit;

[0025] 150: First-in, first-out circuit;

[0026] 160: state control circuit;

[0027] 170: data output circuit;

[0028] 180: data writing circuit;

[0029] 310: controller;

[0030] 320, 330: register;

[0031] 340, 520: First-in, first-out circuit;

[0032] 510: counter;

[0033] 530: output circuit;

[0034] 800: Projection image correction method;

[0035] add_req: address request signal;

[0036] AddXX: address signal;

[0037] CT1, CT2: count value;

[0038] DIN: original image data;

[0039] DL: lower left corner information;

[0040] DR: lower right corner information;

[0041] EE: pixel information;

[0042] EO: pixel information;

[0043] OE: pixel information;

[0044] OO: pixel information;

[0045] Req: at least one read request;

[0046] Rreq: at least one sent request;

[0047] S605, S610, S615, S620, S625, S630, S635, S640, S645, S650: operation;

[0048] S810, S820, S830, S840: operation;

[0049] SC: at least one write completion signal;

[0050] TT: target label value;

[0051] Td: delay time;

[0052] UL: upper left corner information;

[0053] UR: upper right corner information. DETAILED DESCRIPTION

[0054] All words used in this application have their usual meanings. The definitions of the above words in commonly used dictionaries and the use examples of any words discussed herein included in the content of this application are only illustrative and should not limit the scope and meaning of this application. Similarly, this application is not limited to the various embodiments shown in this specification.

[0055] As used herein, "coupled" or "connected" may refer to two or more elements making direct physical or electrical contact with each other, or making indirect physical or electrical contact with each other, or may refer to two or more elements operating or acting on each other. As used herein, the term "circuit" may refer to a device composed of at least one transistor and / or at least one active and passive element connected in a certain manner to process signals.

[0056] Figure 1Schematic diagram of a projection image correction system 100 drawn according to some embodiments of the present application. In some embodiments, the projection trapezoidal correction device 101 can output an address request signal add_req to the projection image correction system 100 according to an image correction algorithm (for example, but not limited to, interpolation correction) executed on the distorted image, so that the projection image correction system 100 can provide all pixel information (hereinafter referred to as multiple second pixel information) to be used for performing an interpolation operation to the interpolation device 102, so that the interpolation device 102 can perform the interpolation operation according to the multiple second pixel information, thereby correcting the distortion in the projection image.

[0057] The projection image correction system 100 includes an address decoding circuit 110, a memory 120, a confirmation circuit 130, a data sorting circuit 140, a first-in first-out (FIFO) circuit 150, a state control circuit 160, a data output circuit 170, and a data writing circuit 180. The address decoding circuit 110 can receive an address request signal add_req from the projection keystone correction device 101, and decode the address request signal add_req to obtain a plurality of address signals AddXX, and transmit the address signals AddXX to the memory 120.

[0058] The memory 120 includes a storage memory 122, a storage memory 124, a storage memory 126, and a storage memory 128. In some embodiments, the storage memory 122, the storage memory 124, the storage memory 126, and the storage memory 128 can store a plurality of pixel information of the original image data DIN in a preset order. For example, the memory 120 is also coupled to the memory 103 via the data writing circuit 180, wherein the memory 103 stores a plurality of original pixel information of the original image data DIN. The memory 120 can obtain the original image data DIN from the memory 103 via the data writing circuit 180, and store the plurality of original pixel information of the original image data DIN in the storage memory 122, the storage memory 124, the storage memory 126, and the storage memory 128 in a preset order. This will be referred to below. Figure 2 illustrate.

[0059] The confirmation circuit 130 can read out a plurality of pixel information (hereinafter referred to as a plurality of third pixel information) from the memory bank 122, the memory bank 124, the memory bank 126, and the memory bank 128 according to these address signals AddXX. In some embodiments, the memory 103 is a dynamic random access memory, and the memory 120 is a static random access memory. The confirmation circuit 130 can confirm whether each of the plurality of third pixel information meets a preset condition. For example, each third pixel information includes a tag value and a valid value. The confirmation circuit 130 compares the tag value of a corresponding one of the plurality of third pixel information with a target tag value TT to confirm whether the tag value of the corresponding one is the same as the target tag value TT, and confirm whether the valid value of the corresponding one is a preset value. If the tag value of the corresponding one is the same as the target tag value and the valid value of the corresponding one is a preset value, the confirmation circuit 130 can confirm that the corresponding one of the plurality of third pixel information meets the preset condition (equivalent to a read hit). Alternatively, if the tag value of the correspondent is different from the target tag value and / or the effective value of the correspondent is not the preset value, the confirmation circuit 130 may confirm that the correspondent of the plurality of third pixel information does not meet the preset condition (equivalent to a read miss). Similarly, the confirmation circuit 130 may confirm whether each of the plurality of third pixel information meets the preset condition.

[0060] In some embodiments, the aforementioned valid value is used to indicate whether the corresponding third pixel information is in a valid state (e.g., an available state). For example, when the valid value is a first logic value, the corresponding third pixel information is in a valid state; conversely, when the valid value is a second logic value, the corresponding third pixel information is in an invalid state and cannot be used for interpolation operations. In some embodiments, the address decoding circuit 110 may decode the address request signal add_req to obtain the aforementioned target tag value TT, and provide the target tag value TT to the confirmation circuit 130. In some embodiments, the confirmation circuit 130 may be implemented by a comparator circuit, but the present application is not limited thereto.

[0061] The data sorting circuit 140 is coupled to the confirmation circuit 130, and determines that the memory 120 lacks at least one first pixel information based on the confirmation result of the confirmation circuit 130 (for example, corresponding to the result of a read miss), and accordingly issues at least one read request Req to obtain the at least one first pixel information from the memory 103 via the state control circuit 160. The at least one first pixel information missing from the memory 120 corresponds to at least one of the plurality of third pixel information that does not meet the aforementioned preset condition. In addition, based on the confirmation result of the confirmation circuit 130, the data sorting circuit 140 also reorders each of the plurality of third pixel information that meets the aforementioned preset condition and at least one first address signal of the plurality of address signals AddXX (which corresponds to the aforementioned at least one first pixel information), and accordingly outputs each of the plurality of third pixel information that meets the aforementioned preset condition and the at least one first address signal after reordering to the first-in-first-out circuit 150. This will be referred to below. Figure 4 illustrate.

[0062] The state control circuit 160 sends the at least one read request Req to the memory 103 when the at least one read request Req has not been sent to the memory 103, so as to obtain the at least one first pixel information from the memory 103 and store the at least one first pixel information in the memory 120 accordingly. In this process, the state control circuit 160 also counts the number of times the at least one read request Req is sent to the memory 103 to generate a count value CT1. The relevant configuration method of the state control circuit 160 will be referred to below. Figure 3 illustrate.

[0063] Specifically, the state control circuit 160 issues at least one read request Req to the data write circuit 180. The data write circuit 180 can obtain at least one first address signal (which can indicate the position information of the at least one first pixel information in the original image data DIN) according to the at least one read request Req, so as to read the at least one first pixel information from the memory 103. Accordingly, the data write circuit 180 can store the at least one first pixel information in the memory 120, and issue at least one write completion signal SC to the data output circuit 170, wherein the at least one write completion signal SC is used to indicate that the at least one first pixel information has been stored in the memory 120. Accordingly, the data output circuit 170 can count according to the at least one write completion signal SC to generate another count value (e.g. Figure 5The data output circuit 170 obtains the plurality of second pixel information (including the at least one first pixel information and each of the plurality of third pixel information that meets the aforementioned preset conditions) required for performing an interpolation operation from the memory 120 and the data sorting circuit 140 (via the first-in-first-out circuit 150) when the count value CT2 is the same as the count value CT1 within the same time period. In this way, the data output circuit 170 can output the plurality of second pixel information to the interpolation device 102 for performing an interpolation operation, thereby correcting the projected image.

[0064] Figure 2 According to some embodiments of the present application, Figure 1 Schematic diagram of the memory 120 in FIG. As described above, the memory bank 122, the memory bank 124, the memory bank 126, and the memory bank 128 of the memory 120 can store a plurality of raw pixel information of the raw image data DIN in a preset order. For example, based on the coordinate position in the raw image data DIN, a plurality of raw pixel information can be stored in the memory bank 122, the memory bank 124, the memory bank 126, and the memory bank 128 in the order of even rows and even columns, even rows and odd columns, odd rows and even columns, and odd rows and odd columns (i.e., the preset order described above), wherein each piece of raw pixel information stored in the memory 120 may include a label value, a valid value, and a pixel data value. The memory bank 122, the memory bank 124, the memory bank 126, and the memory bank 128 can be accessed independently. In some related arts, the projection image correction system can only read out a plurality of pixel data sequentially from the memory in a plurality of cycles, resulting in a low overall processing efficiency. Different from the above-mentioned related art, through the above-mentioned configuration, the projection image correction system 100 can obtain a plurality of pixel information from the storage memory 122 , the storage memory 124 , the storage memory 126 and the storage memory 128 in the same time period to perform the interpolation operation more efficiently.

[0065] Figure 3 According to some embodiments of the present application, Figure 1 In some embodiments, the state control circuit 160 records at least one sent request Rreq, and compares at least one read request Req with at least one sent request Rreq to confirm whether the at least one read request Req has not been sent to the memory 103. Figure 3As shown, the state control circuit 160 includes a controller 310, a register 320, a register 330 and a first-in-first-out circuit 340. The controller 310 receives at least one read request Req and at least one write completion signal SC. The register 320 stores the relevant information of at least one sent request Rreq (for example, it can be, but not limited to, the location information of the pixel information to be accessed by at least one sent request Rreq). The controller 310 can compare whether the received at least one read request Req is the same as the at least one sent request Rreq in the register 320. If the at least one read request Req is the same as the at least one sent request Rreq, it means that the at least one read request Req has been sent to the memory 103 by the data writing circuit 180. Under this condition, the controller 310 will not repeatedly send at least one read request Req to the memory 103.

[0066] On the other hand, if the at least one read request Req is different from the at least one sent request Rreq, it means that the at least one read request Req has never been sent to the memory 103 by the data write circuit 180. Under this condition, the controller 310 will issue the at least one read request Req to the memory 103 via the data write circuit 180. For example, when the at least one read request Req is different from the at least one sent request Rreq, the controller 310 may issue the at least one read request Req to the FIFO circuit 340, thereby issuing the at least one read request Req to the data write circuit 180 via the FIFO circuit 340, and issuing the at least one read request Req to the memory 103 via the data write circuit 180. At the same time, the controller 310 will store the at least one read request Req in the register 320 to update the at least one sent request Rreq (i.e., record the at least one read request Req as one of the at least one sent request Rreq), and count the number of times the at least one read request Req is sent to the memory 103 to generate a count value CT1. The register 330 is further used to store the count value CT1.

[0067] In some embodiments, the data sorting circuit 140 simultaneously sends a flag signal (not shown) when sending the last read request in at least one read request Req, thereby notifying the controller 310 that the last read request corresponding to an interpolation operation has been sent. Accordingly, after the count value CT1 has been transmitted to the data output circuit 170, the controller 310 can reset the count value CT1 to 0 according to the flag signal to prepare for counting the number of times the at least one read request Req corresponding to the next interpolation operation is sent. In some embodiments, the controller 310 can be implemented via a microcontroller circuit or a digital signal processing circuit capable of executing a state machine, but the present application is not limited thereto.

[0068] In other embodiments, the state control circuit 160 may include more registers (not shown) that may be used to temporarily store at least one first pixel information, so that the data output circuit 170 may directly obtain the at least one first pixel information from these registers (rather than from the memory 120). In this way, the waiting time for the data output circuit 170 to obtain the at least one first pixel information may be reduced, thereby further improving the overall data access efficiency.

[0069] Figure 4 According to some embodiments of the present application, Figure 1 Schematic diagram of the reordering operation of the data sorting circuit 140. In some embodiments, each of the plurality of address signals Addxx may further include an offset information. If the confirmation circuit 130 confirms that the third pixel information read out from the memory 120 meets the preset condition (i.e., read hit), the data sorting circuit 140 may read the corresponding number of bits from the pixel data value of the third pixel information according to the offset information corresponding to the third pixel information, and reorder the same. Alternatively, if the confirmation circuit 130 confirms that the third pixel information read out from the memory 120 does not meet the preset condition (i.e., read miss), the data sorting circuit 140 may reorder at least one address signal corresponding to the third pixel information that does not meet the preset condition. Specifically, the confirmation circuit 130 may take out one third pixel information from each of the memory banks 122, 124, 126, and 128 in the same time period based on the address signals AddXX corresponding to an address request signal add_req, and the corresponding pixel points are respectively located at positions such as even rows and even columns, even rows and odd columns, odd rows and even columns, and odd rows and odd columns in the original image data DIN. However, in the interpolation operation, the positions of these pixels will be classified as the upper left corner, the upper right corner, the lower left corner and the lower right corner in the image coordinates. The reordering performed by the data sorting circuit 140 is to complete the above position conversion.

[0070] like Figure 4 As shown, the third pixel information read out from the memory bank 122 is marked as pixel information EE, the third pixel information read out from the memory bank 124 is marked as pixel information EO, the third pixel information read out from the memory bank 126 is marked as pixel information OE, and the third pixel information read out from the memory bank 128 is marked as pixel information OO, which are arranged in a preset order of even rows and even columns, even rows and odd columns, odd rows and even columns, and odd rows and odd columns. In the reordering process, the pixel information EE, the pixel information EO, the pixel information OE, and the pixel information OO are rearranged into upper left corner information UL, upper right corner information UR, lower left corner information DL, and lower right corner information DR according to the mapping coordinates of the corresponding pixels, and are input into the first-in-first-out circuit 150 accordingly.

[0071] It should be understood that if a corresponding pixel information among pixel information EE, pixel information OE, pixel information EO and pixel information OO meets the aforementioned preset conditions, the content of the corresponding pixel information is the corresponding several bits in the aforementioned pixel data value. On the contrary, if the corresponding pixel information does not meet the aforementioned preset conditions (i.e., read miss), the content of the corresponding pixel information is the address signal corresponding to the corresponding pixel information (i.e., the aforementioned at least one first address signal). In other words, in the reordered data, there are address signals corresponding to the pixel information that has not been read and the pixel information that has been read. In this way, the data output circuit 170 can read out the pixel information that was not read (i.e., at least one first pixel information) from the memory 120 according to the address signal in subsequent operations, and read the corresponding several bits in the pixel data value therefrom, and use these bits to replace the data part of the corresponding address signal in the reordered data, thereby providing the interpolation device 102 with a plurality of second pixel information required to perform this interpolation operation.

[0072] Figure 5 According to some embodiments of the present application, Figure 1 The data output circuit 170 is a schematic diagram of the data output circuit 170. The data output circuit 170 includes a counter 510, a first-in-first-out circuit 520, and an output circuit 530. The counter 510 receives at least one write completion signal SC from the data write circuit 180, and counts the received at least one write completion signal SC to generate a count value CT2. The first-in-first-out circuit 520 receives the count value CT1 from the state control circuit 160. The output circuit 530 obtains the count value CT1 from the first-in-first-out circuit 520, and when the count value CT2 is the same as the count value CT1 (equivalent to that all at least one read request Req corresponding to an address request signal add_req has been sent to the memory 103, and the memory 120 has completed obtaining all the missing at least one first pixel information from the memory 103), obtains at least one first pixel information from the memory 120 and obtains the reordered at least one first address signal and each of the plurality of third pixel information that meets the preset condition from the data sorting circuit 140, and replaces the content of the at least one first address signal with the at least one first pixel information, thereby outputting the reordered at least one first pixel information and each of the plurality of third pixel information that meets the preset condition as the plurality of second pixel information, so as to provide the pixel information required for the interpolation device 102 to perform the interpolation operation.

[0073] Fig. 6A According to some embodiments of the present application, Figure 1 A flowchart of a first part of the operation of the projection image correction system 100 performing an interpolation operation, and Figure 6B According to some embodiments of the present application, Figure 1 Flow chart of the second part of the operation of the projection image correction system 100 performing the interpolation operation. In operation S605, the address request signal add_req is received from the projection trapezoid correction device 101. In operation S610, the address decoding circuit 110 decodes the address request signal add_req to obtain a plurality of address signals AddXX. For example, Figure 2 and Figure 4 As shown, the third pixel information stored in the memory bank 122, the memory bank 124, the memory bank 126 and the memory bank 128 are pixel information EE, pixel information EO, pixel information OE and pixel information OO respectively. The address decoding circuit 110 can decode the address request signal add_req according to the pixel image coordinate relationship of the original image data DIN to obtain a plurality of address signals AddXX, wherein XX can correspond to the aforementioned plurality of pixel information EE, EO, OE and OO. For example, the address signal AddEE can represent a corresponding storage address in the memory bank 122, the address signal AddEO can represent a corresponding storage address in the memory bank 124, the address signal AddOE can represent a corresponding storage address in the memory bank 126, and the address signal AddEE can represent a corresponding storage address in the memory bank 128.

[0074] Continue to refer to Fig. 6A In operation S615, the confirmation circuit 130 reads out a plurality of third pixel information from the memory bank 122, the memory bank 124, the memory bank 126, and the memory bank 128 according to the address signals AddXX. In operation S620, the confirmation circuit 130 confirms whether each of the plurality of third pixel information meets a preset condition (i.e., whether the read hits), so as to selectively generate a first or second confirmation result. If so, the confirmation circuit 130 generates a first confirmation result to indicate that the third pixel information meets the preset condition; if not, the confirmation circuit 130 generates a second confirmation result to indicate that the third pixel information does not meet the preset condition. In operation S625, the data sorting circuit 140 determines at least one first pixel information missing from the memory 120 based on the second confirmation result of the confirmation circuit 130 and issues at least one read request Req accordingly, wherein the at least one first pixel information corresponds to each of the plurality of third pixel information that does not meet the preset condition. In operation S630, the data sorting circuit 140 reorders at least one first address signal corresponding to the at least one first pixel information in the plurality of address signals AddXX and each of the plurality of third pixel information that meets the preset condition (eg, Figure 4 As shown), and transmits the reordered at least one first address signal and each of the plurality of third pixel information that meets the preset condition to the first-in-first-out circuit 150.

[0075] Reference Figure 6BIn operation S635, the state control circuit 160 confirms whether the at least one read request Req has been sent to the memory 103, and sends the at least one read request Req to the memory 103 via the data writing circuit 180 when the at least one read request Req has not been sent to the memory 103. In operation S640, the state control circuit 160 counts the number of times the at least one read request Req is sent to the memory 103 to generate a count value CT1. In operation S645, the data writing circuit 180 reads at least one first pixel information from the memory 103 according to the at least one read request Req, stores the read at least one first pixel information in the memory 120, and sends at least one write completion signal SC.

[0076] In operation S650, the data output circuit 170 counts according to at least one write completion signal SC to generate a count value CT2, and when the count value CT2 is the same as the count value CT1, reads at least one first pixel information from the memory 120 and reads out at least one reordered first address signal and each of the plurality of third pixel information that meets the preset condition from the first-in-first-out circuit 150, and replaces at least one first address signal with at least one first pixel information, so as to output each of the plurality of reordered third pixel information that meets the preset condition and at least one first pixel information as a plurality of second pixel information used by the interpolation device 102 to perform an interpolation operation.

[0077] The description of the above-mentioned multiple operations can refer to the above-mentioned multiple embodiments, so it will not be repeated here. The above-mentioned multiple operations are not just examples, and are not limited to being executed in the order in this example. Without violating the operation mode and scope of each embodiment of the present application, these operations can be appropriately added, replaced, omitted, executed in a different order, or can be executed simultaneously or partially simultaneously.

[0078] Figure 7 According to some embodiments of the present application, Figure 1 Schematic diagram of the timing of the projection image correction system 100 executing multiple read requests. In some embodiments, the state control circuit 160 can temporarily store at least one read request Req of the number of bathrooms (greater than 1) through the first-in-first-out circuit 340, thereby realizing the ability to continuously receive multiple read requests (which correspond to at least one read request Req) and continuously send multiple read requests to the memory 103. In other words, the projection image correction system 100 can realize continuous and partially parallel data access to reduce the influence of the delay time Td of reading pixel information from the memory 120.

[0079] In some related technologies, the projection image correction system needs to process a read request (i.e., respond to a read request and read the required pixel information from the high-speed memory) before processing the next read request. This will significantly reduce the overall processing efficiency. Figure 7 As shown, the state control circuit 160 can realize continuous reception of multiple read requests and continuous transmission of multiple read requests, thereby improving the overall processing efficiency.

[0080] Figure 8 FIG. 8 is a schematic diagram of a projection image correction method 800 drawn according to some embodiments of the present application. In some embodiments, the projection image correction method 800 may be, but is not limited to, Figure 1 The projection image correction system 100 is performed.

[0081] In operation S810, when at least one read request corresponding to an interpolation operation has not been sent to a first memory, the at least one read request is sent to the first memory to obtain at least one first pixel information from the first memory, and the at least one first pixel information is stored in a second memory in the projection image correction system. In operation S820, the number of times the at least one read request is sent to the first memory is counted to generate a first count value. In operation S830, counting is performed according to at least one write completion signal to generate a second count value. In operation S840, when the second count value is the same as the first count value, a plurality of second pixel information to be used in the interpolation operation is obtained from the second memory to an interpolation device, so that the interpolation device performs the interpolation operation according to the plurality of second pixel information, wherein the at least one write completion signal indicates that the at least one first pixel information has been stored in the second memory, and the plurality of second pixel information includes the at least one first pixel information.

[0082] The description of the above-mentioned projection image correction method 800 can refer to the above-mentioned multiple embodiments, so it will not be repeated here. The above-mentioned multiple operations are only examples and are not limited to being performed in the order in this example. Without violating the operation mode and scope of each embodiment of the present application, these operations can be appropriately added, replaced, omitted, performed in a different order, or can be performed simultaneously or partially simultaneously.

[0083] In summary, the projection image correction system and method provided in some embodiments of the present application can realize the operation mode of continuously receiving read requests and sending read requests to the memory, thereby improving the efficiency of memory accessing data and reducing the time loss of read data misses, thereby improving the processing efficiency of the overall system.

[0084] Although the embodiments of the present application are described above, these embodiments are not intended to limit the present application. Technicians in this technical field may change the technical features of the present application based on the explicit or implicit contents of the present application. All these changes may fall within the scope of patent protection sought by the present application. The scope of patent protection of the present application shall be based on the scope of the patent application of this specification.

Claims

1. A projection image correction system, characterized in that: include: a state control circuit, when at least one read request corresponding to an interpolation operation has not been sent to a first memory, issuing the at least one read request to the first memory, so as to obtain at least one first pixel information from the first memory, storing the at least one first pixel information in a second memory, and counting the number of times the at least one read request is sent to the first memory to generate a first count value; as well as a data output circuit, which counts according to at least one write completion signal to generate a second count value, and when the second count value is the same as the first count value, obtains a plurality of second pixel information to be used for the interpolation operation from the second memory to an interpolation device, so that the interpolation device performs the interpolation operation according to the plurality of second pixel information, The at least one write completion signal indicates that the at least one first pixel information has been stored in the second memory, and the plurality of second pixel information includes the at least one first pixel information.

2. The projection image correction system according to claim 1, characterized in that: The state control circuit is further configured to record at least one sent request and compare the at least one read request with the at least one sent request to confirm whether the at least one read request has not been sent to the first memory.

3. The projection image correction system according to claim 1, characterized in that: The state control circuit comprises: a first register storing at least one sent request; a second register, storing the first count value; a first-in-first-out circuit, issuing the at least one read request to the first memory; and A controller compares the at least one read request with the at least one sent request to confirm whether the at least one read request has not been sent to the first memory, issues the at least one read request to the first-in-first-out circuit when the at least one read request is different from the at least one sent request, stores the at least one read request in the first register to update the at least one sent request, and counts the number of times the at least one read request is sent to the first memory to generate the first count value.

4. The projection image correction system according to claim 1, characterized in that: The data output circuit comprises: a counter, for counting the at least one write completion signal to generate the second count value; a first-in-first-out circuit, receiving the first count value from the state control circuit; and An output circuit obtains the first count value from the first-in-first-out circuit and reads out the plurality of second pixel information from the second memory when the second count value is the same as the first count value.

5. The projection image correction system according to claim 1, characterized in that: Also includes: A data writing circuit reads the at least one first pixel information from the first memory according to the at least one read request, writes the at least one first pixel information into the second memory, and issues the at least one write completion signal accordingly.

6. The projection image correction system according to claim 1, characterized in that: The second memory includes a plurality of storage bins, and the plurality of storage bins store a plurality of original pixel information in an original image data according to a preset order, and the plurality of original pixel information includes the at least one first pixel information.

7. The projection image correction system according to claim 1, characterized in that: Also includes: an address decoding circuit, decoding a received address request signal to obtain a plurality of address signals, and reading a plurality of third pixel information from a plurality of memory banks in the second memory according to the plurality of address signals; a confirmation circuit, confirming whether each of the plurality of third pixel information meets a preset condition; and a data sorting circuit, which determines that the second memory lacks the at least one first pixel information when at least one of the plurality of third pixel information does not meet the preset condition and issues the at least one read request accordingly, and reorders each of the plurality of third pixel information that meets the preset condition and at least one first address signal, and the at least one first address signal is the at least one of the plurality of address signals corresponding to the plurality of third pixel information that does not meet the preset condition.

8. The projection image correction system according to claim 7, characterized in that: Each of the plurality of third pixel information includes a label value and a valid value, and if the valid value of a corresponding one of the plurality of third pixel information is a preset value and the label value of the corresponding one is the same as a target label value, the confirmation circuit confirms that the corresponding one meets the preset condition.

9. The projection image correction system according to claim 7, characterized in that: Also includes: a first-in-first-out circuit, receiving each of the plurality of reordered third pixel information that meets the preset condition and the at least one first address signal from the data sorting circuit, The data output circuit also replaces the reordered at least one first address signal with the at least one first pixel information, and outputs each of the reordered plurality of third pixel information that meets the preset condition and the at least one first pixel information as the plurality of second pixel information.

10. A projection image correction method, characterized in that: Executed by a projection image correction system, the projection image correction method includes: When at least one read request corresponding to an interpolation operation has not been sent to a first memory, the at least one read request is sent to the first memory to obtain at least one first pixel information from the first memory, and the at least one first pixel information is stored in a second memory in the projection image correction system; Counting the number of times the at least one read request is sent to the first memory to generate a first count value; Counting according to at least one write completion signal to generate a second count value; and When the second count value is the same as the first count value, a plurality of second pixel information to be used in the interpolation operation is obtained from the second memory and provided to an interpolation device, so that the interpolation device performs the interpolation operation according to the plurality of second pixel information, The at least one write completion signal indicates that the at least one first pixel information has been stored in the second memory, and the plurality of second pixel information includes the at least one first pixel information.

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