Semiconductor devices and their fabrication methods

Abstract

This invention discloses a semiconductor device and its fabrication method, which can form an isolation resistor structure in the non-device area of ​​the semiconductor device without increasing the cost of additional masking. The isolation resistor structure has both an isolation effect—it can improve the breakdown voltage between the first trench structure and the second trench structure that isolate different device areas—and a resistive function—it can provide the required resistance value for the device area without occupying the area of ​​the device area, which is beneficial for the deployment of devices within the device area.

Description

Technical Field

[0001] This invention belongs to the field of semiconductor device technology, and specifically relates to a semiconductor device and its fabrication method. Background Technology

[0002] In existing semiconductor devices, resistors often require additional masks during the manufacturing process. When a large resistance value is needed in a semiconductor device, the area required to manufacture the resistor is often very large, and it also accounts for a large proportion of the device area, thus affecting the deployment of other devices in the device area.

[0003] The information disclosed in this background section is intended only to enhance the understanding of the overall background of the invention and should not be construed as an admission or in any way implying that the information constitutes prior art known to those skilled in the art. Summary of the Invention

[0004] The purpose of this invention is to provide a semiconductor device and a method for manufacturing the same, which can form an isolation resistor structure with both isolation effect and resistance function in the non-device area of ​​the semiconductor device without increasing the cost of additional masking, and without occupying the area of ​​the device area.

[0005] To achieve the above objectives, a specific embodiment of the present invention provides the following technical solution:

[0006] A semiconductor device, comprising:

[0007] A semiconductor body includes a substrate, a buried layer disposed on the substrate, and an epitaxial layer disposed on the buried layer;

[0008] An isolation structure is disposed within the semiconductor body, the isolation structure dividing the semiconductor body into several device regions, the isolation structure including a first trench and a second trench;

[0009] The first trench extends from the top surface of the epitaxial layer into the buried layer, and a first trench structure is provided in the first trench, the first trench structure being configured to electrically connect the buried layer to the top surface of the epitaxial layer;

[0010] The second trench extends from the top surface of the epitaxial layer into the substrate, and a second trench structure is provided in the second trench, the second trench structure being configured to electrically connect the substrate to the top surface of the epitaxial layer;

[0011] An isolation resistor structure is disposed within the semiconductor body and located between the first trench and the second trench. The isolation resistor structure is at least used to provide a required resistance value for a device region, and the isolation resistor structure is configured to isolate the first trench structure and the second trench structure. The isolation resistor structure includes a third trench.

[0012] The third trench extends from the top surface of the epitaxial layer into the substrate, and the depth of the third trench is less than the depth of the second trench. A third trench resistor structure is provided in the third trench.

[0013] In one or more embodiments of the present invention, the third trench resistor structure includes:

[0014] A liner is provided on the inner wall of the third groove;

[0015] A dielectric layer is disposed in the third trench and located on the surface of the pad, and the dielectric layer and the pad are partially etched at the top surface of the epitaxial layer to form a first opening;

[0016] A first conductive material is disposed in the third trench and at least fills the first opening.

[0017] In one or more embodiments of the present invention, the first conductive material comprises polycrystalline silicon having a first doping type.

[0018] In one or more embodiments of the present invention, the resistance value of the isolation resistor structure is adjusted by changing the doping concentration of the first conductive material within the first opening.

[0019] In one or more embodiments of the present invention, the first conductive material is subjected to anti-doping with different doping types or heavy doping with the same doping type to change the doping concentration of the first conductive material.

[0020] In one or more embodiments of the present invention, the third trench resistor structure is divided into a connection region and a functional region;

[0021] The connection area is used to form a metal connection that is electrically connected to the first conductive material;

[0022] The first conductive material within the functional region is subjected to anti-doping with different doping types or heavy doping with the same doping type to change the doping concentration of the first conductive material.

[0023] In one or more embodiments of the present invention, the first conductive material in the connection region is subjected to different types of anti-doping to change the connection resistance between the metal connection and the first conductive material.

[0024] In one or more embodiments of the present invention, the width of the third trench ranges from 0.6 μm to 1.3 μm.

[0025] In one or more embodiments of the present invention, the semiconductor device further includes a shallow trench isolation structure formed on the top surface of the epitaxial layer and extending into the epitaxial layer, the shallow trench isolation structure being at least partially overlapping the third trench resistor structure.

[0026] In one or more embodiments of the present invention, the resistance value of the isolation resistor structure is adjusted by adjusting the width of the overlapping area between the third trench resistor structure and the shallow trench isolation structure.

[0027] In one or more embodiments of the present invention, the width of the overlapping region between the shallow trench isolation structure and the third trench resistor structure ranges from 0 μm to 0.4 μm.

[0028] A method for fabricating a semiconductor device, comprising:

[0029] A semiconductor body is provided, the semiconductor body including a substrate, a buried layer disposed on the substrate, and an epitaxial layer disposed on the buried layer;

[0030] A first trench is formed in the semiconductor body, the first trench extending from the top surface of the epitaxial layer to the buried layer;

[0031] A first trench structure is formed in the first trench, and the first trench structure is configured to electrically connect the buried layer to the top surface of the epitaxial layer;

[0032] A second trench and a third trench are formed in the semiconductor body. The second trench surrounds the first trench and extends from the top surface of the epitaxial layer into the substrate and has a first depth. The third trench is located between the first trench and the second trench and extends from the top surface of the epitaxial layer into the substrate and has a second depth less than the first depth.

[0033] While forming a second trench structure in the second trench, a third trench resistor structure is formed in the third trench.

[0034] In one or more embodiments of the present invention, the manufacturing method further includes:

[0035] A shallow trench isolation structure is formed in the semiconductor body, the shallow trench isolation structure exposing a portion of the first trench structure, a portion of the second trench structure and a portion of the third trench resistor structure.

[0036] In one or more embodiments of the present invention, the resistance value of the isolation resistor structure is adjusted by adjusting the width of the overlapping area between the shallow trench isolation structure and the third trench resistor structure, or by adjusting the width of the third trench.

[0037] In one or more embodiments of the present invention, while forming a second trench structure in the second trench, a third trench resistor structure is formed in the third trench, including:

[0038] A liner is formed on the inner walls of the second and third trenches;

[0039] A dielectric layer is formed on the surface of the liner within the second and third trenches;

[0040] The padding and dielectric layer of the bottom wall of the second trench are etched and removed, and a first opening is formed at least on the top surface of the third trench;

[0041] A first conductive material having a first doping type is deposited such that the first conductive material at least fills the second trench and the first opening.

[0042] In one or more embodiments of the present invention, the doping concentration of the first conductive material in the first opening is changed by performing different types of anti-doping or the same type of heavy doping on the first conductive material in the first opening, thereby adjusting the resistance value of the isolation resistor structure.

[0043] Compared with the prior art, the semiconductor device and its fabrication method of the present invention can form an isolation resistor structure in the non-device area of ​​the semiconductor device without increasing the cost of additional masking. The isolation resistor structure has both isolation effect - which can improve the breakdown voltage between the first trench structure and the second trench structure that isolate different device areas; and resistance function - which can provide the required resistance value of the device area; and does not occupy the area of ​​the device area.

[0044] The semiconductor device and its fabrication method of the present invention can adjust the resistance value of the isolation resistor structure by changing the width of the third trench and the doping concentration of the first conductive material in the third trench, or by adjusting the width of the overlapping area between the third trench resistor structure and the shallow trench isolation structure. Attached Figure Description

[0045] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0046] Figure 1 This is a schematic cross-sectional view of a semiconductor device according to an embodiment of the present invention;

[0047] Figure 2 This is a schematic top view of a semiconductor device according to an embodiment of the present invention;

[0048] Figure 3 This is a graph showing experimental data on the resistance value of the isolation resistor structure in a semiconductor device according to different doping in one embodiment of the present invention.

[0049] Figure 4 This is an experimental data graph showing the resistance value of the isolation resistor structure in a semiconductor device under different third trench widths in one embodiment of the present invention.

[0050] Figure 5 This is a flowchart of a method for fabricating a semiconductor device according to an embodiment of the present invention;

[0051] Figures 6a-6m This is a flowchart illustrating the steps of a method for fabricating a semiconductor device according to an embodiment of the present invention. Detailed Implementation

[0052] To enable those skilled in the art to better understand the technical solutions of this invention, the technical solutions of the embodiments of this invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of this invention, and not all embodiments. Based on the embodiments of this invention, all other embodiments obtained by those skilled in the art without creative effort should fall within the scope of protection of this invention.

[0053] As mentioned in the background section, resistors in existing semiconductor devices often require additional masks during the manufacturing process. When a large resistance value is required in a semiconductor device, the area required for the manufactured resistor is often very large and accounts for a large proportion of the device area, thus affecting the deployment of other devices within the device area.

[0054] Based on this, the present invention provides a semiconductor device and a method for fabricating the same, which can form an isolation resistor structure in the non-device area of ​​the semiconductor device without increasing the cost of additional masking. The isolation resistor structure has both an isolation effect - which can improve the breakdown voltage between the first trench structure and the second trench structure that isolate different device areas; and a resistance function - which can provide the required resistance value of the device area, without occupying the area of ​​the device area, which is beneficial to the deployment of devices within the device area.

[0055] like Figure 1As shown, a semiconductor device in one embodiment of the present invention includes a semiconductor body 10, an isolation structure 20 and an isolation resistor structure 30 disposed in the semiconductor body 10, and a shallow trench isolation structure 40 disposed on the top surface of the semiconductor body 10 and partially extending into the semiconductor body 10.

[0056] The semiconductor substrate 10 includes a substrate 11, a buried layer 12 disposed on the substrate 11, and an epitaxial layer 13 disposed on the buried layer 12. The substrate 11 has a first doping type, the buried layer 12 has a second doping type opposite to the first doping type, and the epitaxial layer 13 has a first doping type. The thickness of the epitaxial layer 13 is 12 μm-15 μm, preferably 13 μm.

[0057] For example, the first doping type can be p-type and the second doping type can be n-type. Alternatively, the first doping type can be n-type and the second doping type can be p-type. The p-type dopant can include boron (B), aluminum (Al), indium (In), or combinations thereof, while the n-type dopant can include phosphorus (P), arsenic (As), antimony (Sb), or combinations thereof.

[0058] An isolation structure 20 is disposed within the semiconductor body 10, dividing the semiconductor body 10 into several device regions A. The isolation structure 20 includes a first trench 21 and a second trench 22.

[0059] The first trench 21 is preferably arranged in a ring shape. The first trench 21 extends from the top surface of the epitaxial layer 13 into the buried layer 12. A first trench structure is provided in the first trench 21, which is configured to electrically connect the buried layer 12 to the top surface of the epitaxial layer 13.

[0060] The first trench structure includes a second conductive material 211 electrically connected to the buried layer 12, and a barrier layer 212 formed between the second conductive material 211 and the sidewalls of the first trench 21. The barrier layer 212 includes an oxide layer and a nitride layer. Metallic connections (not shown) can be formed on the second conductive material 211 of the first trench structure to facilitate the application of voltage. The second conductive material 211 includes polycrystalline silicon having a second doping type.

[0061] The second trench 22 is also annular and located around the first trench 21. The second trench 22 extends from the top surface of the epitaxial layer 13 into the substrate 11 and has a first depth D1. A second trench structure is provided within the second trench 22, and the second trench structure is configured to electrically connect the substrate 11 to the top surface of the epitaxial layer 13.

[0062] The second trench structure includes a first conductive material 51 electrically connected to the substrate 11. The first conductive material 51 comprises polysilicon having a first doping type. A pad 52 and a dielectric layer 53 are formed between the first conductive material 51 and the sidewalls of the second trench 22. The pad 52 is preferably an oxide layer, and the dielectric layer 53 is preferably an oxide layer or a nitride layer. Metallic connections (not shown) can also be formed on the first conductive material 51 of the second trench structure to facilitate the application of voltage.

[0063] When different voltages are applied simultaneously to the metal connection of the first trench structure and the metal connection of the second trench structure, the first trench structure and the second trench structure work together to achieve isolation of different device regions A within the semiconductor device.

[0064] An isolation resistor structure 30 is disposed within the semiconductor body 10 and located between the first trench 21 and the second trench 22. The isolation resistor structure 30 is at least used to provide the required resistance value for device region A, and the isolation resistor structure 30 is configured to isolate the first trench structure and the second trench structure. The isolation resistor structure 30 includes a third trench 31.

[0065] The third trench 31 is arranged in a ring shape and is arranged in a concentric ring or near-concentric ring configuration with the first trench 21 and the second trench 22. The width of the third trench 31 ranges from 0.6 μm to 1.3 μm. The third trench 31 extends from the top surface of the epitaxial layer 13 into the substrate 11 and has a second depth D2. The second depth D2 of the third trench 31 is less than the first depth D1 of the second trench 22. A third trench resistor structure is disposed within the third trench 31.

[0066] The third trench resistor structure includes a pad 52, a dielectric layer 53, and a first conductive material 51. The pad 52 is disposed on the inner wall of the third trench 31. The dielectric layer 53 is disposed in the third trench 31 and located on the surface of the pad 52. The dielectric layer 53 and the pad 52 are partially etched at the top surface of the epitaxial layer 13 to form a first opening 311. The first conductive material 51 is disposed in the third trench 31 and at least fills the first opening 311. Metallic connections (not shown) can also be formed on the first conductive material 51 of the third trench resistor structure to facilitate the application of voltage.

[0067] In the above technical solution, the resistance value of the isolation resistor structure 30 can be adjusted by changing the doping concentration of the first conductive material 51 within the first opening 311. For example, the first conductive material 51 within the first opening 311 can be de-doped with different doping types, such as NWELL, NLDD, or NPLUS; or heavily doped with the same doping type, such as PPLUS, to change the doping concentration of the first conductive material 51.

[0068] Further reference Figure 2As shown, the third trench resistor structure 30 is divided into a connection region 32 and a functional region 33. The connection region 32 is used to form a metal connection (not shown) that is electrically connected to the first conductive material 51. The functional region 33 is used to act as a resistor.

[0069] In one embodiment, the first conductive material 51 within the functional region 33 can be subjected to different types of anti-doping or the same type of heavy doping to change the doping concentration of the first conductive material 51 in that region, thereby changing the resistance value of the isolation resistor structure 30. For the first conductive material 51 within the connection region 32, PPLUS doping can be performed to facilitate better electrical connection with the subsequently formed metal connection, reduce the connection resistance between the two, and improve connection stability.

[0070] In another embodiment, the first conductive material 51 in the connection region 32 may be de-doped with different types of doping to increase the connection resistance between the subsequently formed metal connection and the first conductive material 51 in the connection region 32, thereby increasing the overall resistance of the isolation resistance structure 30.

[0071] refer to Figure 3 As shown, Figure 3 The experimental study demonstrates the resistance variation of the isolation resistor structure 30 when the metal connection is formed on the first conductive material 51 with different doping types (reverse doped) and on the first conductive material 51 with the same doping type (heavily doped). In one embodiment, the width of the third trench 31 (dti2 in the figure represents the third trench in the text) is uniformly 1.1 μm, and the extension length of the third trench 31 is 100 μm (the extension length is the length of the functional area in the text). P+ represents PPLUS doping (the first conductive material itself is P-doped), and N+ represents NPLUS reverse doping. The left frame of the figure represents the metal connection formed on the PPLUS-doped first conductive material 51, and the right frame of the figure represents the metal connection formed on the NPLUS-doped first conductive material 51.

[0072] from Figure 3 It can be shown that when the metal connection is formed on the N+ anti-doped first conductive material 51, the resistance of the isolation resistor structure 30 increases by about 1.6 times compared to when the metal connection is formed on the P+ doped first conductive material 51.

[0073] refer to Figure 1 As shown, the shallow trench isolation structure 40 is formed on the top surface of the epitaxial layer 13 and extends into the epitaxial layer 13. The shallow trench isolation structure 40 is at least partially overlapped with the third trench resistor structure.

[0074] In the above technical solution, the resistance value of the isolation resistor structure 30 can also be adjusted by adjusting the width of the third trench 31 or by adjusting the width of the overlapping area between the third trench resistor structure and the shallow trench isolation structure 40. Preferably, the width of the overlapping area between the shallow trench isolation structure 40 and the third trench resistor structure is in the range of 0μm-0.4μm.

[0075] refer to Figure 4 As shown, Figure 4 This study demonstrates the resistance variation of the third trench 31 with different widths for the isolation resistor structure 30, as shown in the experimental research. In one embodiment, the width of the third trench 31 is selected from 1.0 μm and 1.1 μm, and the extension length is uniformly 50 μm (the extension length is the length of the functional area in the text). The left frame of the attached figure represents the width of the third trench 31 selected from 1.0 μm, and the right frame of the attached figure represents the width of the third trench 31 selected from 1.1 μm.

[0076] from Figure 4 It can be shown that when the width of the third trench 31 is set to 1.0 μm, the resistance of the isolation resistor structure 30 increases by about 36% compared to when the width of the third trench 31 is set to 1.1 μm.

[0077] refer to Figure 5 As shown, the present invention also provides a method for fabricating the above-mentioned semiconductor device, comprising:

[0078] S1 provides a semiconductor body, which includes a substrate, a buried layer disposed on the substrate, and an epitaxial layer disposed on the buried layer.

[0079] S2, forming a first trench in the semiconductor body, the first trench extending from the top surface of the epitaxial layer to the buried layer.

[0080] S3, a first trench structure is formed in the first trench, the first trench structure being configured to electrically connect the buried layer to the top surface of the epitaxial layer.

[0081] S4, a second trench and a third trench are formed in the semiconductor body. The second trench surrounds the first trench and extends from the top surface of the epitaxial layer into the substrate and has a first depth. The third trench is located between the first trench and the second trench and extends from the top surface of the epitaxial layer into the substrate and has a second depth less than the first depth.

[0082] S5, while forming the second trench structure in the second trench, forms the third trench resistor structure in the third trench.

[0083] S6, a shallow trench isolation structure is formed in the semiconductor body, the shallow trench isolation structure exposing part of the first trench structure, part of the second trench structure and part of the third trench resistor structure.

[0084] Figures 6a to 6m This is a schematic diagram illustrating the steps of a semiconductor device fabrication method according to an embodiment of the present invention. Figures 6a to 6m The process shown can be used to make Figure 1 The semiconductor device shown. Combined with the above text... Figure 1 The description of semiconductor devices can be incorporated herein.

[0085] refer to Figure 6a As shown, a semiconductor body 10 is provided. The semiconductor body 10 includes a substrate 11 having a first doping type, a buried layer 12 having a second doping type disposed on the substrate 11, and an epitaxial layer 13 having a first doping type disposed on the buried layer 12. The thickness of the epitaxial layer 13 is 12 μm-15 μm. The second doping type is the opposite of the first doping type. For example, when the first doping type is p-type, the second doping type is n-type. Similarly, when the first doping type is n-type, the second doping type is p-type. The p-type dopant may include boron (B), aluminum (Al), indium (In), or combinations thereof, while the n-type dopant may include phosphorus (P), arsenic (As), antimony (Sb), or combinations thereof. The buried layer 12 may have a blanket structure having a substantially the same horizontal extension as the substrate 11, laid flat on the substrate 11. In other embodiments, the buried layer 12 may have a patterned structure.

[0086] A hard mask layer 15 is formed on the top surface of the epitaxial layer 13. The hard mask layer 15 may include a first oxide layer 151 with a thickness of 100 Å to 200 Å, a first nitride layer 152 with a thickness of 1000 Å to 2000 Å, and a TEOS layer 153 with a thickness of 2000 Å to 3000 Å. The hard mask layer 15 may also include only the first oxide layer 151 with a thickness of 100 Å to 200 Å and the first nitride layer 152 with a thickness of 1000 Å to 2000 Å. In some embodiments, the substrate 11, the buried layer 12, and the epitaxial layer 13 are formed of silicon material, the first oxide layer 151 is formed of silicon dioxide, the first nitride layer 152 is formed of silicon nitride, and the TEOS layer 153 is a silicon oxide layer.

[0087] like Figure 6b As shown, a soft mask layer can be used to perform a single etching of the hard mask layer 15 and the semiconductor body 10 to form a first trench 21 that penetrates the hard mask layer 15 and extends into the semiconductor body 10. The first trench 21 extends from the top surface of the epitaxial layer 13 into the buried layer 12. In some embodiments, the soft mask layer may be a photoresist. After the first trench 21 is etched and formed, the soft mask layer is stripped off.

[0088] like Figure 6cAs shown, a barrier layer 212 is grown on the sidewall of the first trench 21. The barrier layer 212 includes an oxide layer and a nitride layer. The thickness of the oxide layer is approximately 100 Å to 200 Å. The thickness of the nitride layer is 100 Å to 300 Å.

[0089] Understandably, during the growth of the barrier layer 212, it will be grown on both the sidewalls and bottom wall of the first trench 21. Therefore, the barrier layer 212 on the bottom wall of the first trench 21 can be removed by subsequent dry etching to expose the buried layer 12. The etching process will form a V-shape at the top of the first trench 21, which will have a better effect on the subsequent filling of the second conductive material 211. The top TEOS layer 153 can be used as an etching stop layer or a protective layer.

[0090] Optionally, before growing the barrier layer 212 on the sidewalls and bottom wall of the first trench 21, a sacrificial oxide layer can be grown on the sidewalls and bottom wall of the first trench 21, and then removed by wet stripping. By stripping the sacrificial oxide layer, damage generated on the sidewalls and bottom wall during the etching process can be removed, the sidewalls of the first trench 21 can be smoothed, and the opening width of the first trench 21 on the top surface of the epitaxial layer 13 can be further widened by the sacrificial oxide layer stripping, which facilitates subsequent processes.

[0091] like Figure 6d As shown, a second conductive material 211 with a second doping type is deposited, such that the second conductive material 211 fills the first trench 21. The second conductive material 211 is in complete contact with the buried layer 12 and achieves electrical connection. The second conductive material 211 is preferably polycrystalline silicon. The second conductive material 211 and the barrier layer 212 together form the first trench structure.

[0092] like Figure 6e As shown, excess second conductive material 211 and part of the TEOS layer 153 can be removed by chemical mechanical polishing (CMP), with the TEOS layer 153 serving as a stop layer for CMP. Subsequently, an anisotropic plasma dry etching process is used to maintain the top surface of the second conductive material 211 at the same horizontal level as the top surface of the first nitride layer 152.

[0093] like Figure 6f As shown, the TEOS layer 153 is removed. Since some of the second conductive material 211 may also be deposited on the substrate 11 of the semiconductor body 10 during the deposition of the second conductive material 211, the second conductive material 211 on the substrate 11 of the semiconductor body 10 is removed at the same time as the TEOS layer 153, in order to obtain better wafer warpage and less stress.

[0094] like Figure 6gAs shown, a second nitride layer 16, approximately 100 Å to 1000 Å thick, is deposited on the top surface of the first nitride layer 152 to cover the second conductive material 211 within the first trench 21 and prevent it from being oxidized in subsequent oxidation steps. The second nitride layer 16 also minimizes the probability of cross-contamination problems that may occur in subsequent processes.

[0095] like Figure 6h As shown, the semiconductor body 10 is etched once again using a soft mask layer to form a second trench 22 and a third trench 31 in the semiconductor body 10. The second trench 22 is formed around the first trench 21. The third trench 31 is formed between the second trench 22 and the first trench 21.

[0096] Understandably, the depth of a trench is related to its width; the smaller the width, the shallower the depth. Therefore, the width of the third trench 31 is smaller than the width of the second trench 22, such that during simultaneous etching, the second trench 22 extends from the top surface of the epitaxial layer 13 into the substrate 11 of the semiconductor body 10 and has a first depth D1, while the third trench 31 extends from the top surface of the epitaxial layer 13 into the substrate 11 of the semiconductor body 10 and has a second depth D2, which is less than the first depth D1. In some embodiments, the soft mask layer can be photoresist. After the second trench 22 and the third trench 31 are etched and formed, the soft mask layer is stripped off.

[0097] like Figure 6i As shown, a liner 52 is grown on the sidewalls and bottom walls of the second trench 22 and the third trench 31 using the same process. For example, a thermal oxidation process is used to oxidize the sidewalls and bottom walls of the second trench 22 and the third trench 31, and the thickness of the liner 52 is approximately 3000 Å to 5000 Å. Since the widths of the second trench 22 and the third trench 31 are relatively wide, while the sidewalls and bottom walls of the second trench 22 and the third trench 31 are oxidized using the thermal oxidation process, the bottom walls and sidewalls of the second trench 22 and the third trench 31 are covered by thermal oxide, but the middle remains open, with a large unfilled space. It is understood that since the width of the second trench 22 is greater than the width of the third trench 31, the remaining space in the second trench 22 after oxidation is also much larger than the remaining space in the third trench 31.

[0098] like Figure 6jAs shown, a dielectric layer 53 is deposited on top of the second trench 22 and the third trench 31, such that the dielectric layer 53 is formed on the sidewalls and bottom walls of the second trench 22 and the third trench 31, as well as on the surface of the second nitride layer 16. The dielectric layer 53 is preferably an oxide layer. The thickness of the dielectric layer 53 can be 5000 Å to 7000 Å. The second trench 22 still has a top opening space of approximately 0.8 μm. The third trench 31 still has a top opening space of approximately 0.1 μm. An air gap may be formed inside the third trench 31, which helps to minimize mechanical stress.

[0099] like Figure 6k As shown, anisotropic etching removes the dielectric layer 53 and pad 52 on the bottom wall of the second trench 22, opening at least part of the bottom of the second trench 22. The anisotropic etching process does not affect the bottom of the third trench 31 due to the small opening space at the top. The etching process forms a V-shape at the top of the second trench 22, which is more effective for the subsequent filling of the first conductive material 51. Simultaneously, the etching process etches the dielectric layer 53 and pad 52 at the top of the third trench 31, forming a first opening 311 at the top surface of the epitaxial layer 13. The formation of the first opening 311 facilitates the subsequent filling of the first conductive material 51 and also provides more space in the third trench 31 to form resistance.

[0100] Optionally, after the dielectric layer 53 is formed, an annealing process can be performed to densify the dielectric layer 53 in order to achieve a better isolation effect.

[0101] Optionally, low-energy boron implantation (e.g., B11 to 5E15 / 7KeV / 0-degree tilt) can be performed on the bottom of the second trench 22 to increase the doping level at the bottom of the second trench 22, thereby allowing the subsequently filled first conductive material 51 to be better connected to the substrate 11.

[0102] like Figure 6l As shown, a first conductive material 51 with a first doping type is deposited such that the first conductive material 51 fills the second trench 22 and at least fills the first opening 311 of the third trench 31. The first conductive material 51 in the second trench 22 is in complete contact with the substrate 11 and achieves electrical connection. To better deposit the first conductive material 51, a staged deposition process can be used. For example, after the first deposition, a dry etching process can be performed to further widen the top opening, thereby achieving better second filling and reducing voids in the second trench 22 and the third trench 31. The first conductive material 51, the dielectric layer 53, and the pad 52 together constitute the second trench structure in the second trench 22. The first conductive material 51 constitutes a resistor in the third trench 31.

[0103] like Figure 6mAs shown, excess first conductive material 51, second nitride layer 16, and first nitride layer 152 can be removed through chemical mechanical polishing (CMP), anisotropic plasma dry etching for etching back, H3PO4 wet etching, and diluted HF wet etching, etc., keeping the top surfaces of the first conductive material 51 and the second conductive material 211 at the same horizontal level as the epitaxial layer 13. The first nitride layer 152 serves as a stop layer for CMP. The wear of the first nitride layer 152 depends on the selective polishing rate, with normal wear less than 500 Å. Similarly, since some first conductive material 51 may also be deposited on the substrate 11 of the semiconductor body 10 during the deposition of the first conductive material 51, the first conductive material 51 on the substrate 11 of the semiconductor body 10 is removed simultaneously with the removal of the first conductive material 51 on the first nitride layer 152 to achieve better wafer warpage and lower stress.

[0104] like Figure 1 As shown, a shallow trench isolation structure 40 can be formed in the epitaxial layer 13. The shallow trench isolation structure 40 exposes the second conductive material 211 of the first trench structure, the first conductive material 51 of the second trench structure, and the first conductive material of the third trench resistor structure.

[0105] The size of the first conductive material 51 exposed in the third trench resistor structure is defined by the shallow trench isolation structure 40, and the resistance value of the third trench resistor structure can be adjusted by adjusting the width of the overlapping area between the shallow trench isolation structure 40 and the third trench resistor structure (which affects the size of the exposed first conductive material 51) or by adjusting the width of the third trench 31.

[0106] Finally, proceed with the normal processes for subsequent CMOS devices: well implantation, gate, LDD implantation, spacer formation, source / drain implantation, silicide formation, ILD (interlayer dielectric layer), metal interconnect formation, BEoL metal layer, and passivation, among other processes.

[0107] Prior to the step of forming the metal connection, the first conductive material 51 in the first opening 311 of the third trench 31 can be de-doped with different doping types or heavily doped with the same doping type using the existing prior process to change the doping concentration of the first conductive material 51 in the first opening 311, thereby adjusting the resistance value of the third trench resistor structure, and finally forming a metal connection on the first conductive material 51 in the third trench 31.

[0108] Compared with the prior art, the semiconductor device and its fabrication method of the present invention can form an isolation resistor structure in the non-device area of ​​the semiconductor device without increasing the cost of additional masking. The isolation resistor structure has both isolation effect - which can improve the breakdown voltage between the first trench structure and the second trench structure that isolate different device areas; and resistance function - which can provide the required resistance value of the device area; and does not occupy the area of ​​the device area.

[0109] The semiconductor device and its fabrication method of the present invention can adjust the resistance value of the isolation resistor structure by changing the width of the third trench and the doping concentration of the first conductive material in the third trench, or by adjusting the width of the overlapping area between the third trench resistor structure and the shallow trench isolation structure.

[0110] It will be apparent to those skilled in the art that the present invention is not limited to the details of the exemplary embodiments described above, and that the invention can be implemented in other specific forms without departing from its spirit or essential characteristics. Therefore, the embodiments should be considered in all respects as exemplary and non-limiting, and the scope of the invention is defined by the appended claims rather than the foregoing description. Thus, all variations falling within the meaning and scope of equivalents of the claims are intended to be included within the present invention. No reference numerals in the claims should be construed as limiting the scope of the claims.

[0111] Furthermore, it should be understood that although this specification describes embodiments, not every embodiment contains only one independent technical solution. This narrative style is merely for clarity. Those skilled in the art should consider the specification as a whole, and the technical solutions in each embodiment can also be appropriately combined to form other embodiments that can be understood by those skilled in the art.

Claims

1. A semiconductor device, characterized by, The semiconductor body comprises a substrate, a buried layer disposed on the substrate, and an epitaxial layer disposed on the buried layer; An isolation structure is disposed in the semiconductor body, the isolation structure divides the semiconductor body into a plurality of device regions, and the isolation structure comprises a first trench and a second trench; The first trench extends from a top surface of the epitaxial layer into the buried layer, and a first trench structure is disposed in the first trench, the first trench structure is configured to electrically connect the buried layer to the top surface of the epitaxial layer; The second trench extends from the top surface of the epitaxial layer into the substrate, and a second trench structure is disposed in the second trench, the second trench structure is configured to electrically connect the substrate to the top surface of the epitaxial layer; An isolation resistance structure is disposed in the semiconductor body and located between the first trench and the second trench, the isolation resistance structure is at least used to provide a required resistance value for a device region, and the isolation resistance structure is configured to isolate the first trench structure and the second trench structure, the isolation resistance structure comprises a third trench; The third trench extends from the top surface of the epitaxial layer into the substrate, and the depth of the third trench is less than the depth of the second trench, and a third trench resistance structure is disposed in the third trench, wherein the third trench resistance structure comprises: a liner disposed on the inner wall of the third trench; a dielectric layer disposed in the third trench and located on the surface of the liner, the dielectric layer and the liner are partially etched at the top surface of the epitaxial layer to form a first opening; and a first conductive material disposed in the third trench and at least filling the first opening, wherein the resistance value of the isolation resistance structure can be adjusted by changing the doping concentration of the first conductive material in the first opening. The first conductive material comprises polysilicon with a first doping type.

2. The semiconductor device according to claim 1, wherein The first conductive material is counter-doped with a different doping type or heavily doped with the same doping type to change the doping concentration of the first conductive material.

3. The semiconductor device of claim 1, wherein The third trench resistance structure is divided into a connection region and a functional region; 4. The semiconductor device of claim 1, wherein The connection region is used to form a metal connection electrically connected to the first conductive material; The first conductive material in the functional region is counter-doped with a different doping type or heavily doped with the same doping type to change the doping concentration of the first conductive material. The first conductive material in the connection region is counter-doped with a different doping type to change the connection resistance of the metal connection to the first conductive material.

5. The semiconductor device of claim 4, wherein, The width of the third trench ranges from 0.6μm to 1.3μm.

6. The semiconductor device of claim 1, wherein A shallow trench isolation structure is also included, the shallow trench isolation structure is formed on the top surface of the epitaxial layer and extends into the epitaxial layer, and the shallow trench isolation structure is at least partially overlapped with the third trench resistance structure.

7. The semiconductor device of claim 1, wherein The resistance value of the isolation resistance structure is adjusted by adjusting the width of the overlapping region of the third trench resistance structure and the shallow trench isolation structure.

8. The semiconductor device of claim 7, wherein, The width of the overlapping region of the shallow trench isolation structure and the third trench resistance structure ranges from 0μm to 0.4μm.

9. The semiconductor device of claim 7, wherein, ​ 10. A method of fabricating a semiconductor device, characterized by, ​ A semiconductor body is provided, the semiconductor body comprising a substrate, a buried layer disposed on the substrate, and an epitaxial layer disposed on the buried layer; A first trench is formed in the semiconductor body, the first trench extending from a top surface of the epitaxial layer to the buried layer; A first trench structure is formed in the first trench, the first trench structure configured to electrically connect the buried layer to the top surface of the epitaxial layer; A second trench and a third trench are formed in the semiconductor body, the second trench disposed around the first trench, the second trench extending from the top surface of the epitaxial layer into the substrate and having a first depth, the third trench located between the first trench and the second trench, the third trench extending from the top surface of the epitaxial layer into the substrate and having a second depth less than the first depth; A second trench structure is formed in the second trench while a third trench resistance structure is formed in the third trench, including: forming a liner on inner walls of the second trench and the third trench; forming a dielectric layer on a surface of the liner in the second trench and the third trench; etching and removing the liner and the dielectric layer of a bottom wall of the second trench, and forming a first opening at least on a top surface of the third trench; depositing a first conductive material having a first doping type, the first conductive material filling at least the second trench and the first opening, wherein a width of the third trench is adjusted, thereby adjusting a resistance value of the third trench resistance structure.

11. The method of fabricating a semiconductor device according to Claim 10, wherein Further comprising: A shallow trench isolation structure is formed in the semiconductor body, the shallow trench isolation structure exposing part of the first trench structure, part of the second trench structure, and part of the third trench resistance structure.

12. The method of fabricating a semiconductor device according to Claim 11, wherein A resistance value of the third trench resistance structure is adjusted by adjusting a width of an overlapping area of the shallow trench isolation structure and the third trench resistance structure.

13. The method of claim 11, wherein: A resistance value of the third trench resistance structure is adjusted by performing counter-doping of different doping types, or re-doping of the same doping type, on the first conductive material in the first opening to change a doping concentration of the first conductive material in the first opening.

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