A packaging structure and manufacturing method of a stacked capacitor

Abstract

The present invention discloses a packaging structure and a preparation method of a stacked capacitor. The packaging structure includes a semiconductor substrate, on the first surface of which a metal thin film layer is deposited to form a bottom metal layer; a columnar array includes the bottom metal layer and a plurality of columns vertically carried on and communicating with the bottom metal layer, and a plurality of dielectric layers and metal layers are deposited on the surface of the columnar array at intervals; a stepped portion includes a plurality of layers of steps parallel to the upper surface of the bottom metal layer, and the upper surface and the lower surface of each layer of step respectively correspond to a metal layer and a dielectric layer one by one; a connecting portion includes a plurality of through electrodes vertically carried on and communicating with the upper surface of the step; a plurality of through connections are respectively used as the positive electrode and the negative electrode of the stacked capacitor; a filling dielectric layer includes a first capacitor dielectric layer filled between the columns and a second capacitor dielectric layer filled between the through electrodes, solving the problems of difficult trench filling, complex etching control and high cost in traditional deep trench capacitors.

Description

Technical Field

[0001] The present invention relates to the field of semiconductor technology, and particularly to a packaging structure and a preparation method of a stacked capacitor. Background Art

[0002] With the rapid increase in the system bandwidth of logic chip systems for artificial intelligence (AI) accelerators, high-performance computing (HPC), and servers, the power consumption of application-specific integrated circuit (ASIC) chips has also increased significantly. The power delivery design (including power noise margin) in system packaging has become increasingly critical. To ensure the effective operation of the power delivery network (PDN) in system packaging, it is crucial to minimize high-frequency switching noise and design a low-impedance power delivery network.

[0003] The most common method to improve power integrity (PI) performance is to optimize the layout design of decoupling capacitors. In particular, silicon capacitor structures with miniaturization, low equivalent series inductance (ESL), and high capacitance values have been widely studied in recent years. To reduce power noise in the hundreds of MHz frequency band, on-chip capacitor solutions such as MOS capacitors, metal-insulator-metal (MIM) capacitors, deep trench capacitors (DTCs), stacked capacitors (ISCs), embedded capacitors, and package bottom capacitors (LSCs) have been widely used in a single package and are considered effective solutions. Generally, multilayer MIM capacitors use high dielectric constant materials, and although they have a large capacitance value, their capacitance density is relatively low. In the past few decades, with the continuous progress of deep silicon etching technology, significant breakthroughs have been made in the research and development of deep trench capacitors. Such capacitors can provide a higher capacitance density within a limited chip area. However, with the continuous increase in capacitance density, a higher aspect ratio is required in design and process to expand the surface area, which has led to a continuous increase in cost and a sharp decline in reliability.

[0004] Therefore, it is necessary to provide a more effective and reliable silicon capacitor to overcome the deficiencies of the above technologies. Summary of the Invention

[0005] In order to overcome the above-mentioned deficiencies of the prior art, the present invention provides a packaging structure and a preparation method of a stacked capacitor. By etching to form a columnar array to form a multilayer stacked capacitor and using a capacitor parallel structure, the problems of difficult trench filling, complex etching control, and extremely high cost in traditional deep trench capacitors are solved, and it has broad application prospects in scenarios such as advanced packaging and high-performance computing.

[0006] The technical solution adopted by the present invention to overcome its technical problems is as follows: In the first aspect of the present invention, a packaging structure of a stacked capacitor is proposed, which at least includes a semiconductor substrate, and a metal thin film layer is deposited on the first surface of the semiconductor substrate to form a bottom metal layer; a columnar array, which at least includes the bottom metal layer and a plurality of columns vertically carried on and communicating with the bottom metal layer, and a plurality of spaced dielectric layers and metal layers are deposited on the surface of the columnar array; a stepped portion, which includes a plurality of steps arranged in parallel on the upper surface of the bottom metal layer, the upper surface of each step corresponds to the metal layer deposited on the surface of the column, and the lower surface corresponds to the dielectric layer deposited on the surface of the column; a connecting portion, the connecting portion includes a plurality of through electrodes, the through electrodes are vertically carried on the upper surface of the step and are respectively communicated with the upper surface of the corresponding step; the plurality of through electrodes are respectively connected to form the positive and negative electrodes of the stacked capacitor to realize capacitance parallel connection; a filling dielectric layer, the filling dielectric layer at least includes a first capacitor dielectric layer filled between the columns and a second capacitor dielectric layer filled between the through electrodes.

[0007] By controlling the etching parameters, the sidewall angle of the columnar array can be adjusted, which is beneficial to the subsequent stacking of capacitor thin films.

[0008] Further, the top surface shape of the column is circular or elliptical.

[0009] Further, the width of the step is determined based on the size of the through electrode.

[0010] Further, the first capacitor dielectric layer, the second capacitor dielectric layer, and the dielectric layer all at least adopt one or a combination of more of silicon oxide, silicon nitride, hafnium oxide, yttrium aluminate, barium titanate, tantalum oxide.

[0011] Further, the bottom metal layer and the metal layer at least adopt a combination of one or more materials of polysilicon, tungsten, copper, titanium, ruthenium.

[0012] In the second aspect of the present invention, a method for manufacturing a stacked capacitor of the packaging structure of the above-mentioned stacked capacitor is also proposed, which includes depositing a metal thin film on the first surface of the semiconductor substrate to form a bottom metal layer, performing photolithography and etching to form a plurality of columns, the columns are vertically carried on the bottom metal layer and communicate with the bottom metal layer, and the columns and the bottom metal layer form a columnar array; sequentially depositing dielectric layers and metal layers at intervals on the surface of the columnar array; filling the first capacitor dielectric layer to obtain a first capacitor structure; performing photolithography and etching on the first capacitor structure to obtain a plurality of steps respectively corresponding to the bottom metal layer and the deposited metal layer; filling the second capacitor dielectric layer; performing photolithography and etching based on the second capacitor dielectric layer to obtain a plurality of through electrodes respectively corresponding to and communicating with the bottom metal layer or the metal layer; performing metal interconnection on the through electrodes to obtain a stacked capacitor with a parallel structure.

[0013] Etching is used to form a columnar array, and the exposure area of the process is larger, which improves the exposure efficiency. Compared with traditional deep trench capacitors, the lithography and etching process windows are increased. Therefore, in actual large-scale production, the process is more stable and the yield is improved. By etching to form a columnar array and combining multi-layer stacked capacitors, capacitor parallel connection is formed, and the overall structure is simpler and the application scenarios are more flexible.

[0014] Furthermore, a high step coverage filling method is adopted for the deposition of the dielectric layer, the deposition of the metal layer, the filling of the first capacitor dielectric layer, and the filling of the second capacitor dielectric layer.

[0015] Furthermore, at least one or more of chemical mechanical polishing, dry etching, and wet etching are used for surface planarization of the filled second capacitor dielectric layer and the second dielectric layer.

[0016] Furthermore, lithography and etching are performed on the second capacitor dielectric layer to obtain a number of through electrodes that connect to the bottom metal layer or the metal layer. Specifically, the through electrodes are obtained by etching based on the selectivity ratio of the second capacitor dielectric layer and the metal layer on the step.

[0017] Furthermore, the photoresist trimming is at least in-situ trimmed by dry plasma etching.

[0018] The beneficial effects of the present invention are:

[0019] 1. Etching is used to form a columnar array, and the exposure area of the process is larger, which improves the exposure efficiency. Compared with traditional deep trench capacitors, the lithography and etching process windows are increased. Therefore, in actual large-scale production, the process is more stable and the yield is improved.

[0020] 2. The sidewall angle of the columnar array is flexibly controllable, which is beneficial to the subsequent stacking of capacitor films, such as the stacking form of MIMIM, and the formation of a better-quality capacitor structure;

[0021] 3. Etching is used to form a columnar array and combined with multi-layer stacked capacitors to form capacitor parallel connection. The overall structure is simpler and the application scenarios are more flexible, and it has broad application prospects in various decoupling circuits and advanced packaging. BRIEF DESCRIPTION OF THE DRAWINGS

[0022] Figure 1 It is a schematic flow chart of a method for preparing a stacked capacitor according to an embodiment of the present invention.

[0023] Figure 2 It is a schematic diagram of the columnar array structure according to an embodiment of the present invention

[0024] Figure 3 It is a schematic diagram of the structure after depositing metal and dielectric layers according to an embodiment of the present invention;

[0025] Figure 4 Schematic diagram for implementing the first step etching;

[0026] Figure 5 Schematic diagram for implementing the second step etching;

[0027] Figure 6 Schematic diagram for implementing the third step etching;

[0028] Figure 7 Schematic diagram after the step etching is completed and the dielectric layer is filled;

[0029] Figure 8 Schematic diagram of the structure after the through electrode is formed;

[0030] Figure 9 Top view of the stacked capacitor package structure;

[0031] In the figure, 100 - semiconductor substrate; 101 - columnar array; 102 - first dielectric layer; 103 - first metal layer; 104 - second dielectric layer; 105 - second metal layer; 106 - first capacitor dielectric layer; 107 - second capacitor dielectric layer; 108 - through electrode. Detailed implementation manners

[0032] To facilitate better understanding of the present invention by those skilled in the art, the present invention will be further described in detail below with reference to the accompanying drawings and specific embodiments. The following is merely exemplary and does not limit the protection scope of the present invention.

[0033] As Figure 1 shown, the flowchart of a method for manufacturing a stacked capacitor according to this embodiment includes the following steps, and the method for manufacturing the stacked capacitor according to the embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0034] S1, deposit a metal thin film on the first surface of the semiconductor substrate to form a bottom metal layer.

[0035] As Figure 2 shown, provide a semiconductor substrate 100, and deposit a metal thin film on the first surface of the semiconductor substrate, i.e., the upper surface in the figure, to form a bottom metal layer.

[0036] In some embodiments of the present application, the material of the semiconductor substrate 100 includes (i) elemental semiconductors, such as silicon or germanium; (ii) compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, or indium phosphide; (iii) alloy semiconductors, such as silicon germanium carbide, silicon germanium, gallium phosphide arsenide, or gallium indium phosphide; or (iv) a combination of the above.

[0037] S2. Perform photolithography and etching to form a number of columns. The columns are vertically supported on the bottom metal layer and communicate with the bottom metal layer. The columns and the bottom metal layer form a columnar array.

[0038] As Figure 2 shown, columns are formed by photolithography and etching. The columnar array 101 is used to fabricate a stacked capacitor structure. The columnar array 101 consists of a number of columns and a bottom metal layer. The bottom metal layer and the columns can be made of the same or different metals.

[0039] In particular, the material of the columns can be a combination of one or more metals such as tungsten (W), tantalum (Ta), gold (Au), etc.

[0040] In some embodiments of the present application, the height of the columns is deeper than the designed depth of the stacked capacitor, expanding the surface area and thus increasing the capacitance density.

[0041] In particular, the top surface shape of the columns can be cylindrical, elliptical or other possible shapes.

[0042] It should be noted that the top surface shape affects the density of the column arrangement and thus affects the capacitance density.

[0043] In particular, the spacing and arrangement position of the columns can be adjusted according to the actual process capabilities and requirements.

[0044] It should be noted that etching needs to ensure that a thin layer of metal is left at the bottom for subsequent wiring. And by controlling the etching parameters, the sidewall angle of the columns can be adjusted. For example, the columns are wider at the bottom and narrower at the top, and their sidewalls form a certain angle with the metal thin film layer.

[0045] S3. Deposit a dielectric layer and a metal layer on the surface of the columnar array at intervals.

[0046] Deposit multiple layers of dielectric and metal on the surface of the columnar array to form a capacitor structure. As Figure 3 shown as an example, on the surface of the columnar array 101, a first dielectric layer 102, a first metal layer 103, a second dielectric layer 104 and a second metal layer 105 are deposited in sequence.

[0047] In some embodiments of the present application, common materials for the first dielectric layer 102 and the second dielectric layer 104 include silicon dioxide (SiO 2 ), silicon nitride (SiNx), hafnium oxide (HfO 2 ), yttrium aluminate (Y 2 O 3 ), barium titanate (BaTiO 3 ), tantalum oxide (Ta 2 O 5 ), etc., or a combination of one or more materials.

[0048] Common materials for the first metal layer 103 and the second metal layer 105 include polysilicon (Poly-Si), tungsten (W), copper (Cu), titanium (Ti), ruthenium (Ru), etc., and combinations of one or more materials.

[0049] Among them, the methods for depositing and forming the first dielectric layer 102, the first metal layer 103, the second dielectric layer 104, and the second metal layer 105 include filling methods with high step coverage, such as atomic layer deposition process, etc.

[0050] It should be noted that the number of deposited metal layers and dielectric layers can be appropriately adjusted according to the actual process capabilities and requirements. This embodiment is only an exemplary illustration of depositing two metal layers and two dielectric layers respectively.

[0051] S4. Fill the first capacitor dielectric layer into the gaps of the columnar array to obtain the first capacitor structure.

[0052] As Figure 3 shown, deposit the first capacitor dielectric layer 106 to fill the gaps of the columnar array, and perform chemical mechanical polishing to make the surface flat without exposing the top of the capacitor structure.

[0053] In some embodiments of the present application, common materials for the first capacitor dielectric layer 106 include silicon oxide (SiO 2 ), silicon nitride (SiNx), etc., and combinations of one or more materials.

[0054] In some embodiments of the present application, the method for forming the first capacitor dielectric layer 106 includes filling methods with high step coverage, such as physical vapor deposition (PVD), chemical vapor deposition (CVD), atomic layer deposition (ALD), etc.

[0055] Specifically, chemical mechanical polishing is used for surface planarization, and other methods can also be used to achieve the same effect. For example, dry etching, wet etching, etc.

[0056] Specifically, the top of the capacitor structure should not be exposed during the planarization process, and the remaining thickness of the first capacitor dielectric layer 106 can be determined according to the design and process requirements.

[0057] S5. Perform photolithography and etching on the first capacitor structure to obtain a number of steps corresponding one by one to the bottom metal layer and the deposited metal layer.

[0058] S51. Perform photolithography on the first capacitor structure and etch based on the metal thin film layer to obtain the first step.

[0059] As Figure 4 shown, in Figure 3Perform lithography on the basis of the formed first capacitor structure to form a first step, perform etching and stop at the surface of the bottom metal layer to form a first step.

[0060] In an embodiment of the present invention, the width of the first step depends on the requirements of subsequent processes, particularly related to the size of the through electrode.

[0061] It should be noted that the etching needs to rely on a good selectivity to stop at the bottom surface of the 101 metal, at least without leaving the first metal layer 103 and the second metal layer 105, so that the bottom metal layer and the subsequent process can form a good electrical connection without short - circuiting with the first metal layer 103 and the second metal layer 105.

[0062] S52, Trim the photoresist to form a second step, then perform etching and stop at the surface of the first metal layer, and trim the photoresist to form a third step, then perform etching and stop at the surface of the second metal layer.

[0063] As Figure 5 shown, during the process of forming the second step, the etching needs to rely on a good selectivity to stop at the surface of the 103 metal, at least without leaving the second metal layer 105, so that the 103 metal layer and the subsequent process can form a good electrical connection without short - circuiting with the second metal layer 105. As Figure 6 shown, during the process of etching the third step, the etching needs to rely on a good selectivity to stop at the surface of the 105 metal. And avoid etching damage to the 101 metal layer and the 103 metal layer, at least ensure the integrity of the thin films of the 101 metal layer and the 103 metal layer.

[0064] The widths of the second step and the third step both depend on the requirements of subsequent processes. In an embodiment of the present invention, they are related to the size of the through electrode.

[0065] In an embodiment of the present invention, when trimming the photoresist, dry plasma etching is usually used for in - situ trimming.

[0066] It should be noted that trimming and etching of the photoresist can be carried out together in the same process without breaking the vacuum environment. The first step, the second step and the third step can be completed in different lithography steps, or three steps can be formed by multiple trimmings in one lithography. The position of the steps can be set at the edge position close to the semiconductor substrate according to requirements, or in the middle position.

[0067] S53, Remove the photoresist.

[0068] After forming three steps corresponding to 3 deposited metal layers, remove the photoresist.

[0069] S6, fill the second capacitor dielectric layer.

[0070] As Figure 7 shown, deposit the second capacitor dielectric layer 107 to fill and perform chemical mechanical polishing.

[0071] In some embodiments of the present application, common materials for the second capacitor dielectric layer 107 include silicon oxide (SiO 2 ), silicon nitride (SiNx), etc., a combination of one or more materials.

[0072] Among them, chemical mechanical polishing is used for surface planarization, and other methods can also be used to achieve the same effect, for example, dry etching, wet etching, etc.

[0073] It should be noted that the top of the capacitor structure should not be exposed during the planarization process, and the surface of the remaining second capacitor dielectric layer 107 can be parallel or non-parallel to the surface of the first capacitor dielectric layer 106.

[0074] S7, perform photolithography and etching based on the second capacitor dielectric layer to obtain a number of through electrodes respectively corresponding to and connected to the metal thin film or metal layer.

[0075] The etching stops at the surface of the bottom metal layer, the first metal layer 103 and the second metal layer 105 to form contacts. Subsequently, metal filling and chemical mechanical polishing are performed to form the through electrode 108.

[0076] Among them, photolithography is used to form cylindrical small holes, and the through electrode 108 is formed by etching the second capacitor dielectric layer 107. The through electrode 108 can be in the form of a connecting via. As Figure 8 shown, the connecting vias are represented by symbols T1, T2, T3. Each deposited metal layer is connected to at least one connecting via, and the number of connecting vias is related to the number of stacked metal film layers.

[0077] Based on the high selectivity of etching the second capacitor dielectric layer 107 for the metal layers 101, 103 and 105, electrical connections are formed.

[0078] S8, perform metal interconnection on the through electrodes to obtain a stacked capacitor with a parallel structure.

[0079] As Figure 9 shown, it is a top view of the capacitor structure after filling the second capacitor dielectric layer. The metal vias are connected through metal interconnection, so that the odd or even layers of the metal layers are respectively connected together to form the positive or negative electrode of the capacitor, thus forming a parallel structure of the capacitor. Through the parallel structure, the capacitance value is increased.

[0080] Through the above preparation method of the stacked capacitor, the stacked capacitor structure as Figure 8 shown is formed.

[0081] In another embodiment of the present invention, there is provided a packaging structure of a stacked capacitor prepared by the above method for preparing a stacked capacitor.

[0082] It should be noted that the stacked capacitor in the present application can be in the form of an on-chip capacitor or in the form of a capacitor structure in a chip for system-level packaging.

[0083] The packaging structure of the stacked capacitor includes a semiconductor substrate, a columnar array, a stepped portion, a connecting portion, and a filling dielectric layer. Among them, a metal thin film layer is deposited on the first surface of the semiconductor substrate to form a bottom metal layer; the columnar array includes at least a plurality of columns vertically carried on and communicating with the bottom metal layer, and a plurality of spaced dielectric layers and metal layers are deposited on the surface of the columnar array; the stepped portion is provided on one side of the semiconductor substrate and includes a plurality of staggered steps parallel to the bottom metal layer, the upper surface of each step corresponds to the metal layer deposited on the surface of the column, and the lower surface corresponds to the dielectric layer deposited on the surface of the column; the connecting portion includes a plurality of through electrodes perpendicular to the steps and penetrating the upper surfaces of the steps; the plurality of through electrodes are respectively connected as the positive and negative electrodes of the stacked capacitor to achieve capacitance parallel connection; the filling dielectric layer includes at least a first capacitor dielectric layer filled between the columns and a second capacitor dielectric layer filled between the through electrodes.

[0084] In one embodiment of the present invention, the top surface shape of the column can be circular, elliptical or other shapes, and the sidewall angle can be different according to device design and actual process capabilities.

[0085] The bottom metal layer can be the same or different metal as the columnar structure. The stacked capacitor needs to rely on multiple levels of steps to achieve external electrical connection of different metal layers. Each dielectric layer and metal layer are alternately stacked, and the thickness of each layer is related to device design and process capabilities. Different through electrodes can have different heights and can be achieved by one or multiple photolithography processes. The height of each step can also be the same or different. Among them, the through electrode can adopt a through hole or other connection forms.

[0086] The present invention discloses a packaging structure and a preparation method of a stacked capacitor. By etching to form a columnar array combined with a multi-layer stacked capacitor and using a capacitor parallel connection structure, the problems of difficult trench filling, complex etching control and extremely high cost in traditional deep trench capacitors are solved, and it has broad application prospects in scenarios such as advanced packaging and high-performance computing.

[0087] It should be noted that: In other embodiments, the steps of the corresponding method are not necessarily executed in the order shown and described in this specification. In some other embodiments, the steps included in the method may be more or less than those described in this specification. In addition, a single step described in this specification may be decomposed into multiple steps for description in other embodiments; and multiple steps described in this specification may also be combined into a single step for description in other embodiments.

[0088] Each embodiment in this specification is described in a progressive manner. For the same or similar parts among the embodiments, reference can be made to each other. Each embodiment focuses on the differences from other embodiments. In particular, for a system or a system embodiment, since it is basically similar to the method embodiment, the description is relatively simple. For the relevant parts, reference can be made to the partial description of the method embodiment. The systems and system embodiments described above are only illustrative, and some or all of the modules can be selected according to actual needs to achieve the purpose of the solution of this embodiment. A person of ordinary skill in the art can understand and implement it without creative work.

Claims

1. A packaging structure of a stacked capacitor, characterized in that: At least: A semiconductor substrate, wherein a metal film layer is deposited on a first surface of the semiconductor substrate to form a bottom metal layer; A columnar array, comprising at least a bottom metal layer and a plurality of columns vertically supported on and connected to the bottom metal layer, wherein a plurality of dielectric layers and metal layers disposed at intervals are deposited on the surface of the columnar array, wherein the metal layer deposited on the surface of the columnar array comprises at least two layers, and the columns are made of metal material; The step portion includes a plurality of steps arranged in parallel on the upper surface of the bottom metal layer, the upper surface of each step corresponds to the metal layer deposited on the surface of the column and the bottom metal layer respectively, and the lower surfaces of the remaining steps except the first step correspond to the dielectric layer deposited on the surface of the column respectively; A connecting portion, the connecting portion comprising a plurality of through electrodes, the through electrodes being vertically supported on the upper surface of the step and respectively connected with the upper surface of the corresponding step; the plurality of through electrodes are respectively connected as the positive electrode and the negative electrode of the stacked capacitor to realize capacitor parallel connection; The filling dielectric layer at least includes a first capacitor dielectric layer filled between the pillars and a second capacitor dielectric layer filled between the through electrodes.

2. The packaging structure of the stacked capacitor according to claim 1, characterized in that: The top surface of the column is circular or elliptical.

3. The packaging structure of the stacked capacitor according to claim 1, characterized in that: The width of the step is determined based on the size of the through electrode.

4. The packaging structure of the stacked capacitor according to claim 1, characterized in that: The first capacitor dielectric layer, the second capacitor dielectric layer and the dielectric layer are all made of at least one or a combination of silicon oxide, silicon nitride, hafnium oxide, yttrium aluminate, barium titanate and tantalum oxide.

5. The packaging structure of the stacked capacitor according to claim 1, characterized in that: The bottom metal layer and the metal layer are at least a combination of one or more materials selected from the group consisting of polysilicon, tungsten, copper, titanium and ruthenium.

6. A method for preparing a stacked capacitor having a packaging structure as claimed in any one of claims 1 to 5, characterized in that: include: Depositing a metal film on the first surface of the semiconductor substrate to form a bottom metal layer, performing photolithography and etching to form a plurality of pillars, wherein the pillars are vertically supported on the bottom metal layer and connected to the bottom metal layer, and the pillars and the bottom metal layer form a columnar array; Depositing a dielectric layer and a metal layer in sequence and at intervals on the surface of the columnar array; Filling the first capacitor dielectric layer to obtain a first capacitor structure; Photolithography and etching are performed on the first capacitor structure to obtain a plurality of steps corresponding to the bottom metal layer and the deposited metal layer respectively; Filling the second capacitor dielectric layer; Photolithography and etching are performed on the second capacitor dielectric layer to obtain a plurality of through electrodes corresponding to and connected to the bottom metal layer or metal layers; The through electrodes are metal interconnected to obtain a stacked capacitor with a parallel structure.

7. The method for preparing a stacked capacitor according to claim 6, characterized in that: The depositing of the dielectric layer, the depositing of the metal layer, the filling of the first capacitor dielectric layer, and the filling of the second capacitor dielectric layer adopt a filling method with a high step coverage rate.

8. The method for preparing a stacked capacitor according to claim 6, characterized in that: The filled second capacitor dielectric layer and the second dielectric layer are planarized by at least one or more of chemical mechanical grinding, dry etching and wet etching.

9. The method for preparing a stacked capacitor according to claim 6, characterized in that: The photolithography and etching of the second capacitor dielectric layer to obtain a plurality of through electrodes connected to the bottom metal layer or metal layer specifically includes etching on the step based on the selection ratio of the second capacitor dielectric layer and the metal layer to obtain the through electrodes.

10. The method for preparing a stacked capacitor according to claim 6, wherein: The first capacitor structure is photolithographically and etched to obtain a plurality of steps corresponding to the bottom metal layer and the deposited metal layer, respectively, including: forming a plurality of steps by one photolithography and multiple photoresist trimmings; the photoresist trimmings are at least trimmed in situ by dry plasma etching.

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