Semiconductor structure, preparation method thereof and chip

Abstract

The invention provides a semiconductor structure, a preparation method thereof and a chip, relates to the technical field of semiconductors, and aims to reduce the process difficulty. The preparation method of the semiconductor structure comprises the following steps: forming a first electrode on a substrate by adopting a sputtering process; forming a dielectric layer on one side, far away from the substrate, of the first electrode; forming a second electrode on one side, far away from the substrate, of the dielectric layer; wherein in the process of forming the first electrode, the substrate is heated, and direct current bias voltage or radio frequency bias power is applied to the substrate; the heating temperature of the substrate ranges from 50 DEG C to 400 DEG C, and the direct current bias voltage changes in the range of-500V to + 150V or the radio frequency bias power changes in the range of 50w to 400w. The semiconductor structure can be applied to a memory chip or a sensor chip, the memory chip can be a nonvolatile memory, and the sensor chip can be a micro electro mechanical system pressure sensor.

Description

Technical Field

[0001] The present application relates to the field of semiconductor technology, and in particular to a semiconductor structure and a preparation method thereof, and a chip. Background Art

[0002] At present, ultra-small sensors using Micro-Electro-Mechanical System (MEMS) technology are becoming mainstream. In MEMS pressure sensors, chemical solution deposition (CSD) process can be used to form films. The cost of the CSD process is low, but its process temperature is high (600℃~750℃), which limits the freedom of material use and process selection and increases the difficulty of the process. Summary of the invention

[0003] The present application proposes a semiconductor structure and a method for preparing the same, as well as a chip, aiming to reduce the difficulty of the process.

[0004] To achieve the above objectives, the embodiments of the present application provide the following technical solutions: On the one hand, a method for preparing a semiconductor structure is provided, the method comprising: forming a first electrode on a substrate by a sputtering process; forming a dielectric layer on a side of the first electrode away from the substrate; forming a second electrode on a side of the dielectric layer away from the substrate; wherein, in the process of forming the first electrode, the substrate is heated, and a DC bias voltage or a radio frequency bias power is applied to the substrate; the heating temperature range of the substrate is 50°C to 400°C, the DC bias voltage varies in the range of -500V to +150V, or the radio frequency bias power varies in the range of 50W to 400W.

[0005] The preparation method provided in the embodiment of the present application adopts a sputtering process to form a first electrode. During the sputtering process, a DC bias voltage is applied to the substrate, and the DC bias voltage varies in the range of -500V to +150V. It can be understood that when the DC bias voltage is a negative voltage, argon ions in the vacuum chamber can be attracted to bombard the substrate. When the DC bias voltage is a positive voltage, electrons in the vacuum chamber can be attracted to bombard the substrate, and plasma heat is generated on the surface of the substrate. The surface temperature of the substrate can be increased, and the subsequent crystal growth of the dielectric material can be promoted. Therefore, even if the heating temperature of the substrate is reduced to the range of 50°C to 400°C, the film quality and characteristics of the subsequently formed dielectric layer can be guaranteed.

[0006] Alternatively, during the sputtering process, an RF bias power is applied to the substrate, and the RF bias power varies in the range of 50W to 400W. It can be understood that when the RF bias power is negative, argon ions in the vacuum chamber can be attracted to bombard the substrate, and when the RF bias power is positive, electrons in the vacuum chamber can be attracted to bombard the substrate, and the surface temperature of the substrate can be increased, which can promote the subsequent crystal growth of the dielectric material. Therefore, even if the heating temperature of the substrate is reduced to the range of 50°C to 400°C, the film quality and characteristics of the subsequently formed dielectric layer can be guaranteed.

[0007] Moreover, compared with using a heater to heat the substrate, or the plasma heat generated by the target atoms falling off and bombarding the substrate, the plasma heat generated by the argon ions and electrons bombarding the substrate can be controlled by controlling the change of the DC bias voltage or the RF bias power. This method is easy to control and has a good heating effect on the substrate.

[0008] In some embodiments, the heating temperature of the substrate ranges from 100°C to 250°C.

[0009] In some embodiments, during the process of forming the dielectric layer by sputtering, the substrate is heated, and the heating temperature of the substrate ranges from 100° C. to 300° C.

[0010] In some embodiments, during the process of forming the dielectric layer by sputtering process, a DC bias voltage or a radio frequency bias power is applied to the substrate, and the DC bias voltage varies in the range of -500V to +150V or the radio frequency bias power varies in the range of 50W to 400W.

[0011] In some embodiments, before forming the first electrode, an adhesion layer is formed on the substrate, the adhesion layer being in contact with the substrate. Forming the first electrode includes: forming the first electrode on a side of the adhesion layer away from the substrate.

[0012] In some embodiments, forming the dielectric layer includes: forming a dielectric film on a side of the first electrode away from the substrate; and patterning the dielectric film using a photolithography process to form the dielectric layer.

[0013] In some embodiments, during the process of forming the first electrode, the heating temperature of the substrate is 200° C., the DC bias voltage is −300 V or the RF bias power is 250 W.

[0014] In some embodiments, the material of the dielectric layer includes a piezoelectric material. During the process of forming the dielectric layer, the heating temperature of the substrate is 200° C., the DC bias voltage is −250 V or the RF bias power is 250 W.

[0015] In some embodiments, the substrate includes a first surface and a second surface relative to each other, and a first electrode is formed on the first surface of the substrate; before forming the first electrode, the preparation method also includes: setting a bias voltage electrode on the second surface of the substrate, and the bias voltage electrode is used to apply a DC bias voltage or a radio frequency bias power to the substrate.

[0016] In some embodiments, before forming the first electrode, the preparation method further includes: disposing a magnet on the second surface of the substrate.

[0017] On the other hand, a semiconductor structure is provided. The semiconductor structure is prepared by the preparation method described in any of the above embodiments. The semiconductor structure includes a substrate, and a first electrode, a dielectric layer, and a second electrode stacked on the substrate.

[0018] On the other hand, a chip is provided. The chip includes the semiconductor structure described in the above embodiment.

[0019] The above-mentioned semiconductor structure and chip have the same structure and beneficial technical effects as the preparation methods provided in some of the above-mentioned embodiments, which will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0020] In order to more clearly illustrate the technical solution in the present application, the following is a brief introduction to the drawings required for use in some embodiments of the present application. Obviously, the drawings described below are only drawings of some embodiments of the present application. For ordinary technicians in this field, other drawings can also be obtained based on these drawings. In addition, the drawings described below can be regarded as schematic diagrams, not the actual size of the product involved in the embodiments of the present application, or the actual process of the method.

[0021] Figure 1 An architectural diagram of a memory chip provided in an embodiment of the present application; Figure 2 A structural diagram of a sensor chip provided in an embodiment of the present application; Figure 3 A structural diagram of a semiconductor structure provided in an embodiment of the present application; Figure 4 A diagram of steps for setting a substrate for a semiconductor structure provided in an embodiment of the present application; Figure 5 A diagram of a step for preparing a first electrode provided in an embodiment of the present application; Figure 6 A parameter diagram of the operating voltage of the magnetron sputtering device provided in an embodiment of the present application; Figure 7 Another step diagram for preparing the first electrode provided in an embodiment of the present application; Figure 8A step diagram for preparing a dielectric layer provided in an embodiment of the present application; Fig. 9 Another step diagram for preparing a dielectric layer provided in an embodiment of the present application; Fig.10 A diagram showing the steps for preparing the second electrode provided in an embodiment of the present application. DETAILED DESCRIPTION

[0022] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments provided by the present application, all other embodiments obtained by ordinary technicians in this field belong to the scope of protection of the present application.

[0023] Unless the context requires otherwise, throughout the specification and claims, the term "comprising" is to be construed in an open, inclusive sense, ie, meaning "including, but not limited to."

[0024] In the following, the terms "first" and "second" are used for descriptive purposes only and are not to be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of the present application, unless otherwise specified, "plurality" means two or more.

[0025] When describing some embodiments, the term "connection" and its derivative expressions may be used. The term "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, a detachable connection, or an integral connection; it can be directly connected or indirectly connected through an intermediate medium. For example, when describing some embodiments, the term "connection" may be used to indicate that two or more components are in direct physical or electrical contact with each other.

[0026] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0027] It will be understood that when a layer or an element is referred to as being on another layer or substrate, it can be directly on the other layer or substrate, or intervening layers may be present between the layer or element and the other layer or substrate.

[0028] Exemplary embodiments are described herein with reference to cross-sectional views that are idealized exemplary drawings. In the drawings, the thickness of layers and the area of ​​regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device, and are not intended to limit the scope of the exemplary embodiments.

[0029] An embodiment of the present application provides a chip, which may be a memory chip or a sensor chip. Figure 1 This is an architectural diagram of the memory chip provided in an embodiment of the present application.

[0030] See also Figure 1 In the case where chip 1 is a memory chip, the memory chip may be a non-volatile memory. The non-volatile memory includes a plurality of memory cells arranged in an array, and each memory cell includes a ferroelectric capacitor.

[0031] Figure 2 This is a structural diagram of the sensor chip provided in an embodiment of the present application.

[0032] See also Figure 2 In the case where the chip 1 is a sensor chip, the sensor chip may be a micro-electro-mechanical system (MEMS) pressure sensor. The MEMS pressure sensor includes at least one sensor unit, and each sensor unit includes a piezoelectric device.

[0033] The above-mentioned ferroelectric capacitors and piezoelectric devices have the following characteristics: Figure 3 The semiconductor structure shown is shown in Figure 3 The semiconductor structure 10 includes a substrate 11, and a first electrode 12, a dielectric layer 13, and a second electrode 14 stacked on the substrate 11. When the semiconductor structure 10 is a ferroelectric capacitor, the material of the dielectric layer 13 includes a ferroelectric material. Alternatively, when the semiconductor structure 10 is a piezoelectric device, the material of the dielectric layer 13 includes a piezoelectric material.

[0034] Exemplarily, the semiconductor structure 10 further includes an isolation layer 19 , which is disposed between the substrate 11 and the first electrode 12 . The isolation layer 19 is used to isolate the first electrode 12 from the substrate 11 to prevent alloying of the two and affecting the conductivity of the first electrode 12 .

[0035] Exemplarily, the semiconductor structure 10 further includes a first adhesion layer 15, which is disposed between the substrate 11 and the first electrode 12, and is used to improve the adhesion between the first electrode 12 and the substrate 11. When the semiconductor structure 10 further includes an isolation layer 19, the first adhesion layer 15 is disposed between the isolation layer 19 and the first electrode 12.

[0036] Exemplarily, the semiconductor structure 10 further includes a second adhesion layer 18 , which is disposed between the dielectric layer 13 and the second electrode 14 , and is used to improve adhesion between the second electrode 14 and the dielectric layer 13 .

[0037] In the process of preparing the above-mentioned semiconductor structure 10, a first electrode 12 is first formed on the substrate 11, and then a dielectric layer 13 is formed on the first electrode 12. In order to promote the crystal growth of the dielectric material, the substrate 11 is usually required to be heated to a high temperature of 500°C~600°C. Due to the high heating temperature of the substrate 11, the material use of the substrate 11 and the freedom of process selection are limited, which increases the process difficulty of preparing the semiconductor structure 10.

[0038] In order to solve the above problems, an embodiment of the present application further provides a method for preparing a semiconductor structure. Figure 4~Figure 10 A diagram of the steps for preparing a semiconductor structure provided in an embodiment of the present application.

[0039] See also Figure 4 , placing the substrate 11 in a vacuum chamber 2 of a magnetron sputtering device.

[0040] Exemplarily, the substrate 11 is a silicon substrate. In this case, the substrate 11 is first cleaned by Standard Cleaning 1 (SC-1), and the cleaning solution used includes ammonium hydroxide (chemical formula: NH4OH), hydrogen peroxide (chemical formula: H2O2) and water (chemical formula: H2O). Then, the substrate 11 is cleaned by Standard Cleaning 2 (SC-2), and the cleaning solution used includes hydrogen chloride (chemical formula: HCl), hydrogen peroxide (chemical formula: H2O2) and water (chemical formula: H2O). Finally, the substrate 11 is placed in the vacuum chamber 2 of the magnetron sputtering device, for example, the substrate 11 is placed on the carrier 3 in the vacuum chamber 2.

[0041] Exemplarily, the substrate 11 is a quartz substrate. In this case, the substrate 11 is first cleaned with an alkoxy cleaning solution, and then cleaned with a cleaning solution containing sulfuric acid (chemical formula: H2SO4) and hydrogen peroxide (chemical formula: H2O2). After the substrate 11 is dried, it is placed in the vacuum chamber 2 of the magnetron sputtering equipment. For example, the substrate 11 is placed on the carrier 3 in the vacuum chamber 2.

[0042] See also Figure 5 A sputtering process is used to form a first electrode 12 on a substrate 11. In the process of forming the first electrode 12, the substrate 11 is heated, the heating temperature of the substrate 11 is in the range of 50°C to 400°C, and a DC bias voltage is applied to the substrate 11 through an anode, and the DC bias voltage varies in the range of -500V to +150V.

[0043] For example, Figure 5 As shown, the electrode target 16 is placed at the cathode of the magnetron sputtering device, and argon gas, or argon gas and oxygen gas, or argon gas and nitrogen gas are introduced into the vacuum chamber 2 through the gas inlet. A magnetic field is set near the electrode target 16, and the electrons in the magnetic field are subjected to the Lorentz force to make spiral motion, which can increase the number of collisions between the electrons and the argon molecules, and increase the number of argon ions generated by the ionization of the argon molecules, thereby increasing the density of the plasma in the vacuum chamber 2. Under the action of the electric field, the argon ions are accelerated and bombarded on the surface of the electrode target 16, causing the target atoms to fall off and deposit on the substrate 11 to form the first electrode 12.

[0044] Furthermore, during the process of forming the first electrode 12 by magnetron sputtering, the stage 3 may be rotated to drive the substrate 11 to rotate, which is beneficial to improving the thickness uniformity of the first electrode 12 .

[0045] For example, see Figure 6 The cathode of the magnetron sputtering equipment receives the target reference voltage, and the anode receives the DC bias voltage. The DC bias voltage varies in the range of -500V~+150V, ensuring that the DC bias voltage is always greater than the target reference voltage, so that the argon ions are accelerated and bombard the target material under the action of the electric field, that is, the value of the target reference voltage should be less than the minimum value of the DC bias voltage -500V.

[0046] Illustratively, during the process of forming the first electrode 12, the heating temperature of the substrate 11 is 50° C., 100° C., 200° C., 225° C., 250° C., 300° C., or 400° C. Illustratively, during the process of forming the first electrode 12, the DC bias voltage applied to the substrate 11 is -500V, -300V, -250V, -175V, +100V, or +150V.

[0047] For example, in the process of forming the first electrode 12 , the heating temperature of the substrate 11 is 200° C., and the DC bias voltage applied to the substrate 11 is −300V.

[0048] Alternatively, see Figure 7 A sputtering process is used to form a first electrode 12 on a substrate 11. In the process of forming the first electrode 12, the substrate 11 is heated, the heating temperature of the substrate 11 is in the range of 50°C to 400°C, and a radio frequency bias power is applied to the substrate 11 through an anode, and the radio frequency bias power varies in the range of 50W to 400W.

[0049] Illustratively, during the process of forming the first electrode 12, the heating temperature of the substrate 11 is 50° C., 100° C., 225° C., 250° C., 300° C., or 400° C. Illustratively, during the process of forming the first electrode 12, the RF bias power applied to the substrate 11 is 50W, 100W, 225W, 250W, or 400W.

[0050] For example, in the process of forming the first electrode 12, the heating temperature of the substrate 11 is 200°C, and the radio frequency bias power applied to the substrate 11 is 250W.

[0051] In the above-mentioned embodiment of the present application, a sputtering process is adopted to form the first electrode 12. During the sputtering process, a DC bias voltage is applied to the substrate 11 through the anode, and the DC bias voltage varies in the range of -500V to +150V. It can be understood that when the DC bias voltage is a negative voltage, argon ions in the vacuum chamber 2 can be attracted to bombard the substrate 11. When the DC bias voltage is a positive voltage, electrons in the vacuum chamber 2 can be attracted to bombard the substrate 11, and plasma heat is generated on the surface of the substrate 11. The surface temperature of the substrate 11 can be increased, and the subsequent crystal growth of the dielectric material can be promoted. Therefore, even if the heating temperature of the substrate 11 is reduced to the range of 50°C to 400°C, the film quality and characteristics of the subsequently formed dielectric layer can be guaranteed.

[0052] Alternatively, during the sputtering process, an RF bias power is applied to the substrate 11 through the anode, and the RF bias power varies in the range of 50W~400W. It can be understood that when the RF bias power is negative, argon ions in the vacuum chamber 2 can be attracted to bombard the substrate 11, and when the RF bias power is positive, electrons in the vacuum chamber 2 can be attracted to bombard the substrate 11, and the surface temperature of the substrate 11 can be increased, which can promote the subsequent crystal growth of the dielectric material. Therefore, even if the heating temperature of the substrate 11 is reduced to the range of 50℃~400℃, the film quality and characteristics of the subsequently formed dielectric layer can be guaranteed.

[0053] Furthermore, compared to heating the substrate 11 with a heater, or generating plasma heat when target atoms fall off and bombard the substrate 11, the plasma heat generated by argon ions and electrons bombarding the substrate 11 can be controlled by controlling the change of the DC bias voltage or the RF bias power. This method is easy to control and has a good heating effect on the substrate 11.

[0054] Illustratively, during the process of forming the first electrode 12 , the substrate 11 is heated, and the heating temperature of the substrate 11 ranges from 100° C. to 250° C. When the heating temperature of the substrate 11 is lowered, the film quality and characteristics of the dielectric layer 13 can also be guaranteed.

[0055] Exemplarily, before forming the first electrode 12 on the substrate 11, an isolation layer 19 can be first formed on the substrate 11. The material of the isolation layer 19 can include at least one of silicon dioxide (chemical formula: SiO2), zirconium dioxide (chemical formula: ZrO2), silicon carbide (chemical formula: SiC), strontium ruthenate (chemical formula: SrRuO3), or strontium titanate (chemical formula: SrTiO3) or aluminum oxide (chemical formula: Al2O3). The film thickness of the isolation layer 19 ranges from 0.003μm to 1μm. The isolation layer 19 is used to isolate the first electrode 12 from the substrate 11 to prevent the two from alloying and affecting the conductive properties of the first electrode 12.

[0056] For example, when the material of the isolation layer 19 includes silicon dioxide, tetraethoxysilane (Tetraethyl orthosilicate, TEOS) can be used to form a silicon dioxide film layer in a low temperature process.

[0057] For example, see Figure 5 and Figure 7 Before forming the first electrode 12 on the substrate 11, a first adhesion layer 15 is formed on the substrate 11. The first adhesion layer 15 is used to improve the adhesion between the first electrode 12 and the substrate 11. The material of the first adhesion layer 15 may include at least one of titanium (chemical formula: Ti), iridium dioxide (chemical formula: IrO2), zirconium dioxide or chromium (chemical formula: Cr). The film thickness of the first adhesion layer 15 ranges from 3nm to 200nm. Finally, the first electrode 12 is formed on the side of the first adhesion layer 15 away from the substrate 11.

[0058] In other embodiments, since the heating temperature of the substrate 11 is reduced during the process of forming the first electrode 12, the first electrode 12 is not easily alloyed with the substrate 11. Therefore, it is not necessary to form an isolation layer 19 on the substrate 11 before forming the first adhesion layer 15. The isolation layer 19 is not set between the first adhesion layer 15 and the substrate 11, that is, the first adhesion layer 15 can be in direct contact with the substrate 11, which can simplify the process and reduce the process cost.

[0059] Exemplarily, the material of the first electrode 12 may include at least one of platinum (chemical formula: Pt), iridium (chemical formula: Ir), rhenium (chemical formula: Re), ruthenium (chemical formula: Ru) or titanium nitride (chemical formula: TiN), and the film thickness of the first electrode 12 ranges from 10nm to 1500nm.

[0060] In some embodiments, see Figure 5 and Figure 7 The substrate 11 includes a first surface 11a and a second surface 11b opposite to each other, and a first electrode 12 is formed on the first surface 11a of the substrate 11. Before forming the first electrode 12, a bias voltage electrode 4 is also provided on the second surface 11b of the substrate 11. For example, the bias voltage electrode 4 can be formed on the surface of the stage 3, and the bias voltage electrode 4 is used to apply a DC bias voltage or a radio frequency bias power to the substrate 11.

[0061] In some embodiments, see Figure 5 and Figure 7 Before forming the first electrode 12, a magnet may be disposed on the second surface 11b of the substrate 11. By disposing a magnetic field near the substrate 11, the number of collisions between electrons and argon molecules near the substrate 11 may be increased, the number of argon ions may be increased, and the density of plasma near the substrate 11 may be increased.

[0062] Based on this, in the process of forming the first electrode 12, by applying a DC bias voltage or a radio frequency bias power to the substrate 11, the number of argon ions and electrons bombarding the substrate 11 can be increased, thereby further increasing the surface temperature of the substrate 11 and promoting the subsequent crystal growth of the dielectric material, which is beneficial to reducing the heating temperature of the substrate 11 and ensuring the film quality and characteristics of the dielectric layer 13.

[0063] See also Figure 8 A dielectric layer 13 is formed on a side of the first electrode 12 away from the substrate 11 .

[0064] For example, Figure 8 As shown, a dielectric target 17 is placed at the cathode of a magnetron sputtering device, and argon gas, or argon gas and oxygen gas, or argon gas and nitrogen gas are introduced into the vacuum chamber 2 through the gas inlet. The composition of the gas introduced depends on the purpose of the dielectric layer 13 to be formed. Electrons in a magnetic field are subjected to the Lorentz force to perform spiral motion, which can increase the number of collisions between electrons and argon molecules, and increase the number of argon ions generated by ionization of argon molecules, thereby increasing the density of plasma in the vacuum chamber 2. Argon ions are accelerated under the action of the electric field and bombard the surface of the dielectric target 17, causing the target atoms to fall off and deposit on the substrate 11, forming a dielectric film on the entire surface. Then, a photolithography process is used to pattern the dielectric film to form a dielectric layer 13.

[0065] During the process of forming the dielectric thin film, the substrate 11 is heated, and the heating temperature of the substrate 11 ranges from 100°C to 300°C. For example, the heating temperature of the substrate 11 is 100°C, 150°C, 200°C, 250°C or 300°C.

[0066] It can be understood that, since a DC bias voltage or RF bias power is applied to the substrate 11 during the process of forming the first electrode 12, and the DC bias voltage or RF bias power is dynamically switched between positive and negative values, argon ions and electrons in the vacuum chamber 2 can be attracted to bombard the substrate 11, thereby increasing the surface temperature of the substrate 11. Therefore, in the process of forming the dielectric thin film, the heating temperature of the substrate 11 can be reduced to 100°C~300°C, and the crystal growth of the dielectric material can be promoted, thereby ensuring the film quality and characteristics of the dielectric layer 13.

[0067] Furthermore, the substrate 11 does not need to be subjected to high temperature treatment after film formation, so that the temperature of the substrate 11 can adapt to the temperature of the photolithography process. Therefore, after the dielectric film is formed, the photolithography process can be used to pattern the dielectric film to form the dielectric layer 13.

[0068] For example, Figure 8 As shown, during the process of forming the dielectric layer 13, a DC bias voltage is applied to the substrate 11, and the DC bias voltage varies in the range of -500V to +150V.

[0069] For example, during the formation of the dielectric layer 13 , the DC bias voltage applied to the substrate 11 is −500 V, −250 V, −175 V, +100 V, or +150 V.

[0070] When the semiconductor structure 10 is a piezoelectric device, the material of the dielectric layer 13 includes a piezoelectric material. During the formation of the dielectric layer 13 , the heating temperature of the substrate 11 is 200° C., and the DC bias voltage applied to the substrate 11 is −250V.

[0071] Or, if Fig. 9 As shown, during the process of forming the dielectric layer 13, a radio frequency bias power is applied to the substrate 11, and the radio frequency bias power varies in the range of 50W to 400W.

[0072] For example, during the formation of the dielectric layer 13 , the RF bias power applied to the substrate 11 is 50 W, 100 W, 225 W, 250 W, or 400 W.

[0073] When the semiconductor structure 10 is a piezoelectric device, the material of the dielectric layer 13 includes a piezoelectric material. During the formation of the dielectric layer 13 , the heating temperature of the substrate 11 is 200° C., and the radio frequency bias power applied to the substrate 11 is 250 W.

[0074] In the above-mentioned embodiment of the present application, the sputtering process is adopted to form the dielectric layer 13. During the sputtering process, a DC bias voltage is applied to the substrate 11 through the anode, and the DC bias voltage varies in the range of -500V~+150V. It can be understood that when the DC bias voltage is a negative voltage, argon ions in the vacuum chamber 2 can be attracted to bombard the substrate 11. When the DC bias voltage is a positive voltage, electrons in the vacuum chamber 2 can be attracted to bombard the substrate 11, and plasma heat is generated on the surface of the substrate 11. The surface temperature of the substrate 11 can be increased, and the crystal growth of the dielectric material can be promoted. Therefore, even if the heating temperature of the substrate 11 is reduced to the range of 100°C~300°C, the film quality and characteristics of the dielectric layer 13 can be guaranteed.

[0075] Alternatively, during the sputtering process, an RF bias power is applied to the substrate 11 through the anode, and the RF bias power varies in the range of 50W~400W. It can be understood that when the RF bias power is negative, argon ions in the vacuum chamber 2 can be attracted to bombard the substrate 11, and when the RF bias power is positive, electrons in the vacuum chamber 2 can be attracted to bombard the substrate 11, and the surface temperature of the substrate 11 can also be increased to promote the crystal growth of the dielectric material. Therefore, even if the heating temperature of the substrate 11 is reduced to the range of 100℃~300℃, the film quality and characteristics of the dielectric layer 13 can be guaranteed.

[0076] Furthermore, compared to heating the substrate 11 with a heater, or generating plasma heat when target atoms fall off and bombard the substrate 11, the plasma heat generated by argon ions and electrons bombarding the substrate 11 can be controlled by controlling the change of the DC bias voltage or the RF bias power. This method is easy to control and has a good heating effect on the substrate 11.

[0077] In addition, since the heating temperature of the substrate 11 is reduced during the process of forming the dielectric layer 13, the first electrode 12 is not easily alloyed with the substrate 11. Therefore, there is no need to form an isolation layer 19 on the substrate 11 before forming the first adhesion layer 15. The isolation layer 19 is not set between the first adhesion layer 15 and the substrate 11, that is, the first adhesion layer 15 can be in direct contact with the substrate 11, which can simplify the process and reduce the process cost.

[0078] Exemplarily, the film thickness of the dielectric layer 13 is different according to different uses. In the case where the semiconductor structure 10 is a piezoelectric device, the material of the dielectric layer 13 includes a piezoelectric material, for example, the piezoelectric material may include at least one of lead zirconate titanate (PZT: PbTiO3 / PbZrO3) or lead niobate titanate (PNZT: PbTiO3 / PbZrO3 / PbNbO3), and the film thickness of the dielectric layer 13 ranges from 0.001 μm to 400 μm.

[0079] See also Fig.10 , a second electrode 14 is formed on a side of the dielectric layer 13 away from the substrate 11 , and thus the preparation of the semiconductor structure 10 is completed.

[0080] Exemplarily, before forming the second electrode 14 on the substrate 11, a second adhesion layer 18 is formed on the substrate 11, and the second adhesion layer 18 is used to improve the adhesion between the second electrode 14 and the dielectric layer 13. The material of the second adhesion layer 18 may include at least one of titanium, iridium dioxide, zirconium dioxide or chromium, and the film thickness of the second adhesion layer 18 ranges from 3nm to 200nm.

[0081] For example, a magnetron sputtering process may be used to form the second electrode 14. Fig.10 As shown, the electrode target 16 is placed at the cathode of the magnetron sputtering device, and argon gas, or argon gas and oxygen gas, or argon gas and nitrogen gas are introduced into the vacuum chamber 2 through the gas inlet. A magnetic field is set near the electrode target 16, and the electrons in the magnetic field are subjected to the Lorentz force to make spiral motion, which can increase the number of collisions between the electrons and the argon molecules, and increase the number of argon ions generated by the ionization of the argon molecules, thereby increasing the density of the plasma in the vacuum chamber 2. Under the action of the electric field, the argon ions are accelerated and bombarded on the surface of the electrode target 16, causing the target atoms to fall off and deposit on the substrate 11 to form the second electrode 14.

[0082] Furthermore, during the process of forming the second electrode 14 by magnetron sputtering, the stage 3 may be rotated to drive the substrate 11 to rotate, which is beneficial to improving the thickness uniformity of the second electrode 14 .

[0083] Exemplarily, the material of the second electrode 14 may include at least one of platinum, iridium, rhenium or ruthenium, and the film thickness of the second electrode 14 ranges from 10 nm to 1500 nm.

[0084] In order to verify the above embodiment, the inventors of the present application also conducted the following comparative experiments: Comparative example: During the process of forming the first electrode and the dielectric layer, the substrate is heated at a temperature of 600° C., and no DC bias voltage is applied to the substrate.

[0085] Example 1: In the process of forming the first electrode 12, the substrate 11 is heated, the heating temperature of the substrate 11 is 250°C, and no DC bias voltage is applied to the substrate; in the process of forming the dielectric layer 13, the substrate 11 is heated, the heating temperature of the substrate 11 is 250°C, and a DC bias voltage is applied to the substrate 11, and the DC bias voltage is -250V.

[0086] Example 2: In the process of forming the first electrode 12, the substrate 11 is heated, the heating temperature of the substrate 11 is 200°C, and a DC bias voltage is applied to the substrate 11, and the DC bias voltage is -300V; in the process of forming the dielectric layer 13, the substrate 11 is heated, the heating temperature of the substrate 11 is 200°C, and a DC bias voltage is applied to the substrate 11, and the DC bias voltage is -250V.

[0087] The comparison between the comparative example and the embodiment can be achieved by obtaining a hysteresis loop (PE loop) of the dielectric layer 13, or observing the cross section of the dielectric layer 13 using a scanning electron microscope (SEM), or obtaining an XRD curve of the dielectric layer 13 using an X-ray diffractometer.

[0088] The results show that the film quality of the dielectric layer 13 in the comparative example, embodiment 1 and embodiment 2 is similar. By comparing the comparative example and embodiment 1, it can be seen that in the process of forming the dielectric layer 13, by applying a DC bias voltage of -250V to the substrate 11, even if the substrate 11 is not heated to 600°C, the heating temperature of the substrate 11 is reduced to 250°C, and the same crystal growth quality can be obtained.

[0089] Furthermore, by comparing Example 1 and Example 2, it can be seen that in the process of forming the first electrode 12, by applying a DC bias voltage of -300V to the substrate 11, even if the substrate 11 is not heated to 250°C, the same crystal growth quality can be obtained by reducing the heating temperature of the substrate 11 to 200°C.

[0090] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that a person skilled in the art can think of within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application should be based on the protection scope of the claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that: include: Forming a first electrode on the substrate by a sputtering process; forming a dielectric layer on a side of the first electrode away from the substrate; forming a second electrode on a side of the dielectric layer away from the substrate; Wherein, in the process of forming the first electrode, the substrate is heated, and a DC bias voltage or a radio frequency bias power is applied to the substrate; The heating temperature range of the substrate is 50° C. to 400° C., the DC bias voltage varies in the range of -500V to +150V, or the RF bias power varies in the range of 50W to 400W.

2. The preparation method according to claim 1, characterized in that: The heating temperature of the substrate ranges from 100°C to 250°C.

3. The preparation method according to claim 1, characterized in that: In the process of forming the dielectric layer by sputtering process, the substrate is heated, and the heating temperature of the substrate is in the range of 100°C to 300°C.

4. The preparation method according to claim 1, characterized in that: In the process of forming the dielectric layer by sputtering process, a DC bias voltage or a radio frequency bias power is applied to the substrate, and the DC bias voltage varies in the range of -500V to +150V or the radio frequency bias power varies in the range of 50W to 400W.

5. The preparation method according to claim 1, characterized in that: Before forming the first electrode, the preparation method further includes: forming an adhesion layer on a substrate, wherein the adhesion layer contacts the substrate; Forming the first electrode includes: The first electrode is formed on a side of the adhesion layer away from the substrate.

6. The preparation method according to claim 1, characterized in that: Forming the dielectric layer includes: forming a dielectric film on a side of the first electrode away from the substrate; The dielectric film is patterned by using a photolithography process to form the dielectric layer.

7. The preparation method according to claim 1, characterized in that: In the process of forming the first electrode, the heating temperature of the substrate is 200° C., the DC bias voltage is -300V or the RF bias power is 250W.

8. The preparation method according to claim 7, characterized in that: The material of the dielectric layer includes piezoelectric material; In the process of forming the dielectric layer, the heating temperature of the substrate is 200° C., the DC bias voltage is -250V or the RF bias power is 250W.

9. The preparation method according to claim 1, characterized in that: The substrate comprises a first surface and a second surface opposite to each other, and the first electrode is formed on the first surface of the substrate; Before forming the first electrode, the preparation method further includes: A bias voltage electrode is disposed on the second surface of the substrate, and the bias voltage electrode is used to apply a direct current bias voltage to the substrate.

10. The preparation method according to claim 9, characterized in that: Before forming the first electrode, the preparation method further includes: A magnet is disposed on the second surface of the substrate.

11. A semiconductor structure, characterized in that: The invention comprises a substrate, and a first electrode, a dielectric layer and a second electrode stacked on the substrate; The semiconductor structure is prepared by the preparation method according to any one of claims 1 to 10.

12. A chip, characterized in that: Comprising the semiconductor structure as claimed in claim 11.

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