Silicon carbide VDMOS (Vertical Double-diffused Metal Oxide Semiconductor) with high drain voltage impact resistance and preparation method

Abstract

The invention provides a silicon carbide VDMOS (Vertical Double-diffused Metal Oxide Semiconductor) with high drain voltage impact resistance and a preparation method. The preparation method comprises the following steps: epitaxially growing a first drift region on a silicon carbide substrate with a drain metal layer; the drift layer comprises a first drift region and a second drift region; forming a barrier layer, etching, performing ion implantation, forming a plurality of uniformly spaced masking layers, a P-type well region, an N-type source region and an N-type region, re-forming the barrier layer, etching, and oxidizing to form an insulating dielectric layer; depositing metal, forming a gate metal layer, re-forming a barrier layer, etching and depositing metal, and forming a source metal layer; and removing the barrier layer to complete preparation. The reliability of the device for resisting the voltage impact of the drain electrode is improved, the gate-source capacitance of the device is reduced, the switching speed of the device is improved, the switching loss of the device is reduced, meanwhile, the body diode conduction loss of the device can be reduced, and the reverse recovery speed of the device is improved.

Description

Technical Field

[0001] The invention relates to a silicon carbide VDMOS with high resistance to drain voltage impact and a preparation method thereof. Background Art

[0002] SiC MOSFET is a typical representative of SiC power devices, and is widely used in electric vehicles, aerospace, power conversion and other fields. For SiC power MOSFET, the performance requirements for devices in different fields have different focuses, but the overall requirements include lower on-resistance, faster switching speed, higher reliability (including gate reliability, drain voltage impact reliability, etc.), and lower body diode conduction loss. Summary of the invention

[0003] The technical problem to be solved by the present invention is to provide a silicon carbide VDMOS with high resistance to drain voltage shock and a preparation method, so as to improve the reliability of the device in resisting drain voltage shock, reduce the gate-source capacitance of the device, increase the switching speed of the device, reduce the switching loss of the device, and at the same time reduce the body diode conduction loss of the device and increase the reverse recovery speed of the device.

[0004] In a first aspect, the present invention provides a method for preparing a silicon carbide VDMOS with high tolerance to drain voltage shock, comprising the following steps:

[0005] Step 1, epitaxially growing a first drift region on a silicon carbide substrate with a drain metal layer;

[0006] Step 2, epitaxially growing a flow balancing layer on the first drift region;

[0007] Step 3, epitaxially growing a second drift region on the current balancing layer, wherein the drift layer includes the first drift region and the second drift region;

[0008] Step 4: forming a barrier layer on the drift layer, etching the barrier layer to form a through hole, and performing ion implantation on the drift layer to form a plurality of evenly spaced masking layers, wherein the ion implantation energy is 230-300 kev;

[0009] Step 5: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation on the drift layer to form a P-type well region. The ion implantation energy is 70-200kev;

[0010] Step 6: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, perform ion implantation on the P-type well region to form an N-type source region, and the ion implantation energy is 70-170kev;

[0011] Step 7: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation on the drift layer to form an N-type region. The ion implantation energy is 70-200kev.

[0012] Step 8: removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the drift layer, and then oxidizing to form an insulating dielectric layer;

[0013] Step 9, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer and the insulating dielectric layer, depositing metal, and forming a first gate metal region;

[0014] Step 10, depositing an insulating medium so that the insulating medium is at the same height as the upper side of the drift layer;

[0015] Step 11, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer and the insulating dielectric layer to the upper side of the first gate metal region, depositing metal to form a second gate metal region, the gate metal layer includes the first gate metal region and the second gate metal region, and the gate metal layer is an inverted T-shape;

[0016] Step 12: remove the original barrier layer, re-form the barrier layer, etch the barrier layer and the drift layer, deposit metal, and form a source metal layer; remove the barrier layer to complete the preparation.

[0017] In a second aspect, the present invention provides a silicon carbide VDMOS with high resistance to drain voltage shock, and the silicon carbide VDMOS is prepared by the method for preparing a silicon carbide VDMOS with high resistance to drain voltage shock described in the first aspect.

[0018] The advantages of the present invention are:

[0019] 1. A uniformly distributed P-type shielding area is constructed inside the device, which protects the corners of the device's trench gate from breakdown caused by electric field concentration without affecting the device's conductive properties;

[0020] Second, in addition to protecting the device's insulating dielectric layer, the P-type shielding layer can protect the device's gate and source through the space charge region formed near the P-type shielding layer when the drain is subjected to a high voltage shock;

[0021] 3. The gate metal layer of the device is an inverted T-shaped structure, which realizes a smaller gate-source capacitance, reduces the gate charge of the device, and improves the switching speed of the device; an N-type current equalization area is constructed under the P-type shielding layer of the device. In order to ensure the protection effect of the P-type shielding area against the drain voltage impact, the thickness of the N-type drift layer from the bottom of the P-type shielding layer to the top of the N-type current equalization layer is 100nm. The N-type current equalization layer can evenly distribute the current inside the device to avoid current concentration. At the same time, the N-type current equalization layer shields the capacitance effect from the gate metal to the drain, which can effectively suppress the gate-drain capacitance of the device, that is, the Maitreya capacitance, which can reduce the platform period of the device's opening and closing, and effectively improve the switching speed of the device;

[0022] Fourth, a Schottky body diode is constructed from the source metal layer to the N-type region inside the device, which can effectively reduce the body diode loss of the device, reduce the reverse recovery time of the device, and increase the switching speed of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The present invention will be further described below in conjunction with embodiments with reference to the accompanying drawings.

[0024] Figure 1 The schematic diagram of the silicon carbide VDMOS with high resistance to drain voltage shock of the present invention.

[0025] Figure 2 A cross-sectional view of the process of a silicon carbide VDMOS with high resistance to drain voltage shock of the present invention Figure 1 .

[0026] Figure 3 A cross-sectional view of the process of a silicon carbide VDMOS with high resistance to drain voltage shock of the present invention Figure 2 .

[0027] Figure 4 A cross-sectional view of the process of a silicon carbide VDMOS with high resistance to drain voltage shock of the present invention Figure 3 .

[0028] Figure 5 A cross-sectional view of the process of a silicon carbide VDMOS with high resistance to drain voltage shock of the present invention Figure 4 .

[0029] Figure 6 A cross-sectional view of the process of a silicon carbide VDMOS with high resistance to drain voltage shock of the present invention Figure 5 .

[0030] Figure 7 A cross-sectional view of the process of a silicon carbide VDMOS with high resistance to drain voltage shock of the present invention Figure 6 .

[0031] Figure 8 A cross-sectional view of the process of a silicon carbide VDMOS with high resistance to drain voltage shock of the present invention Figure 7 .

[0032] Fig. 9 A cross-sectional view of the process of a silicon carbide VDMOS with high resistance to drain voltage shock of the present invention Figure 8 .

[0033] Fig.10 A cross-sectional view of the process of a silicon carbide VDMOS with high resistance to drain voltage shock of the present invention Figure 9 .

[0034] Fig.11 A cross-sectional view of the process of a silicon carbide VDMOS with high resistance to drain voltage shock of the present invention Figure 10 .

[0035] Fig.12 A cross-sectional view of the process of a silicon carbide VDMOS with high resistance to drain voltage shock of the present invention Figure 10 one.

[0036] Fig.13 A cross-sectional view of the process of a silicon carbide VDMOS with high resistance to drain voltage shock of the present invention Figure 10 two.

[0037] Fig.14 A cross-sectional view of the process of a silicon carbide VDMOS with high resistance to drain voltage shock of the present invention Figure 10 three.

[0038] Fig.15 A cross-sectional view of the process of a silicon carbide VDMOS with high resistance to drain voltage shock of the present invention Figure 10 Four.

[0039] Fig.16 A cross-sectional view of the process of a silicon carbide VDMOS with high resistance to drain voltage shock of the present invention Figure 10 five. DETAILED DESCRIPTION

[0040] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0042] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "in contact with ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0043] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that, in addition to the orientations described in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0044] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0045] like Figures 1 to 16 As shown, the embodiment of the present application provides a method for preparing a silicon carbide VDMOS with high tolerance to drain voltage shock, comprising the following steps:

[0046] Step 1, epitaxially growing a first drift region 24 on a silicon carbide substrate 1 with a drain metal layer 8;

[0047] Step 2, epitaxially growing a current balancing layer 21 on the first drift region 24;

[0048] Step 3, epitaxially growing a second drift region 25 on the current balancing layer 21, wherein the drift layer 2 includes a first drift region 24 and a second drift region 25;

[0049] Step 4: forming a barrier layer 9 on the drift layer 2, etching the barrier layer 9 to form a through hole, and performing ion implantation on the drift layer 2 to form a plurality of evenly spaced masking layers 22, wherein the ion implantation energy is 230-300 kev;

[0050] Step 5, removing the original barrier layer 9, re-forming the barrier layer 9, etching the barrier layer 9 to form a through hole, and performing ion implantation on the drift layer 2 to form a P-type well region 4, wherein the ion implantation energy is 70-200kev;

[0051] Step 6, remove the original barrier layer 9, re-form the barrier layer 9, etch the barrier layer 9 to form a through hole, perform ion implantation on the P-type well region 4 to form an N-type source region 41, and the ion implantation energy is 70-170kev;

[0052] Step 7, removing the original barrier layer 9, re-forming the barrier layer 9, etching the barrier layer 9 to form a through hole, and performing ion implantation on the drift layer 2 to form an N-type region 3, wherein the ion implantation energy is 70-200 keV;

[0053] Step 8, removing the original barrier layer 9, re-forming the barrier layer 9, etching the barrier layer 9 to form a through hole, and etching the drift layer 2 to the upper side of the masking layer 22, and then oxidizing to form an insulating dielectric layer 5, and the two sides of the bottom of the insulating dielectric layer 5 are respectively connected to the upper side of the masking layer 22;

[0054] Step 9, removing the original barrier layer 9, re-forming the barrier layer 9, etching the barrier layer 9 and the insulating dielectric layer 5, depositing metal, and forming a first gate metal region 61;

[0055] Step 10, depositing an insulating medium so that the insulating medium is at the same height as the upper side of the drift layer 2;

[0056] Step 11, removing the original barrier layer 9, re-forming the barrier layer 9, etching the barrier layer 9 and the insulating dielectric layer 5 to the upper side of the first gate metal region 61, depositing metal to form the second gate metal region 62, the gate metal layer 6 includes the first gate metal region 61 and the second gate metal region 62, and the gate metal layer 6 is an inverted T-shape;

[0057] Step 12: remove the original barrier layer 9, re-form the barrier layer 9, etch the barrier layer 9 and the drift layer 2, deposit metal, and form a source metal layer 7; remove the barrier layer 9, and complete the preparation.

[0058] In this embodiment, preferably, the doping concentration of the masking layer 22 is higher than the doping concentration of the current equalizing layer 21, the doping concentration of the current equalizing layer 21 is higher than the doping concentration of the drift layer 2, the doping concentration of the N-type region 3 is lower than the doping concentration of the P-type well region 4, and the doping concentration of the P-type well region 4 is lower than the doping concentration of the N-type source region 41.

[0059] like Figure 1 As shown, the silicon carbide VDMOS obtained by the above manufacturing method includes:

[0060] Silicon carbide substrate 1,

[0061] A drift layer 2, wherein the lower side of the drift layer 2 is connected to the upper side of the silicon carbide substrate 1; a current balancing layer 21 and a plurality of shielding layers 22 are provided in the drift layer 2, wherein the shielding layer 22 is located above the current balancing layer 2, and the plurality of shielding layers 22 are evenly spaced;

[0062] An N-type region 3, wherein the lower side of the N-type region 3 is connected to the upper side of the drift layer 1;

[0063] A P-type well region 4, wherein the outer side of the P-type well region 4 is connected to the inner side of the N-type region 3, the lower side of the P-type well region 4 is connected to the upper side of the drift layer 1, and an N-type source region 41 is provided in the P-type well region 4;

[0064] An insulating dielectric layer 5, wherein the lower side of the insulating dielectric layer 5 is connected to the upper side of the drift layer 2, and the outer side of the insulating dielectric layer 5 is connected to the inner side of the P-type well region 4 and the inner side of the N-type source region 41; a groove 51 is provided in the insulating dielectric layer 5, and the groove 51 is an inverted T-shaped groove;

[0065] A gate metal layer 6, wherein the gate metal layer 6 is disposed in the groove 51 and is in an inverted T shape;

[0066] A source metal layer 7, wherein the source metal layer 7 is respectively connected to the N-type region 3, the P-type well region 4 and the N-type source region 41;

[0067] and a drain metal layer 8 , wherein the drain metal layer 8 is connected to the lower side of the silicon carbide substrate 1 .

[0068] A groove 23 is provided on the drift layer 2, the lower part of the insulating dielectric layer 5 is provided in the groove 23, and the two sides of the bottom of the insulating dielectric layer 5 are respectively connected to the upper side of the masking layer 22, the lower side of the gate metal layer 6 is lower than the lower side of the P-type well region 4, the thickness of the N-type region 3 is equal to the thickness of the P-type well region 4, and the spacing between adjacent masking layers 22 is 300-500nm.

[0069] Another embodiment of the present invention:

[0070] The silicon carbide substrate 1, the drift layer 2, and the current balancing layer 21 are all N-type; the masking layer 22 is P-type; the doping concentration of the N-type silicon carbide substrate 1 is 2e18cm -3 , the doping concentration of the N-type drift layer 2 is 1e16cm -3 The doping concentration of the N-type current balancing layer 21 is 1e17cm -3 , the doping concentration of the P-type masking layer 22 is 5e17 cm -3 , the doping concentration of P-type well region 4 is 5e17 cm -3 , the doping concentration of the N-type source region 41 is 2e18cm -3 , the doping concentration of N-type region 3 is 1e17cm -3 The material of the insulating dielectric layer 5 may be one or a combination of silicon dioxide, aluminum nitride, and hafnium dioxide;

[0071] The doping concentration of the silicon carbide substrate 1 is to ensure that a low-resistance ohmic contact is formed with the drain metal layer 8, thereby reducing the overall on-resistance of the device; the doping concentration of the N-type drift layer 2 is a compromise between the reverse withstand voltage and on-resistance of the device; the doping concentration of the N-type region 3 is to reduce the on-resistance of the device while forming a Schottky metal rather than an ohmic contact with the source metal layer 7, thereby forming a Schottky body diode inside the device; the P-type well region 4 is to control the turn-off characteristics of the device while not affecting the gate control capability of the device; the doping concentration of the P-type masking layer 22 is to ensure the tolerance to drain voltage shocks while controlling the impact on the on-resistance of the device; the N-type current equalizing layer 21 is to achieve current equalization inside the device.

[0072] The thickness of the silicon carbide substrate 1 of the device is 1 μm, which is to ensure the support of the subsequent structure preparation of the device. The thickness of the N-type drift layer 2 (referring to the distance from the top of the silicon carbide substrate 1 to the top of the P-type shielding layer 22) is 15-25 μm, which can be adjusted within the above range according to different requirements for the withstand voltage characteristics of the device; the thickness of the P-type shielding layer 22 is 200 nm, which protects the corners of the device trench gate from being concentrated by the electric field and causing breakdown without affecting the conductive characteristics of the device. When the drain is subjected to a high voltage shock, the P-type shielding layer 22 can protect the gate and source of the device through the space charge region formed near the P-type shielding layer 22. The distance from the bottom of the P-type shielding layer 22 to the top of the N-type current balancing layer 21 is 100 nm. The N-type current balancing layer 21 can evenly distribute the current inside the device to avoid current concentration. At the same time, the N-type current balancing layer 21 shields the capacitance effect from the gate to the drain, which can effectively suppress the gate-drain capacitance of the device, that is, the Maitreya capacitance, and can reduce the platform period of the device on and off, effectively improving the switching speed of the device;

[0073] The width of the P-type shielding layer 22 is 200nm, and the spacing between two adjacent shielding layers 22 is 300-500nm. This is to protect the gate and source of the device in the space charge region formed near the P-type shielding layer 22. The width relationship is designed based on the doping concentration of the P-type shielding layer 22 and the N-type drift layer 2.

[0074] The gate metal layer 6 of the device is an inverted T-shaped structure, the thickness of the insulating medium at the bottom of the gate metal layer 6 is 50nm, the thickness of the insulating medium on the side of the gate metal layer 6 is 30nm and 100-200nm respectively, the insulating medium between the gate metal layer 6 and the source metal layer 7 and the N-type source region 41 is wider and the capacitance is smaller, thereby achieving a smaller gate-source capacitance, reducing the gate charge of the device, and improving the switching speed of the device; the thickness of the source metal layer is 200nm, the thickness of the N-type source region 41 is 300nm, the thickness of the P-type well region 4 is 400nm, and the depth of the groove of the drift layer 2 is 100nm; a Schottky body diode is constructed from the source metal layer 7 to the N-type region 3 inside the device, which can effectively reduce the body diode loss of the device, reduce the reverse recovery time of the device, and improve the switching speed of the device.

[0075] Although the specific implementation modes of the present invention are described above, those skilled in the art should understand that the specific implementation modes described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A method for preparing a silicon carbide VDMOS with high tolerance to drain voltage shock, characterized in that: The steps include: Step 1, epitaxially growing a first drift region on a silicon carbide substrate with a drain metal layer; Step 2, epitaxially growing a flow balancing layer on the first drift region; Step 3, epitaxially growing a second drift region on the current balancing layer, wherein the drift layer includes the first drift region and the second drift region; Step 4: forming a barrier layer on the drift layer, etching the barrier layer to form a through hole, and performing ion implantation on the drift layer to form a plurality of evenly spaced masking layers, wherein the ion implantation energy is 230-300 kev; Step 5: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation on the drift layer to form a P-type well region. The ion implantation energy is 70-200kev; Step 6: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, perform ion implantation on the P-type well region to form an N-type source region, and the ion implantation energy is 70-170kev; Step 7: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation on the drift layer to form an N-type region. The ion implantation energy is 70-200kev. Step 8: removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, etching the drift layer, and then oxidizing to form an insulating dielectric layer; Step 9, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer and the insulating dielectric layer, depositing metal, and forming a first gate metal region; Step 10, depositing an insulating medium so that the insulating medium is at the same height as the upper side of the drift layer; Step 11, removing the original barrier layer, re-forming the barrier layer, etching the barrier layer and the insulating dielectric layer to the upper side of the first gate metal region, depositing metal to form a second gate metal region, the gate metal layer includes the first gate metal region and the second gate metal region, and the gate metal layer is an inverted T-shape; Step 12: removing the original barrier layer, re-forming the barrier layer, etching the barrier layer and the drift layer, depositing metal, and forming a source metal layer; The barrier layer is removed to complete the preparation.

2. The method for preparing a silicon carbide VDMOS with high drain voltage shock resistance according to claim 1, characterized in that: The step 8 is specifically as follows: removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and etching the drift layer to the upper side of the masking layer, and then oxidizing to form an insulating dielectric layer, wherein both sides of the bottom of the insulating dielectric layer are respectively connected to the upper side of the masking layer.

3. The method for preparing a silicon carbide VDMOS with high drain voltage shock resistance according to claim 1, characterized in that: The lower side of the gate metal layer is lower than the lower side of the P-type well region.

4. The method for preparing a silicon carbide VDMOS with high drain voltage shock resistance according to claim 1, characterized in that: The thickness of the N-type region is equal to the thickness of the P-type well region.

5. The method for preparing a silicon carbide VDMOS with high drain voltage shock resistance according to claim 1, characterized in that: The distance between adjacent masking layers is 300-500 nm.

6. The method for preparing a silicon carbide VDMOS with high drain voltage shock resistance according to claim 1, characterized in that: The doping concentration of the masking layer is higher than the doping concentration of the current balancing layer, and the doping concentration of the current balancing layer is higher than the doping concentration of the drift layer.

7. The method for preparing a silicon carbide VDMOS with high drain voltage shock resistance according to claim 1, characterized in that: The doping concentration of the N-type region is less than the doping concentration of the P-type well region, and the doping concentration of the P-type well region is less than the doping concentration of the N-type source region.

8. A silicon carbide VDMOS with high tolerance to drain voltage shock, characterized in that: The silicon carbide VDMOS is prepared by any one of the preparation methods of claim 1 to claim 7.

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