Novel asymmetric trench SiC MOSFET device with low resistance and Miller capacitance

Abstract

The invention relates to a novel asymmetric groove SiC MOSFET device with low resistance and Miller capacitance, and belongs to the technical field of semiconductor devices. The device comprises a substrate; the drift region is formed on one surface of the substrate; the N-CSL is formed on the surface of the drift region; the low-barrier diode is formed on one side of the surface of the N-CSL; the second P-well is formed on the other side of the surface of the N-CSL; the trench gate and the auxiliary trench gate are formed on the surface of the low-barrier diode and located on the two sides of the low-barrier diode; the P-base is formed on the surface of the N-CSL and is positioned between the second P-well and the trench gate; the source N + region is formed on the surface of the P-base and is positioned between the second P-well and the trench gate; a source electrode formed on the top of the device; and the drain electrode is formed on the other surface of the substrate. The specific on-resistance of the device can be reduced, the Miller capacitance and the gate charge of the device are reduced, and the switching speed of the device is improved.

Description

Technical Field

[0001] The present invention belongs to the technical field of semiconductor devices and relates to a novel asymmetric trench SiC MOSFET device with low resistance and Miller capacitance. Background Art

[0002] Power semiconductor devices play the role of switches, drivers and rectifiers. Power SiC MOSFET has excellent characteristics such as high switching conversion frequency, large input impedance and good thermal stability. Energy-saving and advanced power SiC MOSFET has gradually become an important cornerstone of my country's information industry and efficiency economy. Power SiC MOSFET is widely used in daily life and various industries. Where there are modern electronic chips, there are power SiC MOSFET. It is an important part of electronic chips to process information safely, efficiently and accurately. With the continuous optimization of technology and process in the semiconductor industry, not only the static characteristics of power devices are required to be excellent, but also their dynamic characteristics are required to be better, so there are higher requirements for switching speed and switching loss.

[0003] In recent years, with the continuous improvement of SiC MOSFET electrical characteristics, process manufacturing technology and reliability, compared with Si bipolar power devices, the unipolar conduction characteristics of SiC MOSFET make it have better switching characteristics and lower switching losses, which makes SiC MOSFET expected to replace Si IGBT in high-frequency applications. As a field effect transistor commonly used in electronic devices, the on-resistance of SiC MOS tube is crucial to circuit performance. The on-resistance determines the conduction loss, but reducing the specific on-resistance will lead to a decrease in the breakdown voltage of the device; while increasing the breakdown voltage of the device will increase the specific on-resistance of the device. Summary of the invention

[0004] In view of this, an object of the present invention is to provide an asymmetric trench SiCMOSFET device with low resistance and Miller capacitance, so as to reduce the specific on-resistance of the device, reduce the feedback capacitance and gate charge of the device, and improve the switching speed of the device.

[0005] In order to achieve the above object, the present invention provides the following technical solutions:

[0006] A novel asymmetric trench SiC MOSFET device with low resistance and Miller capacitance, the device comprising:

[0007] N+ substrate;

[0008] N-Drift formed on the first surface of the N+ substrate;

[0009] N-CSL formed on the surface of N-Drift;

[0010] A P-type low-barrier diode formed on one side of the N-CSL surface;

[0011] a second P-well formed on the other side of the N-CSL surface;

[0012] A trench gate and an auxiliary trench gate formed on the surface of the low barrier diode and located on both sides of the low barrier diode;

[0013] A P-base formed on the surface of the N-CSL and located between the second P-well and the trench gate;

[0014] A source N+ region formed on the surface of the P-base and located between the second P-well and the trench gate;

[0015] a source electrode formed on top of the device; and

[0016] A drain electrode is formed on the second surface of the N+ substrate.

[0017] Furthermore, the low barrier diode includes: a first P-well formed on one side of the N-CSL surface, a P-Channel formed on the surface of the first P-well and located between the trench gate and the auxiliary trench gate, and a source P+ region formed on the surface of the P-Channel and located between the trench gate and the auxiliary trench gate.

[0018] The trench gate disconnects the source P+ region from the first P-well by pinching off the P-channel depletion, so that the first P-well is in a floating state, increasing the potential of the first P-well, thereby reducing the on-resistance of the device.

[0019] Furthermore, the trench gate and the auxiliary trench gate are surrounded by the first oxide layer and the second oxide layer respectively. By increasing the thickness of the first oxide layer and the second oxide layer on the side adjacent to the P-Channel, the gate-source capacitance C introduced by the auxiliary trench gate can be reduced. gs .

[0020] Furthermore, by reducing the width of the N-CSL to reduce the coupling area between the gate and the drain of the device, the gate-drain capacitance of the device, ie, the Miller capacitance, can be reduced, and the gate charge of the device can also be reduced.

[0021] The beneficial effect of the present invention is that the present invention proposes an asymmetric trench SiC MOSFET device with low resistance and Miller capacitance, and integrates a P-type low barrier diode on the basis of a traditional asymmetric trench SiC MOSFET device. Based on the integrated P-type low barrier diode, when the device is forward-conducted, the drain is connected to a positive voltage, and the gate is connected to a 15V positive voltage, the P-channel will be depleted and pinched off, disconnecting the connection between the P+ source region and the P-well, making the P-well float, increasing the P-well potential, and thus reducing the device's specific on-resistance. In addition, by reducing the JFET width (i.e., the width of the N-CSL) between the first P-well and the second P-well, thereby reducing the coupling area between the gate and the drain, the Miller capacitance and gate charge of the device can be reduced, and the switching speed of the device can be increased.

[0022] Other advantages, objectives and features of the present invention will be described in the following description to some extent, and to some extent, will be obvious to those skilled in the art based on the following examination and study, or can be taught from the practice of the present invention. The objectives and other advantages of the present invention can be realized and obtained through the following description. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] In order to make the purpose, technical solutions and advantages of the present invention more clear, the present invention will be described in detail below in conjunction with the accompanying drawings, wherein:

[0024] Figure 1 The overall structure of a SiC MOSFET device provided by an embodiment of the present invention;

[0025] Figure 2 A comparison diagram of the output characteristic curves of the SiC MOSFET of the present invention and the conventional asymmetric trench SiC MOSFET when the gate voltage is 15V and the first quadrant working mechanism diagram of the SiC MOSFET of the present invention;

[0026] Figure 3 The total current density distribution diagram of C-ATMOS and LR-ATMOS during forward conduction;

[0027] Figure 4 The comparison diagram of the breakdown characteristic curves of the two devices;

[0028] Figure 5 The breakdown electric field distribution of two SiC MOSFETs;

[0029] Figure 6 The effect of NCSL on the breakdown voltage (BV) and specific on-resistance (Ron,sp) of two SiC MOSFETs;

[0030] Figure 7 The influence of different CSL widths on the breakdown voltage, on-resistance and Qgd of LR-ATMOS;

[0031] Figure 8 A capacitance comparison curve diagram of the SiC MOSFET of the present invention and the conventional asymmetric trench SiC MOSFET;

[0032] Fig. 9 A comparison diagram of gate charge characteristics of the SiC MOSFET of the present invention and the conventional asymmetric trench SiC MOSFET;

[0033] Fig.10 : are the switching characteristic curves of the SiC MOSFET of the present invention and the conventional asymmetric trench SiC MOSFET;

[0034] Fig.11 A comparison diagram of switching losses between the SiC MOSFET of the present invention and the conventional asymmetric trench SiC MOSFET;

[0035] Fig.12 Schematic diagram of the main process flow of the SiC MOSFET device of the present invention.

[0036] Figure numerals: 1-gate, 2-source, 3-drain, 4-trench gate, 5-auxiliary trench gate, 6-first oxide layer, 7-second oxide layer, 8-source N+ region, 9-source P+ region, 10-P-base, 11-P-channel, 12-first P-well, 13-second P-well, 14-N-CSL, 15-N-Drift, 16-N+SUB. DETAILED DESCRIPTION

[0037] The following describes the embodiments of the present invention by specific examples, and those skilled in the art can easily understand other advantages and effects of the present invention from the contents disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments, and the details in this specification can also be modified or changed in various ways based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that the illustrations provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner, and the following embodiments and features in the embodiments can be combined with each other without conflict.

[0038] Among them, the drawings are only used for illustrative explanations, and they only represent schematic diagrams rather than actual pictures, and should not be understood as limitations on the present invention. In order to better illustrate the embodiments of the present invention, some parts of the drawings may be omitted, enlarged or reduced, and do not represent the size of actual products. For those skilled in the art, it is understandable that some well-known structures and their descriptions in the drawings may be omitted.

[0039] The same or similar numbers in the drawings of the embodiments of the present invention correspond to the same or similar parts; in the description of the present invention, it should be understood that if the terms "upper", "lower", "left", "right", "front", "rear", etc. indicate the orientation or position relationship, they are based on the orientation or position relationship shown in the drawings, which is only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operate in a specific orientation. Therefore, the terms describing the position relationship in the drawings are only used for illustrative purposes and cannot be understood as limiting the present invention. For ordinary technicians in this field, the specific meanings of the above terms can be understood according to specific circumstances.

[0040] like Figure 1 As shown, an asymmetric trench SiC MOSFET device with low resistance and Miller capacitance provided by an embodiment of the present invention is composed of a gate 1, a source 2, a drain 3, a trench gate 4, an auxiliary trench gate 5, a first oxide layer 6, a second oxide layer 7, a source N+ region 8, a source P+ region 9, a P-base 10, a P-channel 11, a first P-well 12, a second P-well 13, an N-CSL 14, an N-Drift 15, and an N+SUB 16.

[0041] The trench gate 4, the auxiliary trench gate 5, the source P+ region 9, the P-channel 11 and the first P-well 12 form a P-type low barrier diode.

[0042] The source P+ region 9 is located on the upper surface of the P-channel 11 and is connected to the source 2. It has a thickness of 0.25 μm and a width of 0.2 μm. It is doped with P-type impurity aluminum (AL) with a doping concentration of 1×10 20 cm -3 The first P-well 12 is located on the lower surface of the P-channel 11, has a thickness of 0.95 μm, a width of 1.3 μm, and is doped with P-type impurity aluminum (AL) at a doping concentration of 2.5×10 17 cm -3 ; The source P+ region 9, the P-channel 11 and the first P-well 12 are arranged vertically to form a P-type low barrier diode, and the P-channel 11 has a thickness of 0.5 μm and a width of 0.2 μm; the trench gate 4 and the auxiliary trench gate 5 are respectively located on both sides of the source P+ region 9, the P-channel 11 and the first P-well 12, and the lower surfaces of the trench gate 4 and the auxiliary trench gate 5 are adjacent to the first P-well 12, and the thickness is 1.0 μm, and the width is 0.85 μm and 0.55 μm respectively. PolySi is doped with N-type impurity phosphorus (P), and the doping concentration is 4×10 16 cm -3.

[0043] The gate 1 is connected to the trench gate 4 and the auxiliary trench gate 5, and the trench gate 4 and the auxiliary trench gate 5 are respectively located inside the first oxide layer 6 and the second oxide layer 7. The thickness of the right side of the first oxide layer 6, that is, the side adjacent to the P-Channel, is 80nm; the thickness of the left side of the second oxide layer 7, that is, the side adjacent to the P-Channel, is also 80nm. The thickness of the remaining sides of the first oxide layer and the second oxide layer is 50nm.

[0044] The source 2 is connected to the source N+ region 8, the source P+ region 9 and the second P-well 13, and is located on the upper surface of the source N+ region 8, the source P+ region 9 and the second P-well 13. The source N+ region 8 has a thickness of 0.25 μm and a width of 0.8 μm. It is doped with N-type impurity nitrogen (Ni) with a doping concentration of 1×10 20 cm -3 The second P-well 13 has a thickness of 1.7 μm and a width of 0.8 μm, and is doped with P-type impurity aluminum (AL) at a doping concentration of 1×10 19 cm -3 .

[0045] The drain 3 is connected to N+SUB16 and is located on the lower surface of N+SUB16. N+SUB16 has a thickness of 5 μm and a width of 3.2 μm. It is doped with N-type impurity nitrogen (Ni) with a doping concentration of 1×10 20 cm -3 ;

[0046] In addition, in the device, there are source N+ region 8, P-base 10, second P-well 13, N-CSL 14, N-Drift 15, and N+SUB 16. Among them, the source N+ region 8 is located on the upper surface of P-base 10, and the left surface of the source N+ region 8 and P-base 10 is adjacent to the right surface of the second P-well 13, and the right surface is adjacent to the left surface of the first oxide layer 6. The source N+ region 8 has a thickness of 0.25 μm and a width of 0.8 μm, and is doped with N-type impurity nitrogen (Ni) with a doping concentration of 1×10 20 cm -3 N-CSL14 is located between the first and second P-well on both sides, and its lower surface is adjacent to the upper surface of N-Drift15. N-CSL14 has a thickness of 1.7μm and a width of 3.2μm. It is doped with N-type impurity nitrogen (Ni) with a doping concentration of 2.5×10 16 cm -3The upper surface of N-Drift15 is located on the lower surface of N-CSL14, and the lower surface of N-Drift15 is located on the upper surface of N+SUB16. N-Drift15 has a thickness of 1.7 μm and a width of 3.2 μm. It is doped with N-type impurity nitrogen (Ni) with a doping concentration of 7×10 15 cm -3 .

[0047] In another embodiment of the present invention, a simulation test is performed on the proposed SiC MOSFET device to verify the excellent performance of the device proposed in the present invention, as follows:

[0048] like Figure 2 As shown, when the gate voltage is 15V and the forward conduction is performed, the output characteristic curve of the SiC MOSFET device of the present invention is compared with the traditional asymmetric trench SiC MOSFET device, as well as the first quadrant working mechanism of the SiC MOSFET device of the present invention. It can be seen that the device of the present invention has better output characteristics than the traditional asymmetric trench SiC MOSFET device.

[0049] like Figure 3 As shown, the total current density distribution of the C-ATMOS and the device of the present invention during the forward conduction process. Figure 3 It can be seen that compared with the traditional asymmetric trench SiC MOSFET device, the device of the present invention still has a larger conduction path even when the WCSL is small. In the J-FET area, the current width of the device of the present invention is 0.64μm, and the current width of the traditional asymmetric trench SiC MOSFET is 0.68μm. This difference is attributed to the integration of the P-type low-barrier diode. When the gate is connected to a positive voltage of 15V, the P-channel is depleted, and the source P+ region connected to the source is disconnected from the second P-well, so that the second P-well is floating and its potential is increased. As a result, the depletion region width is reduced, the JFET resistance is reduced, and the current flowing to the N-Drift is increased. Therefore, compared with the traditional asymmetric trench SiC MOSFET, the device of the present invention has a lower specific on-resistance.

[0050] like Figure 4 As shown in FIG. 1 , a comparison diagram of the breakdown characteristic curves of the two devices is shown. The two devices exhibit similar BV characteristics. Figure 4 The hole density distribution of the device of the present invention under blocking conditions is also shown. Under blocking conditions, the gate is connected to 0V and the lightly doped P-channel cannot be depleted. Therefore, the source P+ region is normally connected to the second P-well, so that the second P-well is grounded, which can deplete the drift region well and show good BV characteristics.

[0051] like Figure 5As shown, the breakdown electric field distribution of two SiC MOSFETs. The maximum breakdown electric field of both devices is at P-well, and the gate oxide electric field of SiC MOSFET is less than 3MV / cm, which is conducive to enhancing the long-term reliability of the gate oxide. Since the N-CSL of the device of the present invention is smaller than that of the traditional asymmetric trench SiC MOSFET, the peak electric field near the bottom of the trench of the device of the present invention is smaller than that of the traditional asymmetric trench SiC MOSFET, and the device reliability is better.

[0052] like Figure 6 The concentration of N-CSL (N CSL ) on the breakdown voltage (BV) and specific on-resistance (Ron,sp) of two SiC MOSFETs. Figure 6 It can be seen that with the increase of N-CSL concentration, the on-resistance tends to decrease and the BV tends to decrease.

[0053] like Figure 7 As shown, different N-CSL widths (W CSL ) on the breakdown voltage, on-resistance and Qgd of LR-ATMOS. Figure 7 It can be seen that with the increase of W CSL With the increase of , the BV and on-resistance of the device both show a downward trend, and Qgd shows an upward trend.

[0054] like Figure 8 The figure shows the capacitance comparison curve of the SiC MOSFET device of the present invention and the conventional asymmetric trench SiC MOSFET. It can be seen that the input capacitance (Ciss) and output capacitance (Coss) of the SiC MOSFET device proposed by the present invention are slightly lower than those of the conventional asymmetric trench SiC MOSFET device. And the feedback capacitance (Crss or C gd ) is significantly smaller than the conventional asymmetric trench SiC MOSFET device. The C extracted by the device of the present invention and the conventional asymmetric trench SiC MOSFET device at Vds = 400V gd 10.98 and 24.45 pF / cm respectively 2 This is because the narrower W CSL Reduces the capacitive coupling between the gate and the source-drain, resulting in C gd Therefore, the HF-FOM value (Ron,sp×C gd ) is 58.3% lower than that of traditional asymmetric trench SiC MOSFET devices.

[0055] like Fig. 9As shown, the gate charge characteristics of the SiC MOSFET device of the present invention and the traditional asymmetric trench SiC MOSFET device are compared. In addition, Fig. 9 A test circuit is also inserted. Fig. 9 It can be seen from the figure that the gate charge (Q gd ) and the total gate charge (V gs = Qg at 0~15V) is 67.7nC / cm 2 and 920nC / cm 2 , lower than the 90.3nC / cm of traditional asymmetric trench SiC MOSFET devices 2 and 970nC / cm 2 . Fig. 9 It can be seen that after the plateau period, the gate charge of the SiC MOSFET device of the present invention is also significantly lower than that of the traditional asymmetric trench SiC MOSFET device. This is because the gate current in this stage is mainly C gs At this time, the SiC MOSFET device of the present invention causes the P-channel connecting the P-well to the source to be cut off, so that the P-well is in a floating state, and the C generated by it gs Also decreased.

[0056] like Fig.10 , which are the switching characteristic curves of the SiC MOSFET device of the present invention and the traditional asymmetric trench SiC MOSFET device. Fig.10 A test circuit is also inserted in. It can be seen that since the SiC MOSFET of the present invention has a lower gate charge, the SiC MOSFET proposed by the present invention has better switching characteristics and can reduce switching losses.

[0057] like Fig.11 As shown in FIG. 11 , the switching loss of the SiC MOSFET device of the present invention is compared with that of the conventional asymmetric trench SiC MOSFET device. As can be seen from FIG. 11 , the switching loss of the device of the present invention is reduced by 15% (from 2.40 mJ / cm 2 Reduced to 2.04mJ / cm 2 ).

[0058] The comparison of relevant parameters of the device of the present invention and the traditional asymmetric trench SiC MOSFET device can be seen in the following table.

[0059] Table 1

[0060] Proposed C-ATMOS (traditional device) Ron,sp <![CDATA[1.58mΩ·cm 2 ]]> <![CDATA[1.70mΩ·cm 2 ]]> <![CDATA[Q gd ]]> <![CDATA[67.7nC / cm 2 ]]> <![CDATA[90.3nC / cm 2 ]]> BV 1255V 1265V <![CDATA[E on ]]> <![CDATA[1.31mJ / cm 2 ]]> <![CDATA[1.26mJ / cm 2 ]]> <![CDATA[E off ]]> <![CDATA[0.73mJ / cm 2 ]]> <![CDATA[1.15mJ / cm 2 ]]> <![CDATA[Ron,sp×C gd ]]> 17.35mΩ·pF 41.57mΩ·pF <![CDATA[Ron,sp×Q gd ]]> 106.97mΩ·nC 153.51mΩ·nC

[0061] In another embodiment of the present invention, a process flow of the device of the present invention is provided. Considering the feasibility of the process, most of the process steps are compatible with the general manufacturing process of the conventional asymmetric trench SiC MOSFET device. Fig.12 As shown, the main process flow of the device proposed in the present invention includes: epitaxial growth, N+ source and P well implantation, trench etching, P base implantation, isolation oxidation, gate oxidation, polysilicon gate deposition and metallization. The difference is that in the process flow of this embodiment, the gate trench needs to be deposited with polysilicon gates, trenched and oxidized multiple times.

[0062] Finally, it should be noted that the above embodiments are only used to illustrate the technical solution of the present invention rather than to limit it. Although the present invention has been described in detail with reference to the preferred embodiments, those skilled in the art should understand that the technical solution of the present invention can be modified or replaced by equivalents without departing from the purpose and scope of the technical solution, which should be included in the scope of the claims of the present invention.

Claims

1. A novel asymmetric trench SiC MOSFET device with low resistance and Miller capacitance, characterized in that: The device includes: N+ substrate; N-Drift formed on the first surface of the N+ substrate; N-CSL formed on the surface of the N-Drift; a P-type low barrier diode formed on one side of the surface of the N-CSL; a second P-well formed on the other side of the N-CSL surface; A trench gate and an auxiliary trench gate formed on the surface of the P-type low barrier diode and located on both sides of the P-type low barrier diode; A P-base formed on the surface of the N-CSL and located between the second P-well and the trench gate; A source N+ region formed on the surface of the P-base and located between the second P-well and the trench gate; a source electrode formed on top of the device; and A drain electrode is formed on the second surface of the N+ substrate.

2. The SiC MOSFET device according to claim 1, characterized in that: The low barrier diode comprises: A first P-well formed on one side of the N-CSL surface; A P-Channel formed on the surface of the first P-well and located between the trench gate and the auxiliary trench gate; and A source P+ region is formed on the surface of the P-Channel and is located between the trench gate and the auxiliary trench gate.

3. The SiC MOSFET device according to claim 1 or 2, characterized in that: The trench gate and the auxiliary trench gate are surrounded by a first oxide layer and a second oxide layer respectively.

4. The SiC MOSFET device according to claim 3, characterized in that: The gate-source capacitance C introduced by the auxiliary trench gate is reduced by increasing the thickness of the first oxide layer and the second oxide layer on one side adjacent to the P-Channel. gs .

5. The SiC MOSFET device according to claim 1, characterized in that: By reducing the width of the N-CSL to reduce the coupling area between the gate and the drain of the device, the gate-drain capacitance of the device, namely the Miller capacitance, is reduced.

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