Separated gate IGBT structure

Abstract

The invention discloses a split gate IGBT (Insulated Gate Bipolar Translator) structure, and belongs to the field of semiconductor devices. Comprising collector metal, a P-type collector region, an N-type field stop layer and an N-type drift region which are sequentially arranged from bottom to top, an N-type storage layer, a P-type body region and emitter metal are sequentially arranged above the N-type drift region, an N + contact region is arranged in the P-type body region, a first oxide layer medium is arranged in the middle of the bottom of the emitter metal, a cross-shaped groove is formed in the N-type drift region, and a second oxide layer medium is arranged in the cross-shaped groove. The cross-shaped groove divides the N-type drift region, the N-type storage layer, the P-type body region and the N + contact region into a left part and a right part. The top of the cross-shaped groove is provided with a gate oxide layer, the bottom of the cross-shaped groove is provided with a second oxide layer medium, the top of the cross-shaped groove is provided with gate polycrystalline silicon which divides the gate oxide layer into a left part and a right part, and the left wide part and the right wide part of the cross-shaped groove are both internally provided with separation gate polycrystalline silicon. According to the split gate IGBT structure provided by the invention, the Miller capacitance and the conduction voltage drop can be effectively reduced.

Description

Technical Field

[0001] The invention relates to a semiconductor device, in particular to a separated gate IGBT structure. Background Art

[0002] Insulated gate bipolar transistor (IGBT) is a new type of power electronic device that combines MOS field effect and bipolar transistor. It not only has the advantages of MOSFET, large input resistance, easy to drive and simple control, but also has the advantages of bipolar transistor, such as low on-state voltage drop and large on-state current. It has become one of the core components in modern power electronic circuits and is widely used in transportation, energy, industry, household appliances and other fields.

[0003] Since the IGBT was introduced in the early 1980s, after more than 30 years of development, the process manufacturing level of the structure of IGBT devices has been continuously improved, and it has now developed to the seventh generation of charge storage insulated gate bipolar transistors (CSTBT). The seventh generation CSTBT introduces an N-type charge storage layer with a higher doping concentration under the surface P-type base region, and introduces a hole barrier under the P-type base region, so that the hole concentration near the emitter end when the device is forward-conducted is greatly increased, thereby enabling the IGBT to obtain a lower forward conduction voltage drop. However, with the continuous increase in the doping concentration of the N-type charge storage layer, the breakdown voltage of the CSTBT device has dropped significantly. In addition, as the cell width becomes smaller and the trench density becomes higher, the gate capacitance also increases. The increase in gate capacitance causes the switching speed of the device to slow down, thereby increasing the switching loss of the device. Summary of the invention

[0004] Purpose of the invention: The purpose of the present invention is to provide a split-gate IGBT structure with effectively reduced Miller capacitance and on-state voltage drop.

[0005] Technical solution: The split-gate IGBT structure described in the present invention includes a collector metal, a P-type collector region, an N-type field stop layer, and an N-type drift region arranged in sequence from bottom to top, an N-type storage layer, a P-type body region, and an emitter metal are arranged in sequence above the N-type drift region, an N+ contact region is arranged in the P-type body region, a first oxide layer medium is arranged in the middle of the bottom of the emitter metal, and split-gate polysilicon is arranged in the left and right wide parts of the cross-shaped groove.

[0006] Preferably, a gate oxide layer is provided on the top of the cross-shaped trench, a second oxide layer dielectric is provided on the bottom, and a gate polysilicon is provided on the top of the cross-shaped trench to divide the gate oxide layer into left and right parts.

[0007] Preferably, the cross-shaped groove has a bilaterally symmetrical structure, and its top is flush with the bottom of the emitter metal.

[0008] Preferably, the bottom end of the N-type storage layer is not lower than the bottom end of the separation gate polysilicon.

[0009] Preferably, the lowest point of the gate polysilicon is not higher than the upper end of the wide portion of the cross-shaped groove.

[0010] Preferably, the potential of the split gate polysilicon is equal to that of the emitter metal.

[0011] Preferably, a cross-shaped groove is provided in the N-type drift region, and the cross-shaped groove divides the N-type drift region, the N-type storage layer, the P-type body region and the N+ contact region into two left and right parts.

[0012] Preferably, the lowest point of the gate polysilicon is located between the lowest point and the highest point of the separation gate polysilicon.

[0013] Preferably, the lowest point of the gate polysilicon is lower than the lowest point of the separated gate polysilicon.

[0014] Preferably, the lowest point of the gate polysilicon is flush with the highest point of the wide portion of the cross-shaped trench.

[0015] Preferably, the first oxide layer medium and the second oxide layer medium are both silicon dioxide.

[0016] Beneficial effects: Compared with the prior art, the present invention has the following significant advantages: (1) In the reverse blocking state of the device, the wide part of the cross-shaped groove can effectively assist in depleting the N-type carrier storage layer. Therefore, under the same breakdown voltage, the structure has a higher concentration of N-type carrier storage layer, thereby having a lower on-state voltage drop; (2) In a split-gate IGBT structure disclosed in this scheme, since the potential of the split-gate polysilicon on the left and right sides of the cross-shaped groove is the same as that of the emitter, during the device switching process, the change of the gate signal is shielded by the split-gate polysilicon, thereby having a lower Miller capacitance, a faster switching speed, and a lower switching loss. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 is a schematic diagram of a cell structure of a split-gate IGBT structure provided in Example 1;

[0018] Figure 2 is a schematic diagram of a cell structure of a split-gate IGBT structure provided in Example 2;

[0019] Figure 3 This is a schematic diagram of a cell structure of a split-gate IGBT structure provided in Example 3. DETAILED DESCRIPTION

[0020] The technical solution of the present invention is further described below in conjunction with embodiments.

[0021] Example 1

[0022] like Figure 1 As shown, the split-gate IGBT structure described in the present invention includes a collector metal 1, a P-type collector region 2, an N-type field stop layer 3, and an N-type drift region 4 arranged in sequence from bottom to top, an N-type storage layer 5, a P-type body region 6, and an emitter metal 9 are arranged in sequence above the N-type drift region 4, an N+ contact region 7 is arranged in the P-type body region 6, and a first oxide layer medium 8 is arranged in the middle of the bottom of the emitter metal 9.

[0023] A cross-shaped groove is provided in the N-type drift region 4, and the cross-shaped groove divides the N-type drift region 4, the N-type storage layer 5, the P-type body region 6 and the N+ contact region 7 into two parts, a gate oxide layer 12 is provided at the top of the cross-shaped groove, and a second oxide layer medium 10 is provided at the bottom. A gate polysilicon 13 is provided at the top of the cross-shaped groove to divide the gate oxide layer 12 into two parts, and a separation gate polysilicon 11 is provided in the left and right wide parts of the cross-shaped groove.

[0024] The lowest point of the gate polysilicon 13 is located between the lowest point and the highest point of the split gate polysilicon 11 .

[0025] The cross-shaped groove is bilaterally symmetrical, and its top is flush with the bottom of the emitter metal 9 .

[0026] The potential of the separate gate polysilicon 11 is equal to the potential of the emitter metal 9 .

[0027] The bottom end of the N-type storage layer 5 is not lower than the bottom end of the separation gate polysilicon 11 .

[0028] Example 2

[0029] like Figure 2 As shown, the same points as those in the first embodiment are not described in detail. The difference lies in that the lowest point of the gate polysilicon 13 is lower than the lowest point of the separation gate polysilicon 11 .

[0030] Example 3

[0031] like Figure 3 As shown, the same points as those in the first embodiment are not described in detail. The difference lies in that the lowest point of the gate polysilicon 13 is higher than the highest point of the separation gate polysilicon 11 and is flush with the highest point of the wide portion of the cross-shaped groove.

[0032] The working principle of the split-gate IGBT structure described in the present invention is as follows:

[0033] When the collector metal 1 is connected to a positive bias, the gate polysilicon 13, the separation gate polysilicon 11, and the emitter metal 9 are connected to a low voltage, the device is in a blocking state, and the separation gate polysilicon 11 located in the wide part of the cross-shaped groove can assist in depleting the N-type storage layer 5, thereby effectively reducing the impact of the N-type storage layer 5 on the device breakdown voltage. When the collector metal 1 is connected to a positive bias, the gate polysilicon 13 is connected to a positive bias higher than the device threshold voltage, and the separation gate polysilicon 11 and the emitter metal 9 are connected to a low voltage, the device is in a conducting state. At this time, since the N-type storage layer 5 forms a hole barrier, the carrier concentration on the emitter side can be effectively increased, thereby greatly reducing the on-resistance of the device, thereby reducing the on-voltage drop of the device.

[0034] Comparison of the advantages and effects of the three structures:

[0035] In the structure described in Example 1, the shielding effect of the separated gate polysilicon 11 on the gate polysilicon 13 is the strongest, and the switching speed is the fastest. In the structure described in Example 2, the shielding effect of the separated gate polysilicon 11 on the gate polysilicon 13 is not as good as that in Example 1, and the switching speed is relatively slow; but since the gate polysilicon 13 is deeper into the N-type drift region 4, the gate polysilicon 13 is conducive to improving the carrier concentration on the emitter side, so the on-state voltage drop is lower than that in Example 1. In the structure described in Example 3, the shielding effect of the separated gate polysilicon 11 on the gate polysilicon 13 is stronger, and the switching speed is fast; but since the depth of the gate polysilicon 13 is shallower than that in Examples 1 and 2, it will result in a lower withstand voltage, and then a higher on-state voltage drop.

Claims

1. A split-gate IGBT structure, comprising a collector metal (1), a P-type collector region (2), an N-type field stop layer (3), and an N-type drift region (4) arranged in sequence from bottom to top, an N-type storage layer (5), a P-type body region (6), and an emitter metal (9) arranged in sequence above the N-type drift region (4), an N+ contact region (7) arranged in the P-type body region (6), and a first oxide layer medium (8) arranged in the middle of the bottom of the emitter metal (9), characterized in that: A cross-shaped groove is arranged in the N-type drift region (4), and separation gate polysilicon (11) is arranged in the left and right wide parts of the cross-shaped groove.

2. The split-gate IGBT structure according to claim 1, characterized in that: A gate oxide layer (12) is provided at the top of the cross-shaped groove, a second oxide layer medium (10) is provided at the bottom, and a gate polysilicon (13) is provided at the top of the cross-shaped groove to divide the gate oxide layer (12) into left and right parts.

3. The split-gate IGBT structure according to claim 1, characterized in that: The cross-shaped groove has a bilaterally symmetrical structure, and its top is flush with the bottom of the emitter metal (9).

4. The split-gate IGBT structure according to claim 1, characterized in that: The potential of the separation gate polysilicon (11) is equal to the potential of the emitter metal (9).

5. The split-gate IGBT structure according to claim 2, characterized in that: The lowest point of the gate polysilicon (13) is not higher than the upper end of the wide part of the cross-shaped groove.

6. The split-gate IGBT structure according to claim 2, characterized in that: The bottom end of the N-type storage layer (5) is not lower than the bottom end of the separation gate polysilicon (11).

7. The split-gate IGBT structure according to claim 1, characterized in that: The cross-shaped groove divides the N-type drift region (4), the N-type storage layer (5), the P-type body region (6) and the N+ contact region (7) into two parts, the left and the right.

8. The split-gate IGBT structure according to claim 5, characterized in that: The lowest point of the gate polysilicon (13) is located between the lowest point and the highest point of the separation gate polysilicon (11).

9. The split-gate IGBT structure according to claim 5, characterized in that: The lowest point of the gate polysilicon (13) is lower than the lowest point of the separation gate polysilicon (11).

10. The split-gate IGBT structure according to claim 5, characterized in that: The lowest point of the gate polysilicon (13) is flush with the highest point of the wide portion of the cross-shaped groove.

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