High-voltage-impact-resistant planar gate VDMOS integrated with TVS

Abstract

The utility model provides a TVS (Transient Voltage Suppressor)-integrated high-voltage-impact-resistant planar gate VDMOS (Vertical Double-diffused Metal Oxide Semiconductor), which is characterized in that the lower side surface of a drift layer is connected to the upper side surface of a silicon carbide substrate, a TVS structural region is arranged in the drift layer, and a bulge part is arranged on the drift layer; the lower side of the well region is connected to the upper side of the drift layer, the well region is provided with an open slot, and one side of the well region is connected to the side of the protrusion; the N-type source region is arranged on the open slot; the lower side surface of the P-type source region is connected to the upper side surface of the drift layer; one side surface of the P-type source region is connected with the N-type source region and the well region; the lower side surface of the gate dielectric layer is connected to the upper side surface of the bump and the well region; the source metal layer is connected to the N-type source region and the P-type source region; the gate metal layer is connected to the gate dielectric layer; and the drain metal layer is connected to the lower side surface of the silicon carbide substrate to discharge the current under the high-voltage condition of the drain, so that the gate of the device is protected from being impacted by the high voltage of the drain to damage the structure of the device.

Description

Technical Field

[0001] The utility model relates to a high-voltage impact-resistant planar gate VDMOS with integrated TVS. Background Art

[0002] As a representative device among silicon carbide power devices, silicon carbide VDMOS is widely used in electric vehicles, aerospace, power conversion and other fields. In aerospace applications, due to the influence of extreme external conditions, the working environment of the device is harsh, and there is a certain probability that a short-term abnormal high-voltage impact of the drain voltage will cause irreversible damage to the device, causing the device to fail directly, causing the power system to collapse, and the inconvenience of the aerospace vehicle being irreparable, which in turn causes immeasurable losses. Utility Model Content

[0003] The technical problem to be solved by the utility model is to provide a planar gate VDMOS with integrated TVS and high voltage impact resistance, which can discharge the current under the condition of high voltage at the drain, thereby protecting the device gate from being impacted by the high voltage at the drain and damaging the device structure.

[0004] The utility model is implemented as follows: a planar gate VDMOS with integrated TVS and high voltage impact resistance, comprising:

[0005] Silicon carbide substrate,

[0006] A drift layer, wherein the lower side of the drift layer is connected to the upper side of the silicon carbide substrate, a TVS structure region is provided in the drift layer, and a protrusion is provided on the drift layer;

[0007] A well region, wherein the lower side of the well region is connected to the upper side of the drift layer, an open groove is provided on the well region, and one side of the well region is connected to the side of the protrusion;

[0008] An N-type source region, the N-type source region is disposed on the opening groove;

[0009] A P-type source region, wherein the lower side of the P-type source region is connected to the upper side of the drift layer, and one side of the P-type source region is respectively connected to the N-type source region and the well region;

[0010] A gate dielectric layer, wherein the lower side of the gate dielectric layer is connected to the upper side of the protrusion and the well region;

[0011] A source metal layer, the source metal layer is connected to the N-type source region and the P-type source region;

[0012] a gate metal layer, the gate metal layer being connected to the gate dielectric layer;

[0013] and a drain metal layer connected to the lower side of the silicon carbide substrate.

[0014] The advantages of the utility model are:

[0015] 1. The basic structure of the device is a planar gate silicon carbide VDMOS device, which has a high gate reliability;

[0016] Second, the TVS structure area is integrated inside the device. The TVS structure area and the N-type drift layer above and below it form a TVS, which can form a conductive path from the drain, N-type drift layer, TVS structure area, N-type drift layer, P-type source area to the source when there is a large voltage shock at the drain, and complete the discharge of the current under the high voltage condition of the drain, thereby protecting the device gate from being impacted by the high voltage of the drain and damaging the device structure;

[0017] 3. The device structure only has a pn junction structure and no gate dielectric structure. It can withstand high voltage and high current in milliseconds and still be recoverable, thus improving the device's ability to cope with harsh high voltage environments and improving its self-recovery ability.

[0018] 4. The maximum depth of the device's P-type source region is equal to the P-type well region. This is to form a low-resistance path to the source when the device is turned on, to avoid thermal burnout of the P-type well region due to excessive resistance, and to improve the device's current resistance in special circumstances. BRIEF DESCRIPTION OF THE DRAWINGS

[0019] The present invention will be further described below in conjunction with the embodiments with reference to the accompanying drawings.

[0020] Figure 1 The utility model is a schematic diagram of a high-voltage impact-resistant planar gate VDMOS with integrated TVS.

[0021] Figure 2 The utility model is a flow chart of a method for preparing a high-voltage impact-resistant planar gate VDMOS with integrated TVS.

[0022] Figure 3 This is a cross-sectional view of the process of a planar gate VDMOS with integrated TVS and high voltage impact resistance in the utility model. Figure 1 .

[0023] Figure 4 This is a cross-sectional view of the process of a planar gate VDMOS with integrated TVS and high voltage impact resistance in the utility model. Figure 2 .

[0024] Figure 5 This is a cross-sectional view of the process of a planar gate VDMOS with integrated TVS and high voltage impact resistance in the utility model. Figure 3 .

[0025] Figure 6 This is a cross-sectional view of the process of a planar gate VDMOS with integrated TVS and high voltage impact resistance in the utility model. Figure 4 .

[0026] Figure 7 This is a cross-sectional view of the process of a planar gate VDMOS with integrated TVS and high voltage impact resistance in the utility model. Figure 5 .

[0027] Figure 8 This is a cross-sectional view of the process of a planar gate VDMOS with integrated TVS and high voltage impact resistance in the utility model. Figure 6 .

[0028] Fig. 9 This is a cross-sectional view of the process of a planar gate VDMOS with integrated TVS and high voltage impact resistance in the utility model. Figure 7 .

[0029] Fig.10 This is a cross-sectional view of the process of a planar gate VDMOS with integrated TVS and high voltage impact resistance in the utility model. Figure 8 . DETAILED DESCRIPTION

[0030] In order to facilitate understanding of the present application, the present application will be described more fully below with reference to the relevant drawings. Embodiments of the present application are provided in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, the purpose of providing these embodiments is to make the disclosure of the present application more thorough and comprehensive.

[0031] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application belongs. The terms used herein in the specification of this application are only for the purpose of describing specific embodiments and are not intended to limit this application.

[0032] It should be understood that when an element or layer is referred to as "on ...", "adjacent to ...", "connected to" or "coupled to" other elements or layers, it can be directly on, adjacent to, connected to or coupled to other elements or layers, or there can be intervening elements or layers. On the contrary, when an element is referred to as "directly on ...", "in contact with ...", "directly connected to" or "directly coupled to" other elements or layers, there is no intervening element or layer. It should be understood that although the terms first, second, third, etc. can be used to describe various elements, components, regions, layers, doping types and / or parts, these elements, components, regions, layers, doping types and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type or part from another element, component, region, layer, doping type or part. Therefore, without departing from the teachings of the present invention, the first element, component, region, layer, doping type or part discussed below can be represented as a second element, component, region, layer or part.

[0033] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," and the like may be used herein to describe the relationship of one element or feature described in the figures to other elements or features. It should be understood that, in addition to the orientations described in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the accompanying drawings is flipped, an element or feature described as "under other elements" or "under it" or "under it" will be oriented as being "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include additional orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0034] When used herein, the singular forms "a", "an", and "said / the" may also include plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include / comprise" or "have" and the like specify the presence of stated features, wholes, steps, operations, components, parts, or combinations thereof, but do not exclude the possibility of the presence or addition of one or more other features, wholes, steps, operations, components, parts, or combinations thereof. At the same time, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0035] like Figure 1 As shown, the embodiment of the present application provides a planar gate VDMOS with integrated TVS and high voltage impact resistance, including:

[0036] Silicon carbide substrate 1,

[0037] A drift layer 2, wherein the lower side of the drift layer 2 is connected to the upper side of the silicon carbide substrate 1, a TVS structure region 21 is provided in the drift layer 2, a protrusion 22 is provided on the drift layer 2, and the TVS structure region 21 is not located directly below the protrusion 22;

[0038] A well region 3, wherein the lower side of the well region 3 is connected to the upper side of the drift layer 2, an opening groove 31 is provided on the well region 3, one side of the well region 3 is connected to the side of the protrusion 22, and the TVS structure region is of P type;

[0039] An N-type source region 4, wherein the N-type source region 4 is disposed on the opening groove 31;

[0040] A P-type source region 5, wherein the lower side of the P-type source region 5 is connected to the upper side of the drift layer 2, and one side of the P-type source region 5 is respectively connected to the N-type source region 4 and the well region 3, and the thickness of the well region 3 is equal to the thickness of the P-type source region 5;

[0041] A gate dielectric layer 6, wherein the lower side of the gate dielectric layer 6 is connected to the upper side of the protrusion 22 and the well region 3;

[0042] A source metal layer 7, wherein the source metal layer 7 is connected to the N-type source region 4 and the P-type source region 5;

[0043] A gate metal layer 8, wherein the gate metal layer 8 is connected to the gate dielectric layer 6;

[0044] and a drain metal layer 9 , wherein the drain metal layer 9 is connected to the lower side of the silicon carbide substrate 1 .

[0045] like Figures 2 to 10 As shown, the preparation method of the above VDMOS includes the following steps:

[0046] Step 1: depositing metal on the lower side of the silicon carbide substrate 1 to form a drain metal layer 9, and depositing and growing a drift layer 2 on the upper side of the silicon carbide substrate 1;

[0047] Step 2, forming a barrier layer a above the drift layer 2, etching a through hole, and performing ion implantation on the drift layer 2 to form a TVS structure region 21 in the drift layer 2, wherein the ion implantation energy is 400-600kev and the depth is 1200nm-1800nm, that is, the thickness of the TVS structure region 21 is 600nm;

[0048] Step 3, remove the original barrier layer a, re-form the barrier layer a, etch to form a through hole, perform ion implantation on the drift layer 2, form a well region 3 and a protrusion 22, the TVS structure region 21 is not located directly below the protrusion 22; the ion implantation energy is 10-200kev, the depth is 600nm, and the thickness of the well region 3 is 600nm;

[0049] Step 4, remove the original barrier layer a, re-form the barrier layer a, etch to form a through hole, perform ion implantation on the well region 3 to form a P-type source region 5, the thickness of the well region 3 is equal to the thickness of the P-type source region 5, the implantation energy is 10-200kev, the depth is 600nm, and the thickness of the P-type source region 5 is 600nm;

[0050] Step 5, remove the original barrier layer a, re-form the barrier layer a, etch to form a through hole, perform ion implantation on the well region 3 to form an N-type source region 4, the implantation energy is 10-100kev, the depth is 300nm, and the thickness of the N-type source region 4 is 300nm;

[0051] Step 6, removing the original barrier layer a, re-forming the barrier layer a, etching to form a through hole, and performing metal deposition through the through hole to form a source metal layer 7;

[0052] Step 7, removing the original barrier layer a, re-forming the barrier layer a, etching to form a through hole, and depositing through the through hole to form a gate dielectric layer 6;

[0053] Step 8: remove the original barrier layer a, re-form the barrier layer a, etch to form a through hole, deposit metal through the through hole to form a gate metal layer 8, remove the barrier layer a, and complete the preparation.

[0054] The doping concentration of the N-type silicon carbide substrate 1 is 2e18cm -3 , the doping concentration of the N-type drift layer 2 is 6e17cm -3 The doping concentration of the TVS structure region 21 is 5e16 cm -3 The doping concentration of the well region 3 is 1e17 cm -3 The doping concentration of the N-type source region 4 is 2e18cm -3 The doping concentration of the P-type source region 5 is 8e18cm -3 The gate dielectric layer 6 is silicon dioxide, the doping concentration of the silicon carbide substrate 1 is to form an ohmic contact with the drain metal layer 9 while reducing the drain contact resistance; the doping concentration of the drift layer 2 is to reduce the on-resistance of the device and ensure the compromise between withstand voltage; the doping concentration of the TVS structure area 21 is to form the TVS structure while avoiding the influence on the on-resistance of the device when it is normally turned on; the doping concentration of the P-type well area 3 is to control the device to be turned off while reducing the inversion charge of the device, reducing the gate charge, and increasing the switching speed of the device; the doping concentration of the N-type source area 4 is to form an ohmic contact with the source metal layer 7, and the doping concentration of the P-type source area 5 is to match the ohmic contact resistance between the source metal layer 7 and the N-type source area 4.

[0055] Although the specific implementation methods of the present invention are described above, those skilled in the art should understand that the specific embodiments described are only illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included in the scope of protection of the claims of the present invention.

Claims

1. A planar gate VDMOS with integrated TVS and high voltage impact resistance, characterized in that: include: Silicon carbide substrate, A drift layer, wherein the lower side of the drift layer is connected to the upper side of the silicon carbide substrate, a TVS structure region is provided in the drift layer, and a protrusion is provided on the drift layer; A well region, wherein the lower side of the well region is connected to the upper side of the drift layer, an open groove is provided on the well region, and one side of the well region is connected to the side of the protrusion; An N-type source region, the N-type source region is disposed on the opening groove; A P-type source region, wherein the lower side of the P-type source region is connected to the upper side of the drift layer, and one side of the P-type source region is respectively connected to the N-type source region and the well region; A gate dielectric layer, wherein the lower side of the gate dielectric layer is connected to the upper side of the protrusion and the well region; A source metal layer, the source metal layer is connected to the N-type source region and the P-type source region; a gate metal layer, the gate metal layer being connected to the gate dielectric layer; and a drain metal layer connected to the lower side of the silicon carbide substrate.

2. A planar gate VDMOS with integrated TVS and high voltage impact resistance as claimed in claim 1, characterized in that: The TVS structure region is not located directly under the protrusion.

3. A planar gate VDMOS with integrated TVS and high voltage impact resistance as claimed in claim 1, characterized in that: The thickness of the well region is equal to the thickness of the P-type source region.

4. The high voltage impact resistant planar gate VDMOS with integrated TVS as claimed in claim 1, characterized in that: The TVS structural region is of P type.

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