A silicon carbide vdmos with high drain voltage surge resistance and a method of manufacture

Abstract

The application provides a silicon carbide VDMOS with high anti-drain voltage impact and a preparation method. A first drift region is epitaxially grown on a silicon carbide substrate with a drain metal layer; a current uniform layer, a second drift region and a drift layer including the first drift region and the second drift region are formed; a barrier layer is formed, etching, ion implantation, a plurality of uniformly spaced mask layers, a P-type well region, an N-type source region, an N-type region, the barrier layer is reformed, etching, oxidation to form an insulating medium layer; metal deposition, gate metal layer formation, barrier layer reforming, etching, metal deposition, source metal layer formation; the barrier layer is removed, and the preparation is completed; the reliability of the device to the drain voltage impact is improved, the gate-source capacitance of the device is reduced, the switching speed of the device is improved, the switching loss of the device is reduced, the body diode conduction loss of the device is reduced, and the reverse recovery speed of the device is improved.

Description

Technical Field

[0001] The invention relates to a silicon carbide VDMOS with high resistance to drain voltage shock and a preparation method thereof. Background Art

[0002] SiC MOSFETs are a typical example of SiC power devices, widely used in electric vehicles, aerospace, power conversion, and other fields. Different fields place varying emphasis on device performance requirements for SiC power MOSFETs, but the overall requirements include lower on-resistance, faster switching speeds, higher reliability (including gate reliability and drain voltage surge reliability), and lower body diode conduction losses. Summary of the Invention

[0003] The technical problem to be solved by the present invention is to provide a silicon carbide VDMOS with high resistance to drain voltage shock and a preparation method, thereby improving the reliability of the device in resisting drain voltage shock, reducing the gate-source capacitance of the device, increasing the switching speed of the device, and reducing the switching loss of the device. At the same time, the body diode conduction loss of the device can be reduced and the reverse recovery speed of the device can be increased.

[0004] In a first aspect, the present invention provides a method for preparing a silicon carbide VDMOS with high resistance to drain voltage shock, comprising the following steps:

[0005] Step 1: epitaxially growing a first drift region on a silicon carbide substrate with a drain metal layer;

[0006] Step 2: epitaxially growing a flow-balancing layer on the first drift region;

[0007] Step 3: epitaxially growing a second drift region on the current balancing layer, wherein the drift layer includes the first drift region and the second drift region;

[0008] Step 4: forming a barrier layer on the drift layer, etching the barrier layer to form a through hole, and performing ion implantation on the drift layer to form a plurality of evenly spaced masking layers, with an ion implantation energy of 230-300 keV;

[0009] Step 5: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation on the drift layer to form a P-type well region. The ion implantation energy is 70-200 keV.

[0010] Step 6: Remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation on the P-type well region to form an N-type source region. The ion implantation energy is 70-170keV.

[0011] Step 7: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation on the drift layer to form an N-type region. The ion implantation energy is 70-200 keV.

[0012] Step 8: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and etch the drift layer, and then oxidize it to form an insulating dielectric layer;

[0013] Step 9: removing the original barrier layer, re-forming the barrier layer, etching the barrier layer and the insulating dielectric layer, and depositing metal to form a first gate metal region;

[0014] Step 10: depositing an insulating medium so that the insulating medium is at the same height as the upper side of the drift layer;

[0015] Step 11: remove the original barrier layer, re-form the barrier layer, etch the barrier layer and the insulating dielectric layer to the upper side of the first gate metal region, deposit metal to form a second gate metal region, the gate metal layer includes the first gate metal region and the second gate metal region, and the gate metal layer is in an inverted T shape;

[0016] Step 12: remove the original barrier layer, re-form the barrier layer, etch the barrier layer and the drift layer, deposit metal to form a source metal layer; remove the barrier layer to complete the preparation.

[0017] In a second aspect, the present invention provides a silicon carbide VDMOS with high resistance to drain voltage shock, wherein the silicon carbide VDMOS is prepared by the method for preparing a silicon carbide VDMOS with high resistance to drain voltage shock described in the first aspect.

[0018] The advantages of the present invention are:

[0019] 1. A uniformly distributed P-type shielding region is constructed inside the device, which protects the corners of the device's trench gate from breakdown caused by electric field concentration without affecting the device's conductive properties;

[0020] Second, in addition to protecting the device's insulating dielectric layer, the P-type shielding layer can also protect the device's gate and source when a high drain voltage surge occurs through the space charge region formed near the P-type shielding layer.

[0021] 3. The gate metal layer of the device has an inverted T-shaped structure, which achieves smaller gate-source capacitance, reduces the gate charge of the device, and improves the switching speed of the device. An N-type current-sharing region is constructed under the P-type shielding layer of the device. In order to ensure the protection effect of the P-type shielding region against drain voltage shock, the thickness of the N-type drift layer from the bottom of the P-type shielding layer to the top of the N-type current-sharing layer is 100nm. The N-type current-sharing layer can evenly distribute the current inside the device to avoid current concentration. At the same time, the N-type current-sharing layer shields the capacitance effect from the gate metal to the drain, which can effectively suppress the gate-drain capacitance of the device, namely the Maitreya capacitance, which can reduce the platform period of device turn-on and turn-off, and effectively improve the switching speed of the device.

[0022] Fourth, a Schottky body diode is constructed from the source metal layer to the N-type region inside the device, which can effectively reduce the body diode loss of the device, reduce the reverse recovery time of the device, and increase the switching speed of the device. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0024] Figure 1 This is a schematic diagram of a silicon carbide VDMOS with high resistance to drain voltage shock according to the present invention.

[0025] Figure 2 This is a cross-sectional view of the process of a silicon carbide VDMOS with high resistance to drain voltage shock of the present invention Figure 1 .

[0026] Figure 3 This is a cross-sectional view of the process of a silicon carbide VDMOS with high resistance to drain voltage shock of the present invention Figure 2 .

[0027] Figure 4 This is a cross-sectional view of the process of a silicon carbide VDMOS with high resistance to drain voltage shock of the present invention Figure 3 .

[0028] Figure 5 This is a cross-sectional view of the process of a silicon carbide VDMOS with high resistance to drain voltage shock of the present invention Figure 4 .

[0029] Figure 6 This is a cross-sectional view of the process of a silicon carbide VDMOS with high resistance to drain voltage shock of the present invention Figure 5 .

[0030] Figure 7 This is a cross-sectional view of the process of a silicon carbide VDMOS with high resistance to drain voltage shock of the present invention Figure 6 .

[0031] Figure 8 This is a cross-sectional view of the process of a silicon carbide VDMOS with high resistance to drain voltage shock of the present invention Figure 7 .

[0032] Figure 9 This is a cross-sectional view of the process of a silicon carbide VDMOS with high resistance to drain voltage shock of the present invention Figure 8 .

[0033] Figure 10 This is a cross-sectional view of the process of a silicon carbide VDMOS with high resistance to drain voltage shock of the present invention Figure 9 .

[0034] Figure 11 This is a cross-sectional view of the process of a silicon carbide VDMOS with high resistance to drain voltage shock of the present invention Figure 10 .

[0035] Figure 12 This is a cross-sectional view of the process of a silicon carbide VDMOS with high resistance to drain voltage shock of the present invention Figure 10 one.

[0036] Figure 13 This is a cross-sectional view of the process of a silicon carbide VDMOS with high resistance to drain voltage shock of the present invention Figure 10 two.

[0037] Figure 14 This is a cross-sectional view of the process of a silicon carbide VDMOS with high resistance to drain voltage shock of the present invention Figure 10 three.

[0038] Figure 15 This is a cross-sectional view of the process of a silicon carbide VDMOS with high resistance to drain voltage shock of the present invention Figure 10 Four.

[0039] Figure 16 This is a cross-sectional view of the process of a silicon carbide VDMOS with high resistance to drain voltage shock of the present invention Figure 10 five. DETAILED DESCRIPTION

[0040] To facilitate understanding of the present application, the present application will be described more fully below with reference to the accompanying drawings. The accompanying drawings provide embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0041] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0042] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. In contrast, when an element is referred to as being "directly on," "in contact with," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Thus, without departing from the teachings of the present invention, the first element, component, region, layer, doping type, or portion discussed below may be represented as a second element, component, region, layer, or portion.

[0043] Spatially relative terms such as "under," "beneath," "beneath," "under," "above," "above," etc., may be used herein to describe the relationship of one element or feature to other elements or features depicted in the figures. It should be understood that, in addition to the orientations depicted in the figures, spatially relative terms also encompass different orientations of the device in use and operation. For example, if the device in the figures is flipped over, an element or feature described as "under" or "beneath" or "beneath" the other elements would be oriented "over" the other elements or features. Thus, the exemplary terms "under" and "under" may encompass both the upper and lower orientations. Additionally, the device may also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0044] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "include," "comprising," "having," and the like specify the presence of stated features, integers, steps, operations, components, parts, or combinations thereof, but do not preclude the presence or addition of one or more other features, integers, steps, operations, components, parts, or combinations thereof. Also, in this specification, the term "and / or" includes any and all combinations of the relevant listed items.

[0045] like Figures 1 to 16 As shown, the embodiment of the present application provides a method for preparing a silicon carbide VDMOS with high resistance to drain voltage shock, comprising the following steps:

[0046] Step 1: epitaxially growing a first drift region 24 on a silicon carbide substrate 1 with a drain metal layer 8;

[0047] Step 2: epitaxially growing a current balancing layer 21 on the first drift region 24;

[0048] Step 3: epitaxially grow a second drift region 25 on the current balancing layer 21 . The drift layer 2 includes a first drift region 24 and a second drift region 25 .

[0049] Step 4: forming a barrier layer 9 on the drift layer 2, etching the barrier layer 9 to form a through hole, and performing ion implantation on the drift layer 2 to form a plurality of evenly spaced masking layers 22, with an ion implantation energy of 230-300 keV;

[0050] Step 5: remove the original barrier layer 9, re-form the barrier layer 9, etch the barrier layer 9 to form a through hole, and perform ion implantation on the drift layer 2 to form a P-type well region 4. The ion implantation energy is 70-200 keV.

[0051] Step 6: remove the original barrier layer 9, re-form the barrier layer 9, etch the barrier layer 9 to form a through hole, and perform ion implantation on the P-type well region 4 to form an N-type source region 41. The ion implantation energy is 70-170 keV.

[0052] Step 7: remove the original barrier layer 9, re-form the barrier layer 9, etch the barrier layer 9 to form a through hole, and perform ion implantation on the drift layer 2 to form an N-type region 3. The ion implantation energy is 70-200 keV.

[0053] Step 8: Remove the original barrier layer 9, re-form the barrier layer 9, etch the barrier layer 9 to form a through hole, and etch the drift layer 2 to the upper side of the mask layer 22, and then oxidize it to form an insulating dielectric layer 5. The two sides of the bottom of the insulating dielectric layer 5 are respectively connected to the upper side of the mask layer 22;

[0054] Step 9: removing the original barrier layer 9, re-forming the barrier layer 9, etching the barrier layer 9 and the insulating dielectric layer 5, and depositing metal to form a first gate metal region 61;

[0055] Step 10: depositing an insulating medium so that the insulating medium is at the same height as the upper side of the drift layer 2;

[0056] Step 11: remove the original barrier layer 9, re-form the barrier layer 9, etch the barrier layer 9 and the insulating dielectric layer 5 to the upper side of the first gate metal region 61, and deposit metal to form the second gate metal region 62. The gate metal layer 6 includes the first gate metal region 61 and the second gate metal region 62, and the gate metal layer 6 is an inverted T-shape.

[0057] Step 12: remove the original barrier layer 9, re-form the barrier layer 9, etch the barrier layer 9 and the drift layer 2, deposit metal to form the source metal layer 7; remove the barrier layer 9, and complete the preparation.

[0058] In this embodiment, preferably, the doping concentration of the masking layer 22 is higher than the doping concentration of the current equalizing layer 21, the doping concentration of the current equalizing layer 21 is higher than the doping concentration of the drift layer 2, the doping concentration of the N-type region 3 is lower than the doping concentration of the P-type well region 4, and the doping concentration of the P-type well region 4 is lower than the doping concentration of the N-type source region 41.

[0059] like Figure 1 As shown, the silicon carbide VDMOS obtained by the above manufacturing method includes:

[0060] Silicon carbide substrate 1,

[0061] A drift layer 2, wherein the lower side of the drift layer 2 is connected to the upper side of the silicon carbide substrate 1; a current balancing layer 21 and a plurality of masking layers 22 are provided in the drift layer 2, wherein the masking layer 22 is located above the current balancing layer 2, and the plurality of masking layers 22 are evenly spaced.

[0062] An N-type region 3, wherein the lower side of the N-type region 3 is connected to the upper side of the drift layer 1;

[0063] A P-type well region 4, wherein the outer side of the P-type well region 4 is connected to the inner side of the N-type region 3, the lower side of the P-type well region 4 is connected to the upper side of the drift layer 1, and an N-type source region 41 is provided in the P-type well region 4;

[0064] an insulating dielectric layer 5, wherein the lower side of the insulating dielectric layer 5 is connected to the upper side of the drift layer 2, and the outer side of the insulating dielectric layer 5 is connected to the inner side of the P-type well region 4 and the inner side of the N-type source region 41; a trench 51 is defined in the insulating dielectric layer 5, and the trench 51 is in an inverted T shape;

[0065] a gate metal layer 6 , the gate metal layer 6 being disposed in the trench 51 and having an inverted T-shape;

[0066] a source metal layer 7 , the source metal layer 7 being connected to the N-type region 3 , the P-type well region 4 , and the N-type source region 41 ;

[0067] and a drain metal layer 8 , wherein the drain metal layer 8 is connected to the lower side of the silicon carbide substrate 1 .

[0068] A groove 23 is provided on the drift layer 2, the lower portion of the insulating dielectric layer 5 is provided in the groove 23, and both sides of the bottom of the insulating dielectric layer 5 are respectively connected to the upper side of the masking layer 22, the lower side of the gate metal layer 6 is lower than the lower side of the P-type well region 4, the thickness of the N-type region 3 is equal to the thickness of the P-type well region 4, and the spacing between adjacent masking layers 22 is 300-500nm.

[0069] Another embodiment of the present invention:

[0070] The silicon carbide substrate 1, drift layer 2, and current-balancing layer 21 are all N-type; the masking layer 22 is P-type; the doping concentration of the N-type silicon carbide substrate 1 is 2e18 cm -3 , the doping concentration of the N-type drift layer 2 is 1e16cm -3 The doping concentration of the N-type current balancing layer 21 is 1e17 cm -3 The doping concentration of the P-type shielding layer 22 is 5e17 cm -3 The doping concentration of the P-type well region 4 is 5e17 cm -3 , the doping concentration of the N-type source region 41 is 2e18cm -3 , the doping concentration of N-type region 3 is 1e17cm -3 , the material of the insulating dielectric layer 5 can be one or a combination of silicon dioxide, aluminum nitride, and hafnium dioxide;

[0071] The doping concentration of the silicon carbide substrate 1 is to ensure that a low-resistance ohmic contact is formed with the drain metal layer 8, thereby reducing the overall on-resistance of the device; the doping concentration of the N-type drift layer 2 is a compromise between the reverse withstand voltage and on-resistance of the device; the doping concentration of the N-type region 3 is to reduce the on-resistance of the device while forming a Schottky metal rather than an ohmic contact with the source metal layer 7, thereby forming a Schottky body diode inside the device; the P-type well region 4 is to control the turn-off characteristics of the device without affecting the gate control capability of the device; the doping concentration of the P-type masking layer 22 is to ensure the tolerance to drain voltage shocks while controlling the impact on the on-resistance of the device; the N-type current sharing layer 21 is to achieve current sharing inside the device.

[0072] The thickness of the silicon carbide substrate 1 of the device is 1μm, which is to ensure the support for the subsequent structure preparation of the device. The thickness of the N-type drift layer 2 (referring to the distance from the top of the silicon carbide substrate 1 to the top of the P-type shielding layer 22) is 15-25μm, which is adjusted within the above range according to the different requirements for the withstand voltage characteristics of the device; the thickness of the P-type shielding layer 22 is 200nm, which protects the corners of the trench gate of the device from being broken down by the electric field concentration without affecting the conductive characteristics of the device. When the drain is subjected to a high voltage shock, the P-type shielding layer 22 can protect the gate and source of the device through the space charge region formed near the P-type shielding layer 22. The distance from the bottom of the P-type shielding layer 22 to the top of the N-type current balancing layer 21 is 100nm. The N-type current balancing layer 21 can evenly distribute the current inside the device to avoid current concentration. At the same time, the N-type current balancing layer 21 shields the capacitance effect from the gate to the drain, which can effectively suppress the gate-drain capacitance of the device, that is, the Maitreya capacitance, which can reduce the platform period of turning on and off the device and effectively improve the switching speed of the device;

[0073] The width of the P-type shielding layer 22 is 200 nm, and the spacing between two adjacent shielding layers 22 is 300-500 nm. This is to protect the gate and source of the device in the space charge region formed near the P-type shielding layer 22. The width relationship is designed based on the doping concentration of the P-type shielding layer 22 and the N-type drift layer 2.

[0074] The gate metal layer 6 of the device has an inverted T-shaped structure. The thickness of the insulating dielectric at the bottom of the gate metal layer 6 is 50nm, and the thickness of the insulating dielectric on the side of the gate metal layer 6 is 30nm and 100-200nm respectively. The insulating dielectric between the gate metal layer 6, the source metal layer 7 and the N-type source region 41 is wider and the capacitance is smaller, thereby achieving a smaller gate-source capacitance, reducing the gate charge of the device, and improving the switching speed of the device; the thickness of the source metal layer is 200nm, the thickness of the N-type source region 41 is 300nm, the thickness of the P-type well region 4 is 400nm, and the depth of the drift layer 2 groove is 100nm; a Schottky body diode is constructed from the source metal layer 7 to the N-type region 3 inside the device, which can effectively reduce the body diode loss of the device, reduce the reverse recovery time of the device, and improve the switching speed of the device.

[0075] Although the specific embodiments of the present invention are described above, those skilled in the art should understand that the specific embodiments described are merely illustrative and are not intended to limit the scope of the present invention. Equivalent modifications and changes made by those skilled in the art in accordance with the spirit of the present invention should be included within the scope of protection of the claims of the present invention.

Claims

1. A method for preparing a silicon carbide VDMOS with high drain voltage surge resistance, characterized in that: The steps include: Step 1: epitaxially growing a first drift region on a silicon carbide substrate with a drain metal layer; Step 2: epitaxially growing a current balancing layer on the first drift region, wherein the current balancing layer is N-type; Step 3: epitaxially growing a second drift region on the current-balancing layer, wherein the drift layer includes a first drift region and a second drift region, and the drift layer is N-type; Step 4: forming a barrier layer on the drift layer, etching the barrier layer to form a through hole, and performing ion implantation on the drift layer to form a plurality of evenly spaced masking layers, wherein the ion implantation energy is 230-300 keV; the masking layer is located above the current balancing layer, and the masking layer is P-type; Step 5: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation on the drift layer to form a P-type well region. The ion implantation energy is 70-200 keV. Step 6: Remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation on the P-type well region to form an N-type source region. The ion implantation energy is 70-170keV. Step 7: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and perform ion implantation on the drift layer to form an N-type region. The ion implantation energy is 70-200 keV. Step 8: remove the original barrier layer, re-form the barrier layer, etch the barrier layer to form a through hole, and etch the drift layer, and then oxidize it to form an insulating dielectric layer; Step 9: removing the original barrier layer, re-forming the barrier layer, etching the barrier layer and the insulating dielectric layer, and depositing metal to form a first gate metal region; Step 10: depositing an insulating medium so that the insulating medium is at the same height as the upper side of the drift layer; Step 11: remove the original barrier layer, re-form the barrier layer, etch the barrier layer and the insulating dielectric layer to the upper side of the first gate metal region, deposit metal to form a second gate metal region, the gate metal layer includes the first gate metal region and the second gate metal region, and the gate metal layer is in an inverted T shape; Step 12: remove the original barrier layer, re-form the barrier layer, etch the barrier layer and the drift layer, and deposit metal to form a source metal layer; The barrier layer is removed to complete the preparation.

2. The method for preparing a silicon carbide VDMOS with high drain voltage surge resistance according to claim 1, wherein: The step 8 specifically includes: removing the original barrier layer, re-forming the barrier layer, etching the barrier layer to form a through hole, and etching the drift layer to the upper side of the mask layer, and then oxidizing to form an insulating dielectric layer, and the two sides of the bottom of the insulating dielectric layer are respectively connected to the upper side of the mask layer.

3. The method for preparing a silicon carbide VDMOS with high drain voltage surge resistance according to claim 1, wherein: The lower side of the gate metal layer is lower than the lower side of the P-type well region.

4. The method for preparing a silicon carbide VDMOS with high drain voltage surge resistance according to claim 1, wherein: The thickness of the N-type region is equal to the thickness of the P-type well region.

5. The method for preparing a silicon carbide VDMOS with high drain voltage surge resistance according to claim 1, wherein: The distance between adjacent masking layers is 300-500 nm.

6. The method for preparing a silicon carbide VDMOS with high drain voltage surge resistance according to claim 1, wherein: The doping concentration of the masking layer is higher than the doping concentration of the current balancing layer, and the doping concentration of the current balancing layer is higher than the doping concentration of the drift layer.

7. The method for preparing a silicon carbide VDMOS with high drain voltage surge resistance according to claim 1, wherein: The doping concentration of the N-type region is lower than the doping concentration of the P-type well region, and the doping concentration of the P-type well region is lower than the doping concentration of the N-type source region.

8. A silicon carbide VDMOS with high drain voltage surge resistance, characterized in that: The silicon carbide VDMOS is prepared by any one of the preparation methods of claim 1 to claim 7.

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