Dual-gate based gan high electron mobility transistor structure and method of fabrication

Abstract

The application discloses a double-gate-based GaN high electron mobility transistor structure and a preparation method thereof. The transistor structure comprises, from bottom to top, a substrate, a nucleation layer, a buffer layer, a channel layer, a barrier layer and a dielectric layer. The dielectric layer is provided with a source trench and a drain trench on two sides thereof, and a gate structure is arranged at a position between the source trench and the drain trench. The gate structure comprises a left gate structure close to the source trench and a right gate structure close to the drain trench, and the left and right gate structures are isolated by a dielectric. The structure makes the electric field of the right gate of the transistor adjustable by the left gate under the same gate voltage, and the distribution of the electric field is more uniform, thereby improving the gate leakage. Meanwhile, the change of the left gate is small, the hole escape and the electron capture are reduced, and the dynamic threshold and other problems of the device are improved. Under the premise of losing a certain on-resistance and gate capacitance, the saturated source-drain current of the device is improved, the gate leakage is reduced, and the gate reliability is improved.

Description

TECHNICAL FIELD

[0001] The application belongs to the technical field of semiconductors, and relates to a nitride power semiconductor device reliability reinforcement technology, in particular to a GaN high electron mobility transistor structure based on a double gate and a preparation method. BACKGROUND

[0002] In order to control power conversion and energy consumption in a power electronic system and improve energy utilization efficiency, an enhanced power switching transistor with higher energy transmission efficiency has entered the public view. Wide bandgap materials have greater advantages in electrical characteristics, thermal performance and energy utilization efficiency compared with low bandgap materials represented by traditional silicon materials. Among them, GaN materials have the advantages of higher mobility carriers and large breakdown electric field.

[0003] A Schottky type p-GaN gate high electron mobility transistor exhibits extremely high commercialization prospects compared with other enhanced device structures. The p-type cap layer structure above the gate barrier layer causes the conduction band of the heterojunction below the gate to be raised above the Fermi level, so that the electrons below the gate are depleted and the threshold value is positively moved. In order to reduce the leakage of the device and improve the gate swing, the use of Schottky contact instead of ohmic contact can improve the reliability of the gate, but the gate reliability is still a key problem of the p-GaN gate hemt. There is a large voltage drop and electric field in the Schottky type p-GaN gate structure, which will exhibit time-dependent degradation, thereby causing a strong increase in gate leakage. The safe gate bias voltage is generally about 6V. Most people believe that the cause of gate breakdown may be Schottky tunneling, leakage of the passivation layer and trap-assisted tunneling in the barrier layer. Changes in the same gate geometry and defect mechanism of the p-type cap layer will also cause reliability to decrease. SUMMARY

[0004] The application proposes a GaN high electron mobility transistor structure based on a double gate and a preparation method to solve the problems in the prior art. The gate structure is redesigned, the p-type cap and field plate structure are improved, and the gate leakage and dynamic threshold problems of the device are solved.

[0005] The GaN high electron mobility transistor structure based on a double gate comprises, from bottom to top, a substrate, a nucleation layer, a buffer layer, a channel layer, a barrier layer and a first dielectric layer, and a second dielectric layer. The two sides of the dielectric layer are respectively provided with a source trench and a drain trench, and the source trench and the drain trench pass through the dielectric layer and the barrier layer and are in contact with the upper surface of the channel layer. The source trench is provided with a source metal, and the drain trench is provided with a drain metal. A gate structure is arranged between the source trench and the drain trench in the dielectric layer.

[0006] The gate structure includes a left gate structure close to the source trench and a right gate structure close to the drain trench, and the left and right gate structures are separated by a dielectric. The right gate structure from bottom to top is a right p-type cap layer and a right gate metal, the right gate metal is higher than the first dielectric layer, and the right gate field plate is located on the upper surface of the first dielectric layer and extends from the side of the right gate metal to the direction of the drain trench. The left gate structure from bottom to top is a left p-type cap layer, a left gate metal and a left gate field plate, the left gate field plate is located above the right gate structure, the upper surface is higher than the upper surface of the second dielectric layer, and the right end of the left gate field plate is located between the right gate field plate and the drain trench in the second dielectric layer.

[0007] As a preferred, the p-type cap layer is directly in contact with the gate metal. The gate metal is a Schottky contact, the width of the left and right p-type cap layers is 0.6 µm, and the thickness is 110 nm. The left and right p-type cap layers are separated by a 0.2 µm dielectric layer. The p-type cap layer is doped with Mg, and the concentration is 2e19 cm-3.

[0008] As a preferred, the height of the left gate field plate is 0.4 µm, and the length is 4 µm. A groove structure with a height of 0.2 µm and a width of 1.9 µm is arranged at one end close to the drain trench. The height of the right gate field plate is 0.2 µm, and the length is 1.8 µm.

[0009] As a preferred, the thickness of the nucleation layer AlN is 0.05 µm; the thickness of the buffer layer Al 0.05 Ga 0.95 N is 2 µm, and the doping concentration is 1e14 cm-3; the channel layer is non-intentionally doped GaN with a thickness of 0.2 µm; the barrier layer is non-intentionally doped Al 0.23 Ga 0.77 N with a thickness of 0.015 µm.

[0010] As a preferred, the etching width of the source trench and the drain trench is 0.5 µm, and the depth is 0.45 µm. The spacing distance between the source trench and the gate structure is 1 µm, and the spacing distance between the gate structure and the drain trench is 10 µm.

[0011] The preparation method of the double-gate-based GaN high electron mobility transistor specifically includes the following steps:

[0012] Step 1, a silicon substrate region of a power semiconductor device is prepared, a C impurity is added to the silicon substrate region by metal organic chemical vapor deposition (MOCVD), and an AlN nucleation layer and an AlGaN buffer layer are sequentially grown by epitaxy. A non-intentionally doped GaN channel layer and a non-intentionally doped AlGaN barrier layer are sequentially grown by metal organic chemical vapor deposition on the AlGaN buffer layer. A first dielectric layer is deposited on the AlGaN barrier layer by plasma enhanced chemical vapor deposition (PECVD).

[0013] Step 2, after opening the right gate window by inductively coupled plasma (ICP) etching the first dielectric layer, continue etching by low damage HCL immersion digital etching process until the AlGaN barrier layer is exposed, and a right gate recess is obtained.

[0014] Step 3, epitaxially grow a right p-type cap layer on the right gate recess by metal organic chemical vapor deposition using Mg as P-type doping. Then deposit Ni / Au on the right p-type cap layer by low pressure chemical vapor deposition (LPCVD) method to a height above the first dielectric layer to form a right gate metal.

[0015] Step 4, deposit aluminum metal on the first dielectric layer to the right of the right gate metal to obtain a right gate field plate. Step 5, deposit a 0.2µm second dielectric layer on the first dielectric layer by plasma enhanced chemical vapor deposition (PECVD) method. Repeat the above steps 2-4 to etch a left gate recess and sequentially deposit a left p-type cap layer, a left gate metal and a left gate field plate.

[0016] Step 6, use low damage HCL immersion digital etching process on both sides of the second dielectric layer until the GaN channel layer is exposed, and continue etching to 0.05µm below the upper surface of the channel layer to obtain a source trench and a drain trench. Use electron beam evaporation to sequentially plate Ti, Al, Ni and Au with thicknesses of 20 nm, 130 nm, 50 nm and 150 nm, and then anneal at 890℃ for 30s in a nitrogen environment to form metal contacts of the source electrode and the drain electrode.

[0017] The beneficial effects of the present application are:

[0018] A GaN high electron mobility transistor structure based on double gates is proposed. The structure is designed as two split gate structures in the gate p-type cap layer region, and the split gates are separated by a dielectric layer. Two field plates with different heights and widths are grown on the double gates. The Sentaurus TCAD simulation results show that under the same gate voltage, the electric field of the right gate can be adjusted by the left gate, making the electric field more uniform, and the defect impact is also reduced to some extent, improving the gate leakage. The same gate relies on the drain measurement electric field to obtain double-layer field plate modulation, so that the device maintains a relatively consistent breakdown voltage under a higher source-drain current. Under the structure of double gates, the left gate has a small band change, reducing the hole escape and electron capture of the pgan structure, thereby improving the dynamic threshold and other problems of the device. BRIEF DESCRIPTION OF DRAWINGS

[0019] Figure 1 is a schematic diagram of a traditional GaN high electron mobility transistor structure;

[0020] Figure 2 is a schematic diagram of a GaN high electron mobility transistor structure proposed by the present application;

[0021] Figure 3 is a schematic diagram of depositing a first dielectric layer in an embodiment;

[0022] Figure 4 is a schematic diagram of etching a right gate recess in an embodiment;

[0023] Figure 5 is a schematic diagram of depositing a right p-type cap in an embodiment;

[0024] Figure 6 is a schematic diagram of preparing a right gate structure in an embodiment;

[0025] Figure 7 is a schematic diagram of preparing a left gate structure in an embodiment;

[0026] Figure 8 is a curve graph of gate leakage of different transistors varying with gate forward voltage bias in an embodiment.

[0027] Figure 9 is a curve graph of threshold drift of different transistors varying with gate bias in an embodiment.

[0028] Wherein, the substrate 101, the nucleation layer 102, the buffer layer 103, the channel layer 104, the barrier layer 105, the dielectric layer 106, the first dielectric layer 106a, the second dielectric layer 106b, the 2DEG region 107, the p-type cap layer 108, the left p-type cap layer 108a, the right p-type cap layer 108b, the source metal 109, the drain metal 110, the gate metal 111, the left gate metal 111a, the right gate metal 111b, the field plate 112, the left field plate 112a, and the right field plate 112b. DETAILED DESCRIPTION

[0029] In order to make the purpose, technical scheme and advantages of the present application more clear, the present application is specifically described below in combination with the drawings.

[0030] Figure 1 is a traditional GaN high electron mobility transistor structure, from bottom to top including a substrate 101, a nucleation layer 102, a buffer layer 103, a channel layer 104, a barrier layer 105, and a dielectric layer 106. The thickness of the nucleation layer 102 is 0.05 µm; the thickness of the buffer layer 103 is 2 µm, the channel layer 104 is non-intentionally doped GaN with a thickness of 0.2 µm; the barrier layer 105 is non-intentionally doped Al 0.23 Ga 0.77 N with a thickness of 0.015 µm.

[0031] The two sides of the medium layer 106 are provided with source trenches and drain trenches, the source trenches and the drain trenches pass through the medium layer 106, the barrier layer 105 and the upper surface of the channel layer 104, the source trenches are provided with source metals 109, and the drain trenches are provided with drain metals 110. The etching width of the source trenches and the drain trenches is 0.5 µm, and the depth is 0.45 µm. The source trenches and the drain trenches are provided with gate structures. The interval distance between the source trenches and the gate structures is 1 µm, and the interval distance between the gate structures and the drain trenches is 10 µm.

[0032] Figure 2 The GaN high electron mobility transistor structure based on the double-gate provided in the application divides the medium layer 106 into a second medium layer 106b and a first medium layer 106a. The gate structure is divided into a left gate structure close to the source trench and a right gate structure close to the drain trench, and the left and right gate structures are isolated by a dielectric. The right gate structure is from bottom to top a right p-type cap layer 108b and a right gate metal 111b, the right gate metal 111b is higher than the first medium layer 106a, and a right gate field plate 112a is located on the upper surface of the first medium layer 106a and extends from the side of the right gate metal 111b to the direction of the drain trench. The left gate structure is from bottom to top a left p-type cap layer 108a, a left gate metal 111a and a left gate field plate 112b, the left gate field plate 112b is located above the right gate structure, the upper surface is higher than the upper surface of the second medium layer 106b, and the right end of the left gate field plate 112b is located between the right gate field plate 112a and the drain trench in the second medium layer 106b.

[0033] The p-type cap layer is doped with Mg, the concentration is 2e19 cm-3, and is directly in contact with the gate metal, the left and right gate cap layers 108a and 108b are controlled by the same potential, and the cross sections are isolated by a dielectric layer 106 with a width of 0.2 µm. The width of the left and right p-type cap layers is 0.6 µm, and the thickness is 110 nm.

[0034] The height of the left gate field plate is 0.4 µm, the length is 4 µm, and a groove structure with a height of 0.2 µm and a width of 1.9 µm is arranged at one end close to the drain trench. The height of the right gate field plate is 0.2 µm, and the length is 1.8 µm.

[0035] The preparation method of the GaN high electron mobility transistor based on the double-gate, specifically includes the following steps:

[0036] Step 1, preparing a silicon substrate region of a power semiconductor device, adding C impurities in the silicon substrate region by metal organic chemical vapor deposition (MOCVD), and sequentially epitaxially growing an AlN nucleation layer and an AlGaN buffer layer. An epitaxially grown unintentionally doped GaN channel layer and an unintentionally doped AlGaN barrier layer are sequentially grown on the AlGaN buffer layer by metal organic chemical vapor deposition. A first dielectric layer is deposited on the AlGaN barrier layer by plasma enhanced chemical vapor deposition (PECVD), as shown in Figure 3 .

[0037] Step 2, after opening a right gate window by inductively coupled plasma (ICP) etching the first dielectric layer, a digital etching process using low-damage HCL immersion is used for continuous etching until the AlGaN barrier layer is exposed, to obtain a right gate recess, as shown in Figure 4 .

[0038] Step 3, a right p-type cap layer is epitaxially grown on the right gate recess by metal organic chemical vapor deposition using Mg as a P-type dopant, as shown in Figure 5 . Ni / Au is deposited above the right p-type cap layer by low pressure chemical vapor deposition (LPCVD) to a height above the first dielectric layer to form a right gate metal.

[0039] Step 4, aluminum metal is deposited on the first dielectric layer to the right of the right gate metal to obtain a right gate field plate, as shown in Figure 6 .

[0040] Step 5, a 0.2µm second dielectric layer is deposited on the first dielectric layer by plasma enhanced chemical vapor deposition (PECVD). The left gate recess is etched and the left p-type cap layer, left gate metal and left gate field plate are sequentially deposited by repeating the above steps 2-4, as shown in Figure 7 .

[0041] Step 6, a digital etching process using low-damage HCL immersion is used on both sides of the second dielectric layer until the GaN channel layer is exposed, and the etching is continued to 0.05µm below the upper surface of the channel layer to obtain a source trench and a drain trench. Ti, Al, Ni and Au with thicknesses of 20 nm, 130 nm, 50 nm and 150 nm are sequentially plated by electron beam evaporation, and then annealed at 890℃ for 30s in a nitrogen environment to form metal contacts of the source electrode and the drain electrode, to obtain a GaN high electron mobility transistor structure as shown in Figure 2 .

[0042] The performance of the two transistor structures shown in Figure 1 and Figure 2 is compared by Sentaurus TCAD simulation verification, and the results are as followsFigure 8 , 9 As shown.

[0043] When the source-drain voltage bias is 0V, a positive gate voltage bias is applied to the gate. Figure 2 The transistor structure shown has its electric field inside the p-type cap layer mitigated, allowing it to withstand higher voltages. Compared to Figure 1 The conventional transistor structure shown has a breakdown voltage of 8.6V, while the novel structure proposed in this application achieves a gate breakdown voltage of 11.4V, an improvement of approximately 32%. When the device is placed under a source-drain bias of 10V, under different gate stress times, compared to the conventional transistor structure, the transistor structure proposed in this application shows an overall reduction in threshold drift of 0.1V~0.3V under stress time, and the gate-drain electric field is significantly reduced, resulting in a lower frequency of electron scattering. The intensity of defect trapping increases with time, leading to a decrease in the electron concentration below the gate, thus causing a positive threshold drift in the initial stage. Electrons at the metal-p-type cap layer interface are gradually depleted, while those at the barrier layer and p-type cap layer interface gradually increase. Hole depletion at the metal interface enters the barrier layer, causing a decrease in energy level, which in turn leads to a negative threshold drift. Both factors work together to influence the threshold drift.

[0044] Placed under different source-drain voltage biases (V) DSQ When a device with voltages of 10V / 20V / 50V is subjected to gate bias, the dual-gate dual-field plate structure proposed in this application can effectively reduce the threshold drift problem. DSQ The improvement effect is optimal at 20V. In the off state with a high drain voltage, the gate metal / p-type cap Schottky junction is slightly forward biased, causing the gate-drain capacitance to charge and some holes to escape from the p-type cap, resulting in hole loss. Higher V... DSQ This leads to more holes flowing out of the gate stack, causing the gate stack to carry more negative charges. The gate's leakage electric field exacerbates the defect mechanism, thereby changing its threshold and affecting stability.

[0045] Obviously, those skilled in the art can make various modifications and variations to this invention without departing from its spirit and scope. It should be noted that the above descriptions are merely specific embodiments of this invention and do not limit the invention. Any modifications and optimizations made within the spirit and principles of this invention should be covered by the claims of this invention.

Claims

1. A method for fabricating a double-gate based GaN high electron mobility transistor, characterized in that: Specifically comprising the following steps: Step 1, preparing a silicon substrate region of a power semiconductor device, adding C impurities in the silicon substrate region by metal organic chemical vapor deposition, and epitaxially growing an AlN nucleation layer and an AlGaN buffer layer in sequence; epitaxially growing a non-intentionally doped GaN channel layer and a non-intentionally doped AlGaN barrier layer on the AlGaN buffer layer by metal organic chemical vapor deposition; and depositing a first dielectric layer on the AlGaN barrier layer by plasma-enhanced chemical vapor deposition; Step 2, after opening a right gate window by inductively coupled plasma etching the first dielectric layer, continuing etching by using a digital etching process of low-damage HCL immersion until the AlGaN barrier layer is exposed to obtain a right gate recess; Step 3, epitaxially growing a right p-type cap layer on the right gate recess by metal organic chemical vapor deposition using Mg as a P-type dopant; and depositing Ni / Au above the right p-type cap layer by low-pressure chemical vapor deposition to be higher than the first dielectric layer to form a right gate metal; Step 4, depositing aluminum metal on the first dielectric layer to the right of the right gate metal to obtain a right gate field plate; the right gate field plate is in direct contact with the right sidewall of the right gate metal; Step 5, depositing a 0.2µm second dielectric layer on the first dielectric layer by plasma-enhanced chemical vapor deposition; etching a left gate recess by repeating the above steps 2-4, the left gate recess being isolated from the right gate recess by the first dielectric layer and the second dielectric layer, and the left gate recess exposing the AlGaN barrier layer, and sequentially depositing a left p-type cap layer, a left gate metal and a left gate field plate; the left gate metal being higher than the second dielectric layer; the left gate field plate being on the second dielectric layer to the right of the left gate metal and being in direct contact with the right sidewall of the left gate metal; Step 6, using a digital etching process of low-damage HCL immersion on both sides of the second dielectric layer until the GaN channel layer is exposed, and continuing etching to 0.05µm below the upper surface of the channel layer to obtain a source trench and a drain trench; the source trench being to the left of the left gate recess, and the drain trench being to the right of the right gate recess; the right end of the left gate field plate being located between the right gate field plate and the drain trench in the second dielectric layer; and sequentially depositing Ti, Al, Ni and Au with thicknesses of 20 nm, 130 nm, 50 nm and 150 nm by electron beam evaporation, and then annealing at 890℃ for 30s in a nitrogen environment to form metal contacts of a source electrode and a drain electrode.

2. A double-gate based GaN high electron mobility transistor structure, comprising from bottom to top a substrate, a nucleation layer, a buffer layer, a channel layer, a barrier layer and a dielectric layer, two sides of the dielectric layer being respectively provided with a source trench and a drain trench, the source trench and the drain trench penetrating through the dielectric layer, the barrier layer and being in contact with the upper surface of the channel layer; a source metal being arranged in the source trench, and a drain metal being arranged in the drain trench; a gate structure being arranged in the dielectric layer at a position between the source trench and the drain trench; characterized in that: Prepared by the method of claim 1; The dielectric layer is divided into a second dielectric layer and a first dielectric layer stacked in sequence; The gate structure comprises a left gate structure close to the source trench and a right gate structure close to the drain trench, and the left and right gate structures are isolated by a dielectric; The dielectric layer is divided into a second dielectric layer and a first dielectric layer stacked in sequence; The right gate structure is from bottom to top a right p-type cap layer and a right gate metal, the right gate metal is higher than the first dielectric layer, and the right gate field plate is located on the upper surface of the first dielectric layer and extends from the side of the right gate metal to the direction of the drain trench; the left gate structure is from bottom to top a left p-type cap layer, a left gate metal and a left gate field plate, the left gate field plate is located above the right gate structure, the upper surface is higher than the upper surface of the second dielectric layer, and the right end of the left gate field plate is located between the right gate field plate and the drain trench in the second dielectric layer.

3. The dual-gate based GaN high electron mobility transistor structure of claim 2, wherein: The left p-type cap layer and the right p-type cap layer are in direct contact with the left gate metal and the right gate metal respectively; the left gate metal and the right gate metal are both Schottky contacts, the width of the left p-type cap layer and the right p-type cap layer is 0.6 µm, the thickness is 110 nm, the interval between the left p-type cap layer and the right p-type cap layer is 0.2 µm, the p-type cap layer is doped with Mg, and the concentration is 2e19 cm-3.

4. The dual-gate based GaN high electron mobility transistor structure of claim 2, wherein: The height of the left gate field plate is 0.4 µm, the length is 4 µm, and a groove structure with a height of 0.2 µm and a width of 1.9 µm is arranged at one end close to the drain trench; the height of the right gate field plate is 0.2 µm, and the length is 1.8 µm.

5. The dual-gate based GaN high electron mobility transistor structure of claim 2, wherein: The nucleation layer is AlN, 0.05 pm thick; the buffer layer is Al 0.05 Ga 0.95 N, 2 pm thick, 1e14 cm-3 doped; the channel layer is unintentionally doped GaN, 0.2 pm thick; the barrier layer is unintentionally doped Al 0.23 Ga 0.77 N, 0.015 pm thick.

6. The dual-gate based GaN high electron mobility transistor structure of claim 2, wherein: The etching width of the source trench and the drain trench is 0.5 µm, and the depth is 0.45 µm.

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