Semiconductor device and method of manufacturing the same

Abstract

The invention provides a semiconductor device and a manufacturing method thereof. A semiconductor device includes: a drain layer formed of a first conductive type semiconductor; a drift layer formed of a first conductivity type semiconductor on one surface of the drain layer; a pillar structure on the drift layer, the pillar structure being formed by alternately arranging a plurality of first conductive type pillars and a plurality of second conductive type pillars; a Schottky barrier diode formed on an upper portion of the second conductive type pillar; and a body layer formed on the Schottky barrier diode and formed of a second conductivity type semiconductor, the second conductivity type body layer being formed on the Schottky barrier diode; the second conductive column has a super junction structure, and has a plurality of saw-toothed outer portions when viewed from a cross section.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and more particularly to semiconductor devices and methods for manufacturing the same. Background Art

[0002] Patent document 1 (Japanese Patent Publication No. 2013-102087) discloses a semiconductor device having a super junction structure. In the semiconductor device, a trench is formed by etching on a first conductive type semiconductor. On the trench, a second conductive type layer is formed by epitaxial growth, resulting in a super junction structure.

[0003] However, in the semiconductor device described in Patent Document 1, when the second conductivity type layer is formed on the trench by epitaxial growth, the opening of the trench is easily blocked. Therefore, a void is easily left inside the trench, resulting in the Schottky barrier diode with the super structure being unable to obtain stable performance. Summary of the invention

[0004] The present disclosure is made to solve the above-mentioned problems, and an object of the present disclosure is to provide a semiconductor device and a method for manufacturing the same.

[0005] In a first aspect, an embodiment of the present disclosure provides a semiconductor device, including:

[0006] a drain layer, wherein the drain layer is formed of a first conductive type semiconductor;

[0007] a drift layer, the drift layer being formed on one side of the drain layer and being made of a first conductive type semiconductor;

[0008] A column structure, wherein the column structure is formed on the drift layer by alternatingly arranging a plurality of first conductive type columns and a plurality of second conductive type columns;

[0009] a Schottky barrier diode formed on an upper portion of the second conductive type column; and

[0010] a main body layer, the main body layer is formed on the Schottky barrier diode and is formed of a second conductive type semiconductor, and the second conductive type main body layer is formed on the Schottky barrier diode;

[0011] The second conductive type column has a super junction structure and has a multi-stage sawtooth outer portion when viewed from a cross section.

[0012] In some of these embodiments,

[0013] The second conductive column comprises:

[0014] a second conductivity type impurity layer; and

[0015] A filling layer is formed inside the impurity layer.

[0016] In some of the embodiments, the filling layer is formed of an insulator or a semiconductor.

[0017] In some embodiments, the impurity concentration of the impurity layer is 1.0×10 17 cm -3 Above and 1.0×10 20 cm -3 the following.

[0018] In some of the embodiments, the first conductive type pillar is formed of first conductive type silicon carbide;

[0019] The impurity layer is formed of second conductivity type silicon carbide.

[0020] In a second aspect, a method for manufacturing a semiconductor device is provided in this embodiment, comprising:

[0021] A first step of forming a drift layer, forming a first conductivity type drift layer by epitaxial growth on a drain layer formed of a first conductivity type semiconductor;

[0022] A second step is to create a body layer, a source layer and a body contact layer in the drift layer, and form a channel region surrounded by the body layer, the source layer and the body contact layer;

[0023] A third step is to form a region for forming a Schottky barrier diode; and

[0024] The fourth step is to form a region for forming a super junction structure;

[0025] in,

[0026] The third step is a step of forming a concave portion, including: a step of performing ion implantation using a mask, the mask forming a hole only inside the channel region; and a step of etching a portion of the ion implantation region using the mask as it is;

[0027] The fourth step is a step of forming a recess, including: a step of performing ion implantation using the mask as it is; and a step of etching a portion of the ion implantation region, wherein the ion implantation step and the etching step are repeated at least twice.

[0028] In some embodiments, the ion implantation process in the second process includes a corner ion implantation process.

[0029] In some of the embodiments, when the ion implantation process in the second process, the third process or the fourth process is observed from a top view, the area of ​​the region where the ion implanted impurities exist is larger than the area of ​​the hole on the mask.

[0030] In some embodiments, the process includes filling the concave portion formed in the fourth process with a semiconductor material or an insulating material; and filling the concave portions formed in the second process and the third process with a metal material.

[0031] According to the present disclosure, a semiconductor device having a super junction structure and a Schottky barrier diode can obtain stable performance.

[0032] The details of one or more embodiments of the present disclosure are set forth in the following drawings and description to make other features, objects, and advantages of the present application more readily apparent. BRIEF DESCRIPTION OF THE DRAWINGS

[0033] The drawings described herein are used to provide further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute improper limitations on the present application.

[0034] Figure 1 is a cross-sectional view of the semiconductor device in Embodiment 1;

[0035] Figure 2 is a cross-sectional view for explaining the method for manufacturing the semiconductor device in the first embodiment;

[0036] Figure 3 is a cross-sectional view for explaining the method for manufacturing the semiconductor device in the first embodiment;

[0037] Figure 4 is a cross-sectional view for explaining the method for manufacturing the semiconductor device in the first embodiment;

[0038] Figure 5 is a schematic diagram for explaining a method for forming a second conductivity type impurity layer of the semiconductor device in Embodiment 1;

[0039] Figure 6 This is a cross-sectional view of a semiconductor device in accordance with the second embodiment.

[0040] In the figure: 1. semiconductor device, 2. drain layer, 3. drift layer, 4. main layer, 5. source layer, 6. main contact layer, 7. gate insulating layer, 8. gate electrode layer, 9. interlayer insulating layer, 10. source electrode layer, 11. wiring electrode layer, 12. drain electrode layer, 13. impurity layer, 14. filling layer (silicon dioxide layer), 15. silicon dioxide layer. DETAILED DESCRIPTION

[0041] In order to more clearly understand the purpose, technical solutions and advantages of the present application, the present application is described and illustrated below in conjunction with the accompanying drawings and embodiments.

[0042] Unless otherwise defined, the technical terms or scientific terms involved in this application shall have the general meaning understood by people with ordinary skills in the technical field to which this application belongs. The words "one", "a", "a", "the", "these" and the like in this application do not represent quantitative restrictions, and they can be singular or plural. The terms "include", "comprise", "have" and any variants thereof involved in this application are intended to cover non-exclusive inclusions; for example, a process, method and system, product or device comprising a series of steps or modules (units) is not limited to the listed steps or modules (units), but may include unlisted steps or modules (units), or may include other steps or modules (units) inherent to these processes, methods, products or devices. The words "connect", "connected", "coupled" and the like involved in this application are not limited to physical or mechanical connections, but may include electrical connections, whether directly or indirectly. The "multiple" involved in this application refers to two or more. "And / or" describes the association relationship of associated objects, indicating that there can be three relationships. For example, "A and / or B" can mean: A exists alone, A and B exist at the same time, and B exists alone. Usually, the character " / " indicates that the objects associated with each other are in an "or" relationship. The terms "first", "second", "third", etc. involved in this application are only used to distinguish similar objects and do not represent a specific ordering of the objects.

[0043] Implementation 1:

[0044] Figure 1 It is a cross-sectional view of the semiconductor device 1 in the first embodiment.

[0045] exist Figure 1 In the figure, the semiconductor device 1 is a silicon carbide planar MOSFET including a Schottky barrier diode having a super junction structure. The semiconductor device 1 includes a drain layer 2, a drift layer 3, a plurality of body layers 4, a plurality of source layers 5, a plurality of body contact layers 6, a plurality of gate insulating layers 7, a plurality of gate electrode layers 8, a plurality of interlayer insulating layers 9, a plurality of source electrode layers 10, a wiring electrode layer 11, a drain electrode layer 12, a plurality of impurity layers 13, a plurality of filling layers 14, a Schottky barrier diode 18, and a Schottky electrode 19.

[0046] The drain layer 2 is formed of first conductive type silicon carbide. For example, the drain layer 2 is formed of n+ type 4H-SiC. For example, the drain layer 2 is formed with nitrogen as an impurity. The drift layer 3 is formed on the first surface ( Figure 1The drift layer 3 is formed of first conductive type silicon carbide, and its impurity concentration may be lower than that of the drain layer 2. For example, the drift layer 3 is an n-type layer. For example, the drift layer 3 is formed on the drain layer 2 by epitaxial growth.

[0047] A plurality of body layers 4 are formed on the drift layer 3. The plurality of body layers 4 are formed of second conductivity type silicon carbide. For example, the plurality of body layers 4 are p-type layers. For example, the plurality of body layers 4 are formed by ion implantation with aluminum as an impurity.

[0048] The plurality of source layers 5 are respectively formed on the plurality of body layers 4. The plurality of source layers 5 are formed of first conductive type silicon carbide, and the impurity concentration thereof is higher than that of the drift layer 3. For example, the plurality of source layers 5 are n+ type layers. For example, the plurality of source layers 5 are formed by ion implantation with nitrogen as an impurity.

[0049] A plurality of body contact layers 6 are respectively formed on the plurality of body layers 4. In each body layer 4, the body contact layer 6 is surrounded by the source layer 5. The plurality of body contact layers 6 are formed of second conductivity type silicon carbide, and the impurity concentration thereof is higher than that of the plurality of body layers 4. For example, the plurality of body contact layers 6 are p+ type layers. For example, the plurality of body contact layers 6 are formed by ion implantation with aluminum as an impurity.

[0050] The plurality of gate insulating layers 7 are formed to contact the source layer 5 on each adjacent body layer 4. Specifically, the plurality of gate insulating layers 7 are formed to span the drift layer 3, the adjacent body layer 4, and each source layer 5 existing inside thereof. For example, the plurality of gate insulating layers 7 are formed by thermal oxidation.

[0051] The plurality of gate electrode layers 8 are respectively formed on the plurality of gate insulating layers 7. For example, the plurality of gate electrode layers 8 are formed of polysilicon by a CVD method.

[0052] The plurality of interlayer insulating layers 9 are formed so as to respectively cover the plurality of gate electrode layers 8. For example, the plurality of interlayer insulating layers 9 are formed by a CVD method.

[0053] The plurality of source electrode layers 10 are formed corresponding to the plurality of body layers 4. The source electrode layer 10 is formed to be in contact with the source layer 5. The source electrode layer 10 may be formed to straddle the body contact layer 6. For example, the plurality of source electrode layers 10 are formed by forming Ni, Ti or the like by sputtering and then performing heat treatment.

[0054] The wiring electrode layer 11 is formed so as to cover the plurality of source electrode layers 10. For example, the wiring electrode layer 11 is formed by a sputtering method using an aluminum alloy or the like.

[0055] The drain electrode layer 12 is formed on the second surface of the drain layer 2 ( Figure 1 For example, the drain electrode layer 12 is formed by forming a film of Ni or the like by sputtering and performing heat treatment.

[0056] The Schottky electrode 19 is formed in a recessed portion that penetrates the body contact layer 6 and the source electrode layer 10 and reaches the drift layer 3. A Schottky barrier diode 18 is formed on a surface where the Schottky electrode 19 contacts the drift layer 3. For example, the Schottky barrier diode 18 and the Schottky electrode 19 are formed by sputtering using aluminum alloy or the like.

[0057] In this embodiment, the column structure C is formed on the drift layer 3. In the column structure C, a plurality of first conductive type columns C1 and a plurality of second conductive type columns C2 are alternately arranged, thereby forming a super junction structure. The plurality of first conductive type columns C1 are part of the layer formed as the drift layer 3. The plurality of second conductive type columns C2 are formed separately from the layer formed as the drift layer 3.

[0058] A plurality of second conductive type columns C2 are respectively formed below the Schottky barrier diode 18. A portion of the Schottky electrode at the upper portion of each second conductive type column C2 is surrounded by the main layer 4, the source layer 5 and the main contact layer 6. The plurality of second conductive type columns C2 each have a plurality of sawtooth-shaped outer portions when viewed from a cross section. Specifically, in the plurality of second conductive type columns C2, a plurality of first inclined portions A1 and a plurality of second inclined portions A2 are alternately arranged in the thickness direction of the drift layer 3. The first inclined portion A1 is formed to extend from one side of the drain layer 2 ( Figure 1 the upper surface in the middle) to the other side ( Figure 1 The second inclined portion A2 is formed so as to narrow in the lateral direction when moving from one side of the drain layer 2 to the other side. At this time, the narrowing degree when forming the second inclined portion A2 is greater than the expansion degree of the first inclined portion A1.

[0059] More specifically, each second conductive column C2 includes an impurity layer 13 and a filling layer 14. The impurity layer 13 forms the outer portion of the second conductive column C2. The impurity layer 13 is formed of second conductive silicon carbide. The impurity layer 13 is a p-type layer. For example, the impurity layer 13 is formed by ion implantation using aluminum as an impurity. The impurity concentration of the impurity layer 13 is greater than 1.0×1017cm-3 and less than 1.0×1020cm-3. The filling layer 14 is formed inside the impurity layer 13. The filling layer 14 is formed of an insulator or a semiconductor. For example, the filling layer 14 is formed of silicon dioxide.

[0060] Thus, in this embodiment, in the drift layer 3, a plurality of first conductive type columns C1 and a plurality of second conductive type columns C2 are arranged alternately to form a vertical groove structure. In this case, if a voltage is applied, the depletion layer will diffuse in the lateral direction. As a result, a depletion layer with a groove depth is formed. At this time, the depletion layer only extends to half of the groove interval, thereby forming a depletion layer with a thickness equivalent to the groove depth. In this way, the diffusion of the depletion layer can be small, and the impurity concentration of the drift layer 3 can be increased by about 5 times compared with the non-super junction structure. Therefore, the on-resistance ON becomes smaller.

[0061] In addition, in this principle, the interval between the trenches is preferably as narrow and deep as possible. In this principle, the withstand voltage is ensured by a mechanism different from that of conventional MOSFETs. As a result, performance that exceeds the so-called silicon limit and silicon carbide limit can be achieved.

[0062] Next, a method for manufacturing the semiconductor device 1 will be described.

[0063] First, three ion implantation processes are performed on the drift layer 3 epitaxially formed on the drain layer. In each of the three ion implantations, a resist pattern is first formed. Then, ion implantation is performed. Then, the resist pattern is removed. As a result, a p-type ion implantation portion, an n+ type ion implantation portion, and a p+ type ion implantation portion are formed. The p-type ion implantation portion is the main body layer 4. The n+ type ion implantation portion is the source layer 5. The p+ type ion implantation portion is the main body contact layer 6.

[0064] Next, use Figures 2 to 4 , a method for manufacturing the Schottky barrier diode 18 having a super junction structure in the semiconductor device 1 is described. Figures 2 to 4 is a cross-sectional view for explaining the method for manufacturing the semiconductor device 1 in the first embodiment. Figures 2 to 4 In the figure, the main body layer 4, the source layer 5, the main body contact layer 6, etc. are omitted.

[0065] like Figure 2 As shown in (a), a mask pattern forming step is performed. In the mask pattern forming step, a silicon dioxide layer 15 is first formed on the entire surface. Then, a resist pattern is formed, and dry etching is performed. Then, the resist pattern is removed. As a result, a mask pattern of the silicon dioxide layer 15 is formed.

[0066] Then, if Figure 2 As shown in (b), a shallow and wide second conductive type impurity layer 13 is formed by corner ion implantation DI. In the ion implantation process, impurities such as aluminum are ion implanted at positions corresponding to the openings of the silicon dioxide layer 15. At this time, the ion implantation is performed in such a manner that a portion of the impurity region is diffused outward from the opening of the mask pattern when viewed from above.

[0067] Then, if Figure 2 As shown in (c), a second conductive type impurity layer 13 with a width smaller than that of the angular ion implantation DI is formed by vertical ion implantation VI. At this time, the vertical ion implantation VI is also performed in such a way that, when viewed from above, a portion of the impurity region diffuses outward relative to the opening of the mask pattern. In addition, the vertical ion implantation VI here should also include ion implantation with an angle of less than 8 degrees to the vertical direction to prevent the problem of ion penetration being deeper than expected.

[0068] Then, if Figure 2 As shown in (d), a portion of the impurity layer 13 is etched without removing the mask pattern of the silicon dioxide layer 15. In the etching step, a portion of the impurity layer 13 is etched at a position corresponding to the opening of the silicon dioxide layer 15. At this time, the silicon dioxide layer 15 is also thinned.

[0069] Then, if Figure 2 As shown in (e), a second conductive type impurity layer 13 is formed by vertical ion implantation VI. At this time, in the ion implantation process, impurities such as aluminum are further ion implanted at positions corresponding to the openings of the silicon dioxide layer 15. At this time, the ion implantation is performed in such a manner that a portion of the impurity region diffuses outward from the opening of the mask pattern when viewed from above. As a result, an impurity layer 13 is further formed.

[0070] Then, if Figure 3 As shown in (f), a portion of the impurity layer 13 is etched without removing the mask pattern of the silicon dioxide layer 15. In the etching step, a portion of the impurity layer 13 is etched at a position corresponding to the opening of the silicon dioxide layer 15. At this time, the silicon dioxide layer 15 is also thinned. Figure 2 (e) and Figure 3 The two steps of (f) can be repeated.

[0071] Then, if Figure 3 As shown in (g), without removing the mask pattern of the silicon dioxide layer 15, a part of the impurity layer 13 and a part of the drift layer 3 are etched. In this etching process, the region where the Schottky barrier diode 18 is to be formed is formed as a recessed portion. At this time, the silicon dioxide layer 15 is also thinned.

[0072] Then, if Figure 3 As shown in (h), a second conductive type impurity layer 13 is formed by vertical ion implantation VI. At this time, in the ion implantation process, impurities such as aluminum are further ion implanted at the position corresponding to the opening of the silicon dioxide layer 15. At this time, the ion implantation is performed in such a manner that a part of the impurity region is diffused outward from the opening of the mask pattern when viewed from above. As a result, an impurity layer 13 is further formed.

[0073] Then, if Figure 3 As shown in (i), a portion of the impurity layer 13 is etched without removing the mask pattern of the silicon dioxide layer 15. In the etching step, a portion of the impurity layer 13 is etched at a position corresponding to the opening of the silicon dioxide layer 15. At this time, the silicon dioxide layer 15 is also thinned.

[0074] Then, if Figure 3 As shown in (j), a second conductive type impurity layer 13 is formed by vertical ion implantation VI. At this time, in the ion implantation process, impurities such as aluminum are further ion implanted at positions corresponding to the openings of the silicon dioxide layer 15. At this time, the ion implantation is performed in such a manner that a portion of the impurity region diffuses outward from the opening of the mask pattern when viewed from above. As a result, an impurity layer 13 is further formed.

[0075] Then, if Figure 4 As shown in (k), a portion of the impurity layer 13 is etched without removing the mask pattern of the silicon dioxide layer 15. In the etching step, a portion of the impurity layer 13 is etched at a position corresponding to the opening of the silicon dioxide layer 15. At this time, the silicon dioxide layer 15 is also thinned.

[0076] Then, if Figure 4 (l) as shown, repeat Figure 3 (j) and Figure 4 (k) is described in the process. Through this process, an impurity layer 13 having a super junction structure is formed. This repetitive process can be repeated multiple times to obtain the column length required to achieve the desired super junction structure characteristics. In other words, multiple ion implantation processes and etching processes are alternately performed as the second conductive type column forming process. As a result, a multi-stage sawtooth impurity layer 13 is formed.

[0077] Then, if Figure 4 As shown in (m), a mask pattern removal step is performed. In the mask pattern removal step, the silicon dioxide layer 15 is removed.

[0078] Next, a heat treatment process is performed to Figure 4 The impurity layer 13 formed by the ion implantation step (m) is activated. The impurity layer 13 can be activated by, for example, heat treatment at 1400 to 1600 degrees Celsius. In addition, a protective film such as a carbon coating can also be used.

[0079] Then, a gate insulating layer forming process is performed. In the gate insulating layer forming process, after necessary pretreatment, the surface of silicon carbide is thermally oxidized into a silicon dioxide film, and further necessary post-treatment is performed. The gate insulating layer forming process is performed, for example, in an environment of 1000 to 1200 degrees Celsius. Then, a resist pattern is formed. Then, the gate insulating film is etched. Then, the resist pattern is removed. As a result, a gate insulating layer 7 is formed.

[0080] Then, if Figure 4 As shown in (n), a filling step is performed. In the filling step, a silicon dioxide layer 14 is formed. The silicon dioxide layer 14 also fills the groove formed by the etching step.

[0081] Then, if Figure 4 As shown in (o), an etch-back process is performed. In the etch-back process, the silicon dioxide layer 14 located above the region where the Schottky barrier diode 18 is to be formed is removed. As a result, the filling layer 14 is formed.

[0082] Then, if Figure 4 As shown in (p), a metal filling step is performed. In this step, aluminum can be filled, for example. Thus, the Schottky barrier diode 18 and the Schottky electrode 19 are formed.

[0083] Then, a gate electrode layer forming process is performed. In the gate electrode layer forming process, a polysilicon film is formed. Then, a resist pattern is formed. Then, the polysilicon film is etched. Then, the resist pattern is removed. As a result, a gate electrode layer 8 is formed. Then, a source electrode layer forming process is performed. In the source electrode layer forming process, a metal film is formed. Then, a resist pattern is formed. Then, the metal film is etched. Then, the resist pattern is removed. Then, metal sintering is performed. As a result, a source electrode layer 10 is formed. In addition, after the source electrode layer 10 is formed, the above-mentioned Schottky electrode 19 can also be formed.

[0084] Then, an interlayer insulating layer forming step is performed. In the interlayer insulating layer forming step, an interlayer insulating layer 9 is formed. Then, a wiring electrode layer forming step is performed. In the wiring electrode layer forming step, a wiring electrode layer 11 is formed. Then, a drain electrode layer forming step is performed. In the drain electrode layer forming step, a metal film is formed. Then, laser annealing is performed. As a result, a drain electrode layer 12 is formed.

[0085] Next, use Figure 5 , a method for forming the second conductive type impurity layer 13 is described.

[0086] Figure 5 This is a schematic diagram for explaining a method for forming a second conductivity type impurity layer in the semiconductor device in the first embodiment.

[0087] Figure 5 FIG. 2 shows an overview of implanting aluminum as impurity ions into the drift layer 3 of silicon carbide. Figure 5 As shown in FIG. 1 , in each ion implantation process, the impurities diffuse radially. The depth of the ion implantation is, for example, about 0.7 μm. In addition, the lateral diffusion of the ion implantation is, for example, about 0.2 μm. Figure 5Not shown, the above ion implantation is repeated by changing the depth, so that in the plurality of second conductive type columns C2, the outer portion of each second conductive type column C2 is formed such that a plurality of first inclined portions A1 and a plurality of second inclined portions A2 are alternately arranged along the thickness direction of the drift layer 3.

[0088] According to the embodiment 1 described above, the plurality of second conductive type columns C2 have multiple serrated outer portions when observed from a cross section. Specifically, the second conductive type columns C2 are formed by an impurity layer 13 and a filling layer 14. Therefore, no voids are generated. As a result, a semiconductor device 1 having a Schottky barrier diode having a super junction structure that can obtain stable performance can be provided. In addition, a semiconductor device 1 having a Schottky barrier diode having a super junction structure that can obtain stable performance can be easily manufactured.

[0089] Furthermore, in the cross-sectional view of the plurality of second conductivity type columns C2, the impurity layer 13 above the body layer 4 may be omitted. In this case, the semiconductor device 1 with stable performance can be manufactured at a lower price.

[0090] In addition, the filling layer 14 is formed of an insulator or a semiconductor. Therefore, the semiconductor device 1 with stable performance can be manufactured more easily.

[0091] In addition, the impurity concentration of the impurity layer 13 is not less than 1.0×10 17 cm −3 and not more than 1.0×10 20 cm −3 . Therefore, stable performance can be obtained more reliably.

[0092] In addition, the first conductive type pillar C1 is formed of the first conductive type silicon carbide, and the impurity layer 13 is formed of the second conductive type silicon carbide. Therefore, in the silicon carbide semiconductor device 1, stable performance can be obtained.

[0093] In addition, a plurality of second conductivity type pillars C2 are formed in the drift layer 3 so that the cross section has a multi-stage sawtooth outer portion. Therefore, the semiconductor device 1 including the Schottky barrier diode having the super junction structure capable of obtaining stable performance can be easily manufactured.

[0094] In addition, the ion implantation process and the etching process are repeated, thereby forming a plurality of second conductive type columns C2 in such a way that the cross section presents a multi-stage sawtooth outer portion. At this time, in the ion implantation process, the impurity is implanted at a position corresponding to the opening of the mask pattern. In the etching process, the mask pattern is used as it is. In this way, there is no need to perform photolithography in each section, and there is no need to align the mask. Furthermore, since a heat-resistant silicon dioxide layer mask is used, ion implantation can be performed at a high temperature of about 500 degrees Celsius, and there will be no problem of ion implantation in deep areas with high aspect ratios. Therefore, the process is greatly simplified. As a result, a semiconductor device 1 having a Schottky barrier diode having a super junction structure that can obtain stable performance can be easily manufactured.

[0095] For example, when silicon carbide etching is performed by ICP-RIE in a SF6-02-Ar atmosphere, the selectivity ratio can reach 8. In this case, even if the silicon dioxide layer 15 is thinned during the etching process, the ion implantation process and the etching process can be repeated multiple times without changing the mask pattern. For example, when the film thickness of the silicon dioxide layer 15 is 3μm, if the thickness of the silicon dioxide layer used as an ion implantation mask is 1μm, a thinning of 2μm is allowed, so the etchable thickness of the silicon carbide layer reaches 16μm. This means that the etching depth can exceed the thickness (about 10μm) of the drift layer 3 of a silicon carbide semiconductor device without a super junction structure and a withstand voltage of about 1000V. In addition, when there is a super junction structure, the thickness of the drift layer 3 can be thinner than when there is no super junction structure. Therefore, the film thickness of the silicon dioxide layer 15 can be made less than 3μm, thereby making it easier to manufacture a semiconductor device 1 with stable performance.

[0096] In addition, in the ion implantation process, the ions are implanted in such a manner that a portion of the impurity region is diffused outward from the opening of the mask pattern in a plan view. Therefore, the semiconductor device 1 with stable performance can be easily manufactured.

[0097] Furthermore, after the ion implantation process and the etching process are repeated, the trench formed by the etching process is filled with an insulator or a semiconductor. Therefore, no void is generated. As a result, the semiconductor device 1 with stable performance can be easily manufactured.

[0098] Implementation 2:

[0099] Figure 6 2 is a cross-sectional view of a semiconductor device in Embodiment 2. In addition, the same reference numerals are used for the same or equivalent parts as those in Embodiment 1, and the description of such parts will be omitted.

[0100] like Figure 6As shown in FIG. 1 , the semiconductor device 1 is a trench MOSFET. A plurality of impurity layers 13 and a plurality of filling layers 14 are further added to the semiconductor device 1 .

[0101] According to the second embodiment described above, in the trench-type semiconductor device 1, the plurality of second conductive type columns C2 have multiple serrated outer portions when viewed from a cross section. Therefore, in the trench-type semiconductor device 1, a semiconductor device 1 having a Schottky barrier diode having a super junction structure that can achieve stable performance can also be obtained.

[0102] In addition, in Embodiment 1 or Embodiment 2, the first conductivity type may be p-type and the second conductivity type may be n-type. In this case, stable performance can also be obtained.

[0103] In addition, Embodiment 1 or Embodiment 2 can also be applied to a semiconductor device 1 containing silicon as a main component. In this case as well, stable performance can be obtained.

[0104] Although some aspects of at least one embodiment have been described above, it should be understood that various changes, modifications and improvements may be easily conceived by those skilled in the art. The changes, modifications and improvements involved are intended to become part of this disclosure and are intended to be within the scope of this disclosure.

[0105] It should be understood that the implementation of the method and apparatus described herein is not limited to the details of the structure and arrangement of the components described in the above description or illustrated in the accompanying drawings. The method and apparatus can be implemented in other embodiments and implemented or executed in various ways.

[0106] The specific embodiments are provided herein only by way of example and are not meant to be limiting.

[0107] The expressions and terms used in this disclosure are for illustrative purposes only and should not be considered as limiting. The use of "includes," "having," "having," "comprising," and variations thereof as used herein means the inclusion of the following listed items, their equivalents, and additional items.

[0108] Reference to "or" may be interpreted as one or more of any terms recited using "or", as well as interpretation of all terms.

[0109] References to front, back, left, right, top, bottom, up, down, horizontal, vertical, inside and outside are for convenience of description. Such references do not mean that the constituent elements of the present disclosure are limited to any particular position or spatial orientation. Therefore, the above description and drawings are only for illustration.

[0110] In addition, it is needless to say that the present disclosure is not limited to the embodiments described above, but includes all embodiments that can achieve the purpose of the present invention.

[0111] The term "embodiment" in this disclosure refers to specific features, structures, or characteristics described in conjunction with the embodiment that may be included in at least one embodiment of the present application. The appearance of this phrase in various locations in the specification does not necessarily mean the same embodiment, nor does it mean that it is mutually exclusive with other embodiments and is independent or optional. It is clearly or implicitly understood by those of ordinary skill in the art that the embodiments described in this application can be combined with other embodiments without conflict.

[0112] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of patent protection. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the scope of protection of the present application. Therefore, the scope of protection of the present application shall be subject to the attached claims.

Claims

1. A semiconductor device, characterized in that: include: a drain layer, wherein the drain layer is formed of a first conductive type semiconductor; a drift layer, the drift layer being formed on one side of the drain layer and being made of a first conductive type semiconductor; A column structure, wherein the column structure is formed on the drift layer by alternatingly arranging a plurality of first conductive type columns and a plurality of second conductive type columns; a Schottky barrier diode formed on an upper portion of the second conductive type column; and a main body layer, the main body layer is formed on the Schottky barrier diode and is formed of a second conductive type semiconductor, and the second conductive type main body layer is formed on the Schottky barrier diode; The second conductive type column has a super junction structure and has a multi-stage sawtooth outer portion when viewed from a cross section.

2. The semiconductor device according to claim 1, wherein: The second conductive column comprises: a second conductivity type impurity layer; and A filling layer is formed inside the impurity layer.

3. The semiconductor device according to claim 2, wherein: The filling layer is formed of an insulator or a semiconductor.

4. The semiconductor device according to claim 2 or 3, characterized in that The impurity concentration of the impurity layer is 1.0×10 17 cm -3 Above and 1.0×10 20 cm -3 the following.

5. The semiconductor device according to claim 2 or 3, characterized in that: The first conductive type column is formed of first conductive type silicon carbide; The impurity layer is formed of second conductivity type silicon carbide.

6. A method for manufacturing a semiconductor device, characterized in that: include: A first step of forming a drift layer, forming a first conductivity type drift layer by epitaxial growth on a drain layer formed of a first conductivity type semiconductor; A second step is to create a body layer, a source layer and a body contact layer in the drift layer, and form a channel region surrounded by the body layer, the source layer and the body contact layer; A third step is to form a region for forming a Schottky barrier diode; as well as The fourth step is to form a region for forming a super junction structure; in, The third step is a step of forming a concave portion, including: a step of performing ion implantation using a mask, the mask forming a hole only inside the channel region; and a step of etching a portion of the ion implantation region using the mask as it is; The fourth step is a step of forming a recess, including: a step of performing ion implantation using the mask as it is; and a step of etching a portion of the ion implantation region, wherein the ion implantation step and the etching step are repeated at least twice.

7. The method for manufacturing a semiconductor device according to claim 6, wherein: The ion implantation step in the second step includes a corner ion implantation step.

8. The method for manufacturing a semiconductor device according to claim 6, wherein: In the ion implantation step in the second step, the third step, or the fourth step, the area of ​​the region where the ion implanted impurities exist is larger than the area of ​​the hole in the mask when viewed from a plan view.

9. The method for manufacturing a semiconductor device according to claim 6, wherein: include: A step of filling the concave portion formed in the fourth step with a semiconductor material or an insulating material; and a step of filling a metal material into the recess formed in the second step and the third step.

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