Method for preparing a semiconductor device

Abstract

The present application discloses a method for preparing a semiconductor device, comprising: providing an epitaxial wafer, comprising a semiconductor substrate and an epitaxial layer located on the upper surface of the semiconductor substrate; forming a first mask layer having a first through hole on the upper surface of the epitaxial layer; forming an i+1th mask layer having an i+1th through hole on the surface of the i-th mask layer having the i-th through hole; etching the epitaxial layer based on the i+1th through hole to form an i-th level groove in the upper surface of the epitaxial layer, so as to sequentially form the first to M-level trenches of an M-level trench structure in the upper surface of the epitaxial layer; before forming the i-level trench, the i+1th mask layer covers the top of the i-th mask layer and covers the sidewalls and bottom of the i-th through hole; the apertures of the 1st to M+1th through holes are sequentially reduced; forming a self-aligned ion implantation window based on at least one of the 1st to M+1th mask layers, performing self-aligned ion implantation, and forming an ion implantation region in the surface of the M-level trench structure.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor device preparation, and in particular to a method for preparing a semiconductor device. Background Art

[0002] With the development of science and technology, planar semiconductor devices have reached a point where shrinking the device cell size has failed to reduce the on-resistance. The main reason is the limitation of the neck resistance of the JFET (Junction Field-Effect Transistor). Even with smaller lithography dimensions, it is difficult to reduce the on-resistance per unit area to 2mΩ·cm. 2 .

[0003] Compared with planar semiconductor devices, trench semiconductor devices can change the conductive channel from horizontal to vertical through the trench structure, eliminating the JFET neck resistance, greatly increasing the cell density, and improving the current handling capability of the semiconductor device.

[0004] Trench semiconductor devices require the fabrication of a multi-level trench structure to facilitate achieving a greater ion implantation depth within the epitaxial layer. Existing fabrication methods require removing the mask layer used to fabricate the multi-level trench structure and then fabricating a new mask layer for ion implantation within the multi-level trench structure. Summary of the Invention

[0005] In view of the above problems, the present application provides a method for preparing a semiconductor device, the specific scheme is as follows:

[0006] A method for preparing a semiconductor device, comprising:

[0007] Providing an epitaxial wafer, the epitaxial wafer comprising a semiconductor substrate and an epitaxial layer located on an upper surface of the semiconductor substrate;

[0008] forming a first mask layer having a first through hole on the upper surface of the epitaxial layer;

[0009] forming an (i+1)th mask layer having an (i+1)th through hole on a surface of the (i)th mask layer having an (i)th through hole;

[0010] The epitaxial layer is etched based on the (i+1)th through-hole to form an (i)th level trench in the upper surface of the epitaxial layer, so as to sequentially form the first to Mth level trenches of an M-level trench structure in the upper surface of the epitaxial layer; wherein M is a positive integer greater than 1; before forming the (i)th level trench, the (i+1)th mask layer covers the top of the (i)th mask layer and covers the sidewalls and bottom of the (i)th through-hole, and i is a positive integer not greater than M; the apertures of the (1)th through-hole to the (M+1)th through-hole decrease in sequence, and the widths of the (1)th to the (M)th level trenches decrease in sequence;

[0011] A self-aligned ion implantation window is formed based on at least one of the first mask layer to the M+1th mask layer, and self-aligned ion implantation is performed to form an ion implantation region in the surface of the M-level trench structure.

[0012] Optionally, in the above preparation method, after the Mth-level trench structure is formed in the upper surface of the epitaxial layer based on the M+1th through hole, the top of the 2nd mask layer to the M+1th mask layer is flush with the upper surface of the 1st mask layer; in the 1st-level trench to the M-1th-level trench, the side wall of the ath-level trench is covered with the a+2th mask layer, where a is a positive integer not greater than M-1.

[0013] Optionally, in the above preparation method, the i-th mask layer and the (i+1)-th mask layer have a wet etching selectivity ratio;

[0014] The method for forming an ion implantation region in a surface of an M-level trench structure includes:

[0015] Based on the wet etching selectivity, the jth mask layer is removed, and the other mask layers are retained to expose the area around the opening of the j-1th level trench; j is a positive integer greater than 1 and not greater than M+1;

[0016] Self-aligned ion implantation is performed using the gap between the j-1th mask layer and the j+1th mask layer as a self-aligned ion implantation window to form ion implantation regions in the sidewall surface of the j-1th level trench and in the bottom surface of the Mth level trench.

[0017] Optionally, in the above preparation method, the epitaxial layer and the ion implantation region have different doping types to form a junction-controlled diode;

[0018] After forming a plurality of ion implantation regions in the surface of the M-th level trench structure, the method further includes:

[0019] Retaining the first mask layer having the first through hole and removing other mask layers, forming an ohmic contact layer in the M-level trench structure, wherein the ohmic contact layer covers the surface of the M-level trench structure and the upper surface of the epitaxial layer exposed by the first through hole, so as to form a plurality of junction-controlled diodes based on the M-level trench structure;

[0020] The M-level trench structure is filled with a dielectric material.

[0021] Optionally, in the above preparation method, the i-th mask layer and the (i+1)-th mask layer have a wet etching selectivity ratio of not less than 100.

[0022] Optionally, in the above preparation method, the first mask layer and the second mask layer have a wet etching selectivity ratio; the second mask layer to the M+1th mask layer are film layers of the same material;

[0023] The method for forming an ion implantation region in a surface of an M-level trench structure includes:

[0024] Based on the wet etching selection ratio, removing the second mask layer to the M+1th mask layer;

[0025] Self-aligned ion implantation is performed using the first through hole in the first mask layer as a self-aligned ion implantation window to implant ions into the M-level trench structure, thereby forming an integrated ion implantation region within the surface of the M-level trench structure and around the opening of the first-level trench.

[0026] Optionally, in the above preparation method, the epitaxial layer and the ion implantation region have different doping types to form a junction-controlled diode;

[0027] After forming a plurality of ion implantation regions, the method further includes:

[0028] After removing the first mask layer, a dielectric material is filled in the M-level trench structure;

[0029] forming a first electrode and a second electrode; wherein the first electrode covers the upper surface of the epitaxial layer, and the second electrode covers the lower surface of the semiconductor substrate;

[0030] A junction-controlled diode is formed between the integrated ion implantation region and the epitaxial layer.

[0031] Optionally, in the above preparation method, the thicknesses of the second mask layer to the (M+1)th mask layer are all smaller than the thickness of the first mask layer.

[0032] Optionally, in the above preparation method, the thicknesses of the second mask layer to the M+1th mask layer are all the same.

[0033] Optionally, in the above preparation method, the epitaxial layer is an N-type doped silicon carbide layer;

[0034] Ion implantation is performed on the surface of the M-level trench structure based on P-type ions.

[0035] By means of the above technical solution, the present application provides a method for preparing a semiconductor device, which can form an M-level trench structure having a 1st-level trench to an M-level trench in the upper surface of the epitaxial layer based on the 1st mask layer to the M+1th mask layer. The 1st mask layer to the M+1th mask layer sequentially have a 1st through hole to an M+1th through hole, and the apertures of the 1st through hole to the M+1th through hole decrease in sequence. Before forming the i-th level trench, the i+1th mask layer covers the top of the i-th mask layer and covers the sidewalls and bottom of the i-th through hole. In this way, based on the i+1th through hole, the i-th level trench of the M-level trench structure can be formed in the upper surface of the epitaxial layer by etching the epitaxial layer, so as to form an M-level trench structure having a 1st-level trench to an M-th level trench in the surface of the epitaxial layer.

[0036] In addition, since the preparation method can form the next mask layer after forming the corresponding first-level groove according to the through hole in the previous mask layer, the surface of each level of groove can be covered by a corresponding mask layer respectively. Therefore, when at least two mask layers have a wet etching selectivity, it can be directly used to form a self-aligned ion injection window using at least one of the 1st mask layer to the M+1th mask layer, and self-aligned ion injection can be performed based on the self-aligned ion injection window, so that an ion injection area can be formed in the surface of the M-level groove structure, and there is no need to prepare a mask layer for ion injection separately. BRIEF DESCRIPTION OF THE DRAWINGS

[0037] In order to more clearly illustrate the technical solutions in the embodiments of the present application or related technologies, the following briefly introduces the drawings required for use in the embodiments or descriptions of the prior art. Obviously, the drawings described below are merely embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on the provided drawings without any creative work.

[0038] The structures, proportions, sizes, etc. depicted in the drawings of this specification are only used to match the contents disclosed in the specification so as to facilitate understanding and reading by persons familiar with this technology. They are not intended to limit the conditions under which this application can be implemented, and therefore have no substantive technical significance. Any structural modifications, changes in proportional relationships, or adjustments in size, without affecting the efficacy and objectives that can be achieved by this application, should still fall within the scope of the technical contents disclosed in this application.

[0039] Figure 1 Schematic diagram of the ion implantation principle based on a single-stage trench;

[0040] Figure 2 Schematic diagram of the ion implantation principle based on multi-level trenches;

[0041] Figure 3-Figure 8 A device structure diagram at different process steps in a method for preparing a semiconductor device;

[0042] Figure 9-Figure 25 A device structure diagram of different process steps of a semiconductor manufacturing method provided in an embodiment of the present application.

[0043] Reference numerals:

[0044] 10-photoresist layer; 11-ion implantation region; 12-multi-level trench; 13-single-level trench; 14-mask layer; 15-epitaxial layer; 16-semiconductor substrate; 17-drift layer; 18-epitaxial wafer; 19-self-aligned ion implantation window; 20-ohmic contact layer; 21-dielectric material; 22-first electrode; 23-second electrode; EL1-first mask layer; EL2-second mask layer; EL3-third mask layer; EL4-fourth mask layer; Via1-first through hole; Via2-second through hole; Via3-third through hole; Via4-fourth through hole; GR1-first-level trench; GR2-second-level trench; GR3-third-level trench. DETAILED DESCRIPTION

[0045] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the embodiments of the present application. Those skilled in the art will know that with the development of technology and the emergence of new scenarios, the technical solutions provided in the embodiments of the present application are also applicable to similar technical problems.

[0046] Obviously, the embodiments described are only some of the embodiments of this application, rather than all of the embodiments. Based on the embodiments in this application, all other embodiments obtained by those of ordinary skill in the art without making creative efforts are within the scope of protection of this application. The terms used in the embodiments of this application are only used to explain the specific embodiments of this application, and are not intended to limit this application.

[0047] Wide-bandgap semiconductors like SiC possess excellent material properties, including a wide bandgap, high critical breakdown electric field, high electron saturation drift velocity, and high thermal conductivity. Therefore, they hold broad application prospects in high-voltage, high-frequency, and high-temperature power electronics. SiC MOSFET devices offer the advantages of high breakdown voltage, low specific on-resistance, high switching speed, and low switching losses. After years of industry research on planar SiC MOSFETs, modern technological advances have reached a point where shrinking the MOS cell size has failed to reduce the on-resistance. This is primarily due to the resistance limitations of the JFET neck region. Even with smaller lithography dimensions, it is difficult to reduce the on-resistance per unit area to 2mΩ·cm. 2 The trench structure can effectively solve this problem. It changes the conductive channel from horizontal to vertical. Compared with the ordinary structure, it eliminates the JFET neck resistance, greatly increases the cell density, and improves the current handling capacity of the power semiconductor.

[0048] However, trench SiC MOSFET devices still face problems in actual process manufacturing and application: the high electric field in the SiC drift region leads to a high electric field on the gate oxide layer. This problem is exacerbated at the trench corners, causing the gate oxide layer to quickly breakdown under high drain voltages. Furthermore, due to the limited depth of P-type ion implantation in wide-bandgap semiconductors such as SiC, many targeted trench gate protection structures and surge protection designs are difficult to implement from a process perspective.

[0049] To address the problem of limited P-type implantation depth and difficulty in diffusion of doping elements in wide bandgap semiconductors such as SiC, a multi-level trench plus ion implantation method can be used. This method can form a deeper P-type ion implantation area in the SiC material without the need for high-energy and high-dose ion implantation, thereby facilitating the formation of a P+ doping masking layer or junction-controlled diode in the SiC material.

[0050] refer to Figure 1 and Figure 2 , Figure 1 Schematic diagram of ion implantation principle based on single-stage trench. Figure 2 Schematic diagram of the ion implantation principle based on multi-level trenches.

[0051] like Figure 1 As shown, when it is necessary to form an integrated continuous ion implantation region 11 in the surface of the single-stage trench 13, as the trench depth in the epitaxial layer 15 increases, when ion implantation is performed on the single-stage trench 13, the ion implantation region 11 on the trench sidewall and bottom will be discontinuous.

[0052] like Figure 2 As shown, when it is necessary to form an integrated continuous ion implantation region 11 in the surface of the multi-level groove 12 , based on the step structure of the multi-level groove 12 , an integrated continuous ion implantation region 11 with good morphology can be formed in the surface of the multi-level groove 12 .

[0053] In addition, while it is not easy for a single-level groove 13 to form multiple separated ion implantation regions 11 on the groove surface, the multi-level groove 12 can be based on the step structure between each level of the groove, which facilitates the precise formation of multiple separated ion implantation regions 11 on the surface of at least two levels of the multi-level groove 12.

[0054] To form a Figure 2 The multi-level trench 12 of the integrated continuous ion implantation region is prepared by conventional processes such as Figure 3-Figure 8 shown.

[0055] refer to Figure 3-Figure 8 , Figure 3-Figure 8 The device structure diagram of a semiconductor device manufacturing method at different process steps is shown. The manufacturing method includes: Figure 3As shown, based on a mask layer 14, a multi-level trench 12 is formed after multiple etchings. Since the mask layer 14 has an etching window with the same width as the opening of the top level trench of the multi-level trench 12, the mask layer 14 covers the epitaxial layer 15 around the opening of the top level trench. Figure 4 As shown, the mask layer 14 for forming the multi-level trenches 13 on the surface of the epitaxial layer 15 is peeled off. Figure 5 As shown, a mask material is filled in the multi-level trench 12, and the mask material also covers the upper surface of the epitaxial layer 15. Then, a patterned photoresist layer 10 is formed on the surface of the epitaxial material through a photolithography process. Figure 6 As shown, the mask material is etched based on the photoresist layer 10 to remove the mask material in the multi-level trench 12, leaving the epitaxial material on the upper surface of the epitaxial layer 15 to form another mask layer 14 with an injection window, and then the photoresist layer 10 is removed. The width of the injection window is larger than the width of the opening of the uppermost first-level trench, so that when ion implantation is performed based on the other mask layer 14 with the injection window, a film as shown in FIG. Figure 2 The ion implantation region 11 is shown as an integrated continuous region.

[0056] As described above, in the conventional preparation method, when forming an integrated continuous ion implantation area 11 in the multi-level trench 12, it is necessary to peel off the original mask layer 14 used for etching to form the multi-level trench and prepare a new mask layer 14 for ion implantation separately. Figure 3 The structure shown in FIG is subjected to ion implantation, and the ion implantation region 11 formed is as shown in FIG. Figure 7 As shown, due to the obstruction of the mask layer 14 originally used for etching the multi-level grooves 12, ion implantation cannot be completed in the sidewall of the topmost groove, thereby causing the ion implantation area 11 in the semiconductor device to be unable to be grounded through the metal layer above the epitaxial layer 15, posing a risk of leakage.

[0057] In addition, although Figure 3-Figure 6 The process flow shown can form Figure 2 The integrated continuous ion implantation region 11, however, Figure 8 As shown, since the process of forming a new mask layer 14 requires filling the multi-level trench 12 with mask material, as shown in FIG. Figure 8 As shown, when the mask material within the multi-level trenches 12 is removed by etching the photoresist layer 10, residual mask material is likely to remain at the corners of the bottom of each trench, affecting the ion implantation depth and dose. The ion implantation region 11 is a P-type implantation region, and when used as a P+ doping mask, this can cause the P-type masking effect to deviate from the designed value.

[0058] Based on the above description, it can be seen that due to the limited depth of P-type ion implantation in SiC materials, many targeted trench gate protection structures and surge protection designs are difficult to implement from a process perspective. On the other hand, it is difficult to prepare superjunction devices. Although the multi-level trench structure can solve the problem of limited P-type implantation depth in SiC materials and achieve deeper P-type ion implantation with lower implantation energy, after the multi-level trench is prepared, the ion implantation mask pattern needs to be re-prepared. The preparation of the new mask pattern requires additional photolithography processes, which increases the complexity of the preparation process. In addition, there is the problem of residual mask material at the corner position of the trench bottom.

[0059] Moreover, there is currently no mature preparation process for forming multiple separate ion implantation areas 11 in local areas of multi-level trenches. When designing semiconductor devices, if selective ion implantation is required on the steps of the multi-level trenches 12 to achieve a special ion implantation area 11 design, the current process is still difficult to achieve.

[0060] In view of this, an embodiment of the present application provides a method for preparing a semiconductor device, comprising:

[0061] Providing an epitaxial wafer, the epitaxial wafer comprising a semiconductor substrate and an epitaxial layer located on an upper surface of the semiconductor substrate;

[0062] forming a first mask layer having a first through hole on the upper surface of the epitaxial layer;

[0063] forming an (i+1)th mask layer having an (i+1)th through hole on a surface of the (i)th mask layer having an (i)th through hole;

[0064] The epitaxial layer is etched based on the (i+1)th through-hole to form an (i)th level trench in the upper surface of the epitaxial layer, thereby forming the first to Mth level trenches of an M-level trench structure in the upper surface of the epitaxial layer; wherein M is a positive integer greater than 1; before forming the (i)th level trench, the (i+1)th mask layer covers the top of the (i)th mask layer and covers the sidewalls and bottom of the (i)th through-hole, and i is a positive integer not greater than M; the apertures of the (1)th through-hole to the (M+1)th through-hole decrease in sequence, and the widths of the (1)th to the (M)th level trenches decrease in sequence;

[0065] A self-aligned ion implantation window is formed based on at least one of the first mask layer to the M+1th mask layer, and self-aligned ion implantation is performed to form an ion implantation region in the surface of the M-level trench structure.

[0066] This preparation method can form an M-level trench structure having a first-level trench to an M-level trench within the upper surface of the epitaxial layer based on the first mask layer to the M+1 mask layer. The first mask layer to the M+1 mask layer sequentially have a first through-hole to an M+1 through-hole, and the apertures of the first through-hole to the M+1 through-hole decrease in sequence. Before forming the i-level trench, the i+1 mask layer covers the top of the i-th mask layer and covers the sidewalls and bottom of the i-th through-hole. In this way, based on the i+1 through-hole, the i-th level trench of the M-level trench structure can be formed within the upper surface of the epitaxial layer, thereby forming an M-level trench structure having a first-level trench to an M-level trench within the surface of the epitaxial layer.

[0067] In addition, since the preparation method can form the next mask layer after forming the corresponding first-level groove according to the through hole in the previous mask layer, the surface of each level of groove can be covered by a corresponding mask layer respectively. Therefore, when at least two mask layers have a wet etching selectivity, it can be directly used to form a self-aligned ion injection window using at least one of the 1st mask layer to the M+1th mask layer, and self-aligned ion injection can be performed based on the self-aligned ion injection window, so that an ion injection area can be formed in the surface of the M-level groove structure, and there is no need to prepare a mask layer for ion injection separately.

[0068] In the embodiments of this application, the method for fabricating a semiconductor device is described using P-type ion implantation in a SiC epitaxial layer as an example. It is readily apparent that the epitaxial layer in a semiconductor device is not limited to SiC and can also be an epitaxial layer of other materials. For example, multi-stage trench ion implantation can be performed in Si epitaxial layers, GaN epitaxial layers, and GaAs epitaxial layers of greater depth. Ion implantation is not limited to P-type implantation and can be either P-type or N-type.

[0069] In order to make the above-mentioned purposes, features and advantages of the present application more obvious and easy to understand, the present application is further described in detail below with reference to the accompanying drawings and specific embodiments.

[0070] refer to Figure 9-Figure 25 , Figure 9-Figure 25 A device structure diagram of different process steps of a semiconductor manufacturing method provided in an embodiment of the present application, the manufacturing method includes:

[0071] Step S11: Figure 9 As shown, an epitaxial wafer 18 is provided. The epitaxial wafer 18 includes a semiconductor substrate 16 and an epitaxial layer 15 located on the upper surface of the semiconductor substrate 16 .

[0072] Optionally, in order to optimize the performance of the semiconductor device, a drift layer 17 may be first formed on the surface of the semiconductor substrate 16 , and then the epitaxial layer 15 may be formed on the surface of the drift layer 17 .

[0073] In other embodiments, the epitaxial layer 15 may be formed directly on the upper surface of the semiconductor substrate 16 .

[0074] Step S12: Figure 10-12 As shown, a first mask layer EL1 having a first through hole Via1 is formed on the upper surface of the epitaxial layer 15 .

[0075] In step S12, you can first Figure 10 As shown, a first mask layer EL1 is formed on the surface of the epitaxial layer 15 to cover the entire surface, and then Figure 11 As shown, a patterned photoresist layer 10 is formed on the surface of the first mask layer EL1 by a photolithography process. Figure 12 As shown, the first mask layer EL1 is etched based on the patterned photoresist layer 10 to form a first through hole Via1 in the first mask layer EL1.

[0076] Step S13: In the case of the i-th through hole Via i The i-th mask layer EL i The i+1th through hole Via is formed on the surface i+1 The i+1th mask layer EL i+1 .

[0077] If i=1, Figure 13 As shown, a second mask layer EL2 having a second through hole Via2 is formed on the surface of the first mask layer EL1 having the first through hole Via1.

[0078] Step S14: Figures 14-18 As shown, based on the i+1th through hole Via i+1 The epitaxial layer 15 is etched to form an i-th level trench GR in the upper surface of the epitaxial layer 15. i , so as to form the first-level trench to the M-th-level trench of the M-level trench structure in the upper surface of the epitaxial layer 15 .

[0079] Wherein, M is a positive integer greater than 1; forming the i-th level groove GR i Before, the i+1th mask layer EL i+1 Covering the i-th mask layer EL i The top of the via hole i The side wall and bottom, i is a positive integer not greater than M; the first through hole Via1 to the M+1 through hole Via M+1 The apertures of the first-level groove GR1 to the M-level groove GR M The width decreases successively.

[0080] In step S14, Figure 13As shown, before forming the first-level trench GR1 , the second mask layer EL2 covers the top of the first mask layer EL1 and covers the sidewalls and the bottom of the first through hole Via1 .

[0081] When i=1, Figure 14 As shown, the epitaxial layer 15 is etched based on the second through hole Via2 to form a first-level trench GR1 of an M-level trench structure in the upper surface of the epitaxial layer 15 .

[0082] When i=2, Figure 15 As shown, after the first-level trench GR1 is formed, a third mask layer EL3 having a third through hole Via3 is formed on the surface of the second mask layer EL2 having the second through hole Via2. Figure 16 As shown, the epitaxial layer 15 is etched based on the third through hole Via3 to form a second-level trench GR2 of an M-level trench structure in the upper surface of the epitaxial layer 15 .

[0083] When i=3, Figure 17 As shown, after the second-level trench GR2 is formed, a fourth mask layer EL4 having a fourth through hole Via3 is formed on the surface of the third mask layer EL3 having the third through hole Via3. Figure 18 As shown, the epitaxial layer 15 is etched based on the fourth through hole Via4 to form a third-level trench GR3 of an M-level trench structure in the upper surface of the epitaxial layer 15 .

[0084] Based on the above description, it can be seen that the preparation method provided in the embodiment of the present application can prepare an M-level trench structure based on an M+1 mask layer. In the embodiment of the present application, M=3 is used as an example for illustration. It should be noted that M is not limited to 3, and M can be any positive integer greater than 1, such as 2, 4, 5, or any other positive integer greater than 1.

[0085] Among the trenches at the first level to the M-1th level, the sidewalls of the ath-level trench are covered with the a+2th mask layer, where a is a positive integer not greater than M-1. Figure 18 As shown, when a=1, the sidewall of the first-level trench GR1 is covered with the third mask layer EL3; when a=2, the sidewall of the second-level trench GR2 is covered with the fourth mask layer EL4.

[0086] like Figure 14 、 Figure 16 and Figure 18 As shown, based on the i+1th through hole Via i+1 The epitaxial layer 15 is etched to form an i-th level trench GR in the upper surface of the epitaxial layer 15. i When the i-th through hole Via is removed synchronously i External (i+1) mask layer EL i+1 and the i-th through hole Via iThe bottom i+1 mask layer EL i+1 , retain the i-th via i The i+1th mask layer EL on the sidewall i+1 Based on this, the epitaxial layer 15 is further etched to form the i-th level trench GR i .

[0087] i=1, such as Figure 14 As shown, based on the second through hole Via2, the epitaxial layer 15 is etched to form the first-level groove GR1 in the upper surface of the epitaxial layer 15, and the second mask layer EL2 outside the first through hole Via1 and the second mask layer EL2 at the bottom of the first through hole Via1 are simultaneously removed, and the second mask layer EL2 on the side wall of the first through hole Via1 is retained. Based on this, the epitaxial layer 15 is further etched to form the first-level groove GR1.

[0088] i=2, such as Figure 16 As shown, when the epitaxial layer 15 is etched based on the third through hole Via3 to form the second-level groove GR2 in the upper surface of the epitaxial layer 15, the third mask layer EL3 outside the second through hole Via2 and the third mask layer EL3 at the bottom of the second through hole Via2 are simultaneously removed, and the third mask layer EL3 on the side wall of the second through hole Via2 is retained. Based on this, the epitaxial layer 15 is further etched to form the second-level groove GR2.

[0089] i=3, such as Figure 18 As shown, when the epitaxial layer 15 is etched based on the 4th through hole Via4 to form the 3rd level groove GR3 in the upper surface of the epitaxial layer 15, the 4th mask layer EL4 outside the 3rd through hole Via3 and the 4th mask layer EL4 at the bottom of the 3rd through hole Via3 are simultaneously removed, and the 4th mask layer EL4 on the side wall of the 3rd through hole Via3 is retained. Based on this, the epitaxial layer 15 is further etched to form the 3rd level groove GR3.

[0090] Step S15: Figures 19-21 As shown, based on the first mask layer EL1 to the M+1 mask layer EL M+1 A self-aligned ion implantation window 19 is formed in at least one of the grooves, and self-aligned ion implantation is performed to form an ion implantation region 11 in the surface of the M-level trench structure.

[0091] In step S15, Figure 19 As shown, by removing the third mask layer EL3, the second mask layer EL2 and the fourth mask layer EL4 are used to form a self-aligned ion implantation window 19, which exposes the bottom of the first-level trench GR1. Figure 20As shown, ions are implanted into the sidewall surface of the second-level trench GR2 through the self-aligned ion implantation window 19 to form an ion implantation region 11. Ions can also be implanted into the bottom surface of the third-level trench GR3 to form an ion implantation region 11 simultaneously. After the ion implantation is completed, the first mask layer EL1 is retained, and the second mask layer EL2 and the fourth mask layer EL4 are removed.

[0092] Based on the above description, it can be seen that the manufacturing method provided in the embodiment of the present application can be based on the first mask layer EL1 to the M+1 mask layer EL M+1 , a first-level trench GR1 to an M-th-level trench GR are formed in the upper surface of the epitaxial layer 15. M The first mask layer EL1 to the M+1 mask layer EL M+1 There are the first through hole Via1 to the M+1 through hole Via1 in sequence. M+1 , the 1st through hole Via1 to the M+1th through hole Via M+1 The aperture decreases successively, forming the i-th level groove GR i Before, the i+1th mask layer EL i+1 Covering the i-th mask layer EL i The top of the via hole i Thus, based on the i+1th through hole Via i+1 The epitaxial layer 15 is etched to form an i-th level trench GR of an M-level trench structure in the upper surface of the epitaxial layer 15. i , so as to form the first-level trench GR1 to the M-th-level trench GR in the surface of the epitaxial layer 15. M M-level groove structure.

[0093] In addition, since the preparation method can form the next mask layer after forming the corresponding first-level groove according to the through hole in the previous mask layer, the surface of each level of groove can be covered by a corresponding mask layer respectively. Therefore, when at least two mask layers have a wet etching selectivity ratio, it can be directly used to use the first mask layer EL1 to the M+1 mask layer EL2. M+1 At least one of them forms a self-aligned ion implantation window 19, and self-aligned ion implantation can be performed based on the self-aligned ion implantation window 19, so that an ion implantation area 11 can be formed in the surface of the M-level trench structure without the need to separately prepare a mask layer for ion implantation.

[0094] Since the first through hole Via1 to the M+1 through hole Via M+1 The apertures of the corresponding grooves GR1 to GR1M are reduced in sequence. MThe width of the grooves decreases successively, so that steps are formed between two adjacent grooves, and the bottom of the previous groove is the opening top area of ​​the adjacent next groove.

[0095] In the embodiments of this application, Figure 18 As shown, based on the M+1th through hole Via M+1 After the M-th level trench structure is formed in the upper surface of the epitaxial layer 15, the second mask layer EL2 to the M+1 mask layer EL M+1 The top of the first mask layer EL1 is flush with the upper surface; the first-level trench GR1 to the M-1-level trench GR M-1 In the middle, the first level groove GR a The sidewalls are covered with the a+2 mask layer EL a+2 , a is a positive integer not greater than M-1. If M=3, the first-level groove GR1 to the second-level groove GR M-1 In the embodiment, the sidewalls of the first-level trench GR1 are covered with the third mask layer EL3, and the sidewalls of the second-level trench GR2 are covered with the fourth mask layer EL4.

[0096] In the embodiment of this application, Figure 18 As shown, based on the first mask layer EL1 to the M+1 mask layer EL M+1 , sequentially forming the first-level trench GR1 to the M-th-level trench GR in the upper surface of the epitaxial layer 15 M Then, the second mask layer EL2 to the M+1 mask layer EL M+1 Remain in the thickness direction of the epitaxial layer 15 ( Figure 18 The vertical direction) part of each mask layer can make each mask layer have a width direction ( Figure 18 In the horizontal direction), the layers are stacked in sequence. Thus, when the second mask layer EL2 to the M+1 mask layer EL are removed, M+1 After one or more of the steps, the set area of ​​the M-level trench structure can be exposed for ion implantation.

[0097] Therefore, in the embodiment of the present application, not only the first mask layer EL1 to the M+1 mask layer EL2 can be used, but also the second mask layer EL3 to the M+1 mask layer EL4 can be used. M+1 Prepare the M-level trench structure, and selectively remove the second mask layer EL2 to the M+1 mask layer EL M+1 One or more of them reuse at least one mask layer to form a self-aligned ion implantation window 19 to selectively implant ions in a set area of ​​the M-level trench structure, and controllably implant ions in the set area of ​​the M-level trench structure.

[0098] In one embodiment of the present application, the i-th mask layer EL i and the i+1th mask layer EL i+1Has a wet etching selectivity ratio, that is, any two adjacent mask layers have a wet etching selectivity ratio. Figure 18 After the device structure is shown, the second mask layer EL2 to the M+1 mask layer EL3 can be selectively removed by utilizing the wet etching selectivity between adjacent mask layers. M+1 One or more of them are used to select the area in the M-level trench structure where ion implantation is required.

[0099] If the i-th mask layer EL i and the i+1th mask layer EL i+1 With a wet etching selectivity, in the preparation method provided in the embodiment of the present application, in one embodiment, the method for forming the ion implantation region 11 in the surface of the M-level trench structure includes: removing the j-th mask layer EL based on the wet etching selectivity. j , retain other mask layers to expose the j-1th level trench GR j-1 The area around the opening; j is a positive integer greater than 1 and not greater than M+1; the j-1th mask layer EL j-1 and the j+1th mask layer EL j+1 The gap between them is the self-aligned ion implantation window 19, and the self-aligned ion implantation is performed in the j-1st level trench GR j-1 The sidewall surface and the M-th level trench GR M Ion implantation regions 11 are respectively formed in the bottom surface of the M-level trench structure, so that a plurality of separated ion implantation regions 11 can be formed in the surface of the M-level trench structure.

[0100] If j=3, then Figure 19 As shown, based on the wet etching selectivity, the third mask layer EL3 is removed, and the other mask layers are retained to expose the area around the opening of the second-level trench GR2 (this area is the bottom area of ​​the first-level trench GR1); the gap between the second mask layer EL2 and the fourth mask layer EL4 is used as the self-aligned ion implantation window 19. After the self-aligned ion implantation is performed, the following can be done: Figure 20 As shown, ion implantation regions 11 are formed in the sidewall surfaces of the second-level trench GR2 and in the bottom surface of the third-level trench GR3 , respectively.

[0101] Taking M=3 as an example, when the i-th mask layer EL i and the i+1th mask layer EL i+1When having a wet etching selectivity, if j=2, the area around the opening of the first-level trench GR1 can be exposed, and the ion implantation area 11 can be formed in the side wall of the first-level trench GR1; if j=3, the area around the opening of the second-level trench GR2 can be exposed, and the ion implantation area 11 can be formed in the side wall of the second-level trench GR2; if j=4, the area around the opening of the third-level trench GR3 can be exposed, and the ion implantation area 11 can be formed in the side wall of the third-level trench GR3.

[0102] Therefore, if the i-th mask layer EL i and the i+1th mask layer EL i+1 With wet etching selectivity, in the embodiment of the present application, Figure 18 Based on the device structure shown, the second mask layer EL2 to the M+1 mask layer EL3 can be removed based on the needs. M+1 One or more of them are used to accurately locate the area in the M-level trench structure where ion implantation is required.

[0103] In the embodiment of the present application, the doping types of the epitaxial layer 15 and the ion implantation region 11 can be different, so that a junction-controlled diode can be formed. At this time, after forming a plurality of ion implantation regions 11 on the surface of the M-th level trench structure, the preparation method can also be as follows: Figure 22 As shown, it also includes: retaining the first mask layer EL1 having the first through hole, and after removing other mask layers, forming an ohmic contact layer 20 in the M-level trench structure, the ohmic contact layer 20 covers the surface of the M-level trench structure and the upper surface of the epitaxial layer 15 exposed by the first through hole Via1, so as to form multiple junction-controlled diodes based on the M-level trench structure; filling the M-level trench structure with a dielectric material 21.

[0104] exist Figure 22 In the manner shown, since a plurality of separated ion implantation regions 11 are formed in the surface of the M-th level trench structure, a plurality of PN structures can be formed in the epitaxial layer 15 to form a plurality of junction-controlled diodes. This manner can be used to form a trench junction-controlled diode structure between two trench gates of a trench gate MOS. Figure 22 The junction-controlled diode with multiple interconnections shown can be used to optimize the device performance of trench MOS.

[0105] In order to facilitate the effective removal of the mask layer based on the wet etching selectivity, the i-th mask layer EL is set i and the i+1th mask layer EL i+1 It has a wet etching selectivity ratio of not less than 100.

[0106] When two adjacent mask layers have a wet etching selectivity ratio of not less than 100, the mask layers can be effectively removed based on the larger wet etching selectivity ratio between the adjacent mask layers, thereby preventing mask material residue.

[0107] In one implementation of the embodiment of the present application, the first mask layer EL1 and the second mask layer EL2 may have a wet etching selectivity ratio; the second mask layer EL2 to the M+1 mask layer EL M+1 The same material film layer, that is, the second mask layer EL2 to the M+1 mask layer EL M+1 The wet etching rate is the same and there is no wet etching selectivity. Figure 18 After forming the M-level trench structure, the method of forming the ion implantation region 11 in the surface of the M-level trench structure includes:

[0108] First, if Figure 23 As shown, based on the wet etching selection ratio, the second mask layer EL2 to the M+1 mask layer EL M+1 Since the second mask layer EL2 to the M+1 mask layer EL M+1 The same material layer is used, so the second mask layer EL2 to the M+1 mask layer EL M+1 Since the first mask layer EL1 and the second mask layer EL2 have a wet etching selectivity, the second mask layer EL2 to the M+1 mask layer EL3 can be removed synchronously based on the wet etching selectivity. M+1 Optionally, as described above, the wet etching selectivity is not less than 100.

[0109] Then, if Figure 24 As shown, the first through hole Via1 in the first mask layer EL1 is used as the self-aligned ion implantation window 19 to perform self-aligned ion implantation to implant ions into the M-level trench structure to form an integrated ion implantation region 11 within the surface of the M-level trench structure and around the opening of the first-level trench.

[0110] exist Figure 23 and Figure 24 In the embodiment shown, the second mask layer EL2 to the M+1 mask layer EL M+1 The same material film layer can have a wet etching selectivity ratio with the first mask layer EL1. Based on the wet etching selectivity ratio, the second mask layer EL2 to the M+1 mask layer EL3 can be removed simultaneously. M+1 By retaining the first mask layer EL1 and using the first through hole Via1 in the first mask layer EL1 as a self-aligned ion implantation window 19, a continuous ion implantation region 11 can be formed within the surface of the M-level trench structure. In this method, ion implantation can be performed on the sidewalls and bottom of each level of the trench, thereby forming a continuous ion implantation region 11, with the top of the ion implantation region 11 located within the surface of the epitaxial layer 15 exposed by the first through hole Via1.

[0111] In the embodiment of the present application, it is not limited to Figure 23 and Figure 24 The method shown in FIG. 1 forms an integrated continuous ion implantation region 11. In the above embodiment, if the i-th mask layer EL i and the i+1th mask layer EL i+1 With wet etching selectivity, the second mask layer EL2 to the M+1 mask layer EL can also be removed by multiple etchings. M+1 Ion implantation is then performed to similarly form an integrated and continuous ion implantation region 11 within the M-level trench structure.

[0112] In the embodiment of the present application, if a continuous ion implantation region 11 is formed in the surface of the M-level trench structure, a junction-controlled diode can be formed based on the continuous ion implantation region 11. In this case, the doping type of the epitaxial layer 15 is different from that of the ion implantation region 11 to form a junction-controlled diode; after forming multiple ion implantation regions 11, as shown in FIG. Figure 25 As shown, the preparation method also includes: after removing the first mask layer EL1, filling the M-level trench structure with a dielectric material 21; forming a first electrode 22 and a second electrode 23; the first electrode 22 covers the upper surface of the epitaxial layer 15, and the second electrode 23 covers the lower surface of the semiconductor substrate 16; wherein a junction-controlled diode is formed between the integrated ion implantation region 11 and the epitaxial layer 15.

[0113] exist Figure 25 The method shown can form an integrated continuous ion implantation region 11 on the surface of the M-level trench structure, thereby forming an integrated junction-controlled diode in the M-level trench structure to optimize semiconductor device performance. This method can be used to prepare superjunction or semi-superjunction devices.

[0114] Optionally, the epitaxial layer 15 is an N-type doped silicon carbide layer, and ion implantation is performed on the surface of the M-level trench structure based on P-type ions. This method can achieve P-type ion implantation at a greater depth in the silicon carbide material.

[0115] In the embodiment of this application, Figures 13 to 14 The process shown, Figures 15 to 16 The process shown, Figures 17 to 18 In the process shown, when forming the trenches at different levels, it is necessary to etch away the other mask layers on the surface of the first mask layer EL1 so that each mask layer is flush with the upper surface of the first mask layer EL1. Multiple etching processes will cause loss of thickness of the first mask layer EL1. In order to avoid over-etching of the first mask layer EL1, the second mask layer EL2 to the M+1 mask layer EL1 are provided. M+1 The thickness of each of the layers is smaller than the thickness of the first mask layer EL1.

[0116] In one implementation of the embodiment of the present application, the second mask layer EL2 to the M+1 mask layer EL3 may be provided.M+1 The thickness of the mask layers EL2 to EL1 are the same, so that the second mask layer EL2 to the M+1 mask layer EL M+1 Process preparation.

[0117] The M-level groove structure has M-level steps. The area around the opening of the i-level groove is the i-level step. Figure 18 As shown, when M=3, the opening of the first-level trench GR1 is surrounded by the first-level step, the opening of the second-level trench is surrounded by the second-level step, and the opening of the third-level trench is surrounded by the third-level step. i+1 The i-th level trench of the M-level trench structure can be formed. Figure 18 As shown, the second epitaxial layer EL2 can form the first-level trench of the M-level trench structure, the third epitaxial layer EL3 can form the second-level trench of the M-level trench structure, and the fourth epitaxial layer EL4 can form the third-level trench of the M-level trench structure.

[0118] If the second mask layer EL2 to the M+1 mask layer EL M+1 The thickness is the same, such as Figure 18 As shown, the steps of each level in the M-level trench structure can have the same width.

[0119] In the embodiment of the present application, the second mask layer EL2 to the M+1 mask layer EL3 may be further provided. M+1 The thickness of at least two of them is different, so that at least two steps of width can be formed in the M-level trench structure. In this way, when the second mask layer EL2 to the M+1 mask layer EL3 are selectively removed, M+1 When forming multiple separated ion implantation regions 11 in the M-level trench structure, one or more of the step surfaces with different widths can be selected for ion implantation to form ion implantation regions 11 with the required width, so as to flexibly control the lateral width of the ion implantation region 11 and better optimize the device performance. M+1 If at least two of the layers have different thicknesses, when forming a continuous ion implantation region 11 in an M-stage trench structure, the lateral width of the ion implantation region 11 corresponding to each step position can be controlled by adjusting the thickness of each mask layer. This allows the continuous ion implantation region 11 to have diverse lateral widths at each step. By adjusting the relative thicknesses of the mask layers, this approach allows for differentiated design of the lateral width of the ion implantation region 11 at different steps, thereby optimizing device performance.

[0120] If the second mask layer EL2 to the M+1 mask layer EL M+1 The thickness of at least two of them is different. Further, the second mask layer EL2 to the M+1 mask layer EL M+1At this time, the widths of the first to Mth steps increase successively, so that the width of the steps is positively correlated with the depth of the steps. The greater the step depth, the greater the step width, which facilitates ion implantation on the surface of the step with a greater depth, thereby ensuring the implantation effect of the ion implantation area 11 in the sidewall of the trench with a greater depth.

[0121] Each mask layer can be prepared by a plasma enhanced chemical vapor deposition (PECVD) process. The deposition thickness of the mask layer can range from 150°C to 350°C.

[0122] In the embodiment of the present application, the thickness of the first mask layer EL1 may be in the range of 2 μm to 5 μm. The second mask layer EL2 to the M+1 mask layer EL M+1 Before etching, each mask layer includes a first film layer portion covering the first mask layer EL1 and a second film layer portion located in the previous through hole. The thickness of the first film layer portion can range from 200nm to 1200nm, and the thickness of the second film layer portion can range from 100nm to 400nm. M+1 For any mask layer in the through hole, since the second film layer is partially located inside the surface of the through hole, the deposition depth is larger, and the first film layer is directly deposited on the upper surface of the first mask layer EL1, the thickness of the first film layer is greater than the thickness of the second film layer.

[0123] It can be seen from the above description that the preparation method provided in the embodiment of the present application can prepare an M-level trench structure in the epitaxial layer 15 based on an M+1 mask layer. The material of the mask layer can be any one of silicon oxide, silicon nitride and polysilicon, and the mask layers of different materials have a larger wet etching selectivity. If the wet etching selectivity of silicon nitride to silicon oxide is greater than 100, the wet etching selectivity of silicon nitride to polysilicon is greater than 100. The material of each mask layer can be set according to demand. The material of the mask layer is not limited to silicon oxide, silicon nitride and polysilicon, etc., and can also be other inorganic materials. The embodiment of the present application does not limit the material of the mask layer.

[0124] The materials of each mask layer can be set to be different, so that each mask layer can have a different wet etching rate. There is a wet etching selectivity ratio between any two mask layers, so that a self-aligned ion implantation window 19 can be formed using the mask layer based on the wet etching selectivity ratio.

[0125] The i-th mask layer EL can also be set i The first material, the i+1th mask layer EL i+1 The first material and the second material have a wet etching selectivity ratio. M+1In the embodiment, an alternating stacked structure of a first material mask layer and a second material mask layer can be formed, and any two adjacent mask layers have a wet etching selectivity ratio, so that a self-aligned ion implantation window 19 can be formed using the mask layer based on the wet etching selectivity ratio.

[0126] It is also possible to set the first mask layer EL1 to the M+1 mask layer EL M+1 At least two of the layers are made of different materials, so that the at least two layers have a wet etching selectivity, so as to form a self-aligned ion implantation window 19 using a mask layer based on the wet etching selectivity.

[0127] In the embodiment of the present application, the self-aligned ion implantation window 19 can be formed by using a mask layer for preparing an M-level trench structure, and after removing the second mask layer EL2 to the M+1 mask layer EL M+1 After at least one of the layers is removed, the remaining mask layers are retained to form a self-aligned ion implantation window 19. Ion implantation is performed directly based on the self-aligned ion implantation window 19, greatly simplifying the process flow of ion implantation after multi-level trench etching. There is no need for re-deposition of thin films and photolithography patterning, resulting in a simple preparation process and low production cost. It also avoids the problem of mask material residue caused by incomplete etching at the groove corners when mask material is re-deposited in the multi-level trenches.

[0128] As mentioned above, in the embodiment of the present application, a junction-controlled diode can be further formed based on the ion implantation region 11 in the M-level trench structure. The conduction voltage drop of the junction-controlled diode is smaller than the body diode of the device, thereby shielding the conduction of the body diode. The junction-controlled diode is a unipolar device and does not have a minority carrier storage effect, which can significantly reduce the switching loss of the semiconductor device.

[0129] In the implementation of this application, if an integrated and continuous ion implantation area 11 is formed in the M-level trench structure, the ion implantation area 11 is not limited to forming a junction-controlled diode located between two trench gates. The M-level trench structure can also be used to form a trench gate of a semiconductor device. The integrated and continuous ion implantation area 11 can also serve as an electric field shielding layer under the surface of the gate dielectric layer of the trench gate to improve the device's withstand voltage and prevent the gate dielectric layer from being broken down at each level of the trench corner.

[0130] Optionally, in an embodiment of the present application, the epitaxial wafer 18 can be a wide bandgap semiconductor material such as silicon carbide, and the injected ions can be P-type ions. The preparation method provided in the embodiment of the present application can solve the problem of limited P-type ion injection depth and difficult diffusion of P-type ions in wide bandgap semiconductor materials through a multi-level trench combined with ion injection method. Deeper P-type ion doping can be achieved in wide bandgap semiconductor materials without the need for high-energy and high-dose ion injection areas.

[0131] In the embodiment of the present application, the multi-layer mask layer can sequentially form a sidewall stacking structure stacked in the horizontal direction on the sidewalls of each level of through hole, such as Figure 18 As shown, the second mask layer EL2 can form a sidewall covering the first through hole Via1, the third mask layer EL3 can form a sidewall covering the second through hole Via2, and the fourth mask layer EL4 can form a sidewall covering the third through hole Via3. The second mask layer EL2 to the fourth mask layer EL4 form a laterally stacked sidewall stack structure. This preparation method can eliminate multiple photolithography processes and simplify the preparation process of multi-level trenches. At the same time, the width of each step can be controlled by controlling the thickness of the sidewalls, so that the minimum line width of the multi-step steps is not limited by the photolithography accuracy. It can also control the lateral width of the ion implantation region 11 corresponding to each step.

[0132] The various embodiments in the specification of this application are described in a progressive, parallel, or progressive and parallel manner. Each embodiment focuses on the differences from other embodiments, and the same or similar parts between the various embodiments can be referenced to each other. The embodiments provided in the embodiments of this application can be combined with each other if there is no contradiction.

[0133] It should be noted that in the description of this application, it should be understood that the description of the drawings and embodiments is illustrative rather than restrictive. The same figure numbers throughout the embodiments of the specification identify the same structure. In addition, for the purpose of understanding and ease of description, the drawings may exaggerate the thickness of some layers, films, panels, regions, etc. It is also understood that when an element such as a layer, film, region or substrate is referred to as "on" another element, the element may be directly on the other element or there may be an intermediate element. In addition, "on" refers to positioning an element on or below another element, but does not essentially mean positioning on the upper side of another element according to the direction of gravity.

[0134] The terms "upper," "lower," "top," "bottom," "inner," "outer," and the like, indicating positions or locations, are based on the positions or locations shown in the accompanying drawings and are intended solely to facilitate and simplify the description of this application. They are not intended to indicate or imply that the devices or elements referred to must have a specific orientation, be constructed, or operate in a specific orientation. Therefore, they should not be construed as limitations on this application. When a component is considered to be "connected" to another component, it may be directly connected to the other component or there may be a centrally located component.

[0135] It should also be noted that, in this document, relational terms such as first and second, etc., are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations. Moreover, the terms "comprises," "comprising," or any other variations thereof are intended to cover non-exclusive inclusion, such that an article or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such article or device. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the article or device comprising the aforementioned elements.

[0136] The above description of the disclosed embodiments is intended to enable one skilled in the art to implement or use the present application. Various modifications to these embodiments will be readily apparent to one skilled in the art, and the general principles defined herein may be implemented in other embodiments without departing from the spirit or scope of the present application. Therefore, the present application is not limited to the embodiments shown herein, but is intended to conform to the widest scope consistent with the principles and novel features disclosed herein.

Claims

1. A method for preparing a semiconductor device, characterized in that: include: Providing an epitaxial wafer, the epitaxial wafer comprising a semiconductor substrate and an epitaxial layer located on an upper surface of the semiconductor substrate; forming a first mask layer having a first through hole on the upper surface of the epitaxial layer; forming an (i+1)th mask layer having an (i+1)th through hole on a surface of the (i)th mask layer having an (i)th through hole; The epitaxial layer is etched based on the (i+1)th through-hole to form an (i)th level trench in the upper surface of the epitaxial layer, so as to sequentially form the first to Mth level trenches of an M-level trench structure in the upper surface of the epitaxial layer; wherein M is a positive integer greater than 1; before forming the (i)th level trench, the (i+1)th mask layer covers the top of the (i)th mask layer and covers the sidewalls and bottom of the (i)th through-hole, and i is a positive integer not greater than M; the apertures of the (1)th through-hole to the (M+1)th through-hole decrease sequentially, and the widths of the (1)th to the (M)th level trenches decrease sequentially; forming a self-aligned ion implantation window based on at least one of the first mask layer to the M+1th mask layer, performing self-aligned ion implantation to form an ion implantation region in the surface of the M-level trench structure; wherein, after the Mth-level trench structure is formed in the upper surface of the epitaxial layer based on the M+1th through hole, the top of the second mask layer to the M+1th mask layer is flush with the upper surface of the first mask layer; in the first-level trench to the M-1th-level trench, the sidewall of the ath-level trench is covered with the a+2th mask layer, where a is a positive integer not greater than M-1; wherein the i-th mask layer and the i+1-th mask layer have a wet etching selectivity ratio; The method for forming the ion implantation region in the surface of the M-level trench structure includes: Based on the wet etching selectivity, the jth mask layer is removed, and other mask layers are retained to expose the area around the opening of the j-1th level trench; j is a positive integer greater than 1 and not greater than M+1; Self-aligned ion implantation is performed using the gap between the j-1th mask layer and the j+1th mask layer as the self-aligned ion implantation window to form ion implantation regions in the sidewall surface of the j-1th level trench and in the bottom surface of the Mth level trench.

2. The preparation method according to claim 1, characterized in that The epitaxial layer and the ion implantation region have different doping types to form a junction controlled diode; After forming a plurality of ion implantation regions in the surface of the M-th level trench structure, the method further includes: Retaining the first mask layer having the first through hole and removing other mask layers, forming an ohmic contact layer in the M-level trench structure, wherein the ohmic contact layer covers the surface of the M-level trench structure and the upper surface of the epitaxial layer exposed by the first through hole, so as to form a plurality of junction-controlled diodes based on the M-level trench structure; The M-level trench structure is filled with a dielectric material.

3. The preparation method according to claim 1, characterized in that The i-th mask layer and the (i+1)-th mask layer have a wet etching selectivity ratio of not less than 100.

4. The preparation method according to claim 1, characterized in that The thicknesses of the second mask layer to the M+1th mask layer are all smaller than the thickness of the first mask layer.

5. The preparation method according to claim 1, characterized in that The thicknesses of the second mask layer to the M+1th mask layer are all the same.

6. The preparation method according to any one of claims 1 to 5, characterized in that The epitaxial layer is an N-type doped silicon carbide layer; Ion implantation is performed on the surface of the M-level trench structure based on P-type ions.

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