A silicon carbide mosfet device and method of manufacture thereof

Abstract

The application discloses a silicon carbide MOSFET device and a preparation method thereof. A short-circuit resistance enhancement region is additionally arranged beside a channel region, the effective channel length of the device is increased, the ability of the device to resist short-circuit current impact is improved, and the short-circuit resistance time of the device is increased. A current diffusion region is arranged between the short-circuit resistance enhancement regions to balance the influence of the short-circuit resistance enhancement regions on the current conduction ability of the device. An electric field modulation region is additionally arranged between well regions, when the device works in a blocking state, the short-circuit resistance enhancement region is effectively prevented from being threatened by a high electric field, and the blocking ability of the device is ensured. A current diffusion region is additionally arranged between the electric field modulation regions, and a current modulation region is arranged above the current diffusion region, so that the current conduction ability of the device is reduced. The device structure and the preparation method are simple, compatible with a traditional silicon carbide MOSFET preparation process, and can realize mass production.

Description

TECHNICAL FIELD

[0001] The present application relates to a kind of switching devices, especially to a kind of silicon carbide MOSFET device and its preparation method. BACKGROUND

[0002] Silicon carbide (SiC) is a third-generation semiconductor material, with large band gap, high critical breakdown field strength, high thermal conductivity and other excellent characteristics. The power device based on SiC material has high breakdown voltage, high power density, high working frequency and other excellent performance. SiC MOSFET is a voltage-controlled switching device, which has competitiveness in high temperature, high frequency, high voltage and high power applications. Using it to replace silicon-based devices can reduce the system size to 1 / 3 of the original. However, the high operating junction temperature and power density of SiC MOSFET put strict requirements on its reliability. As a switching tube device, short circuit condition is an extreme condition that SiC MOSFET is prone to experience. In the on-state of the gate, the device will directly withstand the impact of bus voltage and short circuit current. How to improve the short circuit resistance of the device is an important problem that needs to be solved in device design. Compared with silicon-based devices (short circuit resistance time ≥ 10 μs), the short circuit resistance time of SiC MOSFET is shorter, about 3 μs, mainly due to its shorter channel and lower on-resistance. Lower short circuit resistance time is not conducive to feedback control of the drive signal, affecting the reliability of the system, and directly increasing the channel length will affect the current conduction capability of the device and the sensitivity of the device. SUMMARY

[0003] The purpose of the present application is to decouple the current conduction capability and short circuit resistance of the device, and to provide a silicon carbide MOSFET device. Another purpose of the present application is to provide a preparation method of the device.

[0004] Technical scheme: The silicon carbide MOSFET device according to the present application comprises, from bottom to top, a drain electrode, a drain ohmic contact layer, a heavily doped substrate of a first doping type, a lightly doped first epitaxial layer of a first doping type, a gate dielectric layer, a polysilicon layer of a first doping type, a source ohmic contact layer, a passivation layer, a source electrode and a gate electrode. The top of the lightly doped first epitaxial layer of a first doping type is provided with a pair of well regions of a second doping type and a channel region of a second doping type, and the well region of a second doping type is provided with a source region of a first doping type and a contact region of a second doping type. A short circuit resistance enhancement region of a second doping type is provided between the well regions of a second doping type and beside the channel region of a second doping type to increase the channel length and improve the resistance to short circuit current impact.

[0005] Further, the first doping type is N-type, and the second doping type is P-type.

[0006] Further, the short-circuit resistance enhancement region of the second doping type is arranged in parallel to the channel region of the second doping type, and the short-circuit resistance enhancement region is adjacent to the channel region to resist the impact of short-circuit current together with the channel region, effectively increasing the length of the channel region and increasing the short-circuit resistance time of the device.

[0007] Further, the first current diffusion region for balancing the influence of the short-circuit resistance enhancement region of the second doping type on the current on-off capability of the device is arranged between the short-circuit resistance enhancement regions of the second doping type, so as to reduce the influence of the short-circuit resistance enhancement region on the current on-off capability of the device and ensure the sensitivity of the device.

[0008] Further, the short-circuit resistance enhancement region of the second doping type is arranged in multiple groups perpendicularly to the channel region of the second doping type, and the short-circuit resistance enhancement region of the second doping type is arranged in the first current diffusion region for balancing the influence of the short-circuit resistance enhancement region of the second doping type on the current on-off capability of the device, which can increase the area of the short-circuit resistance enhancement region to improve the ability of the device to resist the impact of short-circuit current, and improve the current on-off capability of the first current diffusion region by increasing the doping concentration of the first current diffusion region to ensure the sensitivity of the device.

[0009] Further, the doping concentration of the first current diffusion region is greater than the doping concentration of the lightly doped first epitaxial layer of the first doping type, and the depth of the first current diffusion region is less than, equal to, or greater than the depth of the short-circuit resistance enhancement region of the second doping type. In the limited space, the short-circuit resistance enhancement region of the second doping type is arranged to be large enough, and in order to balance the influence of the region on the current on-off capability of the device, the doping concentration of the first current diffusion region can be increased or the area of the first current diffusion region can be increased by extending downward.

[0010] Further, the electric field modulation region for maintaining the blocking capability of the device by shielding the short-circuit resistance enhancement region from high electric field is arranged below the short-circuit resistance enhancement region of the second doping type and beside the well region of the second doping type, so as to ensure the effectiveness of the device.

[0011] Further, the second current diffusion region for balancing the influence of the electric field modulation region on the current on-off capability of the device is arranged between the electric field modulation regions, and the second current diffusion region and the electric field modulation region are arranged between the short-circuit resistance enhancement region of the second doping type and the channel region of the second doping type to adjust the current of the second current diffusion region, so as to improve the sensitivity of the device on the premise of ensuring the effectiveness of the device.

[0012] The application further provides a preparation method of the silicon carbide MOSFET device.

[0013] Step 1, a heavily doped substrate of a first doping type is prepared, and a lightly doped first epitaxial layer of the first doping type is formed on the upper surface of the substrate.

[0014] Step 2, forming a well region of the second doping type and a channel region of the second doping type on the upper surface of the lightly doped first epitaxial layer of the first doping type by an ion implantation process;

[0015] Step 3, forming a source region of the first doping type and a contact region of the second doping type in the well region of the second doping type by an ion implantation process;

[0016] Step 4, forming a short-circuit resistance enhancement region of the second doping type in the first epitaxial layer of the first doping type between the well regions of the second doping type by an ion implantation process;

[0017] Step 5, forming a gate dielectric layer on the upper surface of the first epitaxial layer of the first doping type, and growing a polysilicon layer on the gate dielectric layer;

[0018] Step 6, using a photolithography and etching process, forming a passivation layer, and forming a source electrode window in the passivation layer, forming a source ohmic contact layer in the source electrode window, and forming a source electrode on the surface of the source ohmic contact layer; forming a gate electrode window in the passivation layer corresponding to the position of the polysilicon layer, and forming a gate electrode in the gate electrode window;

[0019] Step 7, forming a drain ohmic contact layer on the bottom surface of the heavily doped substrate of the first doping type, and forming a drain electrode on the surface of the drain ohmic contact layer.

[0020] Further, the step 4 further comprises implanting to form a first current diffusion region between the short-circuit resistance enhancement regions of the second doping type.

[0021] Further, the doping concentration of the first current diffusion region is greater than the doping concentration of the lightly doped first epitaxial layer of the first doping type; the depth of the first current diffusion region is less than, equal to, or greater than the depth of the short-circuit resistance enhancement region of the second doping type.

[0022] Further, the step 1 or 3 or 4 further comprises epitaxially forming or implanting to form an electric field modulation region in the lightly doped first epitaxial layer of the first doping type.

[0023] Further, the step 1 or 3 or 4 further comprises epitaxially forming or implanting to form a second current diffusion region and a current modulation region in the lightly doped first epitaxial layer of the first doping type.

[0024] Beneficial effects: compared with the prior art, the present application has the following remarkable advantages: 1, short-circuit resistance enhancement regions are additionally provided beside the channel region, the effective channel length of the device is increased, the ability of the device to resist short-circuit current impact is improved, and the short-circuit resistance time of the device is increased; 2, current diffusion regions are arranged between the short-circuit resistance enhancement regions to balance the influence of the short-circuit resistance enhancement regions on the current conduction ability of the device; 3, electric field modulation regions are additionally provided between the well regions, which effectively prevent the short-circuit resistance enhancement regions from being threatened by high electric fields when the device works in a blocking state, and ensure the blocking ability of the device; 4, current diffusion regions are additionally provided between the electric field modulation regions, and current modulation regions are arranged above the current diffusion regions, which reduce the current conduction ability of the device; 5, the device structure and preparation method are simple, compatible with the traditional silicon carbide MOSFET preparation process, and can realize mass production. BRIEF DESCRIPTION OF DRAWINGS

[0025] Figure 1 is a structural schematic diagram of the present application;

[0026] Figure 2 is a structural top view of the present application;

[0027] Figure 3 is a structural schematic diagram of embodiment 2 of the present application;

[0028] Figure 4 is a structural top view of embodiment 2 of the present application;

[0029] Figure 5 is a structural top view of embodiment 3 of the present application;

[0030] Figure 6 is a structural front view of embodiment 3 of the present application;

[0031] Figure 7 is a structural rear view of embodiment 3 of the present application;

[0032] Figure 8 is a structural schematic diagram of embodiment 4 of the present application. DETAILED DESCRIPTION

[0033] The technical solutions of the present application will be further described below in combination with the drawings.

[0034] Embodiment 1

[0035] As Figure 1 and 2A silicon carbide MOSFET device is shown, comprising, from bottom to top, a drain electrode 115, a drain ohmic contact layer 111, a heavily doped substrate 104 of a first doping type, a lightly doped first epitaxial layer 102 of the first doping type, a gate dielectric layer 108, a polysilicon layer 109 of the first doping type, a source ohmic contact layer 110, a passivation layer 112, a source electrode 113 and a gate electrode 114; a pair of well regions 103 of a second doping type and a channel region 106 of the second doping type are provided on top of the lightly doped first epitaxial layer 102 of the first doping type, a source region 104 of the first doping type and a contact region 105 of the second doping type are provided in the well region 103 of the second doping type, and a short-circuit resistant enhancement region 107 of the second doping type is provided between the well regions 103 of the second doping type and beside the channel region 106 of the second doping type in parallel to the channel region 106 of the second doping type for increasing the channel length and improving the short-circuit current resistance. The first doping type is N-type and the second doping type is P-type.

[0036] A method for manufacturing the silicon carbide MOSFET device is shown, comprising the following steps:

[0037] Step 1, a heavily doped substrate 101 of a first doping type is prepared, and a lightly doped first epitaxial layer 102 of the first doping type is formed on the top surface of the heavily doped substrate 101;

[0038] Step 2, a well region 103 of a second doping type and a channel region 106 of the second doping type are formed on the top surface of the lightly doped first epitaxial layer 102 of the first doping type by ion implantation;

[0039] Step 3, a source region 104 of the first doping type and a contact region 105 of the second doping type are formed in the well region 103 of the second doping type by ion implantation;

[0040] Step 4, a short-circuit resistant enhancement region 107 of the second doping type is formed between the well regions 103 of the second doping type in the first epitaxial layer 102 of the first doping type by ion implantation;

[0041] Step 5, a gate dielectric layer 108 is formed on the top surface of the first epitaxial layer 102 of the first doping type, and a polysilicon layer 109 is grown on the gate dielectric layer 108;

[0042] Step 6, a passivation layer 112 is formed by using photolithography and etching processes, a source window is formed in the passivation layer 112, a source ohmic contact layer 110 is formed in the source window, and a source electrode 113 is formed on the surface of the source ohmic contact layer 110; a gate window is formed in the passivation layer 112 corresponding to the position of the polysilicon layer 109, and a gate electrode 114 is formed in the gate window;

[0043] Step 7, forming a drain ohmic contact layer 111 on the bottom surface of the heavily doped substrate 101 of the first doping type, and forming a drain electrode 115 on the surface of the drain ohmic contact layer 111.

[0044] The above-mentioned silicon carbide MOSFET device, by adding the short-circuit resistant enhancement region 107 of the second doping type beside the channel region 106 of the second doping type, increases the effective channel length of the device, improves the ability of the device to resist short-circuit current impact, and increases the short-circuit resistant time of the device.

[0045] Embodiment 2

[0046] As shown in Figure 3 , 4 and 7, different from embodiment 1, the first current diffusion region 116 for balancing the influence of the short-circuit resistant enhancement region 107 of the second doping type on the current on ability of the device is also provided between the short-circuit resistant enhancement regions 107 of the second doping type. The doping concentration of the diffusion region 116 is greater than the doping concentration of the lightly doped first epitaxial layer 102 of the first doping type, and the depth of the first current diffusion region 116 is equal to the depth of the short-circuit resistant enhancement region 107 of the second doping type (the depth of the first current diffusion region 116 can also be set to be greater than or less than the depth of the short-circuit resistant enhancement region 107 of the second doping type according to the requirement of the current on ability).

[0047] The method for manufacturing the above-mentioned silicon carbide MOSFET device is different from embodiment 1 in that step 4 further includes implanting the first current diffusion region 116 between the short-circuit resistant enhancement regions 107 of the second doping type.

[0048] The above-mentioned silicon carbide MOSFET device, by adding the short-circuit resistant enhancement region 107 of the second doping type beside the channel region 106 of the second doping type, increases the effective channel length of the device, improves the ability of the device to resist short-circuit current impact, and increases the short-circuit resistant time of the device. Meanwhile, in order to balance the influence of the short-circuit resistant enhancement region 107 of the second doping type on the current on ability of the device, the first current diffusion region 116 is provided between the short-circuit resistant enhancement regions.

[0049] Embodiment 3

[0050] As shown in Figure 5 , 6 and 7, different from embodiment 2, the short-circuit resistant enhancement region 107 is provided in multiple (4 are drawn in the figure for convenience of display) perpendicularly to the channel region 106 of the second doping type, and the first current diffusion region 116 is provided in multiple (4 are drawn in the figure for convenience of display) perpendicularly to the short-circuit resistant enhancement region 107 of the second doping type.

[0051] The method for manufacturing the above-mentioned silicon carbide MOSFET device is the same as embodiment 2.

[0052] The above-mentioned silicon carbide MOSFET device, the plurality of short-circuit resistance enhancement regions 107 of the second doping type are arranged vertically to the channel region 106 of the second doping type, which can increase the effective area of the short-circuit resistance enhancement regions, and further maximize the ability of the device to resist short-circuit current impact, and increase the short-circuit resistance time of the device. Meanwhile, the first current diffusion regions 116 are arranged between the short-circuit resistance enhancement regions, the current conduction capacity is increased by increasing the depth of the first current diffusion regions 116, and the influence of the short-circuit resistance enhancement regions 107 of the second doping type on the current conduction capacity of the device is maximally balanced.

[0053] Embodiment 4

[0054] As shown in Figure 8 different from embodiment 2, a set of electric field modulation regions 117 for maintaining the blocking ability of the device threatened by high electric field are arranged below the short-circuit resistance enhancement regions 107 of the second doping type and beside the well region 103 of the second doping type, the current diffusion regions 118 for balancing the influence of the electric field modulation regions 117 on the current conduction capacity of the device are arranged between the electric field modulation regions 117, and the current modulation regions 119 for adjusting the current of the current diffusion regions 118 are arranged between the current diffusion regions 118 and the electric field modulation regions 117 and the short-circuit resistance enhancement regions 107 of the second doping type and the channel region 106 of the second doping type.

[0055] The preparation method of the silicon carbide MOSFET device is different from embodiment 2 and further includes the preparation of the electric field modulation regions 117, the second current diffusion regions 118 and the current modulation regions 119. The electric field modulation regions 117, the second current diffusion regions 118 and the current modulation regions 119 can be epitaxially generated or generated by ion implantation process, but the electric field modulation regions 117 and the second current diffusion regions 118 cannot be epitaxially formed at the same time. Therefore, the electric field modulation regions 117 can be epitaxially formed in step 1, and the second current diffusion regions 118 and the current modulation regions 119 can be ion implanted in step 3 or step 4; or the electric field modulation regions 117, the second current diffusion regions 118 and the current modulation regions 119 can be ion implanted in step 3 or step 4; or the electric field modulation regions 117 and the current modulation regions 119 can be epitaxially formed in step 1, and the second current diffusion regions 118 can be ion implanted in step 3 or step 4, and the like.

[0056] The above-mentioned silicon carbide MOSFET device, in addition to setting the short-circuit resistance enhancement region 107 of the second doping type and the first current diffusion region 116, a set of electric field modulation regions 117 for maintaining the blocking capability of the device threatened by high electric field is arranged below the short-circuit resistance enhancement region 107 of the second doping type and beside the well region 103 of the second doping type, which effectively prevents the short-circuit resistance enhancement region 107 of the second doping type from being threatened by high electric field when the device works in the blocking state, and ensures the blocking capability of the device; the current diffusion regions 118 for balancing the influence of the current diffusion regions 118 on the current on-state capability of the device are arranged between the electric field modulation regions 117; the current modulation regions 119 for adjusting the current of the current diffusion regions 118 are arranged between the current diffusion regions 118 and the electric field modulation regions 117 and the short-circuit resistance enhancement region 107 of the second doping type and the channel region 106 of the second doping type, so as to reduce the influence of the electric field modulation regions on the current on-state capability of the device.

Claims

1. A silicon carbide MOSFET device, comprising, arranged in sequence from bottom to top, a drain electrode (115), a drain ohmic contact layer (111), a heavily doped substrate (101) of a first doping type, a lightly doped first epitaxial layer (102) of a first doping type, a gate dielectric layer (108), a polysilicon layer (109) of a first doping type, a source ohmic contact layer (110), a passivation layer (112), a source electrode (113) and a gate electrode (114); a pair of well regions (103) of a second doping type and a channel region (106) of a second doping type are provided on top of the lightly doped first epitaxial layer (102); a source region (104) of a first doping type and a contact region (105) of a second doping type are provided in the well region (103) of the second doping type; and the device is characterized in that: A second doping type short-circuit tolerance enhancement region (107) for increasing the channel length and improving resistance to short-circuit current impact is provided between the second doping type well regions (103) and next to the second doping type channel region (106); a first current diffusion region (116) for balancing the influence of the second doping type short-circuit tolerance enhancement regions (107) on the current conduction capability of the device is provided between the second doping type short-circuit tolerance enhancement regions (107); a plurality of groups of the second doping type short-circuit tolerance enhancement regions (107) are provided perpendicular to the second doping type channel region (106); a first current diffusion region (116) for balancing the influence of the second doping type short-circuit tolerance enhancement regions (107) on the current conduction capability of the device is provided between the second doping type short-circuit tolerance enhancement regions (107); the second doping type short-circuit tolerance enhancement regions (107) and the first current diffusion region (116) for balancing the influence of the second doping type short-circuit tolerance enhancement regions (107) on the current conduction capability of the device are spaced apart.

2. A silicon carbide MOSFET device, comprising, arranged in sequence from bottom to top, a drain electrode (115), a drain ohmic contact layer (111), a heavily doped substrate (101) of a first doping type, a lightly doped first epitaxial layer (102) of a first doping type, a gate dielectric layer (108), a polysilicon layer (109) of a first doping type, a source ohmic contact layer (110), a passivation layer (112), a source electrode (113) and a gate electrode (114); a pair of well regions (103) of a second doping type and a channel region (106) of a second doping type are provided on top of the lightly doped first epitaxial layer (102) of the first doping type, and a source region (104) of a first doping type and a contact region (105) of a second doping type are provided in the well region (103) of the second doping type; and the device is characterized in that: A second doping type short circuit tolerance enhancement region (107) for increasing the channel length and improving resistance to short circuit current impact is provided between the second doping type well regions (103) and next to the second doping type channel region (106); a first current diffusion region (116) for balancing the influence of the second doping type short circuit tolerance enhancement region (107) on the current conduction capability of the device is provided between the second doping type short circuit tolerance enhancement region (107); and a group of shielding short circuits are provided below the second doping type short circuit tolerance enhancement region (107) and next to the second doping type well region (103). An electric field modulation region (117) is provided for maintaining the device blocking capability when the tolerance enhancement region (107) is threatened by a high electric field; a second current diffusion region (118) is provided between the electric field modulation regions (117) to balance the influence of the electric field modulation region (117) on the device current conduction capability; and a current modulation region (119) is provided between the second current diffusion region (118) and the electric field modulation region (117) and the second doping type short circuit tolerance enhancement region (107) and the second doping type channel region (106) for regulating the current of the second current diffusion region (118).

3. The silicon carbide MOSFET device according to claim 1 or 2, characterized in that: The first doping type is N-type, and the second doping type is P-type.

4. The silicon carbide MOSFET device according to claim 1 or 2, characterized in that: The doping concentration of the first current diffusion region (116) is greater than the doping concentration of the lightly doped first epitaxial layer (102) of the first doping type.

5. A method for preparing a silicon carbide MOSFET device according to any one of claims 1 to 4, characterized in that: The steps include: Preparing a heavily doped substrate (101) of a first doping type, and forming a lightly doped first epitaxial layer (102) of the first doping type on the upper surface thereof; Forming a well region (103) of a second doping type and a channel region (106) of a second doping type on the upper surface of a lightly doped first epitaxial layer (102) of a first doping type by an ion implantation process; forming a source region (104) of the first doping type and a contact region (105) of the second doping type in a well region (103) of the second doping type by an ion implantation process; forming a second doping type short circuit tolerance enhancement region (107) within the first doping type first epitaxial layer (102) and between the second doping type well regions (103) by an ion implantation process; forming a gate dielectric layer (108) on the upper surface of the first epitaxial layer (102) of the first doping type, and growing a polysilicon layer (109) on the gate dielectric layer (108); Using photolithography and etching processes, a passivation layer (112) is formed, a source window is formed in the passivation layer (112), a source ohmic contact layer (110) is formed in the source window, and a source electrode (113) is formed on the surface of the source ohmic contact layer (110); a gate window is formed in the passivation layer (112) at a position corresponding to the polysilicon layer (109), and a gate electrode (114) is formed in the gate window; A drain ohmic contact layer (111) is formed on the bottom surface of a heavily doped substrate (101) of a first doping type, and a drain electrode (115) is formed on the surface of the drain ohmic contact layer (111).

6. The method for preparing a silicon carbide MOSFET device according to claim 5, wherein: The first doping type is N-type, and the second doping type is P-type.

7. The method for preparing a silicon carbide MOSFET device according to claim 5, wherein: The step of injecting the second doping type short circuit tolerance enhancement region (107) also includes injecting to form a first current diffusion region (116).

8. The method for preparing a silicon carbide MOSFET device according to claim 7, wherein: The doping concentration of the first current diffusion region (116) is greater than the doping concentration of the lightly doped first epitaxial layer (102) of the first doping type.

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