Method of forming a semiconductor structure

Abstract

The present disclosure provides a forming method of a semiconductor structure, and relates to the technical field of semiconductor. The forming method comprises: forming an initial semiconductor structure comprising a plurality of channels; forming a stack structure in each channel, and the stack structure extends to the surface of the initial semiconductor structure, the stack structure comprising an insulating layer, an oxidation layer and a sacrificial layer; introducing a protective gas and an auxiliary gas into each channel and reacting to form a protective layer conformally on the surface of the sacrificial layer, the protective gas comprising silicon ions, and the auxiliary gas comprising oxygen ions; etching the stack structure with the protective layer to remove part of the stack structure located at the bottom of the channel and remove the stack structure located at the surface of the functional layer to expose the surface of the substrate and the functional layer. By forming a protective layer on each film layer in the etched device channel, the present disclosure ensures the integrity of the film layer morphology and etching profile after etching, and provides a good structure foundation for subsequent device process.

Description

Technical Field

[0001] This disclosure relates to the field of semiconductor technology, and more specifically, to a method for forming a semiconductor structure. Background Technology

[0002] Memory is widely used in smart devices such as mobile phones and tablets due to its small size, high transmission speed, and high integration. With the evolution of semiconductor manufacturing processes and the continuous reduction in the size of terminal devices, the size of memory is also shrinking, and the feature size of the device is also decreasing accordingly.

[0003] Currently, device feature sizes can reach tens of nanometers or even smaller, which increases the difficulty of manufacturing processes. Especially in etching processes, as feature sizes decrease, defects in the etching profile can occur, thus affecting the functionality of subsequent devices.

[0004] It should be noted that the information disclosed in the background section above is only used to enhance the understanding of the background of this disclosure, and therefore may include information that does not constitute prior art known to those skilled in the art. Summary of the Invention

[0005] In view of this, a method for forming a semiconductor structure is provided, which ensures the integrity and collimation of the etching profile by forming a protective layer when etching a film layer on a device channel.

[0006] Other features and advantages of this disclosure will become apparent from the following detailed description, or may be learned in part from practice of this disclosure.

[0007] According to one aspect of this disclosure, a method for forming a semiconductor structure is provided, the method comprising:

[0008] An initial semiconductor structure is formed, the initial semiconductor structure including a substrate, a functional layer and a plurality of spaced channels formed on the functional layer;

[0009] A stacked structure is formed on the bottom wall and sidewall of each of the channels, and the stacked structure extends to the surface of the initial semiconductor structure, wherein the stacked structure includes an insulating layer, an oxide layer and a sacrificial layer formed sequentially along the surface away from the initial semiconductor structure;

[0010] A protective gas and an auxiliary gas are introduced into each of the channels and reacted to form a protective layer conformally on the surface of the sacrificial layer, wherein the protective gas includes silicon ions and the auxiliary gas includes oxygen ions;

[0011] The stacked structure having the protective layer is etched to remove a portion of the stacked structure at the bottom of the trench and to remove the stacked structure at the surface of the functional layer, so as to expose the substrate and the surface of the functional layer.

[0012] In one exemplary embodiment of this disclosure, within the same channel, the projected area of ​​the protective layer on the substrate is one-tenth to one-fifth of the projected area of ​​the opening of the channel on the substrate.

[0013] In one exemplary embodiment of this disclosure, the protective gas includes at least one of silicon tetrachloride, silane, methylene silane, ethoxysilane, or silicate.

[0014] In one exemplary embodiment of this disclosure, the auxiliary gas includes at least one of oxygen, methanol, or ethanol.

[0015] In one exemplary embodiment of this disclosure, the flow rate of the protective gas is 10 sccm to 100 sccm, and the flow rate of the auxiliary gas is 100 sccm to 500 sccm.

[0016] In one exemplary embodiment of this disclosure, the method includes:

[0017] Under pressure conditions of 5mT to 30mT, the auxiliary gas reacts with the protective gas.

[0018] In one exemplary embodiment of this disclosure, the method includes:

[0019] Under a bias voltage of 1000W to 1500W, the auxiliary gas reacts with the protective gas.

[0020] In one exemplary embodiment of this disclosure, the method for forming the initial semiconductor structure further includes:

[0021] A conductive layer is formed on the substrate;

[0022] Multiple channels are formed within the conductive layer, thereby creating multiple spaced conductive portions in the conductive layer.

[0023] In one exemplary embodiment of this disclosure, the method further includes:

[0024] A first source / drain electrode is formed on the substrate, and the orthographic projection of the first source / drain electrode on the bottom surface of the substrate does not coincide with the orthographic projection of the conductive portion on the bottom surface of the substrate.

[0025] In one exemplary embodiment of this disclosure, the method further includes:

[0026] Remove the remaining protective layer to expose the sidewalls of the sacrificial layer so that the opening sidewalls of the trench are aligned with the substrate.

[0027] In one exemplary embodiment of this disclosure, the method further includes:

[0028] Remove the remaining sacrificial layer to expose the first sidewall, the second sidewall, and the third sidewall, wherein the first sidewall and the second sidewall are two non-coplanar side surfaces on the oxide layer, the third sidewall is a side surface of the insulating layer, and the second sidewall and the third sidewall are coplanar;

[0029] A semiconductor layer is formed conformally on the surface formed by the first sidewall, the second sidewall, and the third sidewall, and the semiconductor layer is connected to the first source and drain.

[0030] In one exemplary embodiment of this disclosure, the method further includes:

[0031] An insulating material layer is filled within the remaining opening portion of the channel, the surface of which is flush with the surface of the initial semiconductor structure;

[0032] A second source / drain electrode is formed on the surface where the insulating material layer and the semiconductor layer are jointly formed to obtain the target semiconductor structure. The orthogonal projection of the second source / drain electrode on the substrate does not coincide with the orthogonal projection of the conductive portion on the substrate.

[0033] In one exemplary embodiment of this disclosure, the initial semiconductor structure further includes a barrier layer formed between the conductive layer and the substrate, the barrier layer being used to prevent the conductive layer from diffusing into the substrate.

[0034] The semiconductor structure formation method disclosed herein involves introducing a protective gas and an auxiliary gas into a channel. The protective gas and the auxiliary gas react to generate a protective layer, which can protect the film layer on the channel sidewalls during subsequent etching. After etching, a complete contour can be formed, reducing structural defects caused by the etching process and improving the collimation of the etched sidewalls. In addition, the protective layer formed by the protective gas and the auxiliary gas is easy to remove, does not increase the complexity of the process, and does not adversely affect subsequent processes. Moreover, this protective layer is versatile and can be applied to etching processes of various film layers. This formation method can improve the overall yield of the device.

[0035] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0036] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this disclosure and, together with the description, serve to explain the principles of this disclosure. It is obvious that the drawings described below are merely some embodiments of this disclosure, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0037] Figure 1 This is a flowchart of a method for forming a semiconductor structure in an exemplary embodiment of the present disclosure.

[0038] Figure 2 This is a schematic diagram of a prior art semiconductor structure in an exemplary embodiment of this disclosure.

[0039] Figure 3 This is a schematic diagram of the substrate and the first source / drain of the semiconductor structure in an exemplary embodiment of the present disclosure.

[0040] Figure 4 This is a schematic diagram of the conductive layer of a semiconductor structure in an exemplary embodiment of this disclosure.

[0041] Figure 5 This is a schematic diagram of the structure of the sub-conductive layer of a semiconductor structure in an exemplary embodiment of this disclosure.

[0042] Figure 6 This is a schematic diagram of the channel structure of a semiconductor structure in an exemplary embodiment of this disclosure.

[0043] Figure 7 This is a schematic diagram of the stacked structure of a semiconductor structure in an exemplary embodiment of the present disclosure.

[0044] Figure 8 This is a schematic diagram of the protective layer of a semiconductor structure in an exemplary embodiment of this disclosure.

[0045] Figure 9 This is a schematic diagram of the etched semiconductor structure in an exemplary embodiment of this disclosure.

[0046] Figure 10 This is a schematic diagram of the semiconductor structure after removing the sacrificial layer in an exemplary embodiment of this disclosure.

[0047] Figure 11 This is a schematic diagram of a semiconductor structure in which a semiconductor layer is formed in an exemplary embodiment of the present disclosure.

[0048] Figure 12 This is a schematic diagram of a semiconductor structure in which an insulating material layer is formed, according to an exemplary embodiment of the present disclosure.

[0049] Figure 13This is a schematic diagram of a semiconductor structure in an exemplary embodiment of the present disclosure.

[0050] The reference numerals in the attached figures are explained as follows:

[0051] 1000, Defect; 2000, Channel; 100, Substrate; 120, Stacked structure; 121, Insulating layer; 122, Oxide layer; 1221, First sidewall; 1222, Second sidewall; 123, Sacrificial layer; 1231, Third sidewall; 200, Protective layer; 310, First source / drain; 320, Second source / drain; 400, Conductive layer; 410, Sub-conductive layer; 420, Conductive part; 401, Barrier layer; 500, Semiconductor layer; 600, Insulating material layer; 700, Isolation layer. Detailed Implementation

[0052] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, they are provided so that this disclosure will be thorough and complete, and will fully convey the concept of the exemplary embodiments to those skilled in the art. The same reference numerals in the drawings denote the same or similar structures, and therefore detailed descriptions of them will be omitted. Furthermore, the drawings are merely illustrative of this disclosure and are not necessarily drawn to scale.

[0053] Although relative terms such as "up" and "down" are used in this specification to describe the relative relationship of one component of an icon to another, these terms are used only for convenience, such as according to the orientation of the examples shown in the accompanying drawings. It is understood that if the device of the icon is flipped upside down, the component described as "up" will become the component described as "down." When a structure is "up" of another structure, it may mean that the structure is integrally formed on the other structure, or that the structure is "directly" mounted on the other structure, or that the structure is "indirectly" mounted on the other structure through another structure.

[0054] The terms “a,” “one,” “the,” “the,” and “at least one” are used to indicate the presence of one or more elements / components / etc.; the terms “including” and “having” are used to indicate an open-ended inclusion and to mean that there may be other elements / components / etc. in addition to the listed elements / components / etc.; the terms “first,” “second,” and “third,” etc., are used only as markers and are not a limitation on the number of objects.

[0055] In related technologies, transistors, as semiconductor devices, are indispensable components of memory cells. They are widely used in electronic circuits, serving functions such as switching control, signal amplification, and voltage regulation. Junction Field-Effect Transistors (JFETs), as voltage-controlled semiconductor devices, can control the current between the source and drain by changing the voltage between the gate and source, thus achieving circuit control.

[0056] In the transistor fabrication process, a gate oxide layer is formed in the transistor channel to isolate the gate and source / drain electrodes. However, due to the small feature size of existing devices, the opening size of the channel is also small, increasing the difficulty of the deposition and etching processes within the channel opening. Currently, during the etching of the gate oxide layer, the different etch selectivity ratios between the gate oxide layer and other film layers result in defects 1000 forming on the sidewalls of the etched channel structure. Figure 2 As shown, a large opening is formed on the side of the channel away from the substrate, resulting in an incomplete etching profile, which affects subsequent process steps, and may even increase the leakage current of the device, affect the threshold voltage of the device, and reduce the overall performance of the device.

[0057] Based on this, the present disclosure provides a method for forming a semiconductor structure, such as... Figure 1 As shown, combined with Figures 3 to 13 The formation method includes steps S10 to S40.

[0058] In step S10: forming an initial semiconductor structure, the initial semiconductor structure including a substrate 100, a functional layer and a plurality of spaced channels 2000 formed on the functional layer;

[0059] Step S20: A stacked structure 120 is formed on the bottom wall and sidewall of each channel 2000, and the stacked structure 120 extends to the surface of the initial semiconductor structure, wherein the stacked structure 120 includes an insulating layer 121, an oxide layer 122 and a sacrificial layer 123 sequentially formed along the surface away from the initial semiconductor structure.

[0060] Step S30: A protective gas and an auxiliary gas are introduced into each channel 2000 and reacted to form a protective layer 200 on the surface of the sacrificial layer 123. The protective gas includes silicon ions and the auxiliary gas includes oxygen ions.

[0061] Step S40: Etch the stacked structure 120 with protective layer 200 to remove part of the stacked structure 120 located at the bottom of the channel 2000 and the stacked structure 120 located on the surface of the functional layer, so as to expose the substrate 100 and the surface of the functional layer.

[0062] The semiconductor structure formation method disclosed herein involves introducing a protective gas and an auxiliary gas into a channel 2000. The protective gas and the auxiliary gas react to generate a protective layer 200. When etching the stacked structure 120 within the channel 2000, the protective layer 200 can protect the film layer on the sidewall of the channel 2000, ensuring the etching integrity between the sidewall of the channel 2000 and the initial semiconductor structure surface, avoiding etching defects at the connection, forming a complete etching profile, reducing structural defects generated by the etching process, and improving the collimation of the etched sidewall. In addition, the protective layer 200 formed by the protective gas and the auxiliary gas is easy to remove, does not increase the complexity of the process, and does not adversely affect subsequent processes. Moreover, this protective layer 200 is versatile and can be applied to etching processes of various film layers, solving the problem of device performance degradation caused by the cumulative effect of etching defects in multiple processes.

[0063] The steps of the method for forming a semiconductor structure according to the embodiments of this disclosure will now be described in detail with reference to the accompanying drawings:

[0064] In the embodiments provided in this disclosure, such as Figures 3 to 6 As shown, in step S10, an initial semiconductor structure is formed, which includes a substrate 100, a functional layer, and a plurality of spaced channels 2000 formed on the functional layer.

[0065] The substrate 100 can be a semiconductor substrate, such as a silicon (Si) substrate, a germanium (Ge) substrate, a silicon-germanium (GeSi) substrate, SOI (Silicon on Insulator), or GOI (Germanium on Insulator). In some embodiments, the semiconductor substrate can also be a substrate including other elemental semiconductors or compound semiconductors, such as silicon carbide (SiC), indium phosphide (InP), or gallium arsenide (GaAs). The embodiments provided in this disclosure are illustrated using a substrate 100 comprising silicon (Si) ions as an example. Of course, for other types of substrates, corresponding modifications or improvements can be made to the embodiments of this disclosure, all of which are within the protection scope of this disclosure.

[0066] Before forming the channel 2000 on the substrate 100, such as Figure 3As shown, the formation method further includes forming a first source / drain 310 on the substrate 100. The substrate 100 may include an epitaxial layer, and the first source / drain 310 can be formed by doping the epitaxial layer. For example, trivalent elements such as boron (B), gallium (Ga), and indium (In) can be doped onto the substrate 100 to form a P-type source / drain region, which is then formed through etching or other processes. Alternatively, pentavalent elements such as phosphorus (P), arsenic (As), and antimony (Sb) can be doped onto the substrate 100 to form an N-type source / drain region, which is then formed through etching or other processes. The type of the first source / drain 310 can be selected according to the actual structure of the device. Of course, to isolate multiple first source / drains 310, an insulating structure can be formed between two adjacent first source / drains 310, such as a silicon dioxide insulating structure. This insulating structure is made of insulating materials commonly used in the art and will not be described in detail here.

[0067] The functional layer may include a conductive layer 400 formed on the substrate 100. After the first source / drain 310 is formed, as... Figure 4 As shown, the forming method further includes: forming a conductive layer 400 on a substrate 100; forming a plurality of isolation trenches within the conductive layer 400 to divide the conductive layer 400 into a plurality of sub-conductive layers 410; and filling the plurality of isolation trenches with an isolation material to form an isolation layer 700, such as... Figure 5 As shown; channels 2000 are formed within each sub-conductive layer 410 to form multiple spaced conductive portions 420, such as Figure 6 As shown. Each conductive portion 420 can serve as a gate in subsequent devices.

[0068] The conductive layer 400 can be made of metallic materials, such as one or more of the following metals: aluminum (Al), copper (Cu), tungsten (W), titanium (Ti), tantalum (Ta), cobalt (Co), and nickel (Ni). The conductive layer 400 can be formed using chemical vapor deposition (CVD), such as atmospheric pressure chemical vapor deposition (APCVD), low pressure chemical vapor deposition (LPCVD), and atomic layer deposition (ALD); or physical vapor deposition (PVD), such as sputtering and electron beam evaporation; or atomic layer epitaxy (ALE); or chemical vapor infiltration (CVI).

[0069] Before forming the conductive layer 400, such as Figures 3 to 13 As shown, a barrier layer 401 can also be formed within the initial semiconductor structure. The barrier layer 401 is used to prevent the conductive layer 400 from diffusing into the substrate 100. Specifically, when the conductive layer 400 is tungsten, the barrier layer 401 can prevent the diffusion of tungsten and other metal atoms in the semiconductor device. The barrier layer 401 can be formed from materials such as titanium nitride (TiN), tantalum nitride (TaN), tungsten nitride (WN), titanium silicide (TiSi2), and tantalum silicide (TaSi2). It can be formed using methods such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), and electrochemical deposition. In some embodiments, the barrier layer 401 can be a single-layer structure or a multi-layer structure. The material, formation method, and number of layers of the barrier layer 401 can be selected according to the actual structural and functional requirements of the device.

[0070] Forming a channel 2000 within each sub-conductive layer 410 includes etching the sub-conductive layer 410 in a direction perpendicular to the substrate 100, from a direction away from the substrate 100 towards a direction closer to the substrate 100, until the surface of the substrate 100 is exposed, thereby forming a channel 2000 within each sub-conductive layer 410. Each channel 2000 divides each sub-conductive layer 410 into two conductive portions 420. The orthographic projection of the conductive portion 420 onto the bottom surface of the substrate 100 does not coincide with the orthographic projection of the first source / drain electrode 310 onto the bottom surface of the substrate 100. That is, each first source / drain electrode 310 is located at the bottom of the channel 2000, while the conductive portion 420 is located at the sidewall of the channel 2000, thereby isolating the conductive portion 420 and the first source / drain electrode 310 in a direction perpendicular to the substrate 100.

[0071] The etching of each sub-conductive layer 410 can be performed using dry etching methods such as plasma etching, ion beam etching, chemical vapor etching (CVE), and laser etching, or wet etching.

[0072] In the embodiments provided in this disclosure, such as Figure 7 As shown, in step S20, a stacked structure 120 is formed on the bottom wall and sidewall of each channel 2000, and the stacked structure 120 extends to the surface of the initial semiconductor structure. The stacked structure 120 includes an insulating layer 121, an oxide layer 122 and a sacrificial layer 123 formed sequentially along the surface away from the initial semiconductor structure.

[0073] In the stacked structure 120, the insulating layer 121 covers the sidewalls and bottom walls of each channel 2000 and extends to the top surface of the initial semiconductor structure. It covers the sidewalls of the conductive portion 420 to provide insulation for the conductive portion 420. The insulating layer 121 can be formed using one or more materials such as silicon nitride (Si3N4), aluminum nitride (AlN), aluminum oxide (Al2O3), tantalum oxide (Ta2O5), or hafnium oxide (HfO2). The insulating layer 121 can be formed using methods such as atomic layer deposition (ALD), chemical vapor deposition (CVD), physical vapor deposition (PVD), and chemical solution deposition.

[0074] An oxide layer 122 is formed conformally on the insulating layer 121. It can serve as a gate oxide layer 122 formed on the initial semiconductor structure to provide electrical insulation and electric field control within the semiconductor structure. The oxide layer 122 can be formed using one or more of the following: silicon dioxide (SiO2), hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3), tantalum oxide (Ta2O5), lanthanum oxide (La2O3), yttrium oxide (Y2O3), hafnium silicon oxide (HfSiO), and zirconium silicon oxide (ZrSiO). The oxide layer 122 can be formed using methods such as atomic layer deposition (ALD), plasma-enhanced chemical vapor deposition (PECVD), sputtering, epitaxial growth, and sol-gel.

[0075] The sacrificial layer 123 is formed conformally on the oxide layer 122, and the sacrificial layer 123 provides a basis for the electrical connection structure of the subsequent structure. The sacrificial layer 123 can be formed using materials such as amorphous silicon (A-Si) or silicon (Si). The sacrificial layer 123 can be formed by chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), sputtering, or other thin film deposition techniques.

[0076] It should be noted that, in the embodiments of this disclosure, conformal formation refers to one film layer being formed on the surface of another film layer, and the cross-sectional shapes of the two film layers are the same or substantially the same in the direction perpendicular to the substrate 100, and the coverage area and formation position of the two film layers are also the same or substantially the same. Furthermore, in this disclosure, the materials and formation processes of the sacrificial layer 123, oxide layer 122, and insulating layer 121 can be adaptively selected and adjusted according to actual structural and process requirements.

[0077] In the embodiments provided in this disclosure, such as Figure 8 and Figure 9 As shown, in steps S30 and S40, a protective gas and an auxiliary gas are introduced into each channel 2000 and reacted to form a protective layer 200 on the surface of the sacrificial layer 123. The protective gas includes silicon ions and the auxiliary gas includes oxygen ions. The stacked structure 120 with the protective layer 200 is etched to remove a portion of the stacked structure 120 located at the bottom of the channel 2000 and to remove the stacked structure 120 located on the surface of the functional layer, so as to expose the substrate 100 and the surface of the functional layer.

[0078] After forming the stacked structure 120, it needs to be etched to form the subsequent structure of the semiconductor structure. However, the inventors discovered that when etching the stacked structure 120, especially when etching the stacked structure 120 located at the junction of the sidewall of the channel 2000 and the surface of the initial semiconductor structure, the anisotropy of etching of each film layer within the stacked structure 120 causes contour defects, forming a structure with a wider opening at the top and a narrower opening at the bottom within the channel 2000. Here, "wider" refers to the size of the opening on the cross-section of the channel 2000. This makes it difficult to guarantee the formation quality of subsequent film layers, affecting the overall performance of the device, such as increasing leakage current, affecting threshold voltage, and reducing reliability. Therefore, before etching the stacked structure 120, a protective gas and an auxiliary gas are introduced into each channel 2000 to form a protective layer 200 on the surface of the sacrificial layer 123.

[0079] The protective gas can be at least one of silicon tetrachloride (SiCl4), silane (SiH4), methylene silane (SiH2), disilane (Si2H6), or silicates, wherein silicates are salts containing silicon ions, and their composition can be determined according to actual usage requirements. The auxiliary gas can be at least one of oxygen (O2), methanol (CH3OH), or ethanol (C2H5OH).

[0080] Taking silicon tetrachloride (SiCl4) as the protective gas and oxygen (O2) as the auxiliary gas as an example, the protective gas and the auxiliary gas react to generate a protective layer 200, which is attached to the surface of the sacrificial layer 123. The reaction process is SiCl4 + O2 → SiO2 + Cl2↑. During this process, silicon dioxide forms the protective layer 200, and the chlorine gas is removed. In subsequent etching processes, the protective layer 200 ensures that the etching profile shape at the interface between the sidewall of the stacked structure 120 and the surface of the initial semiconductor structure is not destroyed, thus ensuring the integrity of the etched structural profile. Of course, the chlorine gas can also be separated and recycled.

[0081] Similarly, if the protective gas and auxiliary gas are other gases, the reaction process will still involve Si. + +O - →SiO2 undergoes a chemical reaction, and the generated byproducts can be removed or vaporized, allowing silicon dioxide to be deposited on the surface of the sacrificial layer 123 to form a protective layer 200. For example, when the protective gas is silane (SiH4), the reaction process is SiH4 + O2 → SiO2 + H2O↑, in which the reaction byproduct water is removed in gaseous form, or the structure can be dried to a certain extent during the formation of the protective layer 200.

[0082] After the protective layer 200 is formed, during the etching process of the stacked structure 120, due to etching anisotropy, the etching rate of the stacked structure 120 on the sidewalls of the channel 2000 is lower than that of the stacked structure 120 located on the surface of the initial semiconductor structure. This ensures that the protective layer 200 guarantees that the sidewalls of the etched structure are collimated to the surface of the substrate 100. Here, collimation means that the sidewalls of the structure and the surface of the substrate 100 are strictly perpendicular (the angle between them is 90 degrees) or approximately perpendicular. The collimation in the embodiments provided herein all have this meaning.

[0083] In the embodiments provided in this disclosure, the reaction conditions for the auxiliary gas and the protective gas are as follows:

[0084] The flow rate of the protective gas is 10 sccm (cubic centimeters per minute) to 100 sccm, for example, it can be 10 sccm, 20 sccm, 30 sccm, 40 sccm, 50 sccm, 60 sccm, 70 sccm, 80 sccm, 90 sccm, 100 sccm, etc. The flow rate of the auxiliary gas is 100 sccm to 500 sccm, for example, it can be 100 sccm, 200 sccm, 300 sccm, 400 sccm, 500 sccm, etc. The flow rates of the protective gas and auxiliary gas can be adjusted adaptively within the above ranges according to actual process requirements.

[0085] The reaction pressure ranges from 5 mT (millitofat per square meter) to 30 mT, for example, it can be 5 mT, 10 mT, 15 mT, 20 mT, 25 mT, 30 mT, etc. The reaction pressure can be selected and adjusted according to actual process requirements.

[0086] The reaction bias voltage ranges from 1000W to 1500W, for example, it can be 1000W, 1100W, 1200W, 1300W, 1400W, 1500W, etc. The reaction bias voltage can be adaptively selected and adjusted according to actual process requirements.

[0087] In the embodiments provided in this disclosure, when forming the protective layer 200, within the same channel 2000, the projected area of ​​the protective layer 200 on the substrate 100 is one-tenth to one-fifth of the projected area of ​​the opening of the channel 2000 on the substrate 100, that is, the area ratio of the two can be 10% to 20%, such as 10%, 11%, 12%, 13%, 14%, 15%, 16%, 17%, 18%, 19%, or 20%. For example, in some embodiments, the size of the opening of the channel 2000 is 60 nm, the thickness of the protective layer 200 formed on one sidewall of the channel 2000 can be 4.5 nm, the thickness of the protective layer 200 formed on both sidewalls of the channel 2000 within one channel 2000 is 9 nm, and the thickness of the protective layer 200 is 15% of the size of the opening of the channel 2000. The dimension of the channel 2000 refers to the maximum (or minimum) distance between the two side walls of the channel 2000 opening, and the thickness of the protective layer 200 refers to the maximum (or minimum) thickness of the protective layer 200 in the direction parallel to the substrate 100. Within this range, the thickness of the protective layer 200 ensures optimal etching performance of the stacked structure 120, guarantees the collimation and integrity of the etched structure profile, and provides a good structural foundation for the formation of subsequent semiconductor structures.

[0088] Furthermore, the protective layer 200 provided in this disclosure can be applied before etching other film layers according to actual process requirements to ensure the integrity and collimation of the etching profile. This protective layer 200 is versatile and applicable to etching processes of various film layers, solving the problem of device performance degradation caused by the cumulative effect of etching defects in multiple processes.

[0089] In the embodiments provided in this disclosure, after etching the stacked structure 120, the formation method further includes: removing the remaining protective layer 200 to expose the sidewalls of the sacrificial layer 123, so that the opening sidewalls of the channel 2000 are aligned with the substrate 100. After etching the stacked structure 120 using the protective layer 200, there will be residues of the protective layer 200. To avoid the influence of the protective layer 200 on subsequent film formation or process steps, it is necessary to remove the remaining protective layer 200. The protective layer 200 can be removed by methods such as wet chemical etching, dry chemical etching, chemical mechanical polishing (CMP), and ion milling. For example, when using wet chemical etching, hydrofluoric acid (HF) or a mixed solution of it (such as buffered hydrofluoric acid, BHF) can be used to etch silicon dioxide; when using dry etching, carbon tetrafluoride (CF4) or octafluorocyclobutane (C4F8) can be converted into a plasma state and then reacted with the silicon dioxide surface to etch it away. The specific removal method can be selected adaptively based on process requirements and structural performance.

[0090] In the embodiments provided in this disclosure, such as Figure 10 and Figure 11 As shown, after removing the remaining protective layer 200, the formation method further includes: removing the remaining sacrificial layer 123 to expose the first sidewall 1221, the second sidewall 1222, and the third sidewall 1231, wherein the first sidewall 1221 and the second sidewall 1222 are two non-coplanar side surfaces on the oxide layer 122, the third sidewall 1231 is a side surface of the insulating layer 121, and the second sidewall 1222 and the third sidewall 1231 are coplanar; a semiconductor layer 500 is formed conformally on the surface jointly formed by the first sidewall 1221, the second sidewall 1222, and the third sidewall 1231, and the semiconductor layer 500 is connected to the first source / drain electrode 310.

[0091] The semiconductor layer 500 extends to the first source / drain electrode 310. In this structure, an electrical connection is formed between the semiconductor layer 500 and the first source / drain electrode 310. The semiconductor layer 500 provides a conductive path for the channel 2000, allowing current to flow between the first source / drain electrode 310 and the second source / drain electrode 320. The semiconductor layer 500 can be made of materials such as polysilicon, strained silicon, silicon-germanium alloy (SiGe), gallium arsenide (GaAs), indium phosphide (InP), gallium silicide (GaSi), and indium silicide (InSi). It can be formed using methods such as chemical vapor deposition (CVD), physical vapor deposition (PVD), molecular beam epitaxy (MBE), and ion implantation.

[0092] In the embodiments provided in this disclosure, such as Figure 12 and Figure 13 As shown, after forming the semiconductor layer 500, the formation method further includes: filling the remaining opening portion of the channel 2000 with an insulating material layer 600, the surface of the insulating material layer 600 being flush with the surface of the initial semiconductor structure; forming a second source / drain electrode 320 on the surface jointly formed by the insulating material layer 600 and the semiconductor layer 500 to obtain the target semiconductor structure, wherein the orthographic projection of the second source / drain electrode 320 on the substrate 100 does not coincide with the orthographic projection of the conductive portion 420 on the substrate 100.

[0093] The insulating material layer 600 fills the remaining openings within the channel 2000 to provide isolation and insulation for the different conductive portions 420 (gates). The insulating material layer 600 can be formed using materials such as silicon dioxide (SiO2), silicon nitride (Si3N4), high-k dielectric materials (such as hafnium oxide (HfO2), zirconium oxide (ZrO2), aluminum oxide (Al2O3)), or organic dielectric materials (such as polyimide (PI)). Its formation method is similar to that of the insulating layer 121, and will not be repeated here.

[0094] After forming the insulating material layer 600, a second source / drain electrode 320 needs to be formed on the surface jointly formed by the insulating material layer 600 and the semiconductor layer 500. The semiconductor layer 500 is electrically connected to the first source / drain electrode 310 and the second source / drain electrode 320. In order to avoid leakage between the second source / drain electrode 320 and the conductive part 420, the orthographic projection of the second source / drain electrode 320 on the substrate 100 can be made not to coincide with the orthographic projection of the conductive part 420 on the substrate 100. That is, the second source / drain electrode 320 is located at the top of the opening of the channel 2000, and the first source / drain electrode 310 is located at the bottom of the opening of the channel 2000. The first source / drain electrode 310 and the second source / drain electrode 320 are arranged opposite each other.

[0095] In the embodiments provided in this disclosure, the target semiconductor structure can be applied in a junction field-effect transistor (JFET), or it can be a transistor with a vertical structure or other applicable types of transistors.

[0096] The semiconductor structure formation method disclosed herein involves introducing a protective gas and an auxiliary gas into a channel 2000. The protective gas and the auxiliary gas react to generate a protective layer 200. When etching the stacked structure 120 within the channel 2000, the protective layer 200 can protect the film layer on the sidewall of the channel 2000, ensuring the etching integrity between the sidewall of the channel 2000 and the initial semiconductor structure surface, avoiding etching defects at the connection, forming a complete etching profile, reducing structural defects generated by the etching process, and improving the collimation of the etched sidewall. In addition, the protective layer 200 formed by the protective gas and the auxiliary gas is easy to remove, does not increase the complexity of the process, and does not have an adverse effect on subsequent process steps.

[0097] It should be noted that although the steps of the semiconductor structure formation method in this disclosure are described in a specific order in the accompanying drawings, this does not require or imply that these steps must be performed in that specific order, or that all the steps shown must be performed to achieve the desired result. Additional or alternative steps may be omitted, multiple steps may be combined into one step, and / or one step may be broken down into multiple steps.

[0098] This disclosure provides a semiconductor structure, such as Figure 13 As shown, the semiconductor structure is prepared using the formation method described above.

[0099] In the embodiments provided in this disclosure, the semiconductor structure may include a gate and a first source / drain 310 and a second source / drain 320 formed on both sides of the gate.

[0100] In this design, two adjacent gates can share a single source-drain pair, saving device space and increasing device density. A channel 2000 structure is included between two adjacent gates. The channel 2000 structure includes a channel 2000, and an insulating layer 121, an oxide layer 122, and a semiconductor layer 500 sequentially formed on both sides of the channel 2000. An insulating material layer 600 fills the opening of the channel 2000.

[0101] The semiconductor structure provided in this disclosure can be fabricated using the semiconductor structure formation method described above. The materials, formation methods, and process steps of each film layer structure are as described in the formation method section above, and will not be detailed here.

[0102] The semiconductor structure disclosed herein has good integrity and high collimation of the formation contours of each internal film layer, resulting in a device with good overall structural performance.

[0103] The semiconductor structure disclosed herein can be a junction field-effect transistor (JFET) or a transistor with a vertical structure, etc., and is applied in memories such as dynamic random access memory (DRAM), static random access memory (SRAM), and flash memory. Of course, it can also be applied to other memory devices not listed here.

[0104] Other embodiments of this disclosure will readily occur to those skilled in the art upon consideration of the specification and practice of the invention disclosed herein. This application is intended to cover any variations, uses, or adaptations of this disclosure that follow the general principles of this disclosure and include common knowledge or customary techniques in the art not disclosed herein. The specification and examples are to be considered exemplary only, and the true scope and spirit of this disclosure are indicated by the appended claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, include: An initial semiconductor structure is formed, the initial semiconductor structure including a substrate, a functional layer and a plurality of spaced channels formed on the functional layer; A stacked structure is formed on the bottom wall and sidewall of each of the channels, and the stacked structure extends to the surface of the initial semiconductor structure, wherein the stacked structure includes an insulating layer, an oxide layer and a sacrificial layer formed sequentially along the surface away from the initial semiconductor structure; A protective gas and an auxiliary gas are introduced into each of the channels and reacted to form a protective layer conformally on the surface of the sacrificial layer, wherein the protective gas includes silicon ions and the auxiliary gas includes oxygen ions; The stacked structure having the protective layer is etched to remove a portion of the stacked structure at the bottom of the trench and to remove the stacked structure at the surface of the functional layer, so as to expose the substrate and the surface of the functional layer.

2. The method for forming a semiconductor structure according to claim 1, characterized in that, Within the same channel, the projected area of ​​the protective layer on the substrate is one-tenth to one-fifth of the projected area of ​​the opening of the channel on the substrate.

3. The method for forming a semiconductor structure according to claim 2, characterized in that, The protective gas includes at least one of silicon tetrachloride, silane, methylene silane, ethoxysilane, or silicate.

4. The method for forming a semiconductor structure according to claim 2, characterized in that, The auxiliary gas includes at least one of oxygen, methanol, or ethanol.

5. The method for forming a semiconductor structure according to claim 2, characterized in that, The flow rate of the protective gas is 10 sccm to 100 sccm, and the flow rate of the auxiliary gas is 100 sccm to 500 sccm.

6. The method for forming a semiconductor structure according to claim 2, characterized in that, The method includes: Under pressure conditions of 5mT to 30mT, the auxiliary gas reacts with the protective gas.

7. The method for forming a semiconductor structure according to claim 2, characterized in that, The method includes: Under a bias voltage of 1000W to 1500W, the auxiliary gas reacts with the protective gas.

8. The method for forming a semiconductor structure according to any one of claims 1-7, characterized in that, The method for forming the initial semiconductor structure further includes: A conductive layer is formed on the substrate; Multiple channels are formed within the conductive layer, thereby creating multiple spaced conductive portions in the conductive layer.

9. The method for forming a semiconductor structure according to claim 8, characterized in that, The method further includes: A first source / drain electrode is formed on the substrate, and the orthographic projection of the first source / drain electrode on the bottom surface of the substrate does not coincide with the orthographic projection of the conductive portion on the bottom surface of the substrate.

10. The method for forming a semiconductor structure according to claim 9, characterized in that, The method further includes: Remove the remaining protective layer to expose the sidewalls of the sacrificial layer so that the opening sidewalls of the trench are aligned with the substrate.

11. The method for forming a semiconductor structure according to claim 10, characterized in that, The method further includes: Remove the remaining sacrificial layer to expose the first sidewall, the second sidewall, and the third sidewall, wherein the first sidewall and the second sidewall are two non-coplanar side surfaces on the oxide layer, the third sidewall is a side surface of the insulating layer, and the second sidewall and the third sidewall are coplanar; A semiconductor layer is formed conformally on the surface formed by the first sidewall, the second sidewall, and the third sidewall, and the semiconductor layer is connected to the first source and drain.

12. The method for forming a semiconductor structure according to claim 11, characterized in that, The method further includes: An insulating material layer is filled within the remaining opening portion of the channel, the surface of which is flush with the surface of the initial semiconductor structure; A second source / drain electrode is formed on the surface where the insulating material layer and the semiconductor layer are jointly formed to obtain the target semiconductor structure. The orthogonal projection of the second source / drain electrode on the substrate does not coincide with the orthogonal projection of the conductive portion on the substrate.

13. The method for forming a semiconductor structure according to claim 8, characterized in that, The initial semiconductor structure further includes a barrier layer formed between the conductive layer and the substrate, the barrier layer being used to prevent the conductive layer from diffusing into the substrate.

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