Display panel

Abstract

A display panel includes a substrate including a first region, a second region, a non-display region surrounding the first region and the second region, and a display region surrounding the non-display region; a plurality of pixels disposed in the display area; a plurality of dummy pixels disposed in the non-display area and not emitting light; and a plurality of signal lines configured to electrically connect the plurality of pixels to the plurality of dummy pixels. Some of the plurality of dummy pixels are disposed between the first region and the second region.

Description

[0001] This application is a divisional application of the patent application with application number 201911187043.4 and title “Display Panel” filed on November 28, 2019.

[0002] Cross-references to related patent applications

[0003] This application claims priority to and the benefit of Korean Patent Application No. 10-2018-0153024 filed in the Korean Intellectual Property Office on November 30, 2018, the disclosure of which is incorporated herein by reference in its entirety. Technical Field

[0004] One or more embodiments relate to a display panel. Background Art

[0005] In today's world, conventional display devices are used in more applications than ever before. The relatively small thickness and light weight of display devices enable an increased range of applications.

[0006] Assuming that the display device is utilized in various ways, various methods may be used to design the shape of the display device, and functional additions may be applied or linked to the display device. Summary of the invention

[0007] As a method of adding functionality that can be connected or linked to a display device, one or more embodiments include a display panel and a device including the display panel, the display panel including an area where a camera, a sensor, etc. can be disposed within the display area.

[0008] However, the one or more embodiments are merely examples, and the scope of the present disclosure is not limited thereto.

[0009] Additional aspects will be set forth in part in the description which follows and, in part, will be obvious from the description, or may be learned by practice of the presented embodiments.

[0010] According to one or more embodiments, a display panel includes: a substrate including a first region, a second region, a non-display region surrounding the first region and the second region, and a display region surrounding the non-display region; a plurality of pixels arranged in the display region; a plurality of dummy pixels arranged in the non-display region and not emitting light; and a plurality of signal lines, the plurality of signal lines being configured to electrically connect the plurality of pixels to a plurality of dummy pixels, wherein some of the plurality of dummy pixels are arranged between the first region and the second region.

[0011] A plurality of dummy pixels may be disposed to surround the first region and the second region.

[0012] Each of the plurality of pixels may include a pixel circuit and a display element, the pixel circuit includes at least one transistor, and the display element is connected to the pixel circuit. Each of the plurality of dummy pixels may include a dummy pixel circuit, the dummy pixel circuit includes at least one dummy transistor. The structure of the pixel circuit may be the same structure as the structure of the dummy pixel circuit.

[0013] The display panel may further include a pixel defining layer disposed on the pixel circuit and the dummy pixel circuit and including an opening corresponding to each of the plurality of pixels. The pixel defining layer may have a flat upper surface corresponding to the dummy pixel.

[0014] The display panel may further include an organic emission layer disposed in the opening of the pixel defining layer corresponding to the pixel. The organic emission layer may be disposed on an upper surface of the pixel defining layer corresponding to the dummy pixel.

[0015] The display panel may further include a first common layer, an organic emission layer, and a second common layer, which are sequentially stacked and disposed in an opening of the pixel defining layer corresponding to the pixel. The first common layer and the second common layer may contact each other on an upper surface of the pixel defining layer corresponding to the dummy pixel.

[0016] The display panel may further include a pixel electrode corresponding to the pixel, an intermediate layer, and a counter electrode, the pixel electrode being connected to the pixel circuit, the intermediate layer being disposed in the opening of the pixel defining layer, and the counter electrode being disposed on the intermediate layer. The opening may expose the pixel electrode, and the counter electrode may contact an upper surface of the pixel defining layer corresponding to the dummy pixel.

[0017] The plurality of signal lines may include signal lines each extending in the first direction and being cut around the first region, and respective two cut portions of the cut signal lines may be connected to each other by a connection line running around the first region.

[0018] Some of the connection lines may be disposed on the same layer as a layer on which the signal line is disposed, and the connection lines and the signal line may be connected to each other by a first bridge metal disposed on a layer different from the layer on which the connection lines and the signal line are disposed.

[0019] Adjacent connection lines among the connection lines may be provided on different layers.

[0020] The display panel may further include a plurality of initialization voltage lines spaced apart from each other around the first area and the second area. The plurality of initialization voltage lines may be connected to each other via an initialization electrode layer in a ring shape surrounding the first area and the second area.

[0021] The initialization electrode layer may be disposed on a layer different from a layer on which the plurality of initialization voltage lines are disposed, and may be connected to the plurality of initialization voltage lines via a contact hole.

[0022] The plurality of signal lines may include: a scan line and a scan connection line, each scan line extending in a first direction and being cut around the first area, each scan connection line connecting two cut portions of each of the scan lines to each other; a previous scan line and a previous scan connection line, each previous scan line extending in the first direction and being cut around the first area, each previous scan connection line connecting two cut portions of each of the previous scan lines to each other; and a light-emitting control line and a light-emitting control connection line, each light-emitting control line extending in the first direction and being cut around the first area, each light-emitting control connection line connecting two cut portions of each of the light-emitting control lines to each other. The scan connection line, the previous scan connection line, and the light-emitting control connection line may be arranged around the first area, and two lines adjacent to each other among the scan connection line, the previous scan connection line, and the light-emitting control connection line may be placed on different layers.

[0023] The scan line may include a first scan line connected to a first dummy pixel among the plurality of dummy pixels. The previous scan line may include a second previous scan line connected to a second dummy pixel, the second dummy pixel being adjacent to the first dummy pixel in a second direction intersecting the first direction. The first scan line and the second previous scan line may be connected to one of the scan connection lines.

[0024] A first light emitting control line among the plurality of light emitting control lines and a second light emitting control line adjacent to the first light emitting control line among the plurality of light emitting control lines may be connected to one of the light emitting control connection lines.

[0025] The dummy pixel may include a dummy pixel circuit. The dummy pixel circuit may include: a switching thin film transistor connected to one of the scanning lines and one of the data lines; a driving thin film transistor, the driving thin film transistor being electrically connected to the switching thin film transistor, and a driving current corresponding to a data signal of the switching thin film transistor flowing through the driving thin film transistor; and a control thin film transistor electrically connected to the driving thin film transistor.

[0026] The dummy pixel circuit may further include a storage capacitor overlapping the driving thin film transistor.

[0027] The plurality of signal lines may include scan lines, each extending in a first direction, and data lines, each extending in a second direction intersecting the first direction and each being cut around the first region. The two corresponding cut portions of the cut data lines may be connected to each other through a data connection line arranged around the first region.

[0028] Some of the data link lines may be disposed on the same layer as a layer on which the data lines are disposed, and may be connected to each other via a second bridge metal disposed on a layer different from the layer on which the data lines are disposed.

[0029] The data link lines may include lower data link lines disposed on the same layer as the layer on which the data lines are disposed and upper data link lines disposed on a layer different from the layer on which the data lines are disposed. The lower data link lines and the upper data link lines may alternate with each other. BRIEF DESCRIPTION OF THE DRAWINGS

[0030] These and / or other aspects will become apparent and more readily understood from the following description of embodiments in conjunction with the accompanying drawings, in which:

[0031] Figure 1 is a schematic perspective view of a display device according to an embodiment;

[0032] Figure 2A , Figure 2B and Figure 2C is a cross-sectional view of a display panel according to an embodiment;

[0033] Figure 3A , Figure 3B and Figure 3C is a cross-sectional view of a display panel according to another embodiment;

[0034] Figure 4 is a schematic plan view of a display panel according to an embodiment;

[0035] Figure 5A yes Figure 4 An enlarged plan view of an embodiment of zone III;

[0036] Figure 5B yes Figure 4 An enlarged plan view of another embodiment of zone III;

[0037] Fig. 6A , Figure 6B , Figure 6C and Fig.6D According to the embodiment Figure 5A A cross-sectional view of a pixel and a dummy pixel taken along lines CC' and BB';

[0038] Fig. 7A and Figure 7B is an equivalent circuit diagram of a pixel according to an embodiment;

[0039] Figure 8 is a plan view of a pixel circuit according to an embodiment;

[0040] Fig. 9 is a plan view schematically illustrating the arrangement of some of the lines around the first region according to an embodiment;

[0041] Fig.10 is along Fig. 9 A cross-sectional view taken along line IV-IV';

[0042] Fig.11 is a plan view of some of the lines around the first area of ​​the display panel according to another embodiment;

[0043] Fig.12 is a plan view of some of the lines around the first area of ​​the display panel according to another embodiment; and

[0044] Fig.13 is along Fig.12 A cross-sectional view taken along line V-V'. DETAILED DESCRIPTION

[0045] Since the present disclosure allows various changes and numerous embodiments, specific embodiments will be shown in the drawings and described in detail in the written description. Hereinafter, the effects and features of the present disclosure and the methods for implementing them will be more fully described with reference to the accompanying drawings showing embodiments of the present disclosure. However, the present disclosure can be embodied in many different forms and should not be construed as being limited to the embodiments set forth herein.

[0046] One or more embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Regardless of the figure numbers, the same or corresponding components are given the same reference numerals, and redundant explanations are omitted.

[0047] It will be understood that although the terms "first", "second", etc. may be used herein to describe various components, these components should not be limited by these terms. These components are only used to distinguish one component from another component.

[0048] As used herein, the singular forms "a", "an" and "the" are intended to include the plural forms as well, unless the context clearly indicates otherwise.

[0049] It will be further understood that the terms “include” and / or “comprises” used herein specify the presence of stated features or components, but do not preclude the presence or addition of one or more other features or components.

[0050] It will be understood that when a layer, region or component is referred to as being “formed on” another layer, region or component, it may be directly or indirectly formed on the other layer, region or component. That is, for example, intervening layers, regions or components may be present.

[0051] For the convenience of explanation, the size of the elements in the drawings may be exaggerated. In other words, since the size and thickness of the components in the drawings are arbitrarily shown for the convenience of explanation, the following embodiments are not limited thereto.

[0052] When a certain embodiment can be implemented differently, a specific process can be performed in an order different from the described order. For example, two processes described successively can be performed substantially at the same time, or in an order opposite to the described order.

[0053] It will also be understood that when a layer, region, or component is referred to as being "connected" or "coupled" to another layer, region, or component, it may be directly connected or coupled to the other layer, region, or component, or there may be intervening layers, regions, or components. For example, when a layer, region, or component is referred to as being "electrically connected" or "electrically coupled" to another layer, region, or component, it may be directly electrically connected or coupled to the other layer, region, or component, or there may be intervening layers, regions, or components.

[0054] Figure 1 is a schematic perspective view of a display device 1 according to the embodiment.

[0055] refer to Figure 1 , the display device 1 includes a display area DA that emits light and a non-display area NDA that does not emit light.

[0056] The display device 1 may provide an image through the display area DA. The display device 1 may include a liquid crystal display (LCD), an electrophoretic display, an organic light emitting display, an inorganic light emitting display, a quantum dot light emitting display, a field emission display, a surface conduction electron emitter display, a plasma display, or a cathode ray display.

[0057] Although an organic light emitting display will now be illustrated and described as the display device 1 according to the embodiment, the present disclosure is not limited thereto, and various types of display devices may be used.

[0058] The display device 1 includes a first region R1 and a second region R2. In the first region R1 and the second region R2, as will be referred to later Figure 2A The first region R1 and the second region R2 can be understood as an opening region or a transmission region capable of transmitting light and / or sound (light and / or sound is output from the electronic component to the outside or transmitted from the outside to the electronic component). Figure 1 In the embodiment, the opening region or the transmission region is the first region R1 and the second region R2, but the present disclosure is not limited thereto and may include three or more opening regions or the transmission region.

[0059] According to an embodiment, when light passes through the first region R1 and the second region R2 , the light transmittance may be approximately 30% or more, 50% or more, 70% or more, 80% or more, or 85% or more.

[0060] The non-display area NDA may include a first non-display area NDA1 surrounding the first and second regions R1 and R2 and a second non-display area NDA2 surrounding the display area DA. The first non-display area NDA1 may completely surround the first and second regions R1 and R2, the display area DA may completely surround the first non-display area NDA1, and the second non-display area NDA2 may completely surround the display area DA.

[0061] Despite Figure 1 The first region R1 and the second region R2 are at the upper right side of the display area DA, but the present disclosure is not limited thereto. According to another embodiment, the positions of the first region R1 and the second region R2 may be changed.

[0062] FIG. 2A to FIG. 2C is a schematic cross-sectional view of a display device 1 according to an embodiment, and can be compared with Figure 1 The cross section corresponds to the line II-II'.

[0063] refer to Figure 2A , the display device 1 may include a display panel 10, and first and second electronic components 20 and 30 respectively corresponding to the first and second regions R1 and R2 of the display panel 10. Although not shown, components such as an input sensing member for sensing a touch input, an anti-reflection member including a polarizer and a retarder or a color filter and a black matrix, and a transparent window may be provided on the display panel 10.

[0064] The display panel 10 may include a substrate 100 , an encapsulation substrate 400A as an encapsulation member facing the substrate 100 , and a sealing member 450 between the substrate 100 and the encapsulation substrate 400A.

[0065] The substrate 100 may include glass or a polymer resin. Examples of polymer resins may include polyethersulfone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate (PC), and cellulose acetate propionate (CAP). The substrate 100 including the polymer resin may be flexible, rollable, and / or bendable. The substrate 100 may have a multilayer structure including a layer including the aforementioned polymer resin and an inorganic layer (not shown). The encapsulation substrate 400A may include glass or the aforementioned polymer resin.

[0066] Thin film transistor TFT, organic light emitting diode OLED as a display element connected to thin film transistor TFT, and signal line SGL are disposed on display area DA of substrate 100. Signal line SGL and dummy thin film transistor TFT' are disposed on first non-display area NDA1 of substrate 100.

[0067] Although not shown, the signal line SGL may provide specific signals (eg, data signals and scan signals) to the first and second regions R1 and R2 in the y direction (ie, in the Figure 2A Display elements separated from each other in the xz plane (in the image).

[0068] The display panel 10 may include through holes corresponding to the first and second regions R1 and R2, respectively. For example, the substrate 100 and the encapsulation substrate 400A may include through holes 100H and through holes 400AH, respectively, wherein the through holes 100H correspond to the first and second regions R1 and R2 and the through holes 400AH correspond to the first and second regions R1 and R2, and portions of the insulating layer IL and / or other elements (those portions corresponding to the first and second regions R1 and R2) between the substrate 100 and the encapsulation substrate 400A may be removed.

[0069] Figure 2A The sealing member 450 is shown to be disposed on both sides of the first region R1 and the second region R2 , but the first region R1 and the second region R2 may be understood to be completely surrounded by the sealing member 450 when viewed from a direction perpendicular to the main surface of the substrate 100 .

[0070] The first electronic component 20 and the second electronic component 30 may be located in the first region R1 and the second region R2, respectively. The first electronic component 20 and the second electronic component 30 may be electronic components that use light or sound. For example, the electronic component may be a sensor that receives and uses light (such as an infrared sensor), a camera that receives light and captures an image, a sensor that outputs and senses light or sound to measure distance or recognize fingerprints, etc., a small lamp that outputs light, or a speaker that outputs sound. Electronic components that use light may use light of various wavelengths such as visible light, infrared light, and ultraviolet light.

[0071] As in Figure 2A In the case where the display panel 10 includes through holes corresponding to the first and second regions R1 and R2 , light or sound output or received by the first and second electronic components 20 and 30 may be more effectively utilized.

[0072] The display panel 10 includes through holes corresponding to the first region R1 and the second region R2. Figure 2A Differently, some components of the display panel 10 may not include through holes. Figure 2BAs shown in FIG. 4 , the package substrate 400A may include through holes 400AH corresponding to the first region R1 and the second region R2, but the substrate 100 may not include through holes. Alternatively, as shown in FIG. Figure 2C As shown in FIG. 4 , both the package substrate 400A and the substrate 100 may not include through holes corresponding to the first region R1 and the second region R2. Figure 2B and Figure 2C As shown in FIG. 1 , even if the substrate 100 does not include the through hole 100H, portions of the insulating layer IL and / or other elements between the substrate 100 and the encapsulation substrate 400A (those portions corresponding to the first region R1 and the second region R2) may be removed, and thus the light transmittance of the first electronic component 20 and the second electronic component 30 may be ensured. When the display device 1 includes Figure 2B and Figure 2C When any one of the display panels 10 is used, the first electronic component 20 and the second electronic component 30 may be electronic components using light.

[0073] FIG. 3A to FIG. 3C is a schematic cross-sectional view of a display device 1 according to other embodiments, and can be compared with Figure 1 The cross section corresponds to the line II-II'.

[0074] With reference above Figure 2A The display device 1 described is similar, Figure 3A The display device 1 may include a display panel 10 including a display element, and first and second electronic components 20 and 30 respectively corresponding to the first and second regions R1 and R2 of the display panel 10. Although not shown, the display device 1 may further include an input detection member, an anti-reflection member, a window, etc., disposed on the display panel 10 for sensing a touch input.

[0075] With reference above Figure 2A Unlike the display panel 10 described above, which includes the encapsulation substrate 400A and the sealing member 450 as encapsulation members, the display panel 10 according to the present embodiment may include a thin film encapsulation layer 400B. In this case, the display panel 10 may have better flexibility. The differences between them will now be discussed and described in detail.

[0076] The thin film encapsulation layer 400B may include at least one inorganic encapsulation layer and at least one organic encapsulation layer. Regarding these layers, Figure 3A A first inorganic encapsulating layer 410 and a second inorganic encapsulating layer 430 and an organic encapsulating layer 420 between the first inorganic encapsulating layer 410 and the second inorganic encapsulating layer 430 are illustrated.

[0077] The first inorganic encapsulation layer 410 and the second inorganic encapsulation layer 430 may include at least one of inorganic insulating materials such as aluminum oxide, titanium oxide, tantalum oxide, hafnium oxide, zinc oxide, silicon oxide, silicon nitride, and silicon oxynitride. The organic encapsulation layer 420 may include a polymer material. Examples of polymer materials may include acrylic resin, epoxy resin, polyimide, and polyethylene.

[0078] The display panel 10 may include through holes corresponding to the first region R1 and the second region R2. For example, the substrate 100 and the thin film encapsulation layer 400B may include through holes 100H corresponding to the first region R1 and the second region R2 and through holes 400BH corresponding to the first region R1 and the second region R2, respectively. As described above, the first electronic component 20 and the second electronic component 30 using light or sound may be disposed in the first region R1 and the second region R2, respectively.

[0079] The display panel 10 includes through holes corresponding to the first region R1 and the second region R2. Figure 3A Differently, the display panel 10 may not include a through hole. Figure 3B As shown in FIG. 4 , the thin film encapsulation layer 400B may include through holes 400BH corresponding to the first and second regions R1 and R2, but the substrate 100 may not include through holes. Alternatively, as shown in FIG. Figure 3C As shown in FIG. 1 , both the thin film encapsulation layer 400B and the substrate 100 may not include through holes corresponding to the first region R1 and the second region R2. Figure 3B and Figure 3C As illustrated in FIG, even if the substrate 100 does not include the through hole 100H, portions of the insulating layer IL and / or other elements between the substrate 100 and the thin film encapsulation layer 400B (those portions corresponding to the first region R1 and the second region R2) can also be removed, and thus the transmittance of the first electronic component 20 and the second electronic component 30 can be ensured.

[0080] like Figure 3A and Figure 3B As shown in , when the thin film encapsulation layer 400B includes a through hole 400BH, each of the at least one inorganic encapsulation layer and the at least one organic encapsulation layer may include a hole corresponding to the through hole 400BH. In this case, the hole of each organic encapsulation layer is made larger than the hole of each inorganic encapsulation layer, and thus the first inorganic encapsulation layer 410 and the second inorganic encapsulation layer 430 may be in direct contact with each other around the first region R1 and the second region R2.

[0081] like Figure 3C As shown in FIG. 1 , when the thin film encapsulation layer 400B does not include a through hole, each of the at least one inorganic encapsulation layer and the at least one organic encapsulation layer may cover the first region R1 and the second region R2. In this case, the insulating layer IL between the substrate 100 and the thin film encapsulation layer 400B may be partially removed. Figure 3A In the embodiment shown in , portions of the insulating layer IL corresponding to the first and second regions R1 and R2 are completely removed, but in other embodiments, only some of the multiple layers constituting the insulating layer IL may be removed.

[0082] Figure 4 is a schematic plan view of a display panel 10 according to an embodiment, and Figure 5A and Figure 5B yes Figure 4 An enlarged plan view of Zone III.

[0083] refer to Figure 4 , the display panel 10 includes a plurality of pixels P arranged in a display area DA. Each of the pixels P may include a display element such as an organic light emitting diode (OLED). The pixel P may emit, for example, red light, green light, blue light, or white light via the OLED. The pixel P used herein may be understood as a pixel that emits one of the red light, green light, blue light, and white light as described above. By being referred to above Figures 2A to 3C The described encapsulation member covers and protects the display area DA from external air or moisture.

[0084] The first non-display area NDA1 surrounds the first region R1 and the second region R2. The first non-display area NDA1 is an area where no image is displayed. Signal lines that provide signals to the pixels P around the first region R1 and the second region R2 may be disposed in the first non-display area NDA1. According to the present embodiment, a dummy pixel Pd that does not emit light is disposed in the first non-display area NDA1.

[0085] The second non-display area NDA2 may include a scan driver 1000 supplying scan signals to the pixels P and the dummy pixels Pd, a data driver 2000 supplying data signals to the pixels P and the dummy pixels Pd, and a main power line (not shown) for supplying a driving voltage and a common voltage.

[0086] Figure 5A and Figure 5B yes Figure 4 An enlarged plan view of Zone III.

[0087] refer to Figure 5A and Figure 5B , the first region R1 and the second region R2 are disposed in the first direction (x direction), the first non-display area NDA1 surrounds the first region R1 and the second region R2, and the display area DA surrounds the first non-display area NDA1.

[0088] A plurality of pixels P are disposed in the display area DA, and a plurality of dummy pixels Pd are disposed in the first non-display area NDA1. A plurality of signal lines may be disposed to electrically connect the plurality of pixels P to the plurality of dummy pixels Pd. In this regard, Figure 5A The diagram shows that each scan line SLa and SLb extending in a first direction (x direction) connects the pixel P in the display area DA to the dummy pixel Pd in ​​the first non-display area NDA1, and the data lines DLa and DLb connect the pixel P to the dummy pixel Pd in ​​a second direction (y direction) intersecting the first direction.

[0089] Some of the scan lines SLa among the scan lines SLa and SLb may each extend in the first direction (x direction) to provide signals to the pixels P placed on the left and right sides of the first non-display area NDA1 and the dummy pixels Pd placed in the first non-display area NDA1, but may be arranged around the first region R1 and the second region R2 in the first non-display area NDA1. Arranging around the corresponding region may mean that if a part of the line extends in a straight line, it will overlap with the corresponding region, and conversely, extending in a curve around the corresponding region so that it does not overlap with the corresponding region. For example, the part of the line may extend in a semicircle around the upper half of the corresponding region, having a curvature matching the corresponding region (i.e., the curvature of a circle) and having a larger radius; however, the shape is not limited thereto, and other shapes may be used, for example, the curve may be only a partial rather than a complete semicircle, and / or the curve may not have a curvature matching the curvature of a circle, etc. Some of the scan lines SLb disposed away from the first and second regions R1 and R2 in the first non-display area NDA1 or the scan lines that do not cross the first non-display area NDA1 may each extend substantially in a straight line.

[0090] Some of the data lines DLa among the data lines DLa and DLb may each extend in the second direction (y direction) to provide signals to the pixels P disposed on the upper and lower sides of the first non-display area NDA1, but may be routed around the first region R1 and / or the second region R2 in the first non-display area NDA1. Some of the data lines DLb disposed between the first region R1 and the second region R2 in the first non-display area NDA1 or the data lines that do not cross the first non-display area NDA1 may each extend substantially in a straight line.

[0091] For example, when the first and second regions R1 and R2 have a circular shape, signal lines placed relatively close to the first and second regions R1 and R2 may be bent with a large curvature along the first and second regions R1 and R2, and signal lines placed relatively far from the first and second regions R1 and R2 may each extend in a straight line.

[0092] According to the present embodiment, dummy pixels Pd placed in the first non-display area NDA1 may be included so as not to emit light even when they receive an electrical signal from a signal line.

[0093] According to the present embodiment, dummy pixels Pd may be included to ensure uniformity of pattern density and uniformity of electrical load. In the case where dummy pixels Pd are not provided in the first non-display area NDA1 and only signal lines SLa, SLb, DLa, and DLb connecting pixels P in the display area DA to each other are provided in the first non-display area NDA1, pattern density is low in the first non-display area NDA1, and therefore, a non-uniform pattern may be formed during etching.

[0094] Also, when the dummy pixel Pd is not disposed in the first non-display area NDA1, a parasitic capacitance or a different load from the central portion of the display area DA may be formed in the first non-display area NDA1 and its surroundings. Therefore, brightness non-uniformity may occur.

[0095] According to the present embodiment, the first non-display area NDA1 includes a pixel circuit PC included in each pixel P (see Fig. 7A and Figure 7B ) a dummy pixel circuit of substantially the same structure as that of the first embodiment, and an electrical signal is applied to the dummy pixel circuit, and thus, both uniformity of pattern density and uniformity of electrical load can be ensured.

[0096] The dummy pixel Pd may be placed in the first non-display area NDA1 between the first region R1 and the second region R2 . However, the present disclosure is not limited thereto.

[0097] For example, Figure 5B As shown in , the dummy pixel Pd may be placed around the first region R1 and / or the second region R2. In other words, the dummy pixel Pd may be disposed not only between the first region R1 and the second region R2, but also on the left, upper, and lower sides of the first region R1 to be close to the display area DA. The dummy pixel Pd may also be disposed at positions on the right, upper, and lower sides of the second region R2, which are close to the display area DA.

[0098] The dummy pixel Pd disposed around the first region R1 and / or the second region R2 may mean a dummy pixel Pd disposed between the pixel P and the first region R1 and / or between the pixel P and the second region R2. Therefore, the dummy pixel Pd may protect the pixel P in the display area DA from electrostatic discharge (ESD) that may occur around the first region R1 and / or the second region R2. In other words, when static electricity is generated around the first region R1 and / or the second region R2, the dummy pixel Pd may be used as a buffer for preventing a large voltage due to ESD from being transmitted to the pixel P.

[0099] FIG. 6A to FIG. 6D is a schematic cross-sectional view of a pixel P and a dummy pixel Pd according to an embodiment.

[0100] refer to Fig. 6A , the pixel P may include a pixel circuit PC including at least one thin film transistor TFT and an organic light emitting diode OLED as a display element. The dummy pixel Pd may include a dummy pixel circuit PC' including at least one dummy thin film transistor TFT'. According to some embodiments, the pixel circuit PC and the dummy pixel circuit PC' may have the same structure. For example, the structure of the pixel circuit PC and the structure of the dummy pixel circuit PC' may have the same layers and elements arranged in the same order, and all the layers and elements have the same size as each other.

[0101] In the dummy pixel Pd, some components of the display element are removed so that no light is emitted even when an electric signal is applied to the dummy pixel circuit PC′.

[0102] According to the present embodiment, the pixel electrode 310 of the organic light emitting diode OLED is not provided in the dummy pixel Pd compared to the pixel P, and thus does not emit light. However, the present disclosure is not limited thereto. The dummy pixel Pd may not include the counter electrode 330 of the organic light emitting diode OLED. In this way, various modifications may be made.

[0103] Despite Fig. 6A In the embodiment, a single thin film transistor TFT is included in the pixel circuit PC and a single thin film transistor TFT' is included in the dummy pixel circuit PC', but the present disclosure is not limited thereto. A plurality of (two to seven) thin film transistors TFT and a plurality of (two to seven) thin film transistors TFT' may be included. In this way, various modifications may be made.

[0104] The structures of the pixels P and the dummy pixels Pd will now be described in stacking order.

[0105] Substrate 100 may include a glass material, a metal material, or a flexible or bendable material. When substrate 100 is flexible or bendable, substrate 100 may include a polymer resin, such as polyethersulfone (PES), polyacrylate (PAR), polyetherimide (PEI), polyethylene naphthalate (PEN), polyethylene terephthalate (PET), polyphenylene sulfide (PPS), polyarylate, polyimide (PI), polycarbonate (PC) or cellulose acetate propionate (CAP). Substrate 100 may have a single layer or multilayer structure of any of the aforementioned materials. The multilayer structure may further include an inorganic layer. In some embodiments, substrate 100 may have a structure of an organic material / inorganic material / organic material.

[0106] The buffer layer 111 may be placed on the substrate 100 and may reduce or prevent foreign matter, moisture, or ambient air from penetrating from under the substrate 100, and may provide a flat surface on the substrate 100. The buffer layer 111 may include an inorganic material (such as an oxide or a nitride), an organic material, or an organic and inorganic composite, and may be formed as a single layer or multiple layers of an inorganic material and an organic material.

[0107] A barrier layer (not shown) may be further included between the substrate 100 and the buffer layer 111. The barrier layer may prevent or minimize the penetration of impurities from the substrate 100, etc. into the semiconductor layers A and A'. The barrier layer may include an inorganic material (such as an oxide or a nitride), an organic material, or an organic and inorganic composite, and may be formed as a single layer or multiple layers of an inorganic material and an organic material.

[0108] The semiconductor layers A and A' may be disposed on the buffer layer 111. The semiconductor layers A and A' may include amorphous silicon or polycrystalline silicon. According to another embodiment, the semiconductor layers A and A' may include an oxide of at least one selected from the group consisting of indium (In), gallium (Ga), tin (Sn), zirconium (Zr), vanadium (V), hafnium (Hf), cadmium (Cd), germanium (Ge), chromium (Cr), titanium (Ti), aluminum (Al), cesium (Cs), cerium (Ce) and zinc (Zn). In some embodiments, the semiconductor layers A and A' may be formed of Zn oxide, In-Zn oxide, Ga-In-Zn oxide, etc., which are materials based on Zn oxide. In other embodiments, the semiconductor layers A and A' may be In-Ga-Zn-O (IGZO), In-Sn-Zn-O (ITZO) or In-Ga-Sn-Zn-O (IGTZO) semiconductors containing metals such as In, Ga or Sn in ZnO. The semiconductor layers A and A' may include a channel region and a source region and a drain region respectively disposed at both sides of the channel region. Each of the semiconductor layers A and A' may be formed as a single layer or a multilayer.

[0109] The gate electrodes G and G' are disposed on the semiconductor layers A and A' so that the gate electrodes G and G' overlap at least partially with the semiconductor layers A and A', and the first gate insulating layer 112 is between the gate electrodes G and G' and the semiconductor layers A and A'. The gate electrodes G and G' may include, for example, molybdenum (Mo), aluminum (Al), copper (Cu), or titanium (Ti), and each may include a single layer or multiple layers. For example, each of the gate electrodes G and G' may include a single layer of Mo.

[0110] The first gate insulating layer 112 may include silicon oxide (SiO 2 ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ), zinc oxide (ZnO 2 )wait.

[0111] A second gate insulating layer 113 may be included such that the second gate insulating layer 113 covers the gate electrodes G and G'. The second gate insulating layer 113 may include silicon oxide (SiO 2 ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ), zinc oxide (ZnO 2 )wait.

[0112] The first storage capacitor plates CE1 and CE1' of the storage capacitors Cst and Cst' may overlap with the thin film transistors TFT and TFT'. For example, the gate electrodes G and G' of the thin film transistors TFT and TFT' may serve as the first storage capacitor plates CE1 and CE1' of the storage capacitors Cst and Cst'.

[0113] The second storage capacitor plates CE2 and CE2' of the storage capacitors Cst and Cst' overlap with the first storage capacitor plates CE1 and CE1', and the second gate insulating layer 113 is between the second storage capacitor plates CE2 and CE2' and the first storage capacitor plates CE1 and CE1'. In this case, the second gate insulating layer 113 may be used as a dielectric layer of the storage capacitors Cst and Cst'. The second storage capacitor plates CE2 and CE2' may include a conductive material including molybdenum (Mo), aluminum (Al), copper (Cu), and titanium (Ti), and each may be formed as a multilayer or a single layer including the foregoing materials. For example, each of the second storage capacitor plates CE2 and CE2' may be a single layer of Mo or a multilayer of Mo / Al / Mo.

[0114] Despite FIG. 6A to FIG. 6D In the embodiment, the storage capacitors Cst and Cst' overlap with the thin film transistors TFT and TFT', but the present disclosure is not limited thereto. The storage capacitors Cst and Cst' may not overlap with the thin film transistors TFT and TFT'. In this way, various modifications may be made.

[0115] An interlayer insulating layer 115 may be included to cover the second storage capacitor plates CE2 and CE2' of the storage capacitors Cst and Cst'. The interlayer insulating layer 115 may include silicon oxide (SiO 2 ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O 5 ), hafnium oxide (HfO 2 ), zinc oxide (ZnO 2 )wait.

[0116] The source electrodes S and S' and the drain electrodes D and D' may be disposed on the interlayer insulating layer 115. Each of the source electrodes S and S' and the drain electrodes D and D' may include a conductive material including Mo, Al, Cu, and Ti, and may be a multilayer or a single layer including the foregoing materials. For example, each of the source electrodes S and S' and the drain electrodes D and D' may be a multilayer of Ti / Al / Ti.

[0117] The via layer 117 and the additional via layer 118 may be disposed on the source electrodes S and S' and the drain electrodes D and D', and the organic light emitting diode OLED may be disposed in a region of the pixel P on the additional via layer 118. In some embodiments, the additional via layer 118 may be omitted.

[0118] The via layer 117 and the additional via layer 118 may have a flat upper surface so that the first electrode 310 may be formed flatly. The via layer 117 and the additional via layer 118 may each be formed as a single layer including an organic material or as a multilayer each including an organic material. The via layer 117 and the additional via layer 118 may include an industrial polymer such as benzocyclobutene (BCB), polyimide, hexamethyldisiloxane (HMDSO), polymethylmethacrylate (PMMA) or polystyrene (PS), a polymer derivative having a phenol group, an propylene polymer, an imine polymer, an propylene ether polymer, an amide polymer, a fluorine polymer, a paraxylene polymer, a vinyl alcohol polymer, a mixture thereof, and the like. The via layer 117 and the additional via layer 118 may include an inorganic material. The via layer 117 and the additional via layer 118 may include silicon oxide (SiO 2 ), silicon nitride (SiN x ), silicon oxynitride (SiON), aluminum oxide (Al 2 O 3 ), titanium oxide (TiO 2 ), Tantalum Oxide (Ta 2 O5 ), hafnium oxide (HfO 2 ), zinc oxide (ZnO 2 ) etc. When the via layer 117 and the additional via layer 118 include an inorganic material, chemical planarization polishing may be performed. The via layer 117 may include both an organic material and an inorganic material.

[0119] In the display area DA of the substrate 100, the organic light emitting diode OLED is placed on the additional via hole layer 118. The organic light emitting diode OLED includes a pixel electrode 310, an opposing electrode 330, and an intermediate layer 320 including an organic emission layer.

[0120] A through hole through which one of the source electrode S and the drain electrode D of the thin film transistor TFT is exposed is formed in the via layer 117 and the additional via layer 118 , and the pixel electrode 310 contacts the source electrode S or the drain electrode D through the through hole and is electrically connected to the thin film transistor TFT.

[0121] The pixel electrode 310 may include a (semi) light-transmitting electrode or a reflective electrode. According to some embodiments, the pixel electrode 310 may include a reflective layer formed of silver (Ag), magnesium (Mg), aluminum (Al), platinum (Pt), palladium (Pd), gold (Au), nickel (Ni), neodymium (Nd), iridium (Ir), chromium (Cr) or a compound thereof, and a transparent or semi-transparent electrode layer formed on the reflective layer. The transparent or semi-transparent electrode layer may include an electrode selected from indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), indium oxide (In 2 O 3 ), at least one of the group consisting of indium gallium oxide (IGO) and aluminum zinc oxide (AZO). According to some embodiments, the pixel electrode 310 may have a stack structure of ITO / Ag / ITO.

[0122] The pixel defining layer 119 may be disposed on the additional via layer 118. The pixel defining layer 119 may define the light emitting area of ​​the pixel P by including openings corresponding to the pixel electrodes 310, respectively, in the display area DA (i.e., openings OP, exposing at least the central portion of the pixel electrode 310 via the openings OP). The pixel defining layer 119 may prevent arcing, etc. from occurring on the edge of the pixel electrode 310 by increasing the distance between the pixel electrode 310 and the edge of the counter electrode 330 disposed above the pixel electrode 310. The pixel defining layer 119 may be formed of an organic insulating material such as polyimide, polyamide, acrylic resin, benzocyclobutene, hexamethyldisiloxane (HMDSO), or phenolic resin via spin coating, etc.

[0123] The pixel P (i.e., the light emitting area of ​​the pixel P) may be defined by the opening OP of the pixel defining layer 119. In other words, the edge of the pixel P may mean the edge of the opening OP of the pixel defining layer 119. The edge of the opening OP of the pixel defining layer 119 may mean the boundary of the pixel electrode 310 exposed through the opening OP.

[0124] The intermediate layer 320 of the organic light emitting diode OLED may include an organic emission layer 321 , and a first common layer 322 and a second common layer 323 which may be disposed on the bottom and the top of the organic emission layer 321 , respectively.

[0125] The organic emission layer 321 may include an organic material including a fluorescent or phosphorescent material that emits red, green, blue, or white light. The organic emission layer 321 may include a low molecular weight organic material or a high molecular weight organic material.

[0126] The first common layer 322 may include a hole injection layer (HIL) and / or a hole transport layer (HTL), and the second common layer 323 may include an electron transport layer (ETL) and / or an electron injection layer (EIL).

[0127] The intermediate layer 320 may be provided to correspond to each of the plurality of first electrodes 310. However, the present disclosure is not limited thereto. The intermediate layer 320 may include a single layer extending over the plurality of first electrodes 310, that is, a first common layer 322 and / or a second common layer 323. In this manner, various modifications may be made. The first common layer 322 and / or the second common layer 323 may be omitted.

[0128] The counter electrode 330 may include a light-transmitting electrode or a reflective electrode. According to some embodiments, the counter electrode 330 may include a transparent or semi-transparent electrode and may include a metal film having a small work function, including lithium (Li), calcium (Ca), lithium fluoride / calcium (LiF / Ca), lithium fluoride / aluminum (LiF / Al), aluminum (Al), silver (Ag), magnesium (Mg), or a compound thereof. A transparent conductive oxide (TCO) such as indium tin oxide (ITO), indium zinc oxide (IZO), zinc oxide (ZnO), or indium oxide (In 2 O 3 The TCO layer of the display area DA and the non-display area NDA may be further disposed on the metal film. The counter electrode 330 may extend over the display area DA and the non-display area NDA, and may be disposed on the intermediate layer 320 and the pixel defining layer 119. The counter electrode 330 may be formed as a monomer constituting a plurality of organic light emitting diodes OLED, and thus may correspond to a plurality of pixel electrodes 310.

[0129] When the pixel electrode 310 includes a reflective electrode and the counter electrode 330 includes a light-transmitting electrode, the light emitted by the intermediate layer 320 is emitted toward the counter electrode 330, and thus the display device 1 may be a top emission type. When the pixel electrode 310 includes a transparent or semi-transparent electrode and the counter electrode 330 includes a reflective electrode, the light emitted by the intermediate layer 320 is emitted toward the substrate 100, and thus the display device 1 may be a bottom emission type. However, the present embodiment is not limited thereto. The display device 1 according to the present embodiment may be a dual emission type that emits light in two directions (i.e., toward the upper surface and the bottom surface of the display device 1).

[0130] Unlike the pixel P, the dummy pixel Pd disposed in the first non-display area NDA1 of the substrate 100 may not include a pixel electrode, and the pixel defining layer 119 may not include an opening corresponding to the dummy pixel Pd. In other words, the pixel defining layer 119 may have a flat upper surface corresponding to the dummy pixel Pd because the pixel defining layer 119 may be formed of an organic material through exposure and curing and may not affect non-uniformity due to pattern density.

[0131] In the region of the dummy pixel Pd, the intermediate layer 320 may be disposed on the pixel defining layer 119. Even when the intermediate layer 320 is disposed in the region of the dummy pixel Pd, the dummy pixel Pd does not include a pixel electrode, and thus light is not emitted by the intermediate layer 320.

[0132] exist Fig. 6A In the embodiment, the organic emission layer 321 , the first common layer 322 , and the second common layer 323 are all disposed in the region of the dummy pixel Pd, like the intermediate layer 320 disposed in the pixel P. However, the present disclosure is not limited thereto.

[0133] As in Figure 6B In the embodiment, the organic emission layer 321, the first common layer 322, and the second common layer 323 may be disposed in the region of the pixel P, and in the region of the dummy pixel Pd, no organic emission layer 321 may be disposed, and only the first common layer 322 and the second common layer 323 may be disposed. In this case, the first common layer 322 and the second common layer 323 may directly contact each other in the region of the dummy pixel Pd.

[0134] Alternatively, as in Figure 6C In the embodiment, the intermediate layer 320 may be disposed in the region of the pixel P, and no intermediate layer 320 may be disposed in the region of the dummy pixel Pd. In this way, various modifications may be made. In this case, the counter electrode 330 may directly contact the upper surface of the pixel defining layer 119 in the region of the dummy pixel Pd.

[0135] Despite FIG. 6A to FIG. 6CIn the embodiment, the counter electrode 330 is disposed not only in the region of the pixel P but also in the region of the dummy pixel Pd, but the present disclosure is not limited thereto. Fig.6D In the embodiment, the counter electrode 330 may not be provided in the dummy pixel Pd. In this case, as in Fig.6D In the embodiment, a conductive layer 310' including the same material as that included in the pixel electrode 310 and placed on the same layer as that on which the pixel electrode 310 is formed, and an organic emission layer 321, a first common layer 322, and a second common layer 323 of an intermediate layer 320 may be provided in the dummy pixel Pd. However, the present disclosure is not limited thereto. At least one of the conductive layer 310', the organic emission layer 321, the first common layer 322, and the second common layer 323 may be omitted.

[0136] Since the opposing electrode 330 is formed over the entire display panel by using an open mask, the opposing electrode 330 may be disposed to correspond to the pixel P and the dummy pixel Pd during the process.

[0137] The capping layer 340 may be disposed on the opposite electrode 330. The capping layer 340 may have a different (lower or higher) refractive index than the opposite electrode 330, and may improve light emitting efficiency by increasing the percentage of light generated by the intermediate layer 320 including the organic emission layer 321 emitted to the outside.

[0138] For example, the capping layer 340 may include an organic material such as poly(3,4-ethylenedioxythiophene) (or PEDOT), 4,4'-bis[N-(3-methylphenyl)-N-phenylamino]biphenyl (TPD), 4,4',4"-tris[(3-methylphenyl)phenylamino]triphenylamine (m-MTDATA), 1,3,5-tris[N,N-bis(2-methylphenyl)-amino]-benzene (o-MTDAB), 1,3,5-tris[N,N-bis(3-methylphenyl)-amino]-benzene (m-MTDAT), 1,3,5-tris[ N,N-Bis(4-methylphenyl)-amino]-benzene (p-MTDAB), 4,4'-bis[N,N-bis(3-methylphenyl)-amino]-diphenylmethane (BPPM), 4,4'-bicarbazolyl-1,1'-biphenyl (CBP), 4,4',4"-tris(N-carbazole)triphenylamine (TCTA), 2,2',2"-(1,3,5-phenyltolyl)tris-[1-phenyl-1H-benzimidazole] (TPBI), and 3-(4-biphenyl)-4-phenyl-5-tert-butylphenyl-1,2,4-triazole (TAZ).

[0139] Alternatively, the capping layer 340 may include an inorganic material such as zinc oxide, titanium oxide, zirconium oxide, silicon nitride, niobium oxide, tantalum oxide, tin oxide, nickel oxide, indium nitride, and gallium nitride. The material of the capping layer 340 is not limited thereto, and various other materials may be used.

[0140] A capping layer (not shown) may be disposed on the capping layer 340. The capping layer protects the organic light emitting diode OLED from damage that may occur during a subsequent process using plasma, etc. The capping layer may include LiF.

[0141] Fig. 7A and Figure 7B is a schematic equivalent circuit diagram of a pixel P of a display panel according to an embodiment.

[0142] refer to Fig. 7A , each pixel P includes a pixel circuit PC and an organic light emitting diode OLED connected to the pixel circuit PC. The pixel circuit PC may include a driving thin film transistor (TFT) T1, a switching TFT T2, and a storage capacitor Cst.

[0143] The switching TFT T2 is connected to the scan line SL and the data line DL, and transmits a data voltage received via the data line DL to the driving TFT T1 according to a switching voltage received via the scan line SL. The storage capacitor Cst is connected to the switching TFT T2 and the driving voltage line PL, and stores a voltage corresponding to a difference between a voltage received from the switching TFT T2 and a driving voltage ELVDD supplied to the driving voltage line PL.

[0144] The driving TFT T1 is connected to the driving voltage line PL and the storage capacitor Cst, and can control the driving current flowing from the driving voltage line PL to the organic light emitting diode OLED according to the voltage value stored in the storage capacitor Cst. The organic light emitting diode OLED can emit light with a certain brightness by the driving current. The counter electrode (e.g., cathode) of the organic light emitting diode OLED can receive the common voltage ELVSS.

[0145] although Fig. 7A 2 illustrates a case where the pixel circuit PC includes two TFTs and one storage capacitor, but the present disclosure is not limited thereto. The number of TFTs and the number of storage capacitors may vary according to the design of the pixel circuit PC.

[0146] refer to Figure 7B The pixel circuit PC may include a plurality of TFTs and a storage capacitor Cst. The TFTs and the storage capacitor Cst may be connected to the signal lines SL, SIL, EL, and DL, the initialization voltage line VL, and the driving voltage line PL.

[0147] Despite Figure 7B In the embodiment, each pixel P is connected to the signal lines SL, SIL, EL and DL, the initialization voltage line VL and the driving voltage line PL, but the present disclosure is not limited thereto. According to another embodiment, the initialization voltage line VL, the driving voltage line PL and at least one of the signal lines SL, SIL, EL and DL can be shared by adjacent pixels.

[0148] The plurality of TFTs may include a driving TFT T1 , a switching TFT T2 , a compensation TFT T3 , a first initialization TFT T4 , an operation control TFT T5 , a light emission control TFT T6 , and a second initialization TFT T7 .

[0149] The signal lines SL, SIL, EL, and DL may include a scan line SL transmitting a scan signal Sn, a previous scan line SIL transmitting a previous scan signal Sn-1 to a second initialization TFT T7, a light emitting control line EL transmitting a light emitting control signal En to an operation control TFT T5 and a light emitting control TFT T6, and a data line DL crossing the scan line SL and transmitting a data signal Dm. The driving voltage line PL transmits a driving voltage ELVDD to the driving TFT T1, and the initialization voltage line VL transmits an initialization voltage Vint for initializing the driving TFT T1 and a pixel electrode of the organic light emitting diode OLED.

[0150] The driving TFT T1 includes a driving gate electrode G1 connected to a first storage capacitor plate CE1 of a storage capacitor Cst, a driving source electrode S1 connected to a driving voltage line PL via an operation control TFT T5, and a driving drain electrode D1 electrically connected to a pixel electrode of the organic light emitting diode OLED via a light emission control TFT T6. The driving TFT T1 receives a data signal Dm according to a switching operation of the switching TFT T2, and converts a driving current I OLED Supply to the organic light emitting diode OLED.

[0151] The switching TFT T2 includes a switching gate electrode G2 connected to the scan line SL, a switching source electrode S2 connected to the data line DL, and a switching drain electrode D2 connected to the driving source electrode S1 of the driving TFT T1 and also connected to the driving voltage line PL via the operation control TFT T5. The switching TFT T2 is turned on according to the scan signal Sn received via the scan line SL, and performs a switching operation of transmitting the data signal Dm received from the data line DL to the driving source electrode S1 of the driving TFT T1.

[0152] The compensation TFT T3 includes a compensation gate electrode G3 connected to the scan line SL, a compensation source electrode S3 connected to the driving drain electrode D1 of the driving TFT T1 and also connected to the pixel electrode of the organic light emitting diode OLED via the light emission control TFT T6, and a first storage capacitor plate CE1 connected to the storage capacitor Cst, a first initialization drain electrode D4 of the first initialization TFT T4, and a compensation drain electrode D3 of the driving gate electrode G1 of the driving TFT T1. The compensation TFT T3 is turned on according to the scan signal Sn received via the scan line SL, and electrically connects the driving gate electrode S1 and the driving drain electrode D1 of the driving TFT T1 to each other, so that the driving TFT T1 is diode-connected.

[0153] The first initialization TFT T4 includes a first initialization gate electrode G4 connected to the previous scan line SIL, a second initialization drain electrode D7 connected to the second initialization TFT T7 and a first initialization source electrode S4 connected to the initialization voltage line VL, and a first initialization drain electrode D4 connected to the first storage capacitor plate CE1 of the storage capacitor Cst, the compensation drain electrode D3 of the compensation TFT T3, and the driving gate electrode G1 of the driving TFT T1. The first initialization TFT T4 is turned on according to the previous scan signal Sn-1 received via the previous scan line SIL, and transmits the initialization voltage Vint to the driving gate electrode G1 of the driving TFT T1, thereby initializing the voltage of the driving gate electrode G1 of the driving TFT T1.

[0154] The operation control TFT T5 includes an operation control gate electrode G5 connected to the light emission control line EL, an operation control source electrode S5 connected to the driving voltage line PL, and an operation control drain electrode D5 connected to the driving source electrode S1 of the driving TFT T1 and the switching drain electrode D2 of the switching TFT T2.

[0155] The light emission control TFT T6 includes a light emission control gate electrode G6 connected to the light emission control line EL, a light emission control source electrode S6 connected to the driving drain electrode D1 of the driving TFT T1 and the compensation source electrode S3 of the compensation TFT T3, and a light emission control drain electrode D6 electrically connected to the second initialization source electrode S7 of the second initialization TFT T7 and the pixel electrode of the organic light emitting diode OLED.

[0156] The operation control TFT T5 and the light emission control TFT T6 are simultaneously turned on according to the light emission control signal En received via the light emission control line EL, and thus the driving voltage ELVDD is transmitted to the organic light emitting diode OLED so that the driving current I OLED Can flow into organic light-emitting diodes OLED.

[0157] The second initialization TFT T7 includes a second initialization gate electrode G7 connected to the previous scan line SIL, a second initialization source electrode S7 connected to the light emission control drain electrode D6 of the light emission control TFT T6 and the pixel electrode of the organic light emitting diode OLED, and a first initialization source electrode S4 connected to the first initialization TFT T4 and a second initialization drain electrode D7 of the initialization voltage line VL. The second initialization TFT T7 is turned on according to the previous scan signal Sn-1 received via the previous scan line SIL, and initializes the pixel electrode of the organic light emitting diode OLED.

[0158] Despite Figure 7B In the embodiment, the first initialization TFT T4 and the second initialization TFT T7 are connected to the previous scan line SIL, but the present disclosure is not limited thereto. According to another embodiment, the first initialization TFT T4 may be connected to the previous scan line SIL and operate according to the previous scan signal Sn-1, and the second initialization TFT T7 may be connected to a separate signal line (e.g., a subsequent scan line) and operate according to a signal transmitted to the separate signal line.

[0159] The second storage capacitor plate CE2 of the storage capacitor Cst is connected to the driving voltage line PL, and the counter electrode of the organic light emitting diode OLED is connected to the common voltage ELVSS. Therefore, the organic light emitting diode OLED can receive the driving current I from the driving TFT T1. OLED And emit light, thereby displaying an image.

[0160] Despite Figure 7B In the embodiment, each of the compensation TFT T3 and the first initialization TFT T4 has a double gate electrode, but each of the compensation TFT T3 and the first initialization TFT T4 may have a single gate electrode.

[0161] Included in Fig. 7A and Figure 7B The pixel circuit PC in the pixel P illustrated in FIG. 1 is applicable to the dummy pixel circuit PC′ included in the dummy pixel Pd.

[0162] Figure 8 is a plan view of a pixel circuit applicable to a display panel according to an embodiment. According to this embodiment, the dummy pixel circuit may be the same as the pixel circuit. Therefore, Figure 8 may be a plan view of a dummy pixel circuit applicable to a display panel according to an embodiment.

[0163] refer to Figure 8, a driving TFT T1, a switching TFT T2, a compensation TFT T3, a first initialization TFT T4, an operation control TFT T5, a light emission control TFT T6, and a second initialization TFT T7 are disposed along the semiconductor layer 1130. The semiconductor layer 1130 may be disposed on a substrate on which a buffer layer including an inorganic insulating material is disposed.

[0164] Some regions of the semiconductor layer 1130 correspond to the semiconductor layers of the driving TFT T1, the switching TFT T2, the compensating TFT T3, the first initialization TFT T4, the operation control TFT T5, the light emission control TFT T6, and the second initialization TFT T7. In other words, it can be understood that the semiconductor layers of the driving TFT T1, the switching TFT T2, the compensating TFT T3, the first initialization TFT T4, the operation control TFT T5, the light emission control TFT T6, and the second initialization TFT T7 are connected to each other and bent into various shapes.

[0165] The semiconductor layer 1130 includes a channel region and a source region and a drain region on two opposite sides of the channel region. The source region and the drain region can be understood as the source electrode and the drain electrode of the relevant TFT. In the following, for the convenience of description, the source region and the drain region are respectively referred to as the source electrode and the drain electrode.

[0166] The driving TFT T1 includes a driving gate electrode G1 overlapping the driving channel region, and a driving source electrode S1 and a driving drain electrode D1 at two opposite sides of the driving channel region. The driving channel region overlapping the driving gate electrode G1 can form a long channel in a narrow space by having a curved shape such as an omega shape. When the driving channel region is long, the driving range of the gate voltage becomes wide, and thus the grayscale of light emitted from the organic light emitting diode OLED can be more finely controlled, and the display quality can be improved.

[0167] The switching TFT T2 includes a switching gate electrode G2 overlapping a switching channel region, and a switching source electrode S2 and a switching drain electrode D2 at two opposite sides of the switching channel region. The switching drain electrode D2 may be connected to the driving source electrode S1.

[0168] The compensation TFT T3 is a double TFT and thus may include a compensation gate electrode G3 respectively overlapping two compensation channel regions, and may include a compensation source electrode S3 and a compensation drain electrode D3 disposed at two opposite sides of the compensation channel region. The compensation TFT T3 may be connected to the driving gate electrode G1 of the driving TFT T1 through a node connection line 1174 to be described later.

[0169] The first initialization TFT T4 is a double TFT and thus may include a first initialization gate electrode G4 respectively overlapping two first initialization channel regions and may include a first initialization source electrode S4 and a first initialization drain electrode D4 disposed at two opposite sides of the first initialization channel region.

[0170] The operation control TFT T5 may include an operation control gate electrode G5 overlapping the operation control channel region, and an operation control source electrode S5 and an operation control drain electrode D5 disposed at two opposite sides of the operation control channel region. The operation control drain electrode D5 may be connected to the driving source electrode S1.

[0171] The light emission control TFT T6 may include a light emission control gate electrode G6 overlapping the light emission control channel region and a light emission control source electrode S6 and a light emission control drain electrode D6 disposed at two opposite sides of the light emission control channel region. The light emission control source electrode S6 may be connected to the driving drain electrode D1.

[0172] The second initialization TFT T7 may include a second initialization gate electrode G7 overlapping the second initialization channel region, and a second initialization source electrode S7 and a second initialization drain electrode D7 disposed at two opposite sides of the second initialization channel region.

[0173] The aforementioned TFTs may be connected to the signal lines SL, SIL, EL, and DL, the initialization voltage line VL, and the driving voltage line PL.

[0174] The scan line SL, the previous scan line SIL, the light emission control line EL, and the driving gate electrode G1 may be disposed on the semiconductor layer 1130 with an insulating layer therebetween.

[0175] The scan line SL may extend in the first direction (x direction). Some regions of the scan line SL may correspond to the switch gate electrode G2 and the compensation gate electrode G3. For example, regions of the scan line SL overlapping the corresponding channel regions of the switch TFT T2 and the compensation TFT T3 may be the switch gate electrode G2 and the compensation gate electrode G3, respectively.

[0176] The previous scan line SIL may extend in the first direction (x direction), and some regions of the previous scan line SIL may correspond to the first initialization gate electrode G4 and the second initialization gate electrode G7, respectively. For example, regions of the previous scan line SIL that overlap with corresponding channel regions of the first initialization TFT T4 and the second initialization TFT T7 may be the first initialization gate electrode G4 and the second initialization gate electrode G7, respectively.

[0177] The light emitting control line EL may extend in the first direction (x direction). Some regions of the light emitting control line EL may correspond to the operation control gate electrode G5 and the light emitting control gate electrode G6, respectively. For example, regions of the light emitting control line EL that overlap with corresponding channel regions of the operation control TFT T5 and the light emitting control TFT T6 may be the operation control gate electrode G5 and the light emitting control gate electrode G6, respectively.

[0178] The driving gate electrode G1 is a floating electrode, and thus may be electrically connected to the compensation TFT T3 through the above-mentioned node connection line 1174 .

[0179] The electrode voltage line HL may be disposed on the scan line SL, the previous scan line SIL, the light emission control line EL, and the driving gate electrode G1 with an insulating layer therebetween.

[0180] The electrode voltage line HL may extend in the first direction (x direction) to cross the data line DL and the driving voltage line PL. A portion of the electrode voltage line HL may cover at least a portion of the driving gate electrode G1 and may form a storage capacitor Cst together with the driving gate electrode G1. For example, the driving gate electrode G1 may serve as a first storage capacitor plate CE1 of the storage capacitor Cst, and a portion of the electrode voltage line HL may serve as a second storage capacitor plate CE2 of the storage capacitor Cst.

[0181] The second storage capacitor plate CE2 of the storage capacitor Cst is electrically connected to the driving voltage line PL. In this regard, the electrode voltage line HL can be connected to the driving voltage line PL arranged on the electrode voltage line HL through the contact hole CNT. Therefore, the electrode voltage line HL can have the same voltage level (constant voltage) as the driving voltage line PL. For example, the electrode voltage line HL can have a constant voltage of +5V. The electrode voltage line HL can be understood as a driving voltage line extending in the first direction (x direction).

[0182] Since the driving voltage line PL extends in the second direction (y direction) and the electrode voltage line HL electrically connected to the driving voltage line PL extends in the first direction (x direction) intersecting the second direction (y direction), multiple driving voltage lines PL and multiple electrode voltage lines HL can form a grid structure in the display area DA.

[0183] According to the present embodiment, the electrode voltage line HL may be disposed on a layer different from a layer on which the driving voltage line PL is disposed, and the electrode voltage line HL may have a greater resistivity than the driving voltage line PL.

[0184] The data line DL, the driving voltage line PL, the initialization connection line 1173 and the node connection line 1174 may be disposed on the electrode voltage line HL with an insulating layer therebetween.

[0185] The data line DL may extend in the second direction (y direction), and may be connected to the switching source electrode S2 of the switching TFT T2 through the contact hole 1154. A portion of the data line DL may be understood as the switching source electrode S2.

[0186] The driving voltage line PL extends in the second direction (y direction) and is connected to the electrode voltage line HL through the contact hole CNT as described above. The driving voltage line PL may also be connected to the operation control TFT T5 through the contact hole 1155. The driving voltage line PL may be connected to the operation control source electrode S5 through the contact hole 1155.

[0187] One end of the initialization connection line 1173 may be connected to the first and second initialization TFTs T4 and T7 through the contact hole 1152 , and the other end of the initialization connection line 1173 may be connected to an initialization voltage line VL to be described below through the contact hole 1151 .

[0188] One end of the node connection line 1174 may be connected to the compensation drain electrode D3 through the contact hole 1156 , and the other end of the node connection line 1174 may be connected to the driving gate electrode G1 through the contact hole 1157 .

[0189] The initialization voltage line VL may be disposed on the data line DL, the driving voltage line PL, the initialization connection line 1173 and the node connection line 1174 with an insulating layer therebetween.

[0190] The initialization voltage line VL extends in the first direction (x direction). The initialization voltage line VL may be connected to the first initialization TFT T4 and the second initialization TFT T7 through the initialization connection line 1173. The initialization voltage line VL may have a constant voltage (eg, -2V).

[0191] The initialization voltage line VL may be disposed on the same layer as the layer on which the second storage capacitor plate CE2 (i.e., the electrode voltage line HL) is disposed, and may include the same material as the material contained in the second storage capacitor plate CE2 (i.e., the electrode voltage line HL). In the display area DA, the pixel electrode of the organic light emitting diode OLED may be connected to the light emission control TFT T6. The pixel electrode may be connected to the connection metal 1175 through the contact hole 1163, and the connection metal 1175 may be connected to the light emission control drain electrode D6 through the contact hole 1153.

[0192] Fig. 9 is a plan view of some of the lines around the first region R1 in the display panel according to the embodiment, and Fig.10 is along Fig. 9 A cross-sectional view taken along line IV-IV'. Fig. 6A and Fig.10 The same reference numerals in the drawings represent the same elements, and thus repeated descriptions thereof are omitted. Fig. 9 An initialization voltage line VL, a previous scan line SIL, a scan line SL, and a light emission control line EL are illustrated.

[0193] Despite Fig. 9 In FIG. 4 , four dummy pixels Pd and two pixels P are arranged around the first region R1, but more pixels and more lines may be arranged. Fig. 9 It is described based on the first zone R1, but Fig. 9 The setting of the line is applicable to the second region R2.

[0194] refer to Fig. 9 , the initialization voltage line VL, the previous scan line SIL, the scan line SL, and the light emitting control line EL may each extend in the first direction (x direction) and may transmit a constant voltage and / or signal to the pixel P and the dummy pixel Pd.

[0195] At least one of the initialization voltage line VL, the previous scan line SIL, the scan line SL, and the light emission control line EL may be cut around the first region R1. That is, a portion of the corresponding line that passes through the first region R1 in a straight line to overlap with the first region R1 is cut to separate two cut portions on either side of the first region R1, and the two cut portions do not overlap with the first region R1. Fig. 9 In the embodiment, all the initialization voltage lines VL, the previous scan lines SIL, the scan lines SL, and the light emitting control lines EL are cut, but the present disclosure is not limited thereto. Only some of the initialization voltage lines VL, the previous scan lines SIL, the scan lines SL, and the light emitting control lines EL may be cut, and the other lines may be arranged to surround the first region R1 without being cut.

[0196] Two cut portions of each line having the first region R1 therebetween may be connected to each other through each of the connection lines SIL-C, SL-C, and EL-C or the initialization electrode layer VL-R that runs around or surrounds the first region R1.

[0197] In other words, the two cut portions of each initialization voltage line VL may be connected to the initialization electrode layer VL-R around the first region R1. The two cut portions of each previous scan line SIL may be connected to each other around the first region R1 through the previous scan connection line SIL-C. The two cut portions of each scan line SL may be connected to each other around the first region R1 through the scan connection line SL-C. The two cut portions of each light emitting control line EL may be connected to each other around the first region R1 through the light emitting control connection line EL-C.

[0198] The previous scan link line SIL-C, the scan link line SL-C, and the light emitting control link line EL-C may be included to detour around the upper side or right side of the first region R1. Although the previous scan link line SIL-C, the scan link line SL-C, and the light emitting control link line EL-C are arc curves in the figure, their detour portions may be zigzag curved lines.

[0199] Each of the initialization voltage line VL, the previous scan line SIL, the scan line SL, and the light emitting control line EL may be cut around the first region R1 in order to protect the pixels P and the dummy pixels Pd from ESD that may be generated around the first region R1.

[0200] Electrostatic charge may be accumulated around the first region R1 that may include at least one opening, and thus ESD is highly likely to occur. When each of the lines around the first region R1 is integrally formed with a single conductive layer, a large voltage due to ESD may be directly applied to the pixel P and / or the dummy pixel Pd without change.

[0201] However, according to the present embodiment, each of the lines around the first region R1 is not formed integrally with the single conductive layer, and is connected to the single conductive layer via each of the connecting lines SIL-C, SL-C, and EL-C or the initialization electrode layer VL-R which is disposed on a layer different from the layer on which the single conductive layer is disposed, and thus a large voltage due to ESD can be prevented from being directly applied to the pixel P and / or the dummy pixel Pd.

[0202] Two cut portions of each initialization voltage line VL having the first region R1 therebetween may be connected to the initialization electrode layer VL-R through the first contact hole CNT1. The initialization electrode layer VL-R may have a ring shape surrounding the first region R1.

[0203] like Fig.10 As shown in FIG. 1 , the initialization voltage line VL may be disposed on the second gate insulating layer 113, and the initialization electrode layer VL-R may be disposed on the via layer 117. The initialization electrode layer VL-R may be electrically connected to the initialization voltage line VL through the first contact hole CNT1, and the middle metal ML may be placed between the initialization electrode layer VL-R and the initialization voltage line VL.

[0204] The middle metal ML may be placed on the interlayer insulating layer 115. The middle metal ML may be connected to the initialization voltage line VL via a first first contact hole CNT1-1 passing through the interlayer insulating layer 115, and the initialization electrode layer VL-R may be connected to the middle metal ML through a second first contact hole CNT1-2. The middle metal ML may be an island-shaped metal disposed only in a region corresponding to the first contact hole CNT1, and may include the same material as that contained in the data line.

[0205] The initialization electrode layer VL-R may be disposed below the additional via layer 118, and thus the additional via layer 118 may be placed between the initialization electrode layer VL-R and the pixel electrode 310 (see Fig. 6A ).

[0206] The corresponding two cutting parts (having a first region R1 between the two cutting parts) of each previous scan line SIL, each scan line SL and each light-emitting control line EL can be respectively connected to the previous scan connection line SIL-C, the scan connection line SL-C and the light-emitting control connection line EL-C via a first bridging metal BM1 which is arranged on a layer different from the layer on which the previous scan connection line SIL-C, the scan connection line SL-C and the light-emitting control connection line EL-C are arranged.

[0207] For example, Fig.10 As shown in the figure, the first bridging metal BM1 can be disposed on the interlayer insulating layer 115 and can be connected to the previous scan link line SIL-C and the previous scan line SIL respectively via the second contact hole CNT2 and the third contact hole CNT3 (each passing through the interlayer insulating layer 115 and the second gate insulating layer 113).

[0208] The previous scan line SIL, the scan line SL, and the light emission control line EL may all be disposed on the same layer. For example, the previous scan line SIL, the scan line SL, and the light emission control line EL may be disposed on the first gate insulating layer 112 .

[0209] The previous scan connection line SIL-C, the scan connection line SL-C and the light-emitting control connection line EL-C can all be set on the same layer as the layer on which the previous scan line SIL is set, or at least one of the previous scan connection line SIL-C, the scan connection line SL-C and the light-emitting control connection line EL-C can be set on a layer different from the layer on which the previous scan line SIL is set.

[0210] exist Fig.10 , the previous scan connection line SIL-C and the light emission control connection line EL-C are disposed on the first gate insulating layer 112, and the scan connection line SL-C is disposed on the second gate insulating layer 113. However, the present disclosure is not limited thereto. For example, the previous scan connection line SIL-C and the light emission control connection line EL-C may be disposed on the second gate insulating layer 113, and the scan connection line SL-C may be disposed on the first gate insulating layer 112. In other words, in a plan view, adjacent lines among the lines arranged around the first region R1 may be disposed on different layers.

[0211] Generally, a distance between lines close to and arranged around the first region R1 is smaller than a distance between adjacent lines in the display area DA, and thus, a problem may occur due to coupling between the lines arranged around the first region R1.

[0212] However, according to the present embodiment, adjacent lines among the lines arranged around the first region R1 are arranged on different layers, and thus the generation of problems due to coupling can be minimized, and the distance between the lines can be minimized, and thus the dead zone around the first region R1 can be minimized.

[0213] Fig.11 is a plan view of some of the lines around the first region R1 of the display panel according to another embodiment. In detail, Fig.11 The preceding scanning line SIL, the scanning line SL, and the light emission control line EL are shown.

[0214] refer to Fig.11, in the first non-display area NDA1, the scan line SL of one dummy pixel Pd among adjacent dummy pixels Pd may be connected to the previous scan line SIL of the other dummy pixel Pd. For example, the first scan line SL1 on the first row that transmits the scan signal to the dummy pixels Pd placed on the left and right sides of the first region R1 may be connected to the second previous scan line SIL2 on the second row in the first non-display area NDA1. For example, in the first non-display area NDA1, the second previous scan line SIL2 may be connected to the first scan line SL1 through the first connection wiring CW1. The first connection wiring CW1 may be placed on a layer different from the layer on which the second previous scan line SIL2 and the first scan line SL1 are placed, and may be connected to the second previous scan line SIL2 and the first scan line SL1 via corresponding contact holes. According to some embodiments, the first connection wiring CW1 may be placed on an interlayer insulating layer 115, which is a layer on which the data line is placed.

[0215] Therefore, both the first scan line SL1 and the second previous scan line SIL2 may be connected to one detour line, for example, the second previous scan link line SIL2 -C.

[0216] According to the present embodiment, since the second previous scan line SIL2 and the first scan line SL1 detour around the first region R1 along a single detour line, the number of scan lines and previous scan lines crossing the first non-display area NDA1 can be reduced.

[0217] In the first non-display area NDA1, the light emitting control line of one pixel of two adjacent pixels may be connected to the light emitting control line of the other pixel. For example, the first light emitting control line EL1 on the first row that transmits the light emitting control signal to the dummy pixels Pd placed on the left and right sides of the first region R1 may be connected to the second light emitting control line EL2 on the second row in the first non-display area NDA1. For example, in the first non-display area NDA1, the second light emitting control line EL2 may be connected to the first light emitting control line EL1 through the second connection wiring CW2. The second connection wiring CW2 may be placed on a layer different from the layer on which the second light emitting control line EL2 and the first light emitting control line EL1 are placed, and may be connected to the second light emitting control line EL2 and the first light emitting control line EL1 respectively via contact holes. According to some embodiments, the second connection wiring CW2 may be placed on the interlayer insulating layer 115, which is the layer on which the data line is placed. Therefore, both the first light emitting control line EL1 and the second light emitting control line EL2 may be connected to one detour line, for example, the first light emitting control connection line EL1-C.

[0218] According to this embodiment, since the first light-emitting control line EL1 and the second light-emitting control line EL2 are routed around the first region R1 along a single detour line instead of being detoured separately, the number of light-emitting control lines crossing the first non-display area NDA1 (i.e., the number of detour lines for each light-emitting control line) can be reduced.

[0219] In the aforementioned embodiment, it has been described that the n-th light emitting control line is connected to the detour portion of the n-1-th light emitting control line. However, it can be understood that the n-1-th light emitting control line is connected to the detour portion of the n-th light emitting control line (where n is a natural number). As described above, when the n-1-th scan line and the n-th previous scan line are connected to each other and the n-1-th light emitting control line and the n-th light emitting control line are connected to each other, the detour portion of the light emitting control line connected to the previous scan line of the scan line and the detour portion of the light emitting control line connected to another light emitting control line may alternate with each other.

[0220] although Fig.11 A structure is illustrated in which the n-1th scan line and the n-th previous scan line are connected to each other and the n-1th light emission control line and the n-th light emission control line are connected to each other, but the present disclosure is not limited thereto. According to another embodiment, the n-1th scan line and the n-th previous scan line may be connected to each other, but the n-1th light emission control line and the n-th light emission control line may not be connected to each other. According to another embodiment, the n-1th light emission control line and the n-th light emission control line may be connected to each other, but the n-1th scan line and the n-th previous scan line may not be connected to each other.

[0221] Fig.12 is a plan view of some of the lines around the first region R1 of the display panel according to another embodiment. In detail, Fig.12 A data line DL is illustrated. Fig.13 is along Fig.12 A cross-sectional view taken along line V-V'.

[0222] refer to Fig.12 Each of the data lines DL may extend in the second direction (y direction), and may transmit data signals to the pixels P disposed in the display area DA and the dummy pixels Pd disposed in the first non-display area NDA1.

[0223] Some data lines DL′ located away from the first region R1 or the second region R2 among the data lines DL crossing the first non-display area NDA1 may not be cut, but each may extend in a straight line shape in the second direction (y direction).

[0224] Each of the data lines DL disposed close to the first region R1 may be cut around the first region R1. Two cut portions of each data line DL may be connected to each other through each of the data link lines DL-Ca and DL-Cb arranged around the first region R1. Fig.12 The curves are arc-shaped, but their detour parts can be zigzag curved lines.

[0225] The data lines DL may each be cut around the first region R1 in order to protect the pixels P and the dummy pixels Pd from ESD that may occur in the first region R1 .

[0226] Electrostatic charge may be accumulated around the first region R1 that may include at least one opening, and thus ESD is highly likely to occur. If each of the lines around the first region R1 is integrally formed with a single conductive layer, a large voltage due to ESD may pass through the data line DL and may be directly applied to the pixel P and / or the dummy pixel Pd.

[0227] However, according to the present embodiment, each of the data lines DL around the first region R1 is not formed integrally with the single conductive layer, and is connected to the single conductive layer via data connection lines DL-Ca and DL-Cb disposed on a layer different from the layer on which the single conductive layer is disposed, and thus a large voltage due to ESD can be prevented from being directly applied to the pixel P and / or the dummy pixel Pd.

[0228] refer to Fig.13 , the cut data line DL may be connected to the lower data link line DL-Ca via the second bridge metal BM2. The second bridge metal BM2 may be placed on the via layer 117, and may be connected to the lower data link line DL-Ca and the data line DL via the fourth contact hole CNT4 and the fifth contact hole CNT5 each passing through the via layer 117, respectively. The second bridge metal BM2 may be placed on the same layer as the layer on which the upper data link line DL-Cb is placed, and may have an island shape.

[0229] The lower data link line DL-Ca included in the data link line DL-C may be disposed on the interlayer insulating layer 115, which is a layer on which the data line DL is disposed. The upper data link line DL-Cb included in the data link line DL-C may be disposed on a via layer 117, which is a layer different from the layer on which the data line DL is disposed.

[0230] Therefore, the data link lines DL-C arranged around the first region R1 may be arranged so that the lower data link lines DL-Ca and the upper data link lines DL-Cb alternate with each other, and thus problems due to coupling between the data link lines DL-C may be minimized and dead zones may also be minimized.

[0231] According to the embodiment, the dummy pixels are disposed between regions corresponding to electronic components such as sensors or cameras, and thus the pattern density and load can be uniform, and thus a high-quality display panel can be provided. However, the aforementioned effects are exemplary, and the effects according to the embodiment will be described in detail in the following description.

[0232] It should be understood that the embodiments described herein should be considered in a descriptive sense only and not for purposes of limitation. Descriptions of features or aspects within each embodiment should typically be considered as available for other similar features or aspects in other embodiments.

[0233] Although one or more embodiments have been described with reference to the drawings, workers skilled in the art will recognize that various changes in form and details may be made therein without departing from the spirit and scope as defined by the following claims.

Claims

1. A display panel, comprising: a substrate, the substrate comprising a first area, a second area, a non-display area surrounding the first area and the second area, and a display area surrounding the non-display area; A plurality of pixels arranged on the display area; a plurality of dummy pixels disposed on the non-display area and not emitting light, the plurality of dummy pixels including a first dummy pixel and a second dummy pixel; a first signal line connected to the first dummy pixel and extending in a first direction; a second signal line connected to the second dummy pixel and spaced apart from the first signal line in a second direction crossing the first direction; a connection wiring connecting the first signal line and the second signal line; as well as A detour line connected to the connection wiring is detour line that detours around the first region.

2. The display panel according to claim 1, wherein: The detour line is provided integrally with the first signal line or the second signal line.

3. The display panel according to claim 1, wherein: At least one edge of the first signal line or the second signal line is arranged in the non-display area.

4. The display panel according to claim 1, wherein: The first signal line is a scan line connected to the first dummy pixel, and The second signal line is a previous scanning line connected to the second dummy pixel.

5. The display panel according to claim 1, wherein: The first signal line is a light emitting control line connected to the first dummy pixel, and The second signal line is a light emission control line connected to the second dummy pixel.

6. The display panel according to claim 1, wherein: The first signal line and the second signal line are provided on the same layer, and The connection wiring is provided at a layer different from the first signal line and the second signal line.

7. The display panel according to claim 1, wherein: The plurality of dummy pixels are disposed to surround the first region and the second region.

8. The display panel according to claim 1, wherein: Each of the plurality of pixels includes a pixel circuit and a display element, the pixel circuit includes at least one transistor, and the display element is connected to the pixel circuit, Each of the plurality of dummy pixels comprises a dummy pixel circuit including at least one dummy transistor, and The structure of the pixel circuit is the same as that of the dummy pixel circuit.

9. The display panel according to claim 1, further comprising a plurality of initialization voltage lines spaced apart from each other around the first area and the second area, in, The plurality of initialization voltage lines are connected to each other via an initialization electrode layer having a ring shape surrounding the first region and the second region.

10. The display panel according to claim 1, wherein: The initialization electrode layer is disposed on a layer different from a layer on which the plurality of initialization voltage lines are disposed, and is connected to the plurality of initialization voltage lines via a contact hole.

11. The display panel according to claim 1, further comprising data lines, each of which extends in the second direction and is cut around the first area, and The corresponding two cut portions of the cut data line are connected to each other through a data connection line arranged around the first region.

12. The display panel according to claim 11, wherein: Some of the data link lines are disposed at the same layer as a layer on which the data lines are disposed, and are connected to each other via a bridge metal disposed at a layer different from the layer on which the data lines are disposed.

13. The display panel according to claim 11, wherein: The data link line includes a lower data link line and an upper data link line, the lower data link line is disposed at the same layer as the layer on which the data line is disposed, the upper data link line is disposed at a layer different from the layer on which the data line is disposed, and The lower data link lines and the upper data link lines alternate with each other.

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