Tized processor communication structure

Abstract

Techniques relating to processor communication structures are disclosed. In some embodiments, a processor includes a plurality of client circuits and a structure circuit including at least a first instance and a second instance of a tile. The tile may include a client input configured to interface with client circuitry, a tile input configured to interface with one or more other tile instances, and communication resources assignable to the client input and the tile input. The communication resources may include a plurality of internal links, a client output configured to interface with client circuitry, and a tile output configured to interface with one or more other tile instances. The control circuitry may assign communication resources for a given tile instance to the client input and at least a portion of the tile input for a next cycle based on priority information in a given cycle. The control circuit may update priority information based on the assignment result over a plurality of cycles.

Description

Background Art Technical Field

[0001] The present disclosure relates generally to processor architectures, and more particularly to a tiled structure for communication between processor circuits.

[0002] Related technical description

[0003] As computer processors increase in complexity, the design of communication structures between components can be important to meeting performance, power consumption, and circuit area targets. For example, in the context of graphics processors, the number of shader pipelines typically increases over time, and communication can occur between various agents (e.g., cache controllers, different types of execution pipelines, fixed function circuits such as samplers, ray accelerator circuits, etc.). Additionally, conventional designs can be difficult to scale to meet the requirements of a given architecture. BRIEF DESCRIPTION OF THE DRAWINGS

[0004] Figure 1A is a diagram illustrating an overview of example graphics processing operations according to some embodiments.

[0005] Figure 1B is a block diagram illustrating an example graphics unit according to some embodiments.

[0006] Figure 2 is a block diagram illustrating an example client configured to communicate via a fabric according to some embodiments.

[0007] Figure 3 is a block diagram illustrating an example tile-based structure circuit according to some embodiments.

[0008] Figure 4 is a block diagram illustrating a detailed example tile including multiple slices according to some embodiments.

[0009] Figure 5 is a block diagram illustrating detailed example slices according to some embodiments.

[0010] Figure 6 is a flow diagram illustrating an example single-cycle arbitration technique for a tile according to some embodiments.

[0011] Figure 7 is a diagram illustrating an example priority comparison for arbitration according to some embodiments.

[0012] Figure 8 is a diagram illustrating an example priority mask matrix for arbitration according to some embodiments.

[0013] Fig. 9is a flow chart illustrating an example multi-cycle priority update technique according to some embodiments.

[0014] Fig.10 is a flow chart illustrating an example method according to some embodiments.

[0015] Fig.11 is a block diagram illustrating an example computing device according to some embodiments.

[0016] Fig.12 is a diagram illustrating an example application of the disclosed systems and devices according to some embodiments.

[0017] Fig.13 is a block diagram illustrating an example computer-readable medium storing circuit design information according to some embodiments. DETAILED DESCRIPTION

[0018] In the disclosed embodiments, a tile-based structure is configured to route communications between various processor agents. Examples of agents in a graphics context include memory interfaces, one or more cache controllers, shader data path circuits, fixed function circuits, etc. In other contexts (e.g., a central processing unit or a microcontroller), similar structures may be implemented.

[0019] The disclosed tile-based structures may have different configurations for different tiles, for example, in terms of the number of inputs and outputs in different directions and internal communication resources. Additionally, the structures may be configured to have different numbers of tiles in different designs. This may advantageously facilitate scaling of the structures for different processor designs or configurations. In some embodiments, the structures support different virtual channels (e.g., non-stallantable channels and stallable channels) that may have different quality of service parameters.

[0020] Within a given tile, the structure can support single-cycle arbitration between inputs by performing various arbitration operations at least partially in parallel for different inputs. The structure can also utilize a priority update scheme based on a multi-cycle window of arbitration results.

[0021] Figure 1A and Figure 1B The following discussion of provides an overview of an example graphics processor, but the disclosed circuits can be used in various types of processors (e.g., central processing units, microcontrollers, machine learning accelerators, etc.). According to some embodiments, Figures 2 to 10 The discussion covers various tiled structure circuits and arbitration techniques.

[0022] Graphics Processing Overview

[0023] refer to Figure 1A, a flowchart illustrating an example processing flow 100 for processing graphics data is shown. In some embodiments, the transformation and lighting procedures 110 may involve processing the lighting information of the vertices received from the application based on the defined light source position, reflectivity, etc., assembling the vertices into polygons (e.g., triangles), and transforming the polygons to the correct size and orientation based on the positioning in three-dimensional space. The clipping procedure 115 may involve discarding polygons or vertices outside the visible area. In some embodiments, geometry processing may utilize object shaders and mesh shaders for flexibility and efficient processing before rasterization. The rasterization procedure 120 may involve defining fragments within each polygon and assigning initial color values ​​to each fragment, for example, based on the texture coordinates of the polygon vertices. Fragments may specify the attributes of the pixels they overlap, but the actual pixel attributes may be determined based on combining multiple fragments (e.g., in a frame buffer), ignoring one or more fragments (e.g., if they are covered by other objects), or both. The shading procedure 130 may involve changing pixel components based on lighting, shadows, bump mapping, translucency, etc. The shading pixels may be assembled in a frame buffer 135. Modern GPUs typically include programmable shaders that allow application developers to customize shading and other processing routines. Thus, in various embodiments, Figure 1A The example elements of the present invention may be performed in various orders, performed in parallel, or omitted. Additional processing procedures may also be implemented.

[0024] Reference now Figure 1B , shows a simplified block diagram of an example graphics unit 150 according to some embodiments. In the illustrated embodiment, graphics unit 150 includes a programmable shader 160, a vertex pipe 185, a fragment pipe 175, a texture processing unit (TPU) 165, an image write buffer 170, and a memory interface 180. In some embodiments, graphics unit 150 is configured to process both vertex data and fragment data using programmable shader 160, which can be configured to process graphics data in parallel using multiple execution pipelines or instances.

[0025] In the illustrated embodiment, vertex pipe 185 may include various fixed-function hardware configured to process vertex data. Vertex pipe 185 may be configured to communicate with programmable shader 160 to coordinate vertex processing. In the illustrated embodiment, vertex pipe 185 is configured to send processed data to fragment pipe 175 or programmable shader 160 for further processing.

[0026] In the illustrated embodiment, the fragment pipe 175 may include various fixed function hardware configured to process pixel data. The fragment pipe 175 may be configured to communicate with the programmable shader 160 to coordinate fragment processing. The fragment pipe 175 may be configured to perform rasterization on polygons from the vertex pipe 185 or the programmable shader 160 to generate fragment data. The vertex pipe 185 and the fragment pipe 175 may be coupled to the memory interface 180 (coupling not shown) to access graphics data.

[0027] In the illustrated embodiment, the programmable shader 160 is configured to receive vertex data from the vertex pipe 185 and fragment data from the fragment pipe 175 and the TPU 165. The programmable shader 160 may be configured to perform vertex processing tasks on the vertex data, which may include various transformations and adjustments to the vertex data. For example, in the illustrated embodiment, the programmable shader 160 is also configured to perform fragment processing tasks on the pixel data, such as texturing and shading. The programmable shader 160 may include multiple sets of multiple execution pipelines for processing data in parallel.

[0028] In some embodiments, the programmable shader includes a pipeline configured to execute one or more different SIMD groups in parallel. Each pipeline may include various stages configured to perform operations (such as extraction, decoding, issuance, execution, etc.) in a given clock cycle. The concept of a processor "pipeline" is well understood and refers to the concept of dividing the "work" of the processor to the execution of instructions into multiple stages. In some embodiments, the decoding, dispatching, execution (i.e., proceeding) and withdrawal of instructions can be examples of different pipeline stages. Many different pipeline architectures may have different element / partial orderings. Various pipeline stages perform such steps on instructions during one or more processor clock cycles, and then pass the instructions or operations associated with the instructions to other stages for further processing.

[0029] The term "SIMD group" is intended to be interpreted according to its well-known meaning, which includes a group of threads for which the processing hardware processes the same instruction in parallel using different input data for different threads. SIMD groups may also be referred to as SIMT (single instruction multiple thread group), single instruction parallel thread (SIPT) or channel stack thread. Various types of computer processors may include multiple groups of pipelines configured to execute SIMD instructions. For example, a graphics processor typically includes a programmable shader core that is configured to execute instructions for a group of related threads in a SIMD manner. Other examples of names that can be used for SIMD groups include: wavefront, clique or warp. SIMD groups may be part of a larger thread group, which may be split into multiple SIMD groups based on the parallel processing capabilities of the computer. In some embodiments, each thread is assigned to a hardware pipeline (which may be referred to as a "channel") that extracts the operands of the thread and performs a specified operation in parallel with other pipelines of the group of threads. It should be noted that a processor may have a large number of pipelines so that multiple separate SIMD groups may also be executed in parallel. In some embodiments, each thread has private operand storage, for example in a register file. Thus, reading a particular register from the register file can provide a version of the register for each thread in the SIMD group.

[0030] As used herein, the term "thread" includes its meaning well known in the art, and refers to a sequence of program instructions that can be scheduled to be executed independently of other threads. Multiple threads may be included in a SIMD group to execute in lockstep. Multiple threads may be included in a task or process (which may correspond to a computer program). Threads of a given task may or may not share resources such as registers and memory. Therefore, when switching between threads of the same task, a context switch may or may not be performed.

[0031] In some embodiments, multiple programmable shader units 160 are included in a GPU. In these embodiments, global control circuitry can assign work to different subsections of the GPU, which in turn can distribute work to shader cores for processing by the shader pipeline.

[0032] In the illustrated embodiment, TPU 165 is configured to schedule fragment processing tasks from programmable shader 160. In some embodiments, TPU 165 is configured to pre-fetch texture data and assign initial colors to fragments for further processing by programmable shader 160 (e.g., via memory interface 180). TPU 165 can be configured to provide fragment components, for example, in normalized integer format or floating point format. In some embodiments, TPU 165 is configured to provide fragments in groups of four ("fragment quads") in a 2x2 format that are processed by a group of four execution pipelines in programmable shader 160.

[0033] In some embodiments, the image write buffer 170 is configured to store processed tiles of an image and can perform operations on the rendered image before transferring it for display or to memory for storage. In some embodiments, the graphics unit 150 is configured to perform tiled deferred rendering (TBDR). In tiled rendering, different portions of screen space (e.g., squares or rectangles of pixels) can be processed separately. In various embodiments, the memory interface 180 can facilitate communication with one or more of various memory hierarchies.

[0034] As discussed above, a graphics processor typically includes dedicated circuits configured to perform certain graphics processing operations requested by a computing system. For example, this may include fixed-function vertex processing circuits, pixel processing circuits, or texture sampling circuits. A graphics processor may also perform non-graphics computing tasks that may use GPU shader cores but may not use fixed-function graphics hardware. As an example, machine learning workloads (which may include inference, training, or both) are typically assigned to a GPU due to the parallel processing capabilities of the GPU. Therefore, a computing kernel executed by a GPU may include program instructions that specify a machine learning task, such as implementing a neural network layer or other aspects of a machine learning model to be executed by a GPU shader. In some cases, a non-graphics workload may also use dedicated graphics circuits, for example, for purposes different from those originally intended.

[0035] In addition, in other embodiments, the various circuits and techniques discussed herein with reference to a graphics processor may be implemented in other types of processors. Other types of processors may include general-purpose processors such as CPUs or machine learning or artificial intelligence accelerators with dedicated parallel processing capabilities. These other types of processors may not be configured to execute graphics instructions or perform graphics operations. For example, other types of processors may not include the fixed-function hardware included in a typical GPU. A machine learning accelerator may include dedicated hardware for certain operations (such as implementing other aspects of a neural network layer or a machine learning model). Generally speaking, there may be design tradeoffs between memory requirements, computing power, power consumption, and programmability of a machine learning accelerator. Therefore, different specific implementations may focus on different performance targets. Developers may choose from a plurality of potential hardware targets for a given machine learning application, such as choosing from a general-purpose processor, a GPU, and different dedicated machine learning accelerators.

[0036] Overview of tiled structures and example tile structures

[0037] Figure 2 is a block diagram illustrating an example fabric circuit 210 connecting multiple clients according to some embodiments. In the illustrated embodiment, the client includes a memory interface 220, a cache level A 230, a cache level B 250, a shader data path circuit 240, and a fixed function circuit 260.

[0038] Memory interface 220 can provide access to system memory. In some embodiments, interface 220 provides access to a shared and dynamically allocated unified memory subsystem. Various clients can utilize memory space via interface 220. Caches can use memory interface 220 to store data in backup memory, such as for eviction or write-through operations. Registers and dedicated memory spaces for various clients can be backed up via memory interface 220.

[0039] Some clients may also communicate directly with each other, for example, for non-memory access such as control packets. Generally speaking, fabric circuitry 210 may support various appropriate packets via a packet-switched network. In a packet-switched implementation, fabric circuitry 210 may route packets from a source to a destination based on header information and may be unaware of the packet payload content.

[0040] The client may include any of various cache levels (e.g., 230 and 250) that may be dedicated to instructions / data or may be shared by both. For example, the various caches may be write-back or write-through implementations. The shader data path circuit 240 may include a SIMD execution pipeline configured to execute various programs (including compute programs, vertex programs, fragment programs, etc.). The fixed function circuit may be configured to perform various operations, such as texture sampling operations, ray tracing operations, or specific vertex operations. In other embodiments, various clients are contemplated in addition to or in place of the illustrated clients.

[0041] In some embodiments, one or more clients may have access to other fabrics, such as a system-on-chip fabric that communicates with elements external to the processor that includes fabric circuitry 210. Thus, fabric circuitry 210 may be one or more fabrics of a given computing system, and different fabrics may have different configurations.

[0042] Examples of communications via the structure include: communications with the level 0 data cache, requests for vertex data from the level 1 cache, fetch requests and fragment feedback data, initialization of SIMD group state in dedicated memory, line fill requests from caches (including data caches, instruction caches, or both), etc. In general, some paths through the structure may be considered more important than others, and these paths may be designed to potentially provide lower latency, different power consumption, etc. to those paths at the expense of other paths.

[0043] Figure 3 2 is a block diagram illustrating an example tiled structure architecture according to some embodiments. In the illustrated embodiment, the structure circuit 210 includes tiles 310A-310M. In this example, each tile includes client inputs and outputs, inputs and outputs to other tiles, internal slices 320A-320N, and internal interfaces between slices. As briefly discussed above, different tiles can have different numbers of client inputs and outputs (likewise, different clients can have different numbers of inputs or outputs to the structure). Different tiles in the structure can also have different numbers or configurations of internal slices.

[0044] As shown, the tiles may be arranged in a chain configuration, with a given tile communicating with its left and right neighbor tiles (except for tiles at the ends of the chain, which may have a single neighbor tile). In other embodiments, various tile connection topologies may be implemented (e.g., ring, star, etc.). Thus, in general, a given tile may receive input from one or more other tiles and send output to one or more other tiles.

[0045] In some embodiments, the structure performs single-cycle arbitration between requests for a given tile based on the current priority of the inputs, and can adjust the priorities over multi-cycle windows.

[0046] Example Block Circuit

[0047] Figure 4 is a block diagram illustrating a more detailed view of a given tile according to some embodiments. In the illustrated embodiment, the tile includes slices 320A-320N, network interfaces (NIs) 430A-430M and 440A-440Q, and buffers 450A and 450B.

[0048] In general, a given tile 310 has multiple inputs and multiple resources that can be assigned to those inputs. For example, resources can include outputs in various directions and links within the tile 310.

[0049] It should be noted that various embodiments herein are described using north / south / east / west or horizontal / vertical coordinates. These terms are used to describe example topologies, but are not intended to limit the positioning of various inputs and outputs. In addition, topologies with other numbers of dimensions may be utilized, such as tiles with 2, 3, 5, 6, etc. sides.

[0050] As indicated by the dashed lines, a slice 320 may include dedicated resources for non-stallantable virtual channels and arbitrated resources for stallable virtual channels. In some embodiments, all resources are arbitrated, but the highest K priority values ​​are dedicated to non-stallantable channels, and a given tile includes enough resources to always satisfy requests from the highest K priority values ​​(even though in these embodiments, specific resources may not be assigned to those channels and dedicated resources may not be physically separated from non-dedicated resources). As described below in Figure 4 The detailed description of the slicing is discussed in detail after the description of Figure 5 Shown in.

[0051] In the illustrated embodiment, network interfaces 430 and 440 provide interfaces to both north and south clients. Different interfaces may have different configurations, for example to conform to different client parameters. The receive (Rx) and transmit (Tx) network interfaces may be configured similarly or differently.

[0052] In the illustrated embodiment, buffer 450 stores packet data output to other tiles in the east and west directions. As shown, in this embodiment, tile 310 also receives input from the east and west directions (e.g., via buffers storing output packets from other tiles).

[0053] As shown, the slices may be arranged according to a chain topology within a tile, although other topologies are contemplated. In some embodiments, the tile may include a crossbar circuit (not shown) at each end of the chain to route communications between tiles (e.g., between a tile input buffer / output buffer and adjacent slice circuits).

[0054] In some embodiments, each input of a tile is one of: a north Tx NI input for packets entering the network from the north in the tile, a south Tx NI input for packets entering the network from the south in the tile, an east input buffer for packets arriving from the tile to the east of the tile, and a west input buffer for packets arriving from the tile to the west of the tile.

[0055] In some embodiments, each input interface to a tile has a single-bit input valid signal that is set when there is a packet available on that interface and a single-bit output ready signal that is set by the tile when the packet has been assigned all required routes through the tile. In some embodiments, each input interface to a tile has an input resource requirement flag that indicates the type of resources required to route the packet from the input to the output of the current tile.

[0056] As an example, the types of resources that an input packet may require may include but are not limited to: connecting to the north Rx NI of the tile, connecting to the south Rx NI of the tile, routing through the east horizontal link of the tile, the east output of the tile; routing through the west horizontal link of the tile, and the west output of the tile.

[0057] Note that in some embodiments, various restrictions may be placed on input resource requirements. For example, in some embodiments, a north input may not require a north Rx NI within the same slice, a south input may not require a south Rx NI within the same slice, an east input may not require an east horizontal link or an east output, a west input may not require a west horizontal link or a west output, each valid input must require at least one north or south Rx NI or east or west output, an east horizontal link if the input requires an east output, an east horizontal link if the Tx NI input requires an Rx NI in a slice to the east of the input, an east horizontal link if the west input requires an Rx NI in any slice except the west-most input, an east horizontal link if the input requires a west output, a west horizontal link if the Tx NI input requires an Rx NI in a slice to the west of the input, and a west horizontal link if the east input requires an Rx NI in any slice except the east-most input. Specific restrictions are included for purposes of explanation (and to provide context for the arbitration techniques discussed below), but are not intended to limit the scope of this disclosure.

[0058] Example Slicing Circuit

[0059] Figure 5 is a block diagram illustrating a detailed example slice according to some embodiments. In the illustrated example, the slice includes multiplexers (MUX) 510, 515, 520A-520N and 530A-530N. As shown, slice 320 has J north client inputs, K north client outputs, M south client inputs and L south client outputs. Similarly, slice 320 has N inputs and outputs in the east and west directions. Therefore, in these embodiments, each slice may have the following main parameters: the number of east / west inputs / outputs N, the number of north inputs J, the number of north outputs K, the number of south inputs M and the number of south outputs L.

[0060] In the illustrated embodiment, MUX 510 receives all east and west inputs and selects outputs to K north clients. Similarly, in the illustrated embodiment, MUX 515 receives all east and west inputs and selects outputs to L north clients.

[0061] In the illustrated embodiment, each MUX 520 and 530 receives one or more horizontal inputs and multiple north inputs, multiple south client inputs, or both. Each MUX 520 and 530 may be configurable by the amount of slice inputs that can access any given horizontal output. In some cases, each horizontal MUX 520 or 530 may have at least as many inputs as the number of north and south inputs plus the horizontal links directly preceding it. However, to increase the efficiency of horizontal link utilization, each horizontal multiplexer may also accept inputs from up to N other horizontal links. In the case of a full set of inputs, each slice becomes a full crossbar switch, but in other embodiments (or in some slices), only a subset of the horizontal inputs may be specified to connect to a specific MUX instance.

[0062] Control circuitry may control the various illustrated multiplexers to select the input that wins arbitration to use a tile resource in a given cycle, for example, based on arbitration techniques discussed in detail below.

[0063] Example arbitration for tile resources

[0064] Figure 6 6 is a flow chart illustrating an example arbitration technique 600 according to some embodiments. In some embodiments, the control circuitry for each tile performs the arbitration technique in each cycle to assign resources to the inputs for that cycle. For example, the control circuitry may assign resources to the inputs for the cycle based on the technique. Figure 5 The multiplexer asserts the control signal. Fig. 9 As discussed, a multi-cycle priority update procedure updates the priorities for the next set of cycles, for example, based on which inputs win arbitration within a window.

[0065] Please note that Figure 7 and Figure 8 An example matrix that may be utilized by the technique 600 is shown and will therefore be incorporated herein by reference. Figure 6 The discussion is briefly cited.

[0066] At 610, in the illustrated embodiment, the control circuit determines input priorities (eg, unique priority identifiers from 0 to N-1 for the N inputs). As discussed above, a subset of the highest priority inputs may be reserved for one or more non-stallantable channels.

[0067] At 620, in the illustrated embodiment, the control circuit forms an N by N priority comparison matrix (PCM), where PCM[i][j] indicates whether input-i or input-j has a greater priority (e.g., a bit may be set in an entry of the matrix if the priority of input-i is greater than or equal to the priority of input-j). For example, foreach(i,j): PCM[i][j]=i.priorityID>=j.priorityID. Note that the same PCM value may be used for multiple cycles, e.g., when the priority has not changed between cycles.

[0068] Brief reference Figure 7 , shows an example PCM 700 where input A has priority 5, input B has priority 7, and input N-1 has priority 2. Note that only a portion of the PCM may actually be stored in the circuit, for example, because the diagonal may be don't care (x) and the two other portions may be mirrored along the diagonal. In this example, PCM[1][0] is set because input B has a higher priority than input A.

[0069] At 630, in the illustrated embodiment, the control circuit forms an N by N priority mask matrix (PMM) for each tile resource R. In this example, if both inputs request resource R and input-i has a priority greater than or equal to input-j, then PMM[i][j] is set. Specifically, foreach(r): r.PMM[i][j] = i.valid&&i.requiresResource[r]&&j.valid&&j.requiresResource[r]&&PCM[i][j]. Note that the control circuit may determine which inputs target which resources based on packet header information indicating the destination client circuit, for example.

[0070] Brief reference Figure 8 , shows an example PMM 800. In this example, the priority is related to Figure 7The priority of inputs A and N is the same, and inputs A and N request resource R (but input B does not). In this example, PMM[0][N-1] is set because both input A and input N-1 request resource R and input A has a greater priority. Note that this data structure can be stored in a compressed form similar to PCM 700, as discussed above, for example, because the diagonal values ​​are known and the remainder can be mirrored.

[0071] At 640, in the illustrated embodiment, the control circuitry sums across each row of the PMM to generate a sub-resource allocation ID for each input to each resource. For example, foreach (i, j): i.allocationID += r.PMM[i][j].

[0072] Reference again Figure 8 , the sub-resource allocation ID for input A is the sum of the rows (top row) of input A. In this embodiment, a sum of zero indicates that input A has no requested resources. A sum of 1 means that A is the highest priority input requesting resources. A sum of N means that A is the lowest priority input requesting resources (all inputs have higher priority and their bits are in the row group).

[0073] At 650, in the illustrated embodiment, the control circuitry performs a resource availability count to determine the number of sub-resources available per resource. This may be based on buffer status, the number of tile outputs of one or more types, and the like.

[0074] At 660, in the illustrated embodiment, the control circuit compares the subresource ID of each input for each resource to the availability count of the resource. For example, in parallel, foreach(r,s):r.availabilityCount+=r.subResourceAvailable[s]. If the ID does not exceed the count, for example, foreach(i,r):i.allocationLegal[r]=i.allocationID[r]<=r.availabilityCount, the control circuit determines a legal allocation. The control circuit can select the input to provide data for a legal allocation, or otherwise stall the input.

[0075] In this way, the assignment of inputs to resources can change each cycle, even for cycles with the same input priority, e.g., because the inputs that actually request a resource can vary from cycle to cycle. Additionally, as discussed above, various calculations (such as determining the PMM for each resource and determining a resource availability count) can be performed in parallel to facilitate single-cycle arbitration (or more generally, arbitration using a small number of cycles).

[0076] Example Priority Update Procedure

[0077] Fig. 9 is a flow diagram illustrating an example priority update technique 900 according to some embodiments. In some embodiments, a priority update window is defined, for example, as a certain number of cycles, and the control circuit updates the priority of inputs for a given tile based on arbitration decisions during the window.

[0078] At 910, in the illustrated example, priority IDs 0 to K-1 are reserved for K non-stagnable inputs. These priority IDs may be dynamically assigned to each priority update procedure, or may be fixed. In other embodiments, a field may indicate whether an input is non-stagnable and a non-stagnable input may be considered to have a higher priority than any stallable input.

[0079] At 920, in the illustrated example, the control circuit determines in the stagnation inputs over M cycles: winner, loser, and non-requester. For example, the winner may be an input whose request is fully allocated the requested resources. In some embodiments, the winner may be divided into a complete winner (an input whose most recent valid request is fully allocated the requested resources) and a partial winner (an input with a previous request that is fully allocated all requested resources within the decision window, but whose most recent valid request is not fully allocated all requested resources within the window). The loser may be an input for which no valid request is fully allocated the requested resources within the decision window. Invalid / non-requesters may be inputs for which no valid request is received within the decision window.

[0080] At 930, in the illustrated example, the control circuitry adjusts the priorities so that the highest priority winner becomes the lowest priority stallable input and the highest priority loser becomes the highest priority stallable input. Invalid inputs may have a resulting priority value between the loser and the winner. In an embodiment that tracks partial winners, the partial winners may have a new priority value between the invalid inputs and the winner. In addition, the control circuitry may reverse the priorities within a given category of inputs, e.g., reverse the priority order for the winner input and the partial winner input.

[0081] In general, the disclosed techniques can advantageously provide fairness over time between stallable inputs. In addition, in some embodiments, priority can only be reduced for non-stallable inputs that have been granted at least one request within a window, thus advantageously guaranteeing forward progress.

[0082] Example Method

[0083] Fig.10 is a flow chart illustrating an example method for using a tiled structure according to some embodiments. Fig.10The methods shown in the can be used in conjunction with any of the computer circuits, systems, devices, elements or components disclosed herein. In various embodiments, some of the method elements shown can be performed concurrently in a different order than shown, or can be omitted. Additional method elements can also be performed as needed.

[0084] At 1010 , in the illustrated embodiment, the computing system assigns communication resources of the tiled fabric circuit for a given cycle based on the input priority information for a given tile instance.

[0085] In some embodiments, the structure includes at least a first instance and a second instance of a tile, and the tile includes: a client input configured to interface with a client circuit of a computing system, a tile input configured to interface with one or more other tile instances, and communication resources assignable to the client input and the tile input. The communication resources may include: a plurality of internal links, a client output configured to interface with the client circuit, and a tile output configured to interface with one or more other tile instances.

[0086] In some embodiments, the assigning assigns the communication resources of a given tile instance to at least a portion of the client input and the tile input for the next period based on priority information of the input of the tile instance.

[0087] In some embodiments, to assign communication resources for a given tile instance, the control circuit is configured to: determine priority information for inputs to the tile instance at least partially in parallel for multiple communication resources and multiple inputs, determine the number of inputs that have a higher priority than the given input and request the same resources, determine for a given resource the number of inputs that the resource can serve in a given cycle, and assign communication resources to the inputs for the given cycle based on the determination of the number of inputs.

[0088] In some embodiments, the communication resources include dedicated resources for one or more non-stagnable virtual channels and arbitration resources for the stallable virtual channels. In some embodiments, the control circuit is configured to assign a set of highest priority indications to the non-stagnable virtual channel inputs.

[0089] At 1020 , in the illustrated embodiment, the computing system updates the priority information of the given tile instance of the fabric circuit based on the assignment results over a plurality of cycles.

[0090] In some embodiments, in order to update the priority information for a given tile instance based on the assignment results over multiple cycles, the control circuit classifies the input to the tile instance based on whether the input receives all or part of the requested resources over multiple cycles, and updates the priority of the input to the tile instance based on the classification. For example, the categories may include: a winner input category, the most recent valid request of the winner input category is fully allocated all requested resources; a partial winner input category, the most recent valid request of the partial winner input category is not fully allocated all requested resources within multiple cycles, for which the previous request is fully allocated all requested resources within the multiple cycles; a loser category, for which no valid request is fully allocated the requested resources within the multiple cycles; and an invalid input category, for which no valid request is received within the multiple cycles. In some embodiments, in order to update the priority, the control circuit prioritizes according to the following order from highest to lowest priority: loser input, invalid input, partial winner input, and then winner input. In some embodiments, the control circuitry may reverse the priority ordering between some of the winner inputs and reverse the priority ordering between the winner inputs.

[0091] In some embodiments, a given tile instance includes multiple slices, and the multiple internal links are links between slices. In some embodiments, the slices are arranged in a chain topology, and the given tile instance includes a crossbar switch at one or both ends of the tile chain (e.g., included as part of an end slice so that the multiplexers of those slices have additional inputs for forming a full crossbar switch). In some embodiments, the crossbar switch is connected to a buffer configured to store data for tile outputs and data from tile inputs.

[0092] In some embodiments, the first instance and the second instance of the tile include different numbers of inputs and different amounts of communication resources. In some embodiments, the fabric circuit includes a chain of tile instances, the chain of tile instances including the first instance and the second instance of the tile, wherein adjacent tile instances in the chain are connected via at least a portion of the tile inputs and the tile outputs of a given tile instance.

[0093] As used herein, the terms "clock" and "clock signal" refer to periodic signals, for example, as in a two-value (binary) electrical signal. The clock changes periodically between the "level" of the clock (such as the voltage range of the electrical signal). For example, a voltage greater than 0.7 volts can be used to represent a clock level, and a voltage less than 0.3 volts can be used to represent another level in a binary configuration. As used herein, the term "clock edge" refers to the change of a clock signal from one level to another. As used herein, in the context of a clock signal, the term "switching" refers to changing the value of a clock signal from one level to another in a binary clock configuration. As used herein, the term clock "pulse" refers to the interval of a clock signal between the continuous edges of a clock signal (for example, the interval between a rising edge and a falling edge or the interval between a falling edge and a rising edge). As used herein, the term "clock cycle" refers to the interval between the edges of a clock (for example, in a conventional embodiment, between rising edges or between falling edges, or in a dual edge embodiment, between adjacent edges).

[0094] Example Device

[0095] Reference now Fig.11 , a block diagram of an example implementation of an exemplary device 1100 is shown. In some embodiments, elements of the device 1100 may be included in a system on a chip. In some embodiments, the device 1100 may be included in a mobile device that may be powered by a battery. Therefore, the power consumption of the device 1100 may be an important design consideration. In the illustrated embodiment, the device 1100 includes a structure 1110, a computing complex 1120, an input / output (I / O) bridge 1150, a cache / memory controller 1145, a graphics unit 1175, and a display unit 1165. In some embodiments, in addition to or in place of the components shown, the device 1100 may include other components (not shown), such as video processor encoders and decoders, image processing or recognition elements, computer vision elements, etc.

[0096] The structure 1110 may include various interconnects, buses, MUXs, controllers, etc., and may be configured to facilitate communication between various elements of the device 1100. In some embodiments, portions of the structure 1110 may be configured to implement a variety of different communication protocols. In other embodiments, the structure 1110 may implement a single communication protocol, and elements coupled to the structure 1110 may be internally converted from the single communication protocol to other communication protocols. Note that the structure 1110 may have a different topology and configuration than the structure circuit 210.

[0097] In the illustrated embodiment, computing complex 1120 includes a bus interface unit (BIU) 1125, a cache 1130, and cores 1135 and 1140. In various embodiments, computing complex 1120 may include various numbers of processors, processor cores, and caches. For example, computing complex 1120 may include 1, 2, or 4 processor cores, or any other suitable number. In one embodiment, cache 1130 is a set of associative L2 caches. In some embodiments, cores 1135 and 1140 may include internal instruction and data caches. In some embodiments, a consistency unit (not shown) in structure 1110, cache 1130, or elsewhere in device 1100 may be configured to maintain consistency between the various caches of device 1100. BIU 1125 may be configured to manage communications between computing complex 1120 and other elements of device 1100. Processor cores such as cores 1135 and 1140 may be configured to execute instructions of a specific instruction set architecture (ISA) that may include operating system instructions and user application instructions.

[0098] The cache / memory controller 1145 may be configured to manage data transfers between the fabric 1110 and one or more caches and memories. For example, the cache / memory controller 1145 may be coupled to an L3 cache, which in turn may be coupled to system memory. In other embodiments, the cache / memory controller 1145 may be coupled directly to the memory. In some embodiments, the cache / memory controller 1145 may include one or more internal caches.

[0099] As used herein, the term "coupled to" may indicate one or more connections between elements, and a coupling may include intermediate elements. Fig.11 In FIG, graphics unit 1175 may be described as being "coupled to" memory via structure 1110 and cache / memory controller 1145. In contrast, in Fig.11 In the illustrated embodiment, graphics unit 1175 is "directly coupled" to structure 1110 because there are no intervening elements.

[0100] Graphics unit 1175 may include one or more processors, such as one or more graphics processing units (GPUs). For example, graphics unit 1175 may receive graphics-oriented instructions, such as Metal or Instructions. Graphics unit 1175 may execute dedicated GPU instructions or perform other operations based on the received graphics-oriented instructions. Graphics unit 1175 may generally be configured to process large blocks of data in parallel and may build images in a frame buffer for output to a display, which may be included in the device or may be a separate device. Graphics unit 1175 may include transformation, lighting, triangle, and rendering engines in one or more graphics processing pipelines. Graphics unit 1175 may output pixel information for displaying an image. In various embodiments, graphics unit 1175 may include programmable shader circuits, which may include highly parallel execution cores configured to execute graphics programs, which may include pixel tasks, vertex tasks, and computational tasks (which may or may not be graphics-related).

[0101] In some embodiments, the disclosed communication structure can be included in the graphics unit 1175 and can be used for communication between data path circuits, one or more cache levels, fixed function circuits, etc. The disclosed technology can advantageously facilitate communication in a scalable manner. It is noted that the disclosed structure can also or alternatively be implemented in other processors such as the computing complex 1120.

[0102] The display unit 1165 may be configured to read data from the frame buffer and provide a stream of pixel values ​​for display. In some embodiments, the display unit 1165 may be configured as a display pipeline. In addition, the display unit 1165 may be configured to blend multiple frames to produce an output frame. In addition, the display unit 1165 may include one or more interfaces (e.g., a touch screen or an external display) for coupling to a user display (e.g., or embedded DisplayPort (eDP).

[0103] The I / O bridge 1150 may include various elements configured to implement, for example, universal serial bus (USB) communications, security, audio, and low-power always-on functionality. The I / O bridge 1150 may also include interfaces such as pulse width modulation (PWM), general purpose input / output (GPIO), serial peripheral interface (SPI), and inter-integrated circuit (I2C). Various types of peripherals and devices may be coupled to the device 1100 via the I / O bridge 1150.

[0104] In some embodiments, the device 1100 includes a network interface circuit (not explicitly shown), which can be connected to the structure 1110 or the I / O bridge 1150. The network interface circuit can be configured to communicate via various networks, which can be wired networks, wireless networks, or both. For example, the network interface circuit can be configured to communicate via a wired local area network, a wireless local area network (e.g., via WiFi), or a wide area network (e.g., the Internet or a virtual private network). In some embodiments, the network interface circuit is configured to communicate via one or more cellular networks using one or more radio access technologies. In some embodiments, the network interface circuit is configured to communicate using device-to-device communication (e.g., Bluetooth or WiFi Direct), etc. In various embodiments, the network interface circuit can provide a connection with various types of other devices and networks for the device 1100.

[0105] Sample Application

[0106] Now go to Fig.12 , shows various types of systems that may include any of the circuits, devices, or systems described above. The system or device 1200 that may incorporate or otherwise utilize one or more of the techniques described herein may be used in a wide variety of fields. For example, the system or device 1200 may be used as part of the hardware of a system such as a desktop computer 1210, a laptop computer 1220, a tablet computer 1230, a cellular or mobile phone 1240, or a television 1250 (or a set-top box coupled to a television).

[0107] Similarly, the disclosed elements can be used in a wearable device 1260, such as a smart watch or a health monitoring device. In many embodiments, a smart watch can implement a variety of different functions—for example, access to email, cellular service, calendar, health monitoring, etc. A wearable device can also be designed to perform only health monitoring functions, such as monitoring a user's vital signs, performing epidemiological functions such as contact tracing, providing communications to emergency medical services, etc. Other types of devices are also contemplated, including devices worn around the neck, devices implantable in the human body, glasses or helmets designed to provide computer-generated reality experiences, such as those based on augmented reality and / or virtual reality, etc.

[0108] The system or device 1200 may also be used in a variety of other environments. For example, the system or device 1200 may be used in the context of a server computer system (such as a dedicated server) or on shared hardware that implements a cloud-based service 1270. Further, the system or device 1200 may be implemented in a wide range of dedicated everyday devices, including devices 1280 common in the home, such as refrigerators, thermostats, security cameras, etc. The interconnection of such devices is generally referred to as the "Internet of Things" (IoT). Elements may also be implemented in various modes of transportation. For example, the system or device 1200 may be used for control systems, guidance systems, entertainment systems, etc. of various types of vehicles 1290.

[0109] Fig.12 The applications shown in are merely exemplary and are not intended to limit the potential future applications of the disclosed system or device. Other example applications include, but are not limited to: portable game devices, music players, data storage devices, unmanned aerial vehicles, etc.

[0110] Example Computer Readable Medium

[0111] The disclosure has described various example circuits in detail above. It is intended that the disclosure encompass not only embodiments including such circuits, but also computer-readable storage media including design information specifying such circuits. Thus, the disclosure is intended to support claims that encompass not only devices including the disclosed circuits, but also storage media that specify the circuits in a format recognized by a manufacturing system configured to produce hardware (e.g., an integrated circuit) that includes the disclosed circuits. Claims to such storage media are intended to cover, for example, entities that generate a circuit design but do not manufacture the design itself.

[0112] Fig.13 13 is a block diagram illustrating an example non-transitory computer-readable storage medium storing circuit design information according to some embodiments. In the illustrated embodiment, semiconductor manufacturing system 1320 is configured to process design information 1315 stored on non-transitory computer-readable medium 1310 and manufacture integrated circuit 1330 based on design information 1315.

[0113] The non-transitory computer-readable storage medium 1310 may include any of a variety of suitable types of memory devices or storage devices. The non-transitory computer-readable storage medium 1310 may be an installation medium, such as a CD-ROM, a floppy disk, or a tape device; a computer system memory or random access memory, such as DRAM, DDR RAM, SRAM, EDO RAM, Rambus RAM, etc.; a non-volatile memory, such as flash memory, a magnetic medium, for example, a hard drive or an optical storage device; a register, or other similar type of memory element, etc. The non-transitory computer-readable storage medium 1310 may also include other types of non-transitory memory or combinations thereof. The non-transitory computer-readable storage medium 1310 may include two or more memory media that may reside in different locations, such as different computer systems connected by a network.

[0114] Design information 1315 may be specified using any of a variety of suitable computer languages, including hardware description languages ​​such as, but not limited to, VHDL, Verilog, SystemC, SystemVerilog, RHDL, M, MyHDL, etc. Design information 1315 may be used by semiconductor manufacturing system 1320 to manufacture at least a portion of integrated circuit 1330. The format of design information 1315 may be recognizable by at least one semiconductor manufacturing system 1320. In some embodiments, design information 1315 may also include one or more cell libraries that specify the synthesis, layout, or both of integrated circuit 1330. In some embodiments, the design information is specified in whole or in part in the form of a netlist that specifies cell library elements and their connectivity. Design information 1315 obtained separately may or may not include sufficient information for manufacturing the corresponding integrated circuit. For example, design information 1315 may specify circuit elements to be manufactured, but not their physical layout. In this case, design information 1315 may need to be combined with layout information to actually manufacture the specified circuit.

[0115] In various embodiments, integrated circuit 1330 may include one or more custom macrocells, such as memory, analog or mixed signal circuits, etc. In this case, design information 1315 may include information related to the included macrocells. Such information may include, but is not limited to, schematic capture databases, mask design data, behavioral models, and device or transistor level netlists. As used herein, mask design data may be formatted according to a graphic data system (GDSII) or any other suitable format.

[0116] Semiconductor manufacturing system 1320 may include any of a variety of suitable elements configured to manufacture integrated circuits. This may include, for example, elements for depositing semiconductor material (e.g., on a wafer that may include a mask), removing material, changing the shape of deposited material, modifying material (e.g., by doping the material or using ultraviolet treatment to modify the dielectric constant), etc. Semiconductor manufacturing system 1320 may also be configured to perform various tests of the manufactured circuits for proper operation.

[0117] In various embodiments, integrated circuit 1330 is configured to operate according to the circuit design specified by design information 1315, which may include performing any of the functions described herein. For example, integrated circuit 1330 may include Figure 1B , Figures 2 to 5 and Fig.11 Any of the various elements shown. In addition, integrated circuit 1330 can be configured to perform various functions described herein in conjunction with other components. In addition, the functionality described herein can be performed by multiple connected integrated circuits.

[0118] As used herein, a phrase of the form "design information specifying a design of a circuit configured to..." does not imply that the circuit in question must be manufactured in order to satisfy the element. Rather, the phrase indicates that the design information describes a circuit that, when manufactured, will be configured to perform the indicated actions or will include the specified components.

[0119] ***

[0120] This disclosure includes references to "an embodiment" or groups of "embodiments" (e.g., "some embodiments" or "various embodiments"). Embodiments are different specific implementations or examples of the disclosed concepts. References to "an embodiment," "one embodiment," "a particular embodiment," etc. are not necessarily to the same embodiment. A large number of possible embodiments are contemplated, including those specifically disclosed, as well as modifications or alternatives that fall within the spirit or scope of the present disclosure.

[0121] The present disclosure may discuss potential advantages that may be generated by the disclosed embodiments. Not all of these implementations will necessarily exhibit any or all of the potential advantages. Whether a particular implementation achieves an advantage depends on many factors, some of which are outside the scope of the present disclosure. In fact, there are many reasons why an implementation that falls within the scope of the claims may not exhibit some or all of any of the disclosed advantages. For example, a particular implementation may include other circuits outside the scope of the present disclosure that, in combination with one of the disclosed embodiments, negate or reduce one or more of the disclosed advantages. In addition, suboptimal design execution of a particular implementation (e.g., a specific implementation technique or tool) may also negate or reduce the disclosed advantages. Even assuming a specific implementation of the technology, the realization of the advantages may still depend on other factors, such as the environmental conditions in which the specific implementation is deployed. For example, the input provided to a particular implementation may prevent one or more problems solved in the present disclosure from occurring in a particular occasion, and as a result, the benefits of its solution may not be realized. In view of the existence of possible factors external to the present disclosure, it is hereby clarified that any potential advantages described herein should not be construed as claim limitations that must be met in order to prove infringement. Instead, the identification of such potential advantages is intended to illustrate the types of improvements available to designers who benefit from the present disclosure. Permanently describing such advantages (eg, stating that a particular advantage "may occur") is not intended to convey a doubt as to whether such advantage can actually be achieved, but rather to recognize that achievement of such advantage typically depends on technical realities of additional factors.

[0122] Unless otherwise stated, the embodiments are non-limiting. That is, the disclosed embodiments are not intended to limit the scope of the claims drafted based on the present disclosure, even if only a single example is described with respect to a particular feature. The embodiments disclosed by the present invention are intended to be illustrative and non-restrictive, without any contrary statement in the present disclosure. Therefore, the present application is intended to allow claims covering the disclosed embodiments, as well as such alternatives, modifications and equivalents, which will be apparent to those skilled in the art who are aware of the beneficial effects of the present disclosure.

[0123] For example, features in this application may be combined in any suitable manner. Accordingly, new claims may be made during the prosecution of this application (or an application claiming priority thereto) for any such combination of features. In particular, with reference to the appended claims, features of dependent claims may be combined, where appropriate, with features of other dependent claims, including claims that are dependent on other independent claims. Similarly, features from corresponding independent claims may be combined, where appropriate.

[0124] Thus, while the appended dependent claims may be drafted such that each dependent claim is dependent upon a single other claim, additional dependencies are also contemplated. Any combination of dependent features consistent with the present disclosure is contemplated and may be claimed in this or another application. In short, the combinations are not limited to those specifically recited in the appended claims.

[0125] It is also contemplated that claims drafted in one format or legal type (eg, apparatus) are intended to support corresponding claims in another format or legal type (eg, method), where appropriate.

[0126] ***

[0127] Because this disclosure is a legal document, various terms and phrases may be subject to regulatory and judicial interpretation. Notice is hereby given that the definitions provided in the following paragraphs and throughout this disclosure will be used to determine how to interpret claims drafted based on this disclosure.

[0128] Unless the context clearly dictates otherwise, reference to an item in the singular (i.e., a noun or noun phrase preceded by "a," "an," or "the") is intended to mean "one or more." Thus, reference to "an item" in a claim does not exclude additional instances of that item without the accompanying context. A "plurality" of an item refers to a group of two or more items.

[0129] The word "may" is used herein in a permissive sense (ie, having the potential to, being able to), rather than the mandatory sense (ie, must).

[0130] The terms "including" and "comprising" and forms thereof are open ended and mean "including, but not limited to."

[0131] When the term "or" is used in this disclosure with respect to a list of options, it will generally be understood to be used in an inclusive sense unless the context provides otherwise. Thus, the expression "x or y" is equivalent to "x or y, or both," and thus encompasses 1) x but not y, 2) y but not x, and 3) both x and y. On the other hand, phrases such as "either x or y, but not both" make it clear that "or" is used in an exclusive sense.

[0132] The expressions "w, x, y, or z, or any combination thereof" or "... at least one of w, x, y, and z" are intended to cover all possibilities involving individual elements up to the total number of elements in the set. For example, given the set [w, x, y, z], these phrases cover any single element in the set (e.g., w but not x, y, or z), any two elements (e.g., w and x, but not y or z), any three elements (e.g., w, x, and y, but not z), and all four elements. The phrase "... at least one of w, x, y, and z" thus refers to at least one element in the set [w, x, y, z], thereby covering all possible combinations in the list of elements. The phrase should not be interpreted as requiring the presence of at least one instance of w, at least one instance of x, at least one instance of y, and at least one instance of z.

[0133] In this disclosure, various "labels" may precede a noun or noun phrase. Unless the context provides otherwise, different labels used for a feature (e.g., "a first circuit," "a second circuit," "a particular circuit," "a given circuit," etc.) refer to different instances of the feature. Additionally, unless otherwise stated, the labels "first," "second," and "third" do not imply any type of ordering (e.g., spatial, temporal, logical, etc.) when applied to features.

[0134] The phrase "based on" or is used to describe one or more factors that influence a determination. This term does not exclude the possibility that additional factors may influence the determination. That is, a determination may be based only on the specified factors or on the specified factors and other unspecified factors. Consider the phrase "A is determined based on B." This phrase specifies that B is a factor used to determine A or that B influences the determination of A. This phrase does not exclude that the determination of A may also be based on some other factor such as C. This phrase is also intended to cover embodiments in which A is determined based only on B. As used herein, the phrase "based on" is synonymous with the phrase "based at least in part on."

[0135] The phrases "in response to" and "in response to" describe one or more factors that trigger an effect. The phrase does not exclude the possibility that additional factors may influence or otherwise trigger the effect, either in conjunction with the specified factors or independently of the specified factors. That is, the effect may be responsive to these factors alone, or may be responsive to the specified factors as well as other unspecified factors. Consider the phrase "A is performed in response to B." The phrase specifies that B is a factor that triggers the execution of A or triggers a specific result of A. The phrase does not exclude that the execution of A may also be responsive to certain other factors, such as C. The phrase also does not exclude that the execution of A may be performed jointly in response to B and C. This phrase is also intended to cover embodiments in which A is performed only in response to B. As used herein, the phrase "in response to" is synonymous with the phrase "at least partially in response to." Similarly, the phrase "in response to" is synonymous with the phrase "at least partially in response to."

[0136] ***

[0137] Within the present disclosure, different entities (which may be variously referred to as "units," "circuits," other components, etc.) may be described or claimed as being "configured to" perform one or more tasks or operations. This expression—[an entity] configured to [perform one or more tasks]—is used herein to refer to a structure (i.e., a physical thing). More specifically, this expression is used to indicate that this structure is arranged to perform one or more tasks during operation. A structure may be considered to be "configured to" perform a task even if the structure is not currently being operated. Therefore, an entity described or stated as "configured to" perform a task refers to a physical thing used to implement the task, such as a device, a circuit, a system with a processor unit, and a memory storing executable program instructions, etc. This phrase is not used herein to refer to an intangible thing.

[0138] In some cases, various units / circuits / components may be described herein as performing a set of tasks or operations. It should be understood that these entities are "configured to" perform those tasks / operations, even if not specifically stated.

[0139] The term "configured to" is not intended to mean "configurable to". For example, an unprogrammed FPGA would not be considered "configured to" perform a particular function. However, the unprogrammed FPGA may be "configurable to" perform that function. After being appropriately programmed, the FPGA may then be considered "configured to" perform the particular function.

[0140] For purposes of a U.S. patent application based on the present disclosure, stating in a claim that a structure is “configured to” perform one or more tasks is expressly intended not to invoke 35 U.S.C. §112(f) for that claim element. If the applicant wishes to invoke section 112(f) during prosecution of a U.S. patent application based on the present disclosure, it would use the “means for [performing the function]” construct to phrase the claim element.

[0141] Different "circuits" may be described in the present disclosure. These circuits constitute hardware that includes various types of circuit elements, such as combinational logic, clock storage devices (e.g., flip-flops, registers, latches, etc.), finite state machines, memories (e.g., random access memory, embedded dynamic random access memory), programmable logic arrays, etc. Circuits may be custom designed or taken from standard libraries. In various specific implementations, circuits may include digital components, analog components, or a combination of both, as appropriate. Certain types of circuits may be generally referred to as "units" (e.g., decoding units, arithmetic logic units (ALUs), functional units, memory management units (MMUs), etc.). Such units are also referred to as circuits or circuits.

[0142] Thus, the disclosed circuits / units / components and other elements illustrated in the drawings and described herein include hardware elements, such as those described in the preceding paragraphs. In many cases, the internal arrangement of hardware elements in a particular circuit can be specified by describing the functionality of the circuit. For example, a particular "decode unit" may be described as performing the function of "processing an opcode for an instruction and routing the instruction to one or more of a plurality of functional units," meaning that the decode unit is "configured to" perform that function. For one skilled in the computer arts, this functional specification is sufficient to suggest a set of possible structures for the circuit.

[0143] In various embodiments, as described in the preceding paragraphs, circuits, units, and other elements may be defined by the functions or operations they are configured to implement. The arrangement relative to each other and such circuits / units / components and the way they interact form a microarchitecture definition of hardware, which is ultimately manufactured in an integrated circuit or programmed into an FPGA to form a physical implementation of the microarchitecture definition. Therefore, the microarchitecture definition is considered by those skilled in the art to be a structure from which many physical implementations can be derived, all of which fall into the broader structure described by the microarchitecture definition. That is, a technician with a microarchitecture definition provided in accordance with the present disclosure can implement the structure by coding a description of a circuit / unit / component in a hardware description language (HDL) such as Verilog or VHDL without excessive experimentation and using the application of ordinary technicians. HDL descriptions are often expressed in a way that can be displayed as functional. However, for those skilled in the art, the HDL description is a way to convert the structure of a circuit, unit, or component into the next level of specific implementation details. Such HDL descriptions may take the form of behavioral code (which is generally non-synthesizable), register transfer language (RTL) code (which is generally synthesizable compared to behavioral code), or structural code (e.g., a netlist specifying logic gates and their connectivity). The HDL description may be sequentially synthesized for a library of cells designed for a given integrated circuit manufacturing technology, and may be modified for timing, power, and other reasons to obtain a final design database that is sent to the factory to generate masks and ultimately produce integrated circuits. Some hardware circuits or portions thereof may also be custom designed in a schematic editor and captured into an integrated circuit design along with the synthesized circuits. The integrated circuit may include transistors and other circuit elements (e.g., passive elements such as capacitors, resistors, inductors, etc.), as well as interconnects between transistors and circuit elements. Some embodiments may implement multiple integrated circuits coupled together to implement the hardware circuit, and / or discrete elements may be used in some embodiments. Alternatively, the HDL design may be synthesized into a programmable logic array such as a field programmable gate array (FPGA), and may be implemented in an FPGA. This decoupling between the design of a set of circuits and the subsequent low-level implementation of those circuits often leads to a situation where a circuit or logic designer never specifies a specific set of structures for the low-level implementation beyond a description of what the circuits are configured to do, because that process is performed at different stages of the circuit implementation process.

[0144] The fact that many different low-level combinations of circuit elements can be used to achieve the same specification of a circuit results in a large number of equivalent structures for that circuit. As noted, these low-level circuit implementations can vary depending on variations in manufacturing technology, the foundry selected to manufacture the integrated circuit, the cell libraries provided for a particular project, etc. In many cases, the selection made by different design tools or methodologies to produce these different implementations can be arbitrary.

[0145] Furthermore, for a given embodiment, a single implementation of a particular functional specification of a circuit typically includes a large number of devices (e.g., millions of transistors). Thus, the shear volume of this information makes it impractical to provide a complete description of the low-level structure used to implement a single embodiment, let alone the large number of equivalent possible implementations. For this reason, the present disclosure describes the structure of the circuit using functional shorthand commonly used in the industry.

Claims

1. A device, comprising a processor, wherein the processor comprises: Multiple client circuits; A structure circuit, the structure circuit comprising at least a first instance and a second instance of a block, wherein the block comprises: a client input configured to interface with a client circuit; a tile input configured to interface with one or more other tile instances; and A communication resource, the communication resource being assignable to the client input and the tile input, wherein the communication resource comprises: Multiple internal links; a client output configured to interface with a client circuit; and a tile output, the tile output being configured to interface with one or more other tile instances; A control circuit, the control circuit being configured to: In a given cycle, assigning communication resources of a given tile instance to the client input and at least a portion of the tile input for a next cycle based on priority information of the input for the given tile instance; and Priority information for a given tile instance of the fabric circuit is updated based on the assignment results over a plurality of cycles.

2. The apparatus of claim 1 , wherein to assign communication resources for a given tile instance, the control circuit is configured to: Determining input priority information for the tile instance; determining, at least partially in parallel, for a plurality of communication resources and a plurality of inputs, a number of inputs having a higher priority than a given input and requesting the same resource; determining, for a given resource, a number of inputs that the resource is capable of servicing in the given period; as well as Communication resources are assigned to inputs for the given period based on the determination of the number of inputs.

3. The apparatus of claim 1, wherein the communication resources comprise: dedicated resources for one or more non-stallantable virtual channels; and Arbitration resources for stallable virtual channels. 4 . The apparatus of claim 3 , wherein the control circuit is configured to assign a set of highest priority indications to non-stallantable virtual channel inputs.

5. The apparatus of claim 1 , wherein in order to update the priority information for a given tile instance based on the assignment result over a plurality of cycles, the control circuit is configured to: classifying input to the tile instance based on whether the input to the tile instance received all or a portion of the requested resources over the plurality of cycles; and A priority for input to the tile instance is updated based on the classification.

6. The device according to claim 5, The input categories include: a winner input class whose most recent valid request is fully allocated all requested resources; a partial winner input class whose most recent valid request was not fully allocated all requested resources within the plurality of cycles and for which a previous request was fully allocated all requested resources within the plurality of cycles; a loser class, for which no valid request was fully allocated the requested resource within the plurality of cycles; and An invalid input category for which no valid requests were received within the plurality of cycles.

7. The apparatus of claim 6, wherein to update the priority, the control circuit is configured to prioritize according to the following order from highest to lowest priority: The loser enters; Invalid input; Some winners enter; then Winner enters. 8 . The apparatus of claim 7 , wherein to update the priority, the control circuit is further configured to invert the priority ordering between the partial winner inputs and invert the priority ordering between the winner inputs. 9 . The apparatus of claim 1 , wherein the first tile instance comprises a plurality of slices, and the plurality of internal links are links between slices.

10. The apparatus of claim 9, wherein the slices are arranged in a chain topology, and wherein the first tile instance comprises a crossbar at one or both ends of the slice chain, wherein the crossbar is connected to a buffer configured to store: data output for the tile; and Data from the tile input.

11. The apparatus of claim 1, wherein the first instance and the second instance of the tile include different numbers of inputs and different amounts of communication resources.

12. The apparatus according to claim 1, wherein the structural circuit comprises: A chain of tile instances, the chain of tile instances comprising the first instance and the second instance of the tile, wherein adjacent tile instances in the chain are connected via at least a portion of a tile input and a tile output of a given tile instance.

13. The apparatus of claim 1, wherein the apparatus is a computing device, the computing device further comprising: monitor; and Network interface circuit.

14. The apparatus of claim 1, wherein the processor comprises: a plurality of SIMD pipelines, the plurality of SIMD pipelines being configured to execute instructions; and Fixed function circuitry configured to control the SIMD pipeline to perform operations for at least one of the following types of programs: Graphics shader programs; and Machine learning program.

15. A method comprising: A computing system assigns communication resources of a tiled fabric circuit for a given cycle, wherein the fabric includes at least a first instance and a second instance of a tile, wherein the tile includes: a client input configured to interface with client circuitry of the computing system; A tile input configured to interface with one or more other tile instances; and A communication resource, the communication resource being assignable to the client input and the tile input, wherein the communication resource comprises: Multiple internal links; a client output configured to interface with a client circuit; and a tile output, the tile output being configured to interface with one or more other tile instances; wherein the assigning comprises assigning communication resources of a given tile instance to the client input and at least a portion of the tile input for a next period based on priority information of the input for the given tile instance; and Priority information for a given tile instance of the fabric circuit is updated by the computing system over a plurality of cycles based on the assignment results.

16. The method of claim 15, wherein the assigning comprises: Determining input priority information for the tile instance; determining, at least partially in parallel, for a plurality of communication resources and a plurality of inputs, a number of inputs having a higher priority than a given input and requesting the same resource; determining, for a given resource, a number of inputs that the resource is capable of servicing in the given period; as well as Communication resources are assigned to inputs for the given period based on the determination of the number of inputs.

17. A non-transitory computer-readable storage medium storing thereon design information, the design information specifying a design of at least a portion of a hardware integrated circuit in a format recognizable by a semiconductor manufacturing system, the semiconductor manufacturing system being configured to use the design information to produce the circuit according to the design, wherein the design information specifies that the circuit comprises: Multiple client circuits; A structure circuit, the structure circuit comprising at least a first instance and a second instance of a block, wherein the block comprises: a client input configured to interface with a client circuit; A tile input configured to interface with one or more other tile instances; and A communication resource, the communication resource being assignable to the client input and the tile input, wherein the communication resource comprises: Multiple internal links; a client output configured to interface with a client circuit; and a tile output, the tile output being configured to interface with one or more other tile instances; A control circuit, the control circuit being configured to: In a given cycle, assigning communication resources of a given tile instance to the client input and at least a portion of the tile input for a next cycle based on priority information of the input for the given tile instance; and Priority information for a given tile instance of the fabric circuit is updated based on the assignment results over a plurality of cycles.

18. The non-transitory computer-readable storage medium of claim 17, wherein to assign communication resources for a given tile instance, the control circuit is configured to: Determining input priority information for the tile instance; determining, at least partially in parallel, for a plurality of communication resources and a plurality of inputs, a number of inputs having a higher priority than a given input and requesting the same resource; determining, for a given resource, a number of inputs that the resource is capable of servicing in the given period; as well as Communication resources are assigned to inputs for the given period based on the determination of the number of inputs.

19. The non-transitory computer-readable storage medium of claim 17, wherein the communication resources comprise: dedicated resources for one or more non-stallantable virtual channels; as well as Arbitration resources for stallable virtual channels.

20. The non-transitory computer-readable storage medium of claim 17, wherein to update the priority information for a given tile instance based on the assignment result over a plurality of cycles, the control circuit is configured to: classifying input to the tile instance based on whether the input to the tile instance received all or a portion of the requested resources over the plurality of cycles; and A priority for input to the tile instance is updated based on the classification.

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