Ruthenium carbide for DRAM capacitor mold patterning

Abstract

Methods of forming electronic devices and film stacks include depositing a ruthenium carbide hard mask on a capacitor mold formed on a substrate. A hard mask oxide and a patterned photoresist are formed, and the pattern of the patterned photoresist is transferred into the ruthenium carbide hard mask. Film stacks comprising a ruthenium carbide hard mask on a capacitor mold are also described.

Description

Technical Field

[0001] Embodiments of the present disclosure generally relate to the fabrication of integrated circuits. In particular, embodiments of the present disclosure relate to film stacks and methods of forming film stacks for electronic devices using ruthenium carbide hardmasks.

[0002] background

[0003] Reliably manufacturing sub-micron and smaller feature structures is one of the key requirements for very large scale integration (VLSI) and ultra large scale integration (ULSI) of semiconductor devices. However, as circuit technology continues to miniaturize, the size and spacing of circuit features (such as interconnects) place additional demands on processing capabilities. Various semiconductor components (such as interconnects, vias, capacitors, transistors) require precise positioning of high aspect ratio features. Reliably forming these components is critical to further improving device and density.

[0004] In addition, the electronics and semiconductor industries are continually striving for higher production yields while improving the uniformity of deposited layers on increasingly larger substrates. These same factors combined with new materials are also enabling higher density circuits per unit area on substrates.

[0005] During the formation of many electronic devices, hard masks are used to protect portions of a substrate from being removed. Hard masks are often used during patterning operations. Once patterning has been completed, the hard mask is often removed, leaving the protected portions of the substrate. Removal of the hard mask material can be done independently or in conjunction with other etching processes. The ability to remove the hard mask material without affecting other surface features, also known as etch selectivity, is a useful feature.

[0006] Developing hard mask materials with high etch selectivity is critical to patterning new generations of NAND and DRAM devices. For each technology node device, a capacitor die hard mask with 30% higher selectivity than the previous node is required. Currently, boron-doped silicon is used for DRAM capacitor die patterning for N to N+2 nodes.

[0007] As the N+2 node has been proposed, the dopant concentration is dominated by boron. Therefore, increasing the boron dopant concentration is unlikely to continue to sufficiently improve the hard mask selectivity.

[0008] Therefore, there is a continuing need in the art for capacitor mold hard masks with improved selectivity.

[0009] Overview

[0010] One or more embodiments of the present disclosure are directed to a method comprising depositing a ruthenium carbide hard mask on a capacitor mold formed on a substrate. Forming a hard mask oxide on the ruthenium carbide layer. Forming a patterned photoresist on the hard mask oxide. Transferring a pattern of the patterned photoresist to the ruthenium carbide hard mask to form a patterned ruthenium carbide hard mask.

[0011] Other embodiments of the present disclosure relate to methods comprising forming a capacitor mold on a substrate. The capacitor mold comprises a silicon oxide (SiO) layer, and a silicon carbonitride (SiCN) layer or a silicon nitride (SiN) layer on the silicon oxide layer. The thickness of the silicon oxide (SiO) layer is in the range of 1 micron to 3 microns, and the thickness of the SiCN layer or the SiN layer is at most 1000 angstroms. Optionally, one or more of an amorphous silicon film or a carbon film is directly deposited on the capacitor mold. A ruthenium carbide hard mask is deposited on the capacitor mold or on an optional amorphous silicon film or carbon film (if present). The ruthenium carbide hard mask contains ruthenium in the range of 20 to 45 atomic %, and hydrogen in the range of 5 to 15 atomic %. The sum of the thickness of the optional amorphous silicon film or carbon film and the ruthenium carbide hard mask is in the range of 2500 angstroms to 3500 angstroms. A hard mask oxide is formed on the ruthenium carbide layer. An antireflective coating comprising one or more of a dielectric antireflective coating (DARC) or a bottom antireflective coating (BARC) is formed on the hard mask oxide. A photoresist having a pattern is formed on the antireflective coating. The pattern of the photoresist is transferred to the antireflective coating, the hard mask oxide, and the ruthenium carbide hard mask by exposing the substrate to an etchant plasma comprising an oxygen content, a chlorine content, and a carbonyl sulfide content to form a patterned hard mask oxide, a patterned ruthenium carbide hard mask, and remove the antireflective coating. The chlorine content is in the range of 5% to 15% of the oxygen content by mole, and the carbonyl sulfide content is in the range of 5% to 10% of the oxygen content by mole. The remaining photoresist and antireflective coating are removed, leaving a patterned hard mask oxide and a patterned ruthenium carbide hard mask. The pattern of the patterned hard mask oxide and the patterned ruthenium carbide hard mask is optionally transferred to an optional amorphous silicon film or a carbon film.

[0012] Other embodiments of the present disclosure are directed to a film stack comprising: a capacitor mold; a ruthenium carbide hard mask on the capacitor mold; a hard mask oxide on the ruthenium carbide hard mask; and a patterned photoresist on the hard mask oxide.

[0013] BRIEF DESCRIPTION OF THE DRAWINGS

[0014] Thus, the manner in which the above-described features of the present disclosure may be understood in detail, a more particular description of the present disclosure, briefly summarized above, may be obtained by reference to the embodiments, some of which are illustrated in the accompanying drawings. It should be noted, however, that the drawings illustrate only typical embodiments of the present disclosure and, therefore, should not be considered limiting of the scope of the present disclosure, as the disclosure may admit to other equally effective embodiments.

[0015] Figure 1 describing a plasma processing chamber for use with embodiments of the present disclosure; and

[0016] FIG. 2A to FIG. 2D A process flow of a method according to one or more embodiments of the present disclosure is described.

[0017] For ease of understanding, the same reference numerals have been used, where possible, to represent the same elements common to the figures. The figures are not drawn to scale and may be simplified for clarity. Elements and features of one embodiment may be beneficially incorporated into other embodiments without repetition.

[0018] Specific description

[0019] Before describing several exemplary embodiments of the present disclosure, it should be understood that the present disclosure is not limited to the details of construction or process steps set forth in the following description. The present disclosure is capable of other embodiments and can be practiced or carried out in various ways.

[0020] As used in this specification and the appended claims, the term "substrate" refers to a surface, or a portion of a surface, on which a process acts. It will also be understood by those skilled in the art that reference to a substrate may also refer to only a portion of a substrate unless the context clearly indicates otherwise. In addition, reference to depositing on a substrate may mean a bare substrate as well as a substrate having one or more films or features deposited or formed thereon.

[0021] As used herein, "substrate" represents any substrate or material surface formed on a substrate on which film processing is performed during a manufacturing process. For example, depending on the application, the substrate surface on which processing may be performed includes materials such as silicon, silicon oxide, strained silicon, silicon on insulator (SOI), carbon-doped silicon oxide, amorphous silicon, doped silicon, germanium, gallium arsenide, glass, sapphire, and any other material such as metals, metal nitrides, metal alloys and other conductive materials. Substrates include, but are not limited to, semiconductor wafers. The substrate may be exposed to a pretreatment process to polish, etch, reduce, oxidize, hydroxylate, anneal, UV cure, electron beam cure, and / or bake the substrate surface. In addition to performing film processing directly on the surface of the substrate itself, in the present disclosure, any of the disclosed film processing steps may also be performed on an underlying layer formed on the substrate (as disclosed in more detail below), and the term "substrate surface" is intended to include such an underlying layer, as indicated by the context.

[0022] The term "on" indicates that there is direct contact between elements. The term "directly on" indicates that there is no intermediate element between the elements and they are in direct contact.

[0023] As used in this specification and the appended claims, the terms "precursor," "reactant," "reactive gas," and the like are used interchangeably to represent any gaseous species that can react with a substrate surface.

[0024] Some embodiments of the present disclosure advantageously provide novel hard mask materials with improved selectivity relative to boron-doped silicon. In some embodiments, a ruthenium carbide film is used as a hard mask with selectivity relative to adjacent hard mask oxides and / or capacitor mold components. Some embodiments provide a ruthenium carbide hard mask that can be ashed or etched from a substrate surface.

[0025] Figure 1 is a schematic representation of an exemplary substrate processing system 132 according to an embodiment of the present disclosure that may be used for ruthenium carbide deposition or other processes. Examples of suitable processing chambers and tools include, but are not limited to system, which can use DxZ TM Processing chamber, PRECISION System, PRODUCER TM System, such as PRODUCER SE TM Processing chamber and PRODUCER GT TM processing chambers, such systems are available from Applied Materials, Inc., Santa Clara, Calif. It is contemplated that the processes described herein may be performed on other substrate processing systems, including systems from other manufacturers.

[0026] like Figure 1 The illustrated substrate processing system 132 includes a processing chamber 100 coupled to a gas panel 130 and a controller 110. The processing chamber 100 generally includes a top 124, a side 101, and a bottom wall 122, defining an internal processing space 126. A support pedestal 150 is disposed in the internal processing space 126 of the chamber 100. The pedestal 150 is supported by pillars 160 or pedestal supports and is typically made of aluminum, ceramic, or other suitable materials. The pedestal 150 can be moved in a vertical direction within the chamber 100 using a displacement mechanism (not shown), or can be rotated about a central axis of the pillar 160 using a suitable rotation mechanism (not shown).

[0027] The pedestal 150 shown includes an embedded heating element 170 suitable for controlling the temperature of a substrate 190 supported on a surface 192 of the pedestal 150. The pedestal 150 can be resistively heated by applying an electric current to the heater element 170 from the power supply 106. The heater element 170 can be made of a nickel-iron-chromium alloy (e.g., ) sheath tube. The current provided by the power supply 106 is regulated by the controller 110 to control the heat generated by the heater element 170 to maintain the substrate 190 and the susceptor 150 at a substantially constant temperature during film deposition. The supplied current can be adjusted to selectively control the temperature of the susceptor 150 between about 100° C. and about 700° C.

[0028] A temperature sensor 172 (eg, a thermocouple) may be embedded in the support pedestal 150 to monitor the temperature of the pedestal 150 in a conventional manner. The measured temperature is used by the controller 110 to control the power supplied to the heating element 170 to maintain the substrate at a desired temperature.

[0029] The vacuum pump 102 is coupled to a port formed in the bottom of the chamber 100. The vacuum pump 102 is used to maintain a desired gas pressure in the processing chamber 100. The vacuum pump 102 also exhausts post-processing gases and byproducts of the process from the chamber 100.

[0030] The processing system 132 may also include additional equipment to control the chamber pressure, such as valves (eg, throttle valves and isolation valves) located between the processing chamber 100 and the vacuum pump 102 to control the chamber pressure.

[0031] A showerhead 120 having a plurality of holes 128 is located at the top of the processing chamber 100, above the substrate support pedestal 150. The holes 128 of the showerhead 120 are used to introduce process gases into the chamber 100. The holes 128 can have different sizes, numbers, distributions, shapes, designs, and diameters to facilitate the flow of various process gases according to different process requirements. The showerhead 120 is connected to a gas panel 130, which allows various gases to be supplied to the internal processing space 126 during the process. The process gas mixture discharged from the showerhead 120 forms a plasma, which enhances the pyrolysis of the process gas, thereby depositing material on the surface 191 of the substrate 190.

[0032] The gas panel 130 may also be used to control and supply various evaporated liquid precursors. Although not shown, the liquid precursor from the liquid precursor supply may be evaporated, for example by a liquid injection evaporator, and delivered to the processing chamber 100 in the presence of a carrier gas. The carrier gas is typically an inert gas, such as nitrogen, or a rare gas, such as argon or helium. Alternatively, the liquid precursor may be evaporated from an ampoule by a heat and / or vacuum enhanced evaporation process.

[0033] The showerhead 120 and the substrate support pedestal 150 may form a pair of spaced electrodes in the internal processing space 126. One or more RF power supplies 140 provide a bias potential to the showerhead 120 via a matching network 138 to promote plasma generation between the showerhead 120 and the pedestal 150. Alternatively, the RF power supply 140 and the matching network 138 may be coupled to the showerhead 120, the substrate pedestal 150, or to both the showerhead 120 and the substrate pedestal 150, or to an antenna (not shown) disposed outside the chamber 100. In one embodiment, the RF power supply 140 may provide a power between about 50 watts and about 10,000 watts at a frequency of about 50 kHz to about 100 MHz. In another embodiment, the RF power supply 140 may provide a power between about 500 watts and about 1,800 watts at a frequency of about 50 kHz to about 13.6 MHz.

[0034] The controller 110 includes a central processing unit (CPU) 112, a memory 116, and support circuits 114 for controlling the process sequence and regulating the flow of gas from the gas panel 130. The CPU 112 may be any form of general purpose computer processor that may be used in an industrial environment. Software routines may be stored in the memory 116, such as a random access memory, a read-only memory, a floppy or hard disk drive, or other form of digital storage. The support circuits 114 are conventionally coupled to the CPU 112 and may include cache memory, clock circuits, input / output systems, power supplies, etc. Bidirectional communications between the controller 110 and the various components of the processing system 132 are carried over a plurality of signal cables, such as a signal bus 118, referred to as a signal bus. Figure 1 shown.

[0035] refer to FIG. 2A to FIG. 2D , an example process for forming an electronic device is illustrated using a schematic cross-sectional representation of the electronic device. The shading shown in the figure is used to show the different components and should not be considered to represent any specific construction material unless otherwise specified.

[0036] Figure 2A An electronic device 200 is described having a capacitor die 210 formed on a substrate 205. The capacitor die 210 of some embodiments comprises one or more of silicon oxide (SiO), silicon carbide (SiC), or silicon carbonitride (SiCN). When used in this specification and the appended claims, unless otherwise specified, chemical formulas represent only the elemental identity of the film and do not imply stoichiometry. For example, a SiO film comprises silicon and oxygen atoms. A typical silicon oxide film mainly comprises silicon dioxide (SiO2), which implies a specific stoichiometric relationship. In some embodiments, the elemental formula of a layer means that the element in the layer is greater than or equal to about 95%, 98%, 99%, or 99.5% by atom. Those skilled in the art will recognize that interlayer diffusion of atoms may occur unintentionally, thereby affecting the overall composition of the layer. Thus, for example, in a silicon oxide (SiO) layer, the sum of silicon atoms and oxygen atoms accounts for greater than or equal to 95%, 98%, 99%, or 99.5% of the total number of atoms in the layer, allowing for a small amount of contamination and interlayer diffusion atoms. In other words, the layer "consists essentially of the element," where consisting essentially of means that the element accounts for greater than or equal to 95%, 98%, 99%, or 99.5% by atoms. The term "consists essentially of" can be applied to any individual layer described herein and is not limited to the example of silicon oxide.

[0037] The capacitor mold 210 of some embodiments includes a silicon oxide (SiO) layer 212 and a second layer 214, which includes one or more of a silicon carbonitride (SiCN) layer or a silicon nitride (SiN) layer. The thickness of the silicon oxide layer 212 of some embodiments is in the range of 0.5 microns to 5 microns, or in the range of 1 micron to 3 microns. In some embodiments, the thickness of the silicon oxide layer 212 is at most 3.5 microns.

[0038] In some embodiments, the second layer 214 comprises a silicon carbonitride (SiCN) layer. In some embodiments, the second layer 214 comprises a silicon nitride (SiN) layer. The thickness of the second layer 214, either the SiCN layer or the SiN layer, is at most or or In some embodiments, the thickness of the second layer 214 is arrive within the range of arrive within the range.

[0039] The silicon oxide layer 212 and the second layer 214 may be formed using any suitable technique known to those skilled in the art. For example, the layers may be formed by chemical vapor deposition (CVD), plasma enhanced chemical vapor deposition (PECVD), atomic layer deposition (ALD), plasma enhanced atomic layer deposition (PEALD), or physical vapor deposition (PVD).

[0040] In some embodiments, the substrate 205 and / or the capacitor mold 210 have a substantially flat surface. Alternatively, the substrate 205 and / or the capacitor mold 210 of some embodiments have a patterned structure in which a surface with grooves, holes or through holes is formed. Although the substrate 205 is depicted as a single body, it will be understood by those skilled in the art that the substrate may contain one or more material layers used in semiconductor devices such as metal contacts, trench isolation, gates, bit lines, or any other interconnect features. The substrate 205 may include one or more metal layers, one or more dielectric materials, semiconductor materials, and other combinations thereof for manufacturing semiconductor devices. For example, the substrate 205 may include oxide materials, nitride materials, polysilicon materials, etc. depending on the application. In an embodiment requiring a memory application, the substrate 205 may include silicon substrate materials, oxide materials, and nitride materials, with or without polysilicon in between.

[0041] In some embodiments, substrate 205 includes a plurality of alternating oxide and nitride materials (i.e., oxide-nitride-oxide (ONO)) deposited on a surface of the substrate. In various embodiments, substrate 205 may include a plurality of alternating oxide and nitride materials, one or more oxide or nitride materials, polycrystalline silicon or amorphous silicon materials, oxides alternating with amorphous silicon, oxides alternating with polycrystalline silicon, undoped silicon alternating with doped silicon, undoped polycrystalline silicon alternating with doped polycrystalline silicon, or undoped amorphous silicon alternating with doped amorphous silicon. Substrate 205 may be any substrate or material surface on which film processing is performed. For example, substrate 205 may be a material such as crystalline silicon, silicon oxide, silicon oxynitride, silicon nitride, strained silicon, silicon germanium, tungsten, titanium nitride, doped or undoped polysilicon, doped or undoped silicon wafers and patterned or unpatterned wafers, silicon on insulator (SOI), carbon-doped silicon oxide, silicon nitride, doped silicon, germanium, gallium arsenide, glass, sapphire, low-k dielectrics, and combinations of the foregoing.

[0042] Figure 2BThe electronic device 220 is illustrated after an optional hard mask bottom layer 222 is formed on the capacitor mold 210. The hard mask bottom layer 222 of some embodiments includes one or more of an amorphous silicon (a-Si) film or a carbon (C) film. In some embodiments, the hard mask bottom layer 222 includes an amorphous silicon film. In some embodiments, the hard mask bottom layer 222 includes a carbon film. The hard mask bottom layer 222 of some embodiments is formed directly on the capacitor mold 210 without an intervening layer.

[0043] As shown, the optional seed layer 224 is formed on the hard mask bottom layer 222. In some embodiments, the optional seed layer 224 is formed directly on the hard mask bottom layer 222. In some embodiments, the optional seed layer 224 is formed directly on the capacitor mold 210 and the hard mask bottom layer 222 is omitted. In one or more embodiments, the optional seed layer 224 includes boron. In some embodiments, the thickness of the optional seed layer 224 is at most or in to within the range of to within the range.

[0044] A ruthenium carbide hard mask 226 is formed on the capacitor mold 210. In the embodiment shown in the figure, the ruthenium carbide hard mask 226 is formed directly on the optional seed layer 224 on the hard mask bottom layer 222. In some embodiments, the optional hard mask bottom layer 222 and the optional seed layer 224 are omitted, and the ruthenium carbide hard mask 226 is formed directly on the capacitor mold 210. In some embodiments, the hard mask bottom layer 222 is omitted, the ruthenium carbide hard mask 226 is formed directly on the optional seed layer 224, and the optional seed layer 224 is formed on the capacitor mold 210.

[0045] The ruthenium carbide hard mask 226 can be an amorphous, semi-crystalline or crystalline material. The hard mask can also be referred to as a ruthenium-doped carbon film. However, those skilled in the art will appreciate that ruthenium-doped carbon films and ruthenium carbide films can be used interchangeably and may depend on the degree of crystallinity of the material.

[0046] Some embodiments of the ruthenium carbide hard mask 226 have a ruthenium composition in the range of 20 to 45 atomic % ruthenium. In some embodiments, the composition of the ruthenium carbide hard mask 226 includes a range of greater than 0 to 50 atomic % ruthenium, 5 to 50 atomic % ruthenium, 10 to 45 atomic % ruthenium, 20 to 45 atomic % ruthenium, or a range of 25 to 40 atomic % ruthenium, or a range of 30 to 35 atomic % ruthenium.

[0047] Some embodiments of the ruthenium carbide hard mask 226 have a hydrogen composition in the range of 2 to 20 atomic % hydrogen. In some embodiments, the composition of the ruthenium carbide hard mask 226 includes a range of 5 to 15 atomic % hydrogen, or a range of 8 to 12 atomic % hydrogen. In some embodiments, the composition of the ruthenium carbide hard mask 226 includes less than or equal to 15 atomic % hydrogen, less than or equal to 10 atomic % hydrogen, or less than or equal to 5 atomic % hydrogen.

[0048] In some embodiments, the ruthenium carbide hard mask 226 includes a range of greater than 0 to 50 atomic % ruthenium, and less than or equal to 15 atomic % hydrogen, with the remainder being carbon. In some embodiments, the ruthenium carbide hard mask 226 includes a range of 10 to 45 atomic % ruthenium and less than or equal to 10 atomic % hydrogen, with the remainder being carbon. In some embodiments, the ruthenium carbide hard mask 226 includes a range of 20 to 45 atomic % ruthenium, and 5 to 15 atomic % hydrogen, with the remainder being carbon. In some embodiments, the ruthenium carbide hard mask 226 includes a range of 20 to 45 atomic % ruthenium, and less than or equal to 15, 10, or 5 atomic % hydrogen, with the remainder being carbon.

[0049] In some embodiments, the thickness of the ruthenium carbide hard mask 226 is between to within the range of to within the range of to In some embodiments, the thickness of the ruthenium carbide hard mask is within the range of to In some embodiments, the thickness of the optional hard mask bottom layer 222 is within the range of to The thickness of the ruthenium carbide hard mask 226 is within the range of to In some embodiments, the combined thickness of the optional hard mask bottom layer 222 and the ruthenium carbide hard mask 226 is within a range of to In some embodiments, the combined thickness of the optional hard mask bottom layer 222, the selective seed layer 224, and the ruthenium carbide hard mask 226 is within a range of to within the range.

[0050] In the embodiment shown, hard mask oxide 228 is formed on ruthenium carbide hard mask 226. Hard mask oxide 228 can be any suitable material known to those skilled in the art that has an etch selectivity relative to ruthenium carbide hard mask 226. In some embodiments, the thickness of hard mask oxide 228 is between 100 and 200 nm. to within the range.

[0051] In the embodiment shown, an advanced patterning film (APF) 230 is formed on the hard mask oxide 228. The advanced patterning film 230 of some embodiments comprises carbon or a diamond-like carbon film. In some embodiments, the thickness of the advanced patterning film 230 is between 100 and 200 nm. to In some embodiments, the thickness of the advanced patterned film 230 is greater than and less than or equal to or

[0052] A dielectric anti-reflective coating (DARC) 232 is formed on the advanced patterned film 230. The DARC 232 may be formed using any suitable technique known to those skilled in the art. The dielectric anti-reflective coating 232 of some embodiments includes silicon oxynitride (SiON). In some embodiments, the thickness of the DARC 232 is between 100 and 200 nm. to In some embodiments, the thickness of DARC 232 is greater than and less than or equal to

[0053] A bottom anti-reflective coating (BARC) 234 is formed on the DARC 232. The BARC 234 may be formed using any suitable technique known to those skilled in the art. In some embodiments, the thickness of the BARC 234 is between 1000 and 2000. to In some embodiments, the thickness of BARC 234 is greater than and less than or equal to

[0054] A photoresist 236 is formed on the BARC 234. The photoresist 236 can be deposited using any suitable technique known to those skilled in the art. The photoresist 236 is patterned by any suitable technique (e.g., photolithography) to form a patterned photoresist and expose the top surface 235 of the BARC 234. In some embodiments, the photoresist 236 is an energy-sensitive resist material that can be patterned by exposing the energy-sensitive resist material to UV radiation via a patterning device such as a mask (not shown), and then developing the energy-sensitive resist material in a suitable developer. After the energy-sensitive resist material is developed, there are through openings 237 in the photoresist 236 that define the pattern.

[0055] Figure 2CThe electronic device 220 is illustrated after the pattern of the photoresist 236 is transferred to the antireflective coatings 232, 234, the advanced patterned film 230, the hard mask oxide layer 228, and the ruthenium carbide hard mask 226. In some embodiments, transferring the pattern of the photoresist 236 removes the photoresist 236, the BARC 234, the DARC 232, and the advanced patterned film 230, thereby leaving behind the patterned hard mask oxide 248 and the patterned ruthenium carbide hard mask 246. In the embodiment shown, the pattern transfer also forms the patterned hard mask bottom layer 242 and the patterned seed layer 244. In some embodiments, the optional hard mask bottom layer 222 and the optional seed layer 224 are present and are not patterned together with the ruthenium carbide hard mask 226.

[0056] In some embodiments, pattern transfer occurs by exposing the substrate to an etchant plasma using the photoresist 236 as a mask. The etchant plasma in some embodiments comprises an oxygen (O2) content and a chlorine (Cl2) content. The chlorine content in the etchant plasma in some embodiments is in the range of 5% to 15% by mole of the oxygen content. In some embodiments, the chlorine content in the etchant plasma is less than or equal to 15%, 10%, or 5% by mole of the oxygen content.

[0057] In some embodiments, the etchant plasma contains carbonyl sulfide (COS) content. The COS content of some embodiments is in the range of 1% to 10% of the oxygen content on a molar basis.

[0058] In some embodiments, the etchant plasma comprises oxygen, chlorine and carbonyl sulfide. The composition of the etchant plasma of some embodiments is 1-10% COS, 5-15% Cl2 based on the amount of O2 by mole.

[0059] In some embodiments, the photoresist 236, the anti-reflective coatings 232, 234, and the advanced patterning film 230 are removed simultaneously with the pattern transfer. In some embodiments, one or more of the photoresist 236, the anti-reflective coatings 232, 234, or the advanced patterning film 230 remain after the pattern transfer and are removed in another independent process.

[0060] Figure 2D An embodiment of an electronic device 240 is illustrated after transferring a pattern to a capacitor mold 210 to form an electronic device 260 having a patterned capacitor mold 262. In the illustrated embodiment, the patterned capacitor mold 262 includes a patterned silicon oxide layer 264 and a patterned second layer 266.

[0061] Figure 2DThe electronic device 240 is depicted after removing the patterned hard mask oxide 248, the patterned ruthenium carbide hard mask 246, the patterned optional seed layer 244, and the patterned optional hard mask bottom layer 242. The patterned hard mask oxide 248, the patterned ruthenium carbide hard mask 246, the patterned optional seed layer 244, and the patterned optional hard mask bottom layer 242 can be removed simultaneously with the pattern transfer to the capacitor mold 210 or in one or more separate processes. In some embodiments, the patterned ruthenium carbide hard mask 246, the patterned optional seed layer 244, and the patterned optional hard mask bottom layer 242 are removed using a plasma containing an oxygen content and a chlorine content.

[0062] References throughout this specification to "one embodiment," "certain embodiments," "one or more embodiments," or "an embodiment" mean that a particular feature, structure, material, or characteristic described in conjunction with the embodiment is included in at least one embodiment of the present disclosure. Thus, phrases such as "in one or more embodiments," "in certain embodiments," "in an embodiment," or "in an embodiment" appearing throughout this specification do not necessarily refer to the same embodiment of the present disclosure. Additionally, particular features, structures, materials, or characteristics may be combined in any appropriate manner in one or more embodiments.

[0063] Although the disclosure herein has been described with reference to specific embodiments, it will be understood by those skilled in the art that the described embodiments are merely illustrative of the principles and applications of the disclosure. It will be apparent to those skilled in the art that various modifications and variations may be made to the methods and apparatus of the disclosure without departing from the spirit and scope of the disclosure. Therefore, the disclosure may include modifications and variations within the scope of the appended claims and their equivalents.

Claims

1. A method comprising: depositing a ruthenium carbide hard mask on a capacitor mold formed on a substrate; forming a hard mask oxide on the ruthenium carbide layer; forming a patterned photoresist on the hard mask oxide; and The pattern of the patterned photoresist is transferred to the ruthenium carbide hard mask to form a patterned ruthenium carbide hard mask.

2. The method of claim 1, wherein the ruthenium carbide hard mask comprises ruthenium in a range of 20 to 45 atomic %.

3. The method of claim 2, wherein the ruthenium carbide hard mask contains less than or equal to 15 atomic % hydrogen.

4. The method of claim 1, further comprising transferring the pattern of the patterned ruthenium carbide hard mask into the capacitor mold.

5. The method of claim 4, further comprising etching the patterned ruthenium carbide hard mask from the capacitor mold.

6. The method of claim 1, wherein transferring the pattern of the patterned photoresist to the ruthenium carbide hard mask comprises exposing the substrate to an etchant plasma comprising an oxygen content and a chlorine content.

7. The method of claim 6, wherein the chlorine content is less than or equal to 15% by mole of the oxygen content.

8. The method of claim 7, wherein the etchant plasma further comprises carbonyl sulfide content.

9. The method of claim 9, wherein the carbonyl sulfide content is less than or equal to 10% of the oxygen content on a molar basis.

10. The method of claim 1, wherein the thickness of the ruthenium carbide hard mask is to within the range.

11. The method of claim 1, further comprising: forming one or more of a carbon film or an amorphous silicon film on the capacitor mold between the capacitor mold and the ruthenium carbide hard mask.

12. The method of claim 11, wherein the thickness of the combination of the carbon film, the amorphous silicon film and the ruthenium carbide hard mask is between to within the range.

13. The method of claim 1, wherein the capacitor mold comprises a silicon oxide (SiO) layer. 14 . The method of claim 13 , wherein the capacitor mold further comprises a silicon carbonitride (SiCN) layer or a silicon nitride (SiN) layer on the silicon oxide layer.

15. The method of claim 14, wherein the thickness of the silicon oxide (SiO) layer is at most 3 μm, and the thickness of the SiCN layer is at most 16. A method comprising: A capacitor mold is formed on a substrate, the capacitor mold comprising a silicon oxide (SiO) layer and a silicon carbonitride (SiCN) layer or a silicon nitride (SiN) layer on the silicon oxide layer, wherein the thickness of the silicon oxide (SiO) layer is in the range of 1 μm to 3 μm, and the thickness of the SiCN layer or the SiN layer is at most Optionally depositing one or more of an amorphous silicon film or a carbon film directly on the capacitor mold; A ruthenium carbide hard mask is deposited on the capacitor mold and the optional amorphous silicon film or carbon film (if present), the ruthenium carbide hard mask comprising ruthenium in the range of 20 to 45 atomic % and hydrogen in the range of 5 to 15 atomic %, the sum of the thickness of the optional amorphous silicon film or carbon film and the ruthenium carbide hard mask being in the range of 2500 to 1000 angstroms. within the scope of forming a hard mask oxide on the ruthenium carbide layer; forming an antireflective coating on the hard mask oxide, the antireflective coating comprising one or more of a dielectric antireflective coating (DARC) or a bottom antireflective coating (BARC); forming a photoresist on the anti-reflective coating, wherein the photoresist has a pattern; transferring the pattern of the photoresist to the antireflective coating, the hard mask oxide, and the ruthenium carbide hard mask by exposing the substrate to an etchant plasma comprising an oxygen content in the range of 5% to 15% by mole of the oxygen content, a chlorine content in the range of 5% to 10% by mole of the oxygen content, and removing the antireflective coating to form a patterned hard mask oxide, a patterned ruthenium carbide hard mask, and removing the antireflective coating; removing the remaining photoresist and antireflective coating to leave the patterned hard mask oxide and the patterned ruthenium carbide hard mask; and The patterns of the patterned hard mask oxide and patterned ruthenium carbide hard mask are optionally transferred into the optional amorphous silicon film or carbon film.

17. A membrane stack comprising: Capacitor mold; a ruthenium carbide hard mask on the capacitor mold; a hard mask oxide on the ruthenium carbide hard mask; and A photoresist is patterned on the hard mask oxide.

18. The film stack of claim 17, wherein the ruthenium carbide hard mask comprises ruthenium in the range of 20 to 45 atomic % and less than or equal to 15 atomic % hydrogen, with the remainder being carbon.

19. The film stack of claim 17, wherein the thickness of the ruthenium carbide hard mask is to within the range.

20. The film stack of claim 17, further comprising one or more of a carbon film or an amorphous silicon film between the capacitor mold and the ruthenium carbide hard mask, and the thickness of the combination of the carbon film, the amorphous silicon film and the ruthenium carbide hard mask is between 100 and 150 nm. to within the range.

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