Metal-insulator-metal (MIM) capacitor with curved electrodes

Abstract

A method for fabricating a metal-insulator-metal (MIM) capacitor by etching a dielectric layer to form a via or contact hole, a trench region, and a trench in the dielectric layer; depositing a conformal metal in the through hole or contact hole, the trench region and the trench, wherein the deposited conformal metal forms a through hole or contact in the through hole or contact hole; depositing a bottom electrode metal in the trench region to form a bottom electrode of a metal-to-metal (MIM) capacitor; removing bottom electrode metal from the bottom electrode to form a disc-shaped upper surface; depositing an insulator material on the bottom electrode to form an insulator layer of the MIM capacitor; and depositing a top electrode metal on the insulator layer to form a top electrode of the MIM capacitor.

Description

[0001] Related patent applications

[0002] This application claims priority to commonly owned U.S. Patent Application No. 63 / 426,256 filed on November 17, 2022, the entire contents of which are hereby incorporated by reference for all purposes. Technical Field

[0003] The present disclosure relates to metal-insulator-metal (MIM) capacitors, for example, MIM capacitors in analog / mixed-signal / RF-CMOS circuits. Background Art

[0004] A Metal-Insulator-Metal (MIM) capacitor is a capacitor constructed of a metal top electrode, a metal bottom electrode, and an insulator (dielectric) sandwiched between the two metal electrodes.

[0005] MIM capacitors are important components in many circuits, such as many analog, mixed-signal, and radio frequency complementary metal oxide semiconductor (RF CMOS) circuits. MIM capacitors generally provide better performance than alternatives such as POP (Poly-Oxide-Poly) capacitors and MOM (Metal-Oxide-Metal Lateral Flux) capacitors due to lower resistance, better matching, and / or better signal-to-noise ratio.

[0006] MIM capacitors are typically arranged only below the top metal layer, for example using an existing top-1 metal layer as the bottom electrode, thereby constructing a top electrode with a different metal (e.g., Ti / TiN, Ta / TaN, W), and connecting the overlying top metal layer to the top and bottom electrodes of the capacitor through corresponding vias.

[0007] Conventional MIM capacitors are built on aluminum interconnects and include an insulator layer formed between an aluminum bottom electrode (top-1 metal layer) and a metal top electrode (e.g., Ti, TiN, or Al). The Al bottom electrode and the metal top electrode are each connected to a corresponding pad (top metal layer) through one or more vias, for example, each via being formed by filling a via hole with tungsten (W) or other suitable metal. The insulator layer may be, for example, having about The thickness of the SiN layer is .

[0008] Another conventional MIM capacitor is built on a copper (Cu) interconnect and includes an insulator layer formed between a Cu bottom electrode (top-1 metal layer) and a metal top electrode (e.g., Ta, TaN, or TiN). The Cu bottom electrode and the metal top electrode are each connected to a corresponding pad (top metal layer) through one or more vias, for example, each via formed by filling a via hole with copper or other suitable metal. As with the capacitor built on the Al interconnect, the insulator layer of the capacitor built on the Cu interconnect can be, for example, having about The insulator layer also acts as a dielectric diffusion barrier for the copper of the bottom electrode.

[0009] As used herein, a "via" refers to a conductive via formed by plugging a via hole or otherwise depositing a conductive material (e.g., tungsten) in a via hole, the via hole having a small diameter or width (e.g., a diameter or width of less than 1 μm), and thereby having a relatively large resistance, such as a resistance of at least 1 ohm per via. For example, conventional vias typically have a small diameter in the range of 0.1 μm to 0.5 μm, and, for example, may have a resistance of about 10 ohms per via, particularly for vias formed from tungsten or other high resistance materials. Therefore, conventional MIM capacitors typically include multiple vias (e.g., multiple vias between a top electrode and a top electrode pad and / or multiple vias between a bottom electrode and a bottom electrode pad) to reduce the overall resistance to some extent. As used herein, in the context of a MIM capacitor, a "via connection" refers to a via extending from a capacitor electrode (top electrode or bottom electrode) to an overlying conductive pad.

[0010] MIM capacitors can also be constructed between a polysilicon (e.g., polysilicide) layer and a metal layer. The polysilicon layer can be connected to a pad in the metal layer by one or more contacts, each contact being formed by filling a contact hole with a suitable material. As used herein, "contact" refers to a conductive contact formed by plugging a contact hole or otherwise depositing a conductive material (e.g., tungsten) in the contact hole, the contact hole having a small diameter or width (e.g., a diameter or width less than 1 μm), and thus having a relatively large resistance, such as a resistance of at least 1 ohm per contact. For example, conventional contacts typically have a small diameter in the range of 0.1 μm to 0.5 μm, and, for example, particularly for contacts formed of tungsten or other high resistance materials, may have a resistance of about 10 ohms per contact. Therefore, conventional MIM capacitors typically include multiple contacts (e.g., multiple contacts between a polysilicon layer / active layer forming a bottom electrode and a bottom electrode pad) to reduce the total resistance to some extent. As used herein, in the context of a MIM capacitor, a "contact connection" refers to a contact extending from a polymeric capacitor electrode to an overlying conductive pad.

[0011] As mentioned above, due to lower resistance, better matching and better signal-to-noise ratio, MIM capacitors can provide performance that is superior to other alternatives. For example, MIM capacitors can provide better performance than POP (polymerization-oxide-polymerization) capacitors and MOM (metal-oxide-metal lateral flux) capacitors. In addition, in MIM capacitors, the resistance of each of the top electrode and the bottom electrode will usually affect the MIM capacitor performance, especially when used in RF applications. In addition, for example, compared with other certain types of capacitors, MIM capacitors are typically built at a high cost. For example, compared with POP (polymerization-oxide-polymerization) capacitors and MOM (metal-oxide-metal lateral flux) capacitors, MIM capacitors typically require additional mask layers and many additional process steps.

[0012] Conventional MIM capacitors can be constructed by a top electrode, a bottom electrode, and an insulator (dielectric) sandwiched therebetween, and are therefore metal-insulator-metal (MIM). A MIM capacitor can be constructed between an Mx metal layer and an Mx+1 metal layer. A MIM capacitor includes an insulator layer formed between a bottom electrode (a portion of the Mx metal layer) and a metal top electrode. The bottom electrode and the metal top electrode are each connected to a corresponding contact and connected by one or more through holes. A pad can be etched or formed in the Mx+1 metal layer.

[0013] Typically, MIM capacitors may be constructed with an additional mask layer to define the top electrode, and therefore may be more expensive to manufacture than MOM and POP capacitors. If the bottom electrode is made of aluminum, it may be rough and have bumps or protrusions, which results in a low and uncontrolled breakdown voltage. Conventional MIM capacitors may suffer from a low and uncontrolled breakdown voltage due to the bumps or protrusions located in the bottom electrode (especially the aluminum bottom plate). As used herein, a bump is a protrusion that is large enough to significantly reduce the breakdown voltage of the MIM capacitor.

[0014] There is a need for MIM capacitors that can be manufactured at lower cost, particularly without the addition of masking layers, and that have improved breakdown voltage by having fewer protrusions. Summary of the invention

[0015] Aspects include a method of constructing a MIM capacitor in a MIM module that can be performed simultaneously with constructing an interconnect structure without using additional masks. One aspect of the process constructs a MIM capacitor without a mask by etching a trench in a dielectric layer, whereby a first chemical mechanical polish (CMP) of the entire integrated circuit structure recesses and erodes the bottom electrode metal adjacent to the trench to a depth sufficient to construct a MIM capacitor whose bottom electrode is below the upper surface of the dielectric layer. In the case where the MIM capacitor bottom electrode crosses over the rest of the integrated circuit structure below the upper surface of the dielectric layer, a second CMP polishes away the dielectric layer material from the rest of the chip without damaging the dielectric layer of the MIM capacitor. Aspects also include a MIM capacitor in a MIM module, wherein the MIM capacitor has a disc-shaped bottom electrode.

[0016] One aspect provides a method comprising: etching a dielectric layer to form a through hole or contact hole, a groove area and a trench in the dielectric layer; depositing conformal metal in the through hole or contact hole, the groove area and the trench, wherein the deposited conformal metal forms a through hole or contact in the through hole or contact hole; depositing a bottom electrode metal in the groove area to form a bottom electrode of a metal-to-metal (MIM) capacitor; removing a portion of the bottom electrode metal from the bottom electrode to form a disk-shaped upper surface of the bottom electrode; depositing an insulator material on the bottom electrode to form an insulator layer of the MIM capacitor; and depositing a top electrode metal on the insulator layer to form a top electrode of the MIM capacitor.

[0017] According to one aspect, a device is provided, comprising: a metal-insulator-metal (MIM) capacitor, the MIM capacitor comprising: a bottom electrode, the bottom electrode comprising a bottom electrode metal and having a disk-shaped upper surface; a top electrode, the top electrode comprising a top electrode metal and having a substantially convex lower surface positioned relative to the disk-shaped upper surface of the bottom electrode; and an insulator layer located between the top electrode and the bottom electrode. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] The figures illustrate an example method of building a MIM capacitor in a MIM module simultaneously with an interconnect structure without using additional masks, and an example MIM capacitor having a disk-shaped bottom electrode.

[0019] Figure 1 A cross-sectional side view of a metal-insulator-metal (MIM) module is shown having a MIM capacitor constructed of a curved top electrode, a curved bottom electrode, and a curved insulator (dielectric) sandwiched therebetween.

[0020] Figure 2A cross-sectional side view of an interconnect structure and a MIM module with a MIM capacitor having a disk-shaped surface is shown.

[0021] Figure 3A A cross-sectional side view of a wafer and etched dielectric layer used to build a MIM capacitor in a MIM module simultaneously with an interconnect structure is shown.

[0022] Figure 3B Shows Figure 3A Top view of a wafer, where the trench is a continuous trench surrounding the tank area.

[0023] Figure 3C Shows Figure 3A Top view of a wafer, where the grooves may be segmented, such as four grooves in four directions surrounding the groove area but not connected.

[0024] Figure 3D A conformal metal layer is deposited thereon. Figure 3A A cross-sectional side view of a wafer of FIG. 1 , wherein the conformal metal layer is used to build a MIM capacitor in a MIM module simultaneously with the interconnect structure.

[0025] Figure 3E shows the bottom electrode metal after it has been deposited onto the wafer Figure 3B Cross-sectional side view of a wafer.

[0026] Figure 3F shows the wafer after the first chemical mechanical polishing (CMP) Figure 3C Cross-sectional side view of the interconnect structure and MIM module.

[0027] Figure 3G Shown after deposition of insulator and top electrode metal Figure 3D Cross-sectional side view of the interconnect structure and MIM module.

[0028] Figure 3H shows the wafer after the second chemical mechanical polishing (CMP) Figure 3E Cross-sectional side view of the interconnect structure and MIM module.

[0029] Fig. 3I shows that after the Mx+1 metal layer has been deposited on the wafer Figure 3F Cross-sectional side view of the interconnect structure and MIM module.

[0030] Figure 3J Shown after the Mx+1 metal layer has been patterned and etched Figure 3G Cross-sectional side view of the interconnect structure and MIM module.

[0031] Figure 4It is shown how the Preston equation explains the removal rate of the bottom electrode metal.

[0032] FIG. 5A to FIG. 5C The implications of Preston's equation are shown, where the removal rate can depend on the pattern density.

[0033] Figure 6 A cross-sectional side view of a MIM capacitor constructed between a silicided polysilicon layer and an M1 metal layer is shown.

[0034] Figure 7 A flow chart of a method for constructing a MIM capacitor is shown.

[0035] Figure 8 A flow chart of a method for constructing a MIM capacitor is shown.

[0036] Fig. 9 A cross-sectional side view of a MIM capacitor having a curved surface is shown.

[0037] Reference numerals for any illustrated element that appear in multiple different figures have the same meaning in the multiple figures, and reference or discussion herein to any illustrated element in the context of any particular figure also applies to every other figure (if any) in which the same illustrated element is shown. DETAILED DESCRIPTION

[0038] Aspects provide methods for constructing a MIM capacitor in a MIM module that can be performed simultaneously with constructing an interconnect structure without using an additional mask, and an example MIM capacitor has a disk-shaped bottom electrode. It is not necessary to construct the interconnect structure simultaneously, and the method for constructing a MIM capacitor in a MIM module can be performed without constructing the interconnect structure simultaneously without exceeding the scope.

[0039] Figure 1A cross-sectional side view of a MIM module 134 with a MIM capacitor 110 is shown. The MIM capacitor 110 can be constructed in a dielectric layer 140 between an Mx metal layer 128 and an Mx+1 metal layer 130. The dielectric layer 140 can have a trough 144 and a groove 146. The trough 144 is a recess in the dielectric layer 140 in which the MIM capacitor 110 can be constructed. The groove 146 is a recess in the dielectric layer 140 near the trough 144 that facilitates the removal of material to form a curved electrode. The MIM capacitor 110 can be constructed in the trough 144 and consists of a bottom electrode 114, an insulator layer 112, and a top electrode 116. The bottom electrode 114 is below an upper surface 148 of the dielectric layer 140. The bottom electrode 114 and the top electrode 116 can be in the form of a plate. A bottom electrode connector 156 can be optionally formed in the groove 146. The MIM capacitor 110 may be surrounded by a groove 146 (single or multiple grooves, or dummy grooves) so that a polishing step can be used to remove a portion of the bottom electrode material to form a slightly curved surface of the bottom electrode material in the dielectric layer 140 to be formed into the MIM capacitor 110. Optionally, the groove 146 can also serve as a bottom electrode connector 156. The bottom electrode 114 can be made of a refractory metal and can be polished so that the surface is smooth and substantially free of protrusions. For the purposes of this disclosure, free of protrusions means that the surface does not have a protrusion or protrusion that is large enough to significantly reduce the breakdown voltage of the MIM capacitor 110. Refractory metals are a class of highly heat-resistant and wear-resistant metals. In the present disclosure, they are metals (e.g., Ti, TiN, W, Ta, TaN, Co) used in semiconductor processes, and their melting point temperatures are significantly higher than 400°C. Because the back-end of line (BEOL) semiconductor process is controlled to less than about 400°C, the refractory metal does not produce bulges due to thermal stress relief, and can therefore provide capacitors with high and consistent breakdown voltages. For example, tungsten or cobalt can be used without bulges. The surface without bulges can have a tighter breakdown voltage distribution because it has no outliers and can be the result of using refractory metals. Alternatively, aluminum Al can be used with high radio frequency RF power during deposition (so-called smooth metal) with large grain size and reduced film roughness.

[0040] Figure 2A cross-sectional side view of an interconnect structure 232 and a MIM module 234 having a MIM capacitor 210 is shown. The method constructs the MIM capacitor 210 simultaneously with the interconnect structure 232, which does not require the addition of a mask as part of the construction process. The MIM capacitor 210 can be constructed in a dielectric layer 240 between the Mx metal layer 228 and the Mx+1 metal layer 230. The dielectric layer 240 can have a via 242, a slot 244, and a groove 246. The slot 244 is a groove in the dielectric layer 240 in which the MIM capacitor 210 can be constructed, as further described below. The groove 246 is a groove in the dielectric layer 240 near the slot 244, which facilitates the removal of material to form a curved electrode, as further described below. The MIM capacitor 210 can be constructed in the slot 244 and consists of a bottom electrode 214, an insulator layer 212, and a top electrode 216. One or more through holes 252 can be deposited in the via hole 242 of the interconnect structure 232. The bottom electrode connector 256 may optionally be formed in the groove 246. The capacitor 210 may be surrounded by the groove 246 (single or multiple grooves, or dummy grooves) so that a polishing step may be used to remove a portion of the bottom electrode material to allow the capacitor 210 to be formed in the groove area 244. The polishing step forms a slightly curved surface of the bottom electrode material in the dielectric layer 240 where the capacitor 210 is to be formed. Optionally, in addition to using tungsten W vias 252 (via-x), the groove 246 may also serve as the bottom electrode connector 256. The bottom electrode 214 may be made of a refractory metal and may be polished so that the surface is smooth and substantially free of protrusions. For the purposes of this disclosure, free of protrusions means that the surface does not have protrusions or protrusions that are large enough to significantly reduce the breakdown voltage of the MIM capacitor 210.

[0041] FIG. 3A to FIG. 3J An example process for forming a MIM capacitor according to one aspect is shown. FIG. 3A to FIG. 3J Each of the figures shows a cross-sectional view at two locations of the integrated circuit structure 300 under construction, namely a first location (labeled “interconnect structure” 332) where an upper metal pad connected to the Mx metal layer 328 (e.g., a Cu MTOP layer) is formed and a second location (labeled “MIM module” 334) where an upper metal pad connected to the Mx metal layer 328 (e.g., a Cu MTOP layer) is formed. Figure 3A As shown, a MIM capacitor 310 is being constructed at this second location.

[0042] Figure 3AA cross-sectional side view of a wafer is shown on which a MIM module 334 including a MIM capacitor can be fabricated. The Mx metal layer 328 can be any layer of interconnect metal, for example. The MIM module 334 can be constructed simultaneously with the interconnect structure 332. The MIM module 334 begins by applying a dielectric layer 340 to the Mx metal layer 328 of the wafer. Chemical mechanical planarization (CMP) can be performed. A photoresist layer (not shown) can be deposited over the dielectric layer 340 and patterned to define openings to form one or more vias 342, a tank region 344, and one or more trenches 346. Etching can then be performed through the openings in the photoresist layer to define the vias 342, the tank region 344, and the trench 346, thereby exposing the top surface area of ​​the Mx metal layer 328. The vias 342 are patterned simultaneously with the tank region 344 (large size opening) and the trench 346 (dummy pattern surrounding the tank region 344 to reduce the pattern density, as will be further described) in the dielectric layer 340. The via hole 342 is relatively small (typically in the range of 0.1 μm to 0.5 μm), the groove area 344 is relatively large (e.g., in the range of 1 μm to 100 μm), and the width of the groove 346 is between the diameter of the via hole 342 and the diameter or width of the groove area 344 (e.g., in the range of 1 μm to 10 μm). Figure 3A As shown, the trench region 344 is surrounded by a trench 346 . Figure 3A A single trench is shown in FIG, but alternatively, multiple trenches with different widths may be implemented to achieve a desired pattern density variation. Plasma etching may be performed on dielectric layer 340 to form via holes 342 in interconnect structure 332, trench regions 344 in MIM module 334, and trenches 346 in dummy structures surrounding trench regions 344.

[0043] Figure 3B Shows Figure 3A A top view of a MIM capacitor (in construction) is shown, wherein trench 346 is a continuous trench around the perimeter of tub region 344. A portion of dielectric layer 340 extends completely around the perimeter of tub region 344 where the MIM capacitor will be constructed, and wherein trench 346 extends completely around the perimeter of the portion of dielectric layer material 340. Figure 3C Shows Figure 3A A top view of an alternative example of a MIM capacitor (in construction) is shown in which the groove 346 is a segmented groove that includes a series of individual grooves around the periphery of the groove region 344, such as four grooves in four directions surrounding the groove region 344 but not connected, so that the groove 346 extends partially around the periphery of the portion of the dielectric layer material 340 surrounding the groove region 344.

[0044] Figure 3DA conformal metal layer 360 (e.g., tungsten W) is shown being applied to a wafer to fabricate a MIM capacitor. A titanium nitride TiN liner (not shown) or glue layer may be deposited at a thickness of about 50 Å to 300 Å, followed by the deposition of a conformal metal layer 360, such as tungsten W. The conformal metal layer 360 may be formed by plasma enhanced chemical vapor deposition (PECVD) such that it is deposited with a substantially uniform thickness on all exposed surfaces. The conformal metal layer 360 (e.g., tungsten W film) may have a relatively large tensile stress. The deposition thickness of the tungsten W layer may generally not be greater than about 5000 Å, and may have any suitable thickness for subsequently defining an insulator layer of the MIM capacitor being formed, for example, in to range (for example, to For example, to or about ). If the conformal metal layer 360 is too thick, it may cause peeling or wafer breakage during subsequent chemical mechanical polishing (CMP) of the conformal metal layer 360. The via hole 342 in the dielectric layer 340 of the interconnect structure 332 may be completely filled with the conformal metal layer 360 to form the through hole 352, but the groove area 344 and the trench 346 may be partially filled with the conformal metal layer 360.

[0045] Figure 3E Deposition on a wafer to form a bottom electrode is shown. The bottom electrode metal 370 (e.g., titanium nitride (TiN) or titanium nitride (TiN) plus tungsten (W)) can be deposited by physical vapor deposition (PVD) or a combination of PVD and chemical vapor deposition (CVD) methods. Titanium nitride (TiN) can have compressive stress (for films less than 1um) and can be used to compensate for the tensile stress of tungsten (W) used for the conformal metal layer 360. When used for the bottom electrode, refractory metals (TiN, W, etc.) do not produce protrusions, which can also provide a higher and more consistent breakdown voltage. Alternatively, aluminum Al can be used with high radio frequency RF power during deposition (a so-called smooth metal) with a large grain size and reduced film roughness. In Figure 3E In the example shown, the bottom electrode metal 370 covers the interconnect structure 332 and completely fills the trench 346 of the MIM module 334. The bottom electrode metal 370 also substantially fills or at least very nearly fills the trench region 344 of the MIM module 334 to form the bottom electrode 314.

[0046] Figure 3FA cross-sectional side view of the interconnect structure 332 and the MIM module 334 after the first chemical mechanical polishing (CMP) of the wafer is shown. CMP may be performed to remove the bottom electrode metal 370 and the conformal metal layer 360 outside the through hole 352 of the interconnect structure 332. The CMP may further remove a portion of the bottom electrode metal 370 and the conformal metal layer 360 from the trough area 344 and the trench 346. The high down force (HDF or high pressure) combined with the pattern of the trench 346 near the trough area 344 allows for intentional recessing of the MIM module 334, in particular, the top surface 318 of the bottom electrode metal 370 within the trough area 344 is disc-shaped, that is, the upper surface 318 of the bottom electrode metal 370 expresses a convex function. For clarity, a convex function is a function in which a line segment between any two points on a graph of the function is located above the graph between the two points. The polishing pressure may typically be 3 psi to 5 psi (pounds per square inch) or higher, and a highly selective slurry (polishing rate for metals significantly higher than polishing rate for dielectric materials) may be used for the first CMP process. Due to the reduced pattern density provided by the trenches 346 surrounding the trough region 344 (the formation of the trenches reduces the pattern density), the CMP may be recessed into the bottom electrode metal 370 in the trough region 344 (notably, the depth D is in the range of about 0.1 μm to 0.50 μm (i.e., 1000 angstroms to 5000 angstroms), for example, about 0.2 μm or 2000 angstroms), and into the trenches 346 (to a much lesser extent), thereby forming a dished (slightly recessed) upper surface in the bottom electrode metal 370, particularly in the bottom electrode 314. The upper surface 318 of the bottom electrode metal 370, which forms the bottom electrode of the MIM capacitor, is therefore located below the upper surface 348 of the dielectric layer 340. The first CMP process can produce a smooth disk-shaped upper surface 318 that can provide a higher breakdown voltage MIM capacitor (in construction). The first CMP process can remove protrusions that are large enough to significantly reduce the breakdown voltage of the MIM capacitor. The polished disk-shaped upper surface 318 of the bottom electrode 314 can be non-bumpy, meaning that the surface does not have protrusions that are large enough to significantly reduce the breakdown voltage of the capacitor.

[0047] like Figure 3FAs shown, the curvature caused by the CMP used for polishing is microscopic and not significantly macroscopic. For example, the depression to a depth D between about 0.1 μm and about 0.5 μm (e.g., about 0.2 μm (2000A)) may occur in the vertical direction (depth D) on a horizontal scale (width W) between about 1 μm and about 100 μm (e.g., about 10 μm), which represents a very small deviation from the flat (planar) surface at an angle of about 2 degrees at the periphery of the depression in the groove area 344 and the groove 346. The disc-shaped (slightly concave) upper surface 318 may not affect the capacitance matching because all the disc-shaped upper surfaces polished in a single wafer may have approximately the same depression depth. Capacitance matching is achieved when two capacitors have the same or very similar physical dimensions to maintain the same or very similar capacitance values. Capacitance matching can be an important characteristic for capacitors used in precision analog applications or SAR ADCs (successive approximation register analog-to-digital converters). Due to variations in consumables such as polishing pads, polishing slurries and other factors, CMP recess depths may more easily vary between two different wafer batches. Within a single wafer, particularly within a die (device), recess variations can be very small, so capacitance matching can be preserved. In addition, the finished disc-shaped (slightly recessed) upper surface 318 of the bottom electrode metal 370 (particularly in the bottom electrode 314) can be polished to a smooth, non-protruding surface. The polished disc-shaped (slightly recessed) upper surface 318 can be non-protruding during manufacturing and after a later thermal cycle, where refractory metals are unlikely to produce protrusions due to stress relief from subsequent thermal treatments.

[0048] like Figure 4 As shown, Preston's equation can explain the use of dummy trench patterns to create curved bottom electrode metal 370 in the trench region. The removal rate of chemical mechanical polishing (CMP) can be proportional to the down force and speed.

[0049] RR=K P *P*V

[0050] in

[0051] RR = Removal Rate

[0052] K P = Preston coefficient

[0053] P = applied pressure

[0054] V = Linear velocity

[0055] The removal rate RR may increase with increasing downwardly applied pressure P and / or increasing linear velocity V.

[0056] FIG. 5A to FIG. 5CThe meaning of Preston's equation is shown, where the removal rate RR can depend on the local pattern density. By engineering the local pattern density, the desired amount of dishing and corrosion of the bottom electrode metal can be achieved. Differences in pattern density can lead to differences in polishing rate, and such pattern density sensitivity can be engineered to produce desired dishing and corrosion. Figure 5A The pattern density (P 实际 =10*P 应用 The removal rate at 10% pattern density may be equal to ten times the overburden removal rate because the actual applied pressure is 10 times the applied pressure since it is ultimately applied to only 10% of the wafer surface area, even though the total material removed may be similar. Figure 5B A wafer with 50% pattern density (P 实际 =2*P 应用 ). The removal rate at 50% pattern density may be equal to twice the overburden removal rate, although the total material removed may be similar. Figure 5C The wafer without pattern (P 实际 =P 应用 ), so that the wafer has been flattened

[0057] Figure 3GA cross-sectional side view of the interconnect structure 332 and the MIM module 334 after applying the insulator layer 312 and the top electrode metal 380 is shown. The top electrode metal deposition can be performed after the insulator deposition. The insulator layer 312 can be a silicon nitride layer (SiN) with a thickness of about 500A, and can be deposited on the top of the finished disk-shaped (slightly concave) upper surface 318 of the bottom electrode metal 370 by PECVD (plasma enhanced chemical vapor deposition). Alternatively, the insulator layer 312 can be silicon oxide or a high-k dielectric (where k>7), such as Al2O3 (κ~10), Ta2O5 (K~25) and HfO2 (κ~22), ZrO2 (K~35), etc., and can be deposited on the top of the finished disk-shaped (slightly concave) upper surface 318 of the bottom electrode metal 370 by ALD (atomic layer deposition). The insulator layer 312 is therefore similarly disk-shaped (slightly concave). The insulator layer 312 may have a substantially uniform thickness between the top electrode 316 and the bottom electrode 314. The top electrode metal 380 may be titanium nitride (TiN), titanium plus titanium nitride (Ti+TiN), titanium nitride plus tungsten (TiN+W), aluminum (Al), or any suitable metal deposited on top of the disk-shaped (slightly concave) insulator layer 312. The bump in the top electrode metal may not be a problem for the capacitor breakdown voltage. By depositing both the insulator layer 312 and the top electrode metal 380, the MIM capacitor 310 may be constructed in the disk-shaped trench region 344. The MIM capacitor 310 may include a bottom electrode 314, an insulator layer 312, and a top electrode 316.

[0058] Figure 3H A cross-sectional side view of the interconnect structure 332 and the MIM module 334 after a second chemical mechanical polish (CMP) of the wafer is shown. The second CMP can be performed to remove the top electrode metal 380 and the insulator layer 312 outside the through hole 352 of the interconnect structure 332 and outside the groove area 344 and the trench 346 of the MIM module 334. The second CMP process can planarize the wafer surface, including the top surface of the top electrode metal 380. The bottom surface 317 of the top electrode metal 380 facing the insulator layer 312 is curved to match the top surface of the disk-shaped (slightly concave) insulator layer 312, which matches the top surface 318 of the bottom electrode 314, leaving the curved top electrode metal 380, thereby forming the top electrode 316 in the groove area 344 of the MIM module 334. The first CMP (see Figure 3F ) and the second CMP (see Figure 3H) can be mainly the down force (pressure) used. The first CMP process can use a high down force (HDF or high pressure), together with a dummy groove pattern around the groove area, to intentionally create a depression in the MIM module. For the first CMP process, the polishing pressure can be typically 3psi to 5psi (pounds per square inch) or higher. The second CMP process can use a low down force (LDF or low pressure) to flatten the surface. The polishing pressure can be lower than the polishing pressure used for the first CMP process, for example 1psi to 2psi. The selectivity of the slurry used for the first CMP and the second CMP can also be different. The first CMP process can use a high selectivity slurry that polishes metals (such as conformal metal layer 360 and bottom electrode metal 370) at a much higher rate than oxides. The second CMP process can use a low selectivity slurry that polishes metals (such as top electrode metal 380) at a rate similar to that of dielectrics (e.g., insulator layer 312 and oxides).

[0059] Fig. 3I A cross-sectional side view of an interconnect structure 332 and a MIM module 334 is shown after deposition of an Mx+1 metal layer 330 which may be formed on a wafer. This Mx+1 metal layer 330 may be formed as part of a CMOS interconnect fabric.

[0060] Figure 3J A cross-sectional side view of the interconnect structure 332 and the MIM module 334 after metal patterning and etching is shown. The Mx+1 metal layer 330 can be patterned and etched. This can be part of the CMOS interconnect structure. A slight overetch can be used to etch through the top electrode metal 380 layer in the area between the tank area 344 and the trench 346 to avoid short circuits. The MIM capacitor 310 is completely built in the dielectric layer 340 between the Mx metal layer 328 and the Mx+1 metal layer 330. The MIM capacitor 310 has a bottom electrode 314, an insulator layer 312, and a top electrode 316. The bottom electrode 314 is electrically connected to the Mx metal layer 328 through the bottom electrode metal 370 and the conformal metal layer 360 in the tank area 344. In the example where the Mx metal layer 328 of the interconnect structure 332 is formed continuously with the Mx metal layer 328 of the MIM module 334, in the interconnect structure 332, the bottom electrode pad 322 is formed in the Mx+1 metal layer 330 and is electrically connected to the Mx metal layer 328 through the via 352. In the MIM module 334, the top electrode pad 320 in the Mx+1 metal layer 330 is electrically connected to the top electrode 316 through a portion of the top electrode metal 380. An optional bottom electrode pad 321 may also be formed in the Mx+1 metal layer 330 and is electrically connected to the Mx metal layer 328 through a bottom electrode connector 356, which may be formed in the trench 346 by a conformal metal layer 360 and a bottom electrode metal 370. Figure 3J As shown, the MIM module 334 is completed and ready for the wafer to continue with CMOS interconnect fabrication.

[0061] like Figure 6 As shown, the MIM capacitor 610 may alternatively be constructed between a silicided polysilicon layer and an M1 metal layer. In the case of polysilicide, the dielectric layer may be a poly-metal dielectric (PMD) layer. The polysilicide layer 638 may be on the polysilicon layer 637. The MIM capacitor 610 may be constructed in a poly-metal dielectric (PMD) layer 641 between the polysilicide layer 638 and the M1 metal layer 639. The MIM capacitor 610 has a bottom electrode 614, an insulator layer 612, and a top electrode 616. The bottom electrode 614 is electrically connected to the polysilicide layer 638 through a bottom electrode metal 670 in the trench region 644 and a conformal metal layer 660. In an example where the polysilicide layer 638 of the CMOS interconnect structure 636 is formed continuously with the polysilicide layer 638 of the MIM module 634, the bottom electrode pad 622 is formed in the M1 metal layer 639 and is electrically connected to the polysilicide layer 638 through the contact 653. The top electrode pad 620 in the M1 metal layer 639 is electrically connected to the top electrode 616 through the top electrode metal 680. The optional bottom electrode pad 621 may also be formed in the M1 metal layer 639 and is electrically connected to the polysilicide layer 638 through the bottom electrode connector 656, which may be formed in the trench 646 by the conformal metal 660 and the bottom electrode metal 670. The bottom electrode 614 may be made of a refractory metal and may be polished so that the surface is smooth and substantially free of protrusions. For the purposes of this disclosure, free of protrusions means that the surface does not have protrusions or protrusions that are large enough to significantly reduce the breakdown voltage of the MIM capacitor 610.

[0062] The disc-shaped MIM capacitor structure may be different from other MIM structures. It may have a slightly curved insulator layer, and the bottom electrode surface may be smooth (polished) and non-protruding (refractory metal). The grooves around the slot area can be used to provide a local pattern density for polishing to form a curved bottom electrode surface, and optionally connected to the bottom electrode. Different pattern densities may provide different curved bottom electrode surfaces. MIM capacitors may be constructed between two metal layers, or between a silicided polysilicon layer and an M1 metal layer.

[0063] Figure 7 A manufacturing method is shown in which a MIM capacitor can be constructed simultaneously with an interconnect structure without using additional masks. A dielectric layer is deposited 702 and one or more via holes, a slot region, and one or more trenches are etched. The pattern of the trenches surrounding the slot region reduces the pattern density. See FIG. 3A to FIG. 3C. Conformal metal is deposited 704 to form the via. The tungsten W deposition layer may be performed by plasma enhanced chemical vapor deposition (PECVD) and may be conformal such that it is deposited with a substantially uniform thickness on all exposed surfaces. The via may be completely filled with the conformal metal (e.g., tungsten W) of the conformal metal layer, but the slots and trenches may be partially filled with the conformal metal. See Figure 3D . Deposit 706 bottom electrode metal to form a bottom electrode. Figure 3E . A portion of the bottom electrode metal is removed 708 to form a recess in the trough region. The wafer is polished by chemical mechanical polishing (CMP) with a high down force (HDF or high pressure) and / or a high selectivity slurry to remove the bottom electrode metal and the conformal metal outside the vias, troughs, and trenches, and recess into the troughs (to a greater extent) and the trenches (to a much lesser extent), thereby forming a curved bottom electrode surface in the trough region. See Figure 3F An insulator layer is deposited 710 on the disk-shaped upper surface 318, i.e., onto the exposed surface, thereby coating the disk-shaped upper surface 318 of the bottom electrode metal 370. In one example, silicon nitride (SiN) is deposited by PECVD (plasma enhanced chemical vapor deposition). Alternatively, silicon oxide or a high-k dielectric is deposited by ALD (atomic layer deposition). See Figure 3G A top electrode metal is deposited 712 on the insulator layer to overfill the recess, i.e., completely cover the insulator layer and fill any recess caused by the removal of 708. The top electrode metal may be titanium nitride (TiN), titanium plus titanium nitride (Ti+TiN), titanium nitride plus tungsten (TiN+W), aluminum (Al), or any suitable metal. Figure 3G Excess top electrode metal is removed 714 to form a top electrode in the recess. The wafer is polished by chemical mechanical polishing (CMP) with a low down force (LDF or low pressure) and / or a low selectivity slurry to planarize the surface and remove the top electrode metal and insulator outside the vias, slots, and trenches. See Figure 3H A metal layer is formed 716 by deposition on the wafer, which may be part of a CMOS interconnect structure. Fig. 3I The metal layer is patterned and etched 718 through the top electrode metal layer in the area between the trough region and the trench, which may be part of a CMOS interconnect structure. Figure 3J .

[0064] Figure 8A method for building a MIM capacitor simultaneously with an interconnect structure in a MIM module without using an additional mask is shown. A dielectric layer is etched 802 to form a through hole or contact hole, a slot region, and a trench in the dielectric layer. A conformal metal is deposited 804 in the through hole or contact hole, the slot region, and the trench, wherein the deposited conformal metal forms a through hole or contact in the through hole or contact hole. A bottom electrode metal is deposited 806 in the slot region to form a bottom electrode of a metal-insulator-metal (MIM) capacitor. A portion of the bottom electrode metal is removed 810 from the bottom electrode to form a disk-shaped upper surface. An insulator material is deposited 812 on the bottom electrode to form an insulator layer of the MIM capacitor. A top electrode metal is deposited 814 on the insulator layer to form a top electrode of the MIM capacitor.

[0065] Fig. 9 A cross-sectional side view of a MIM capacitor 910 is shown. The MIM capacitor 910 has a bottom electrode 914, an insulator layer 912, and a top electrode 916. The bottom electrode 914 has an upper disk-shaped surface 918. For the purposes of this disclosure, a "disk-shaped surface" means a non-planar surface. The top electrode 916 has a substantially convex surface 917 positioned opposite the disk-shaped surface 918 of the bottom electrode 914, which is separated from the disk-shaped surface 918 of the bottom electrode 914 by a similarly shaped insulator layer 912, i.e., has a substantially convex surface positioned opposite the disk-shaped surface 918 of the bottom electrode 914 and a substantially concave surface opposite the substantially convex surface 917 of the top electrode 916.

[0066] Aspects may be used in any wafer FAB. Integration of the processes described herein may be compatible with foundry CMOS process flows.

[0067] Although examples have been described above, other modifications and examples may be made in accordance with this disclosure without departing from the spirit and scope of these disclosed examples.

Claims

1. A method, comprising: etching the dielectric layer to form vias or contact holes, slots and trenches in the dielectric layer; Depositing conformal metal in the through hole or contact hole, the groove area and the trench, wherein the deposited conformal metal forms a through hole or a contact in the through hole or contact hole, respectively; depositing a bottom electrode metal in the trench region to form a bottom electrode of a metal-insulator-metal (MIM) capacitor; removing a portion of the bottom electrode metal from the bottom electrode to form a disk-shaped upper surface; depositing an insulator material on the bottom electrode to form an insulator layer of the MIM capacitor; as well as A top electrode metal is deposited on the insulator layer to form a top electrode of the MIM capacitor. 2 . The method of claim 1 , wherein removing the portion of the bottom electrode metal from the bottom electrode comprises chemical-mechanical polishing.

3. The method of claim 1 or claim 2, wherein removing the portion of the bottom electrode metal from the bottom electrode comprises chemical-mechanical polishing with a downforce and a selective slurry sufficient to remove the portion of the bottom electrode metal from the trench region.

4. The method of claim 1 or claim 3, wherein removing the portion of the bottom electrode metal from the bottom electrode of the MIM capacitor comprises removing a protrusion large enough to substantially reduce a breakdown voltage of the MIM capacitor.

5. The method of claim 1 or claim 2, wherein removing the portion of the bottom electrode metal from the bottom electrode comprises recessing the bottom electrode to a depth between about 0.1 μm and about 0.5 μm and a width between about 1 μm and about 100 μm.

6. The method of claim 1 or claim 2, wherein removing the portion of the bottom electrode metal from the bottom electrode comprises removing the bottom electrode metal adjacent to the trench to a depth sufficient to construct a MIM capacitor whose bottom electrode is below an upper surface of the dielectric layer.

7. A method according to claim 1 or claim 2, wherein the via or contact is a through hole, and the method comprises: depositing the dielectric layer on the lower metal layer; depositing an upper metal layer over the via and the top electrode; as well as A pattern is etched in the upper metal layer to form a bottom electrode pad electrically connected to the bottom electrode through the via and to form a top electrode pad electrically connected to the top electrode.

8. The method of claim 1 or claim 2, wherein the via or contact is a contact, and the method comprises: depositing the dielectric layer on the polymerized silicide layer; depositing a metal layer on the contact and the top electrode; as well as A pattern is etched in the metal layer to form a bottom electrode pad electrically connected to the bottom electrode through the contact and to form a top electrode pad electrically connected to the top electrode.

9. A device, comprising: A metal-insulator-metal (MIM) capacitor, the MIM capacitor comprising: a bottom electrode comprising a bottom electrode metal and having a disc-shaped upper surface; a top electrode comprising a top electrode metal and having a substantially convex lower surface positioned opposite the disk-shaped upper surface of the bottom electrode; and An insulator layer is located between the top electrode and the bottom electrode. 10 . The apparatus of claim 9 , wherein the disk-shaped upper surface of the bottom electrode has a depth between about 0.1 μm and about 0.5 μm and a width between about 1 μm and about 100 μm.

11. An apparatus as claimed in claim 9 or claim 10, wherein the insulator layer has a substantially uniform thickness between the top electrode and the bottom electrode.

12. The apparatus of claim 9 or claim 10, wherein the disk-shaped upper surface of the bottom electrode has no protrusions large enough to substantially reduce the breakdown voltage of the MIM capacitor.

13. The apparatus according to claim 9 or claim 10, comprising: a trench, the trench comprising the bottom electrode metal; and A portion of a dielectric layer material, wherein the portion of the dielectric layer material is located between the trench and the MIM capacitor.

14. The apparatus of claim 13, wherein the portion of dielectric layer material extends partially around a perimeter of the MIM capacitor, and wherein the trench extends partially around a perimeter of the portion of dielectric layer material.

15. The apparatus of claim 13, wherein the portion of dielectric layer material extends entirely around a perimeter of the MIM capacitor, and wherein the trench extends entirely around a perimeter of the portion of dielectric layer material.

16. The apparatus of claim 9 or claim 10, comprising: a lower metal layer electrically connected to the bottom electrode of the MIM capacitor; and an upper metal layer electrically connected to the top electrode of the MIM capacitor; a bottom electrode pad electrically connected to the bottom electrode through a through hole; and A top electrode pad is electrically connected to the top electrode of the MIM capacitor.

17. The apparatus of claim 9 or claim 10, comprising: a polymeric silicide layer electrically connected to the bottom electrode of the MIM capacitor; and a metal layer electrically connected to the top electrode of the MIM capacitor; a bottom electrode pad electrically connected to the bottom electrode through a contact; and A top electrode pad is electrically connected to the top electrode of the MIM capacitor.

18. The apparatus of claim 9 or claim 10, comprising: A dielectric layer has an upper surface, wherein a bottom electrode of the MIM capacitor is located below the upper surface of the dielectric layer.

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