Three-dimensional metal-insulator-metal (MIM) capacitor and trench

Abstract

A method of fabricating a three-dimensional (3D) metal-insulator-metal (MIM) capacitor and a trench is achieved by etching a dielectric layer to form a via or contact hole, a bucket, and a trench in the dielectric layer; depositing a conformal metal in the via hole or the contact hole, the bucket, and the trench, where the deposited conformal metal forms a bottom portion and a sidewall portion of a 3D bottom electrode of a metal-insulator-metal (MIM) capacitor in the bucket, and wherein the deposited conformal metal forms a via or contact in the via hole or the contact hole; removing at least a portion of the dielectric layer and the conformal metal from the lip of the barrel; depositing an insulator layer on the 3D bottom electrode to form an insulator layer of the MIM capacitor; and depositing a metal layer on the insulator layer to form a top electrode of the MIM capacitor.

Description

[0001] Related patent applications

[0002] This application claims priority to commonly owned U.S. Patent Application No. 63 / 426,292 filed on November 17, 2022, the entire contents of which are hereby incorporated by reference for all purposes. Technical Field

[0003] The present disclosure relates to metal-insulator-metal (MIM) capacitors in, for example, analog / mixed-signal / RF-CMOS circuits, and more particularly to three-dimensional (3D) MIM capacitors. Background Art

[0004] A Metal-Insulator-Metal (MIM) capacitor is a capacitor constructed with a metal top electrode, a metal bottom electrode, and an insulator (dielectric) sandwiched between the two metal electrodes. The electrodes may be in the form of plates.

[0005] MIM capacitors are important components in many circuits, such as many analog, mixed-signal, and radio frequency complementary metal oxide semiconductor (RF CMOS) circuits. MIM capacitors can provide performance advantages over other alternatives due to lower resistance, better matching, and better signal-to-noise ratio. For example, MIM capacitors can provide better performance than POP (polysilicon-oxide-polysilicon) capacitors and MOM (metal-oxide-metal lateral flux) capacitors.

[0006] MIM capacitors are typically configured to be built just below a top metal layer, for example using an existing top-1 metal layer as a bottom electrode, constructing a top electrode with a different metal (e.g., titanium or titanium nitride (Ti / TiN), tantalum or titanium nitride (Ta / TaN), or tungsten (W)), and connecting the overlying top metal layer to the top and bottom electrodes of the capacitor through corresponding interconnect structures. The top electrode typically has a higher resistance than the bottom electrode, for example because the top electrode may be limited by thickness constraints and material selection for integration, thereby limiting the performance of conventional MIM capacitors.

[0007] Conventional MIM capacitors can be constructed with aluminum interconnect structures or with copper interconnect structures. MIM capacitors include an insulator layer formed between a bottom electrode (usually using an existing interconnect layer, aluminum or copper) and a metal top electrode (usually an additional metal layer inserted between two existing interconnect metal layers, with a metal such as Ti, TiN, Ta or TaN). The metal bottom electrode and the metal top electrode are each connected to a corresponding connection pad through one or more vias. The insulator layer can be, for example, a layer having about The thickness of the SiN layer is .

[0008] As used herein, a "via" is a connection between two metal layers, and a "contact" is a connection between the polysilicon / active layer and M1. The contact or via can be formed by plugging a via hole or a contact hole or otherwise depositing a conformal conductive material (e.g., tungsten) in the via hole or the contact hole and thus has a relatively large resistance, such as a resistance of at least 1 ohm per via, the via hole or the contact hole having a small diameter or width, such as a diameter or width of less than 1 μm. For example, conventional vias or contacts typically have a small diameter in the range of 0.1 μm to 0.5 μm, and, for example, particularly for vias or contacts formed from tungsten or other high resistance materials, can have a resistance of about 10 ohms per via. Therefore, conventional MIM capacitors typically include multiple vias or contacts (e.g., multiple vias or contacts between the top electrode and the top electrode pad and / or multiple vias or contacts between the bottom electrode and the bottom plate electrode pad) to reduce the overall resistance to some extent. As used herein, a "via" or "contact" in the context of a MIM capacitor refers to a via or contact that extends from a capacitor electrode (either the top electrode or the bottom electrode) to an overlying conductive pad.

[0009] In addition, MIM capacitors are typically expensive to construct, for example, compared to some other types of capacitors. For example, MIM capacitors typically require additional mask layers and many additional process steps compared to POP capacitors and MOM capacitors. MIM capacitors also typically use a relatively large silicon area, resulting in inefficient area usage, especially in the case of larger MIM capacitors.

[0010] Furthermore, in conventional MIM capacitors, the top electrode is thinner, thus providing a higher series resistance, because the vertical thickness of the top electrode is limited by the vertical distance between adjacent metal layers (eg, the top metal layer and the top-1 metal layer) in which the MIM capacitor is formed.

[0011] As mentioned above, conventional MIM capacitors can be constructed with a top electrode, a bottom electrode and an insulator (dielectric) sandwiched therebetween, and are therefore metal-insulator-metal (MIM) capacitors. MIM capacitors include an insulator layer formed between a bottom electrode (Mx metal layer) and a metal top electrode. The bottom electrode and the metal top electrode are each connected to a corresponding pad (Mx+1 top metal layer) through one or more through holes. Typically, MIM capacitors can be constructed with an additional mask layer to define the top electrode, so they may be more expensive to manufacture than metal-oxide-metal (MOM) and polysilicon-oxide-polysilicon (POP) capacitors. If the bottom electrode is made of aluminum, it may be rough and have a hillock or protrusion (uneven surface), which results in a low and uncontrolled breakdown voltage. A hillock is a protrusion large enough to significantly reduce the breakdown voltage of a MIM capacitor.

[0012] There is a need for a MIM capacitor that can be manufactured at a lower cost, particularly without added masking layers, and has an improved spatial density and / or an improved breakdown voltage by having fewer hillocks. Summary of the invention

[0013] Various aspects provide three-dimensional MIM capacitors that can be constructed simultaneously with interconnect structures and without adding any additional masks to the process, and have improved spatial density and / or improved breakdown voltage by having fewer hillocks. One aspect provides a process for constructing a 3D MIM capacitor by etching a trench in a dielectric layer without additional masks, whereby a first chemical mechanical polish (CMP) of the entire integrated circuit structure dish-shapes and erodes the electrode metal adjacent to the trench to a depth sufficient to construct the 3D MIM capacitor across the rest of the integrated circuit structure below the upper surface of the dielectric layer. In the case where the 3D MIM capacitor is below the upper surface of the dielectric layer, a second CMP polishes away the dielectric layer material from the rest of the integrated circuit structure without damaging the 3D MIM capacitor.

[0014] According to one aspect, a method is provided, the method comprising: etching a dielectric layer to form a via hole or a contact hole, a tub, and a trench in the dielectric layer; depositing conformal metal in the via hole or the contact hole, the tub, and the trench, wherein the deposited conformal metal forms a bottom portion and a sidewall portion of a three-dimensional bottom electrode of a metal-insulator-metal (MIM) capacitor in the tub, and wherein the deposited conformal metal forms a via or a contact in the via hole or the contact hole; removing at least a portion of the dielectric layer and the conformal metal from a lip of the tub; depositing an insulator material on the bottom electrode to form an insulator layer of the MIM capacitor; and depositing a metal layer on the insulator layer to form a top electrode of the MIM capacitor.

[0015] One aspect provides a device, which includes: a three-dimensional metal-insulator-metal (MIM) capacitor, which includes: a three-dimensional bottom electrode; a top electrode; and an insulator layer, which is located between the top electrode and the bottom electrode; an Mx metal layer or a silicided polysilicon layer, which is electrically connected to the three-dimensional bottom electrode; an Mx+1 metal layer or an M1 metal layer, which includes a top electrode; a metal pad, which is electrically connected to the Mx metal layer or the silicided polysilicon layer through a through hole or a contact, respectively, wherein the height of the three-dimensional bottom electrode is less than the height of the through hole or the contact.

[0016] According to another aspect, a device is provided, which includes: a three-dimensional metal-insulator-metal (MIM) capacitor, which includes: a three-dimensional bottom electrode; a top electrode; and an insulator layer, which is located between the top electrode and the bottom electrode; an Mx metal layer or a silicided polysilicon layer, which is electrically connected to the three-dimensional bottom electrode; an Mx+1 metal layer or an M1 metal layer, which includes a top electrode; and a metal pad, which is electrically connected to the Mx metal layer or the silicided polysilicon layer through a trench connection, respectively, wherein the height of the three-dimensional bottom electrode is less than the height of the trench connection. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] The figures illustrate examples of three-dimensional MIM capacitors built simultaneously with interconnect structures, and without adding masks to the process.

[0018] Figure 1 A cross-sectional side view of a three-dimensional MIM capacitor is shown.

[0019] FIG. 2A to FIG. 2D A cross-sectional view of a three-dimensional MIM capacitor built simultaneously with vias or contacts and without adding masks to the process is shown, where the height of the three-dimensional bottom electrode is shorter than the height of the vias or contacts.

[0020] Figure 3A A cross-sectional side view of a wafer is shown on which a three-dimensional MIM capacitor can be fabricated in a dielectric layer having vias, barrels, and trenches.

[0021] Figure 3B Shows Figure 3A Top view of a wafer where the groove is a continuous groove around the barrel.

[0022] Figure 3C Shows Figure 3A Top view of a wafer, where the grooves may be segmented, e.g., four grooves surround the barrel in four directions but are not connected.

[0023] Figure 3D 1 shows a wafer after applying a conformal metal layer (e.g., tungsten W) to fabricate a three-dimensional MIM capacitor. Figure 3A Cross-sectional side view of a wafer.

[0024] Figure 3E shows the wafer after the first chemical mechanical polishing (CMP) Figure 3D Cross-sectional side view of a wafer.

[0025] Figure 3F shows that after the insulator has been deposited Figure 3E Cross-sectional side view of a wafer.

[0026] Figure 3G shows the wafer after the second chemical mechanical polishing (CMP) Figure 3F Cross-sectional side view of a wafer.

[0027] Figure 3H It shows that after the Mx+1 metal layer is deposited on the wafer Figure 3G Cross-sectional side view of a wafer.

[0028] Fig. 3I Shown after the Mx+1 metal layer has been patterned and etched Figure 3H Cross-sectional side view of a wafer.

[0029] Figure 4 A cross-sectional side view of a MIM capacitor built between a silicided polysilicon layer and an M1 metal layer is shown.

[0030] Figure 5 Shown is how the Preston Equation explains the removal rate of conformal metal.

[0031] FIG. 6A to FIG. 6C The implications of Preston's equation are shown, where the removal rate can depend on the pattern density.

[0032] Figure 7 A flow chart showing a method of constructing a three-dimensional MIM capacitor.

[0033] Figure 8 A flow chart showing a method of constructing a three-dimensional MIM capacitor.

[0034] Reference numerals for any illustrative element that appear in multiple different figures have the same meaning in the multiple figures, and reference or discussion herein to any illustrative element in the context of any particular figure also applies to every other figure (if any) in which the same illustrative element is shown. DETAILED DESCRIPTION

[0035] The three-dimensional MIM capacitor can be built simultaneously with the interconnect structure and without adding masks to the process, and has improved spatial density and / or improved breakdown voltage by having fewer hillocks.

[0036] Figure 1A cross-sectional side view of an integrated circuit structure 100 having a three-dimensional (3D) MIM capacitor 104 is shown. The 3D MIM capacitor 104 may have a 3D electrode 114 that includes: (i) a bottom portion 114A formed on the Mx metal layer 102; and (ii) a vertically extending sidewall portion 114B that extends upward from the Mx metal layer 102 and is defined by a barrel 110 in the dielectric layer 106. The barrel 110 is a recess in the dielectric layer 106 in which the 3D MIM capacitor 104 may be constructed. An insulator layer 120 is formed on the 3D electrode 114 and includes: (i) a bottom portion 120A formed on the bottom portion 114A of the 3D electrode 114; and (ii) a sidewall portion 120B that covers the vertically extending sidewall portion 114B of the 3D electrode 114. The insulator layer 120 may be a conformal layer. The top electrode 130 may be in the Mx+1 layer.

[0037] FIG. 2A to FIG. 2D 2 and 3D MIM capacitors 204. Figure 2A shows a first cross-sectional side view, Figure 2B Shown by Figure 2A A second cross-sectional side view taken along the cutting line 2B-2B is shown, and Figure 2C Shown by Figure 2A A top cross-sectional view taken along cutting line 2C-2C is shown. Figure 2D Shown by Figure 2A A third cross-sectional side view taken along the cutting line 2D-2D shown. FIG. 2A to FIG. 2DAs shown together, the bottom electrode 201 of the MIM capacitor 204 includes: (a) a horizontally extending Mx metal layer 202; and (b) a 3D electrode 214, which is formed on the Mx metal layer 202 and has: (i) a bottom portion 214A, which is formed on the Mx metal layer 202; and (ii) a vertically extending sidewall portion 214B, which extends upward from the Mx metal layer 202. In some examples, the Mx metal layer 202 can be formed in a copper interconnect layer, such as a top copper interconnect layer referred to herein as a "Cu MTOP layer". The Mx metal layer 202 can be formed above a barrier layer such as a Ta / TaN barrier layer (not shown). The 3D electrode 214 can be formed in a barrel 210 formed in a dielectric layer 206. The dielectric layer 206 can be an interlayer dielectric (ILD) or a polysilicon metal dielectric (PMD). As discussed herein, barrel 210 may be a wide "barrel". 3D electrode 214 may be formed of a conformal material such as tungsten (W) or other suitable material, for example, formed of the same material as conductive via 224 and formed simultaneously with the conductive via, as discussed below. 3D electrode 214 is electrically coupled to Mx metal layer 202. Three-dimensional 3D electrode 214 may be cup-shaped or any other 3D geometric shape.

[0038] 3D MIM capacitor 204 may be referred to as a “single-layer” MIM capacitor because it uses only a single metal interconnect layer to form capacitor 204. Insulator layer 220 is formed in 3D electrode 214 and includes: (i) bottom portion 220A formed on bottom portion 214A of 3D electrode 214; and (ii) sidewall portion 220B covering vertically extending sidewall portion 214B of 3D electrode 214. Insulator layer 220 may be a conformal layer formed of SiN or other suitable dielectric materials.

[0039] The top electrode 230 is formed above the insulator layer 220 and extends downward into a three-dimensional, for example, cup-shaped barrel formed by the insulator layer 220, particularly defined by the top surface of the bottom portion 220A and the surface of the sidewall portion 220B. Figure 2B As shown, the 3D electrode 214 of the bottom electrode 201 significantly increases the capacitance area between the top electrode 230 and the bottom electrode 201 through both the horizontally extending bottom portion 220A and the vertically extending sidewall portion 220B of the insulator layer 220. The top electrode 230 may be formed of aluminum or other suitable materials.

[0040] The bottom electrode 201 may also be conductively connected to the top side bond pad 234, for example, by at least one via 224 connecting the bond pad 234 to the Mx metal layer 202. In some embodiments, the barrel 210 in which the 3D electrode 214 is formed may be formed simultaneously with the at least one narrow via cavity 208 in which at least one via 224 is formed. The barrel 210 and the via cavity 208 may be filled simultaneously, for example, by conformal metal deposition, to form the 3D electrode 214 and the via 224.

[0041] like Figure 2C As shown, the barrel 210 in which the 3D electrode 214 is formed (followed by the insulator layer 220 and the top electrode 230) can have a square shape from a top view. In other embodiments, the barrel can have a square shape with rounded corners, a rectangular shape, a rectangular shape with rounded corners, a circular shape, an oval shape, a cross shape, or any other suitable shape.

[0042] like Figure 2A As shown, the three-dimensional structure of the 3D MIM capacitor 204 defines not only a displacement current path through the bottom portion 220A of the insulator layer 220 (generally indicated by the dashed arrow 226), but also a displacement current path through the vertically extending sidewall portion 220B of the insulator layer 220 (generally indicated by the dashed arrow 228). Each insulator layer sidewall 220B provides an additional capacitive coupling area between the top electrode 230 and the bottom electrode 201. The bottom portion 220A of the insulator layer 220 effectively defines a capacitor in which the top electrode and the bottom electrode extend horizontally, and each insulator layer sidewall 220B effectively defines an additional capacitor in which the top electrode and the bottom electrode extend vertically. Therefore, the three-dimensional structure of the 3D MIM capacitor 204 thus defines a significantly increased capacitive coupling area between the top electrode 230 and the bottom electrode 201, for example, compared to conventional MIM capacitors. The three-dimensional bottom electrode 214 has a height 262 that is less than the height 260 of the through hole 224, wherein the respective heights 260, 262 are defined from a common plane at the top surface of the Mx metal layer 202. The difference between the height 262 of the three-dimensional bottom electrode 214 and the height 260 of the through hole 224 is between about 0.1 μm and about 0.5 μm. Figure 2A As illustrated, the height of the via 224 is the same as the height of the trench connection 222 .

[0043] FIG. 2A to FIG. 2DIt is also shown that the 3D MIM capacitor 204 formed in the barrel 210 can be surrounded by a trench connection 222 formed in a (single or multiple, continuous or segmented) trench 211. The barrel 210 is a recess in the dielectric layer 206 in which the 3D MIM capacitor 204 can be built. The trench 211 is a recess in the dielectric layer 206 near the barrel 210 that facilitates the removal of material at the lip of the barrel 210. The trench 211 can selectively form a local pattern density and produce a recess of the dielectric barrel lip 209 in the 3D MIM capacitor 204 (see Figure 2B ). The conformal metal cup in trench 211 may also optionally be used to form a trench connection 222 that provides an optional additional connection to bottom electrode 201 in addition to via 224 (via x) and may be electrically coupled to an optional bottom side bonding pad 236.

[0044] FIG. 2A to FIG. 2D The example 3D MIM capacitor 204 shown may have a bottom electrode made of conformal metal and be hillock-free. The MIM capacitor may be constructed between Mx and Mx+1, or between silicided polysilicon and M1. The top electrode 230 and topside bonding pad 234 may be in the Mx+1 layer.

[0045] The structure of 3D MIM capacitor 204 may be different from other MIM structures. According to the three-dimensional MIM of this example, it can be constructed in the same layer as the through hole or contact at the same time. The through hole can be constructed in the interlayer dielectric (ILD) layer between two metal layers (Mx and Mx+1), or the contact can be constructed in the polysilicon metal dielectric (PMD) layer between silicided polysilicon and M1. According to the MIM capacitor of this example, it can be constructed between two metal layers (Mx and Mx+1), or between silicided polysilicon and M1. The groove around the conformal metal barrel can be used to design the local pattern density, and is also optionally connected to the bottom electrode. The bottom electrode can be formed by conformal metal. The bottom electrode can also be formed by refractory metal (such as tungsten or cobalt), and is hillock-free, with a consistent breakdown voltage. Refractory metal is a class of metals that is highly heat-resistant and wear-resistant. In the present disclosure, they are metals (e.g., Ti, TiN, W, Ta, TaN, or Co) used in semiconductor processes, whose melting point temperatures are significantly higher than 400°C. Because the back-end-of-line (BEOL) semiconductor process is controlled below about 400°C, the refractory metals do not produce hillocks due to thermal stress release, and thus can provide capacitors with high and consistent breakdown voltages. The hillock-free surface can have a tighter breakdown voltage distribution because it has no outliers and can be a result of using refractory metals. Alternatively, during deposition, aluminum Al (a so-called smooth metal) can be used with high radio frequency RF power, with a large grain size and reduced film roughness.

[0046] Aspects can be used in any fabrication process (FAB). The integration of the process described herein can be compatible with foundry CMOS process flows.

[0047] FIG. 3A to FIG. 3I An exemplary method for forming a 3D MIM capacitor 304 (see Fig. 3I , for example, a cross-sectional view of an example process for an integrated circuit (IC) device similar to the example 3D MIM capacitor 204 shown in FIG. 2 . FIG. 3A to FIG. 3I The figures in FIG. 3 show cross-sectional views of two locations of an integrated circuit structure 300 being constructed according to an example, namely: a first location (labeled “interconnect structure”) at which a first upper metal Mx+1 334 (e.g., an aluminum bonding pad—see FIG. 334 ) is formed. Fig. 3I ) through one or more through holes 324 (see Fig. 3I ) is connected to the Mx metal layer 302 (e.g., Cu MTOP layer), which is a typical process in integrated circuit construction; and a second location (labeled "3DMIM module"), where a single-layer 3D MIM capacitor 304 is formed (see Fig. 3I According to one aspect, dishing / etching from a first chemical mechanical polish (CMP) removes a portion of the conformal layer from the barrel lip, which eliminates one masking layer compared to conventional processes, and dishing / etching from a second CMP removes a portion of the insulator layer outside the 3D MIM capacitor, which eliminates another masking layer compared to conventional processes.

[0048] Figure 3A 3. A selected portion of an Mx metal layer 302 (e.g., a Cu MTOP layer) in an IC structure 300 being constructed is shown. A first structure 302A of the Mx metal layer 302 is designated for a typical interconnect structure, while a second structure 302B of the Mx metal layer 302 is designated for a 3D MIM capacitor 304 (see FIG. 3) being constructed. Fig. 3I ). The first structure 302A may or may not be adjacent to (i.e., electrically connected to) the second structure 302B. Both structures 302A and 302B may be formed over respective barrier layers (not shown), such as Ta / TaN barrier layers, for example, by a process including the following operations: Cu deposition over the barrier layer followed by a copper CMP (chemical mechanical planarization) process.

[0049] After forming the Mx metal layer 302, a dielectric layer 306 may be deposited over the Mx metal layer 302. The dielectric layer 306 may include a first dielectric region portion 306A over the first structure 302A and a second dielectric region portion 306B over the second structure 302B. The dielectric layer 306 may be a combination of multiple dielectric films configured to protect underlying active integrated circuits. For example, the dielectric layer 306 may include the following four layers deposited in the following order: (1) 0.1 μm silicon nitride, (2) 0.1 μm silicon rich oxide (SRO), (3) 0.68 μm phosphosilicate glass (PSG), and (4) 0.59 μm silicon oxynitride (SiON).

[0050] A photoresist layer (not shown) may be deposited and patterned, followed by at least one etch to define a plurality of via holes 308, a barrel 310 for the 3D MIM capacitor 304 being constructed, and one or more trenches 311. The via holes 308, trenches 311, and barrel 310 may be etched simultaneously. The shape and size of barrel 310 may be selected based on various parameters, such as for efficient fabrication of 3D MIM capacitor 304 (e.g., efficient deposition of top electrode material (e.g., aluminum) into wide barrel 310) and / or for desired performance characteristics of the resulting 3D MIM capacitor 304. In some embodiments, barrel 310 may be formed to have a width W in the range of 1 μm to 100 μm. 桶 , and a vertical height H in the range of 1 μm to 10 μm 桶 In some embodiments, barrel 310 has a width in a direction inward through the page in a range of 1 μm to 100 μm, which may be similar to the illustrated width W. 桶 The same, for example in the case of a square or circular barrel 310. The groove 311 width dimension may be in the range of 1 μm to 10 μm.

[0051] In some embodiments, the barrel 310 may be formed to have a height to width aspect ratio (H) less than or equal to 2.0. 桶 / W 桶 ), for example to allow efficient filling of the barrel 310 by the conformal material. For example, the barrel 310 may be formed to have an aspect ratio H in the range of 0.1 to 2.0, for example in the range of 0.5 to 2.0. 桶 / W 桶 In some embodiments, barrel 310 may be formed to have an aspect ratio H less than or equal to 1.5. 桶 / W 桶 , for example, to effectively fill the barrel 310 with a conformal material. For example, the barrel 310 may be formed to have an aspect ratio H in the range of 0.5 to 1.5, or more specifically in the range of 0.8 to 1.2. 桶 / W桶 .

[0052] In some examples, the via holes 308 may be formed to have a width W in the range of 0.1 μm to 0.8 μm. 通孔 The width W of the barrel 310 is 桶 Greater than the width W of the through hole 308 通孔 For example, in some embodiments, the width W of barrel 310 桶 is the width W of the through hole 308 通孔 In a specific example, the width W of the barrel 310 is at least twice as large as 桶 is the width W of the through hole 308 通孔 At least five times as large as, for example, the width W of the barrel 桶 The width of the trench 311 may be between 1 μm and 100 μm. The width of the trench 311 may be between the width W of the via hole 308 通孔 and the width W of the barrel 310 桶 between 1 μm and 10 μm, for example.

[0053] Figure 3B Shows Figure 3A A top view of an illustrated 3D MIM capacitor 304 (under construction) in which trench 311 is a continuous trench around the perimeter of barrel 310. Trench 311 is in dielectric layer 306 and around the perimeter of barrel 310 for the 3D MIM capacitor. A portion of dielectric layer 306 is located between trench 311 and barrel 310 of the 3D MIM capacitor. A portion of dielectric layer 306 extends completely around the perimeter of barrel 310, and trench 311 extends completely around the perimeter of that portion of the dielectric layer. Figure 3C Shows Figure 3A A top view of an alternative example of a 3D MIM capacitor 304 (under construction) is illustrated, in which the trench 311 is a segmented trench comprising a series of individual trenches 311 around the perimeter of the barrel 310, for example, four trenches in four directions around the barrel 310 but not connected.

[0054] like FIG. 3A to FIG. 3I As shown, the 3D MIM capacitor 304 can be constructed simultaneously with the interconnect structure without using an additional mask on top of the mask required for the interconnect structure. Figure 3AAs shown, the interconnect structure starts with a patterning and etching step to form a hole 308 in the dielectric layer 306, which is part of a standard process for producing vias. The via hole 308 (small) on the interconnect structure is patterned simultaneously with the barrel 310 (large size opening, as described above) and the trench 311 (dummy pattern that at least partially surrounds the barrel 310 to reduce the pattern density) of the 3D MIM module. The via hole 308 is small, 0.1μm to 0.5μm, and the trench 310 is relatively large, 1μm to 100μm, and the width dimension of the trench 311 is between the critical dimension (CD) of the hole 308 and the CD of the barrel 310, for example, about 1μm to 10μm. The 3D MIM capacitor 304 can be surrounded by (single or multiple, continuous or segmented) trenches to provide the desired pattern density. Figure 3B A single trench 311 is shown in FIG, but multiple trenches with different widths may alternatively be implemented to achieve a desired pattern density variation. Plasma etching may be performed to simultaneously produce holes 308, trench 311 (dummy structure), and barrel 310 (3D MIM module). Trench 311 may be used to provide pattern density to produce a desired recessed portion of barrel lip 309 to form a capacitor, which will be further described. In addition to normal vias (via x), the conformal metal cup in trench 311 may also be used as a bottom electrode connection. A conformal metal bottom electrode without hillocks may be formed. 3D MIM modules may be constructed between Mx and Mx+1 metal layers, or between silicided polysilicon and M1.

[0055] Next, if Figure 3D As shown, a titanium nitride TiN liner (not shown) or glue layer may be deposited to have approximately to A conformal metal 312 (e.g., tungsten (W)) is then deposited on the structure 300 such that the conformal metal 312 fills the via holes 308 to form one or more vias 324 and forms a conformal layer on the bottom and sidewall surfaces of the barrel 310. The conformal metal 312 is thus in electrical contact with both the first structure 302A and the second structure 302B, which may be part of the Mx metal layer 302. The conformal metal 312 deposition may be performed by plasma enhanced chemical vapor deposition (PECVD) such that it is deposited on all exposed surfaces with a substantially uniform thickness. The conformal metal 312 may have a relatively large tensile stress. The deposition thickness of the conformal metal 312 may generally be limited to approximately If the conformal metal 312 is deposited too thick, it may cause delamination or wafer breakage during the subsequent chemical mechanical polishing (CMP) step. The via cavity 308 may be completely filled with the conformal metal 312 , but the barrel 310 and the trench 311 may be partially filled with the conformal metal 312 .

[0056] like Figure 3EAs shown, after a first chemical mechanical polish (CMP), at the lip of the barrel 310, the conformal metal 312 is removed due to dishing, and some of the dielectric layer 306 is removed due to erosion. The first chemical mechanical polish (CMP) may be performed to remove portions of the conformal metal 312 on the top side of the structure 300, such as portions of the conformal metal 312 above the via 324 and the barrel 310. The first CMP also removes at least portions of the dielectric layer 306 that define the trench 311, and in particular, may be removed at the barrel lip 309. The remaining conformal metal 312 in the barrel 310 defines a 3D electrode 314 that includes a bottom portion 314A and a sidewall portion 314B that extends upward from the bottom portion 314A (i.e., extends upward from the second interconnect structure 302B). 3D electrode 314 and underlying second interconnect structure 302B (e.g., copper) together define the bottom electrode 301 of the formed 3D MIM capacitor 304. As indicated above, second structure 302B and bottom portion 314A together form the bottom portion of bottom electrode 301. Due to the reduced pattern density around barrel 310 (due to trench 311), the pad used in CMP can be significantly dished into the barrel, thereby removing the conformal metal 312 between barrel 310 and trench 311 (or the lip of the barrel), and removing some of the dielectric layer 306 (the erosion amount of dielectric layer 306 can be about 1 / 4 of the dielectric layer 306). ). The erosion of the dielectric layer 306 is mainly due to the reduced local pattern density, and thus the local pressure at the lip of the bucket 310 increases. The three-dimensional 3D electrode 314 can be cup-shaped or any other 3D geometric shape.

[0057] Next, if Figure 3F As shown, an insulator layer 320 (e.g., a silicon nitride (SiN) layer or other conformal dielectric material) is deposited over the structure 300 and extends downward into the barrel 310 to cover the 3D electrode 314. A bottom portion 320A of the insulator layer 320 is formed on a surface of the bottom portion 314A of the 3D electrode 314, and a sidewall portion 320B of the insulator layer 320 is formed to cover the vertically extending sidewall portion 314B of the 3D electrode 314. The insulator layer 320 defines an insulator layer in the formed 3D MIM capacitor 304. The insulator layer 320 may have a substantially uniform thickness between the 3D electrode 314 and the top electrode 330 (see Fig. 3I ). The insulator layer 320 may have any suitable thickness, for example to For example to For example to or about The thickness is within the range of . The insulator layer 320 can be silicon nitride (SiN) and can be deposited by PECVD (plasma enhanced chemical vapor deposition). Alternatively, silicon oxide or high-k dielectrics (k>7) such as Al2O3 (κ is about 10), Ta2O5 (κ is about 25) and HfO2 (κ is about 22), ZrO2 (κ is about 35) and others can be deposited by ALD (atomic layer deposition).

[0058] Figure 3G A second chemical mechanical polish (CMP) of structure 300 is shown. The second CMP may be performed to remove portions of insulator layer 320 outside of barrel 310 and expose interconnects 324 in the interconnect structure. The second CMP may be performed with a much lower polishing pressure to flatten the wafer with reduced dishing, thereby leaving the insulator layer 320 in barrel lip 309 intact. Due to the erosion discussed above with respect to the first CMP, the second CMP successfully polishes away the insulator layer 320 from the rest of the integrated circuit structure without damaging the insulator layer 320 in barrel lip 309. The difference between the first CMP and the second CMP is primarily the down force (polishing pressure) used. The first CMP process may use a high down force (HDF or high pressure) and a pattern of trenches 311 to intentionally create dishing and erosion. For the first CMP process, the polishing pressure may be 3 psi to 5 psi (pounds per square inch) or higher. The second CMP process may use a low down force (LDF or low pressure) to flatten the surface. The polishing pressure of the second CMP process may be 1 psi to 2 psi or lower. The selectivity of the polishing slurry used for the first CMP and the second CMP can also be different. The first CMP process can use a high selectivity polishing slurry that polishes metal at a much higher rate than oxide. The second CMP process can use a low selectivity polishing slurry that polishes metal at a similar rate to dielectrics (insulator layer 320 and dielectric layer 306).

[0059] The sidewall portion 314B of the 3D bottom electrode 314 is shortened by dishing / erosion performed by the first CMP (see Figure 3E ), so the height 362 of the three-dimensional bottom electrode 314 (see Fig. 3I ) is lower than the rest of the integrated circuit structure 300. This allows the insulator layer 320 to be removed from the dielectric layer 306 in the interconnect structure during the second CMP (see Figure 3G ), without polishing away the insulator layer 320 from the barrel lip 309 in the 3D MIM module. Because the three-dimensional bottom electrode 314 is shorter, there is no need to mask the insulator layer 320 in the 3D MIM module during the removal of the insulator layer 320 from the interconnect structure.

[0060] like Figure 3HAs shown, an Mx+1 metal layer 346 may be formed on the wafer. The Mx+1 metal layer 346 may be part of a CMOS interconnect fabric. The Mx+1 metal layer 346 (e.g., aluminum) may be deposited so as to extend into the remaining unfilled portions of the barrel 310 and the trench 311 to cover the insulator layer 320.

[0061] Finally, if Fig. 3I As shown, the Mx+1 metal layer 346 can be patterned and etched to define the Mx+1 layer pad 334 and the top electrode 330 extending downward into the barrel 310, thereby forming the 3D MIM capacitor 304. The three-dimensional bottom electrode 314 has a height 362 less than the height 360 of the through hole 324, wherein the corresponding heights 360, 362 are defined from a common plane at the top surface of the Mx metal layer 302. The optional bottom side pad 336 can also be patterned and etched to be conductively connected to the second interconnect structure 302B through the metal layer 346 filling the trench 311. As shown, when the first structure 302A is adjacent to (i.e., electrically coupled to) the second structure 302B (e.g., copper) forming a portion of the bottom electrode 301, the second structure 302B can be conductively connected to the top side pad 334 through at least one through hole 324. Thus, the top electrode 330 is formed in the Mx+1 metal layer. Fig. 3I Metal patterning and etching as commonly used is shown, which can be part of a CMOS interconnect construction. A slight over-etching can allow etching through the insulator layer 320 in the area between the barrel 310 and the trench 311 to avoid short circuits. As shown, the MIM capacitor 304 is complete and ready for the structure 300 to continue with additional CMOS interconnect construction (if any).

[0062] like Figure 4 As shown, in another example, a MIM capacitor can be constructed between the silicided polysilicon and the metal layer M1. Figure 4The illustrated example 3D MIM capacitor 400 may have a bottom electrode 401 made of a conformal metal (e.g., tungsten) and may be substantially hillock-free. The example 3D MIM capacitor 400 may have a polysilicon layer 454 and a polycide layer 452. A 3D bottom electrode 414 may be formed in a barrel 410 formed in a polysilicon metal dielectric (PMD) layer 406. The three-dimensional bottom electrode 414 has a height 462 less than a height 460 of a contact 425, wherein respective heights 460, 462 are defined from a common plane at a top surface of the polycide layer 452. The 3D bottom electrode 414 may be formed of a conformal metal such as tungsten (W) or other suitable material, for example, formed of the same material and formed simultaneously with the contact 425. The 3D bottom electrode 414 is electrically coupled to the polycide layer 452. The insulator layer 420 may be a conformal layer formed of SiN or other suitable dielectric material. The top electrode 430 is formed above the insulator layer 420. In examples where the various polysilicon layers 454 are formed or connected continuously, the bottom electrode 401 (polysilicon layer 454, polycide 452, and 3D bottom electrode 414) may also be conductively connected to the top side bonding pad 434, for example, by connecting the metal-1 layer pad 434 to at least one contact 425 of the polycide 452. The conformal metal cup in the trench 411 may also optionally be used to form a trench connection 422, which provides an optional additional electrode connection to the polycide layer 452 in addition to the contact 425 and may be electrically coupled to an optional bottom side connection pad 436. Chemical mechanical polishing (CMP) may produce a 3D MIM capacitor with a three-dimensional bottom electrode 414 having a height 462 less than the height 460 of the contact 425. By varying the CMP parameters, the desired capacitor height may be obtained. More or less of the dielectric layer 406 at the barrel lip 409 may be removed. For example, the CMP parameters may be adjusted to remove approximately 100% of the dielectric layer 406 at the bucket lip 409 by erosion. The difference between the height 462 of the 3D bottom electrode 414 and the height of the contact 425 is between about 0.1 μm and about 0.5 μm. Figure 4 As illustrated, the height of the contact 425 is the same as the height of the trench connection 422 .

[0063] like Figure 5 As shown, Preston's equation can account for the use of trenches 311 to engineer local pattern density variations to achieve desired dishing and erosion from a CMP process. The removal rate of chemical mechanical polishing (CMP) can be proportional to the down force and velocity.

[0064] RR=K P *P*V

[0065] in

[0066] RR = Removal Rate

[0067] K P = Preston coefficient

[0068] P = applied pressure

[0069] V = Linear speed

[0070] FIG. 6A to FIG. 6C The implications of Preston's equation are shown, where the local removal rate can depend on the local pattern density. By designing the local pattern density, the desired amount of dishing and erosion at the cup lip can be achieved. Differences in pattern density can result in differences in polishing rates to produce different dishing and erosion. Fig. 6A A wafer with a 10% pattern density (P 实际 =10*P 施加 ). The removal rate at 10% pattern density may be equal to ten times the blanket removal rate because the actual applied pressure is 10 times the applied pressure since it is ultimately applied to only 1 v% of the wafer surface area, but the total material removed may be similar. Figure 6B A wafer with 50% pattern density (P 实际 =2*P 施加 ). The removal rate at 50% pattern density may be twice the unpatterned removal rate, but the total material removed may be similar. Figure 6C The wafer without pattern (P 实际 =P 施加 ), so that the wafer has been flattened.

[0071] Figure 7 A method for constructing a 3D MIM capacitor is shown. A dielectric layer is deposited and etched 702 to form via holes, barrels, and trenches. Figure 3A . Deposit 704 conformal metal to form the vias and coat the walls and bottom of the barrel and the trenches. Figure 3D . Remove 706 some conformal metal from the lip of the barrel. See Figure 3E An insulator layer is deposited 708 over the vias and in the conformal metal coated barrels and trenches. Figure 3F . Remove the insulator layer above the 710 via. See Figure 3G . Top electrode metal is deposited 712 on the insulator layer in the barrel and trench. See Figure 3H The top electrode metal is patterned and etched 714 in the area between the barrel and the trench. Fig. 3I .

[0072] Figure 8A method for building a 3D MIM capacitor is shown. A dielectric layer is etched 802 to form a via hole or contact hole, a barrel, and a trench. Conformal metal is deposited 804 in the via hole or contact hole, the barrel, and the trench to form a three-dimensional conductor. The conformal metal is removed 806 from the lip of the barrel. An insulator layer is deposited 808 on the three-dimensional electrode. A metal layer is deposited 810 on the insulator layer to form a top electrode of the MIM capacitor.

[0073] Although examples have been described above, other modifications and examples may be made in accordance with this disclosure without departing from the spirit and scope of these disclosed examples.

Claims

1. A method, comprising: etching a dielectric layer to form via holes or contact holes, barrels, and trenches in the dielectric layer; depositing conformal metal in the via cavity or the contact cavity, the bucket, and the trench, wherein the deposited conformal metal forms a bottom portion and sidewall portions of a three-dimensional bottom electrode of a metal-insulator-metal (MIM) capacitor in the bucket, and wherein the deposited conformal metal forms a via or a contact in the via cavity or the contact cavity; removing at least a portion of the dielectric layer and conformal metal from a lip of the bucket; depositing an insulator layer on the three-dimensional bottom electrode to form an insulator layer of the MIM capacitor; as well as A metal layer is deposited on the insulator layer to form a top electrode of the MIM capacitor. 2 . The method of claim 1 , comprising depositing the dielectric layer on an Mx metal layer. 3 . The method of claim 1 , comprising depositing the dielectric layer on a polycide layer.

4. The method of claim 1, 2 or 3, wherein removing at least the portion of the dielectric layer and conformal metal from the lip of the bucket comprises removing at least the portion of the dielectric layer and conformal metal from the trench.

5. The method of claim 1, 2 or 3, wherein removing at least the portion of the dielectric layer and conformal metal from the lip of the bucket comprises chemical mechanical polishing.

6. The method of claim 1, 2 or 3, wherein removing at least the portion of the dielectric layer and conformal metal from the lip of the bucket comprises chemical mechanical polishing using a downward force and a selective polishing liquid.

7. The method of claim 1, 2 or 3, wherein depositing an upper metal layer comprises depositing the upper metal layer on an interconnect structure.

8. The method of claim 1, 2 or 3, comprising etching a pattern in the upper metal layer to form a top side metal pad electrically coupled to the three-dimensional bottom electrode through the via or the contact, and forming the top electrode.

9. A device, comprising: A three-dimensional metal-insulator-metal (MIM) capacitor, the three-dimensional metal-insulator-metal (MIM) capacitor comprising: Three-dimensional bottom electrode; a top electrode; and an insulator layer, the insulator layer being located between the top electrode and the three-dimensional bottom electrode; An Mx metal layer or a silicided polysilicon layer, wherein the Mx metal layer or the silicided polysilicon layer is electrically connected to the three-dimensional bottom electrode; An Mx+1 metal layer or an M1 metal layer, wherein the Mx+1 metal layer or the M1 metal layer includes the top electrode; a metal pad, wherein the metal pad is electrically connected to the Mx metal layer or the silicided polysilicon layer through a through hole or a contact, The height of the three-dimensional bottom electrode is smaller than the height of the through hole or the contact. 10 . The device of claim 9 , wherein the Mx metal layer or the silicided polysilicon layer comprises a metal. 11 . The device according to claim 9 , wherein the Mx metal layer or the silicided polysilicon layer comprises a silicided polysilicon layer.

12. The device of claim 9, 10 or 11, wherein the difference between the height of the three-dimensional bottom electrode and the height of the via or the contact is between about 0.1 μm and about 0.5 μm.

13. The device of claim 9, 10 or 11, wherein the insulator layer has a substantially uniform thickness between the three-dimensional bottom electrode and the top electrode.

14. The device of claim 9, 10 or 11 comprising a trench in a dielectric layer surrounding the perimeter of the three-dimensional MIM capacitor.

15. The device of claim 14, comprising a portion of a dielectric layer between the trench and the three-dimensional MIM capacitor.

16. The device of claim 15, wherein the portion of the dielectric layer extends completely around a perimeter of the three-dimensional MIM capacitor, and wherein the trench extends completely around a perimeter of the portion of the dielectric layer.

17. The device of claim 9, 10 or 11, wherein the three-dimensional bottom electrode comprises tungsten.

18. The device of claim 9, 10 or 11, wherein the via or the contact comprises tungsten.

19. A device, comprising: A three-dimensional metal-insulator-metal (MIM) capacitor, the three-dimensional metal-insulator-metal (MIM) capacitor comprising: Three-dimensional bottom electrode; a top electrode; and an insulator layer, the insulator layer being located between the top electrode and the three-dimensional bottom electrode; An Mx metal layer or a silicided polysilicon layer, wherein the Mx metal layer or the silicided polysilicon layer is electrically connected to the three-dimensional bottom electrode; An Mx+1 metal layer or an M1 metal layer, wherein the Mx+1 metal layer or the M1 metal layer includes the top electrode; and a metal pad, wherein the metal pad is electrically connected to the Mx metal layer or the silicided polysilicon layer through a trench connection, The height of the three-dimensional bottom electrode is smaller than the height of the trench connection.

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