Inductive drain and / or body step in RF switch stacks

Abstract

Methods and devices are disclosed for reducing gate induced drain / body leakage current (GIDL) generated when a FET switch stack is in an off state. Such a device includes an inductor coupled as part of a bias network with a drain / source terminal and / or a body terminal of a transistor within a switching stack. A hybrid method of implementing a combination of resistors and inductors as part of a bias network is also described.

Description

[0001] CROSS-REFERENCE TO RELATED APPLICATIONS

[0002] This application claims priority to U.S. patent application No. 17 / 807,663, filed on June 17, 2022, the contents of which are incorporated herein by reference in their entirety. background (1) Technical field

[0004] The present disclosure relates to radio frequency (RF) switches and, more particularly, to methods and devices for overcoming the undesirable effects of body leakage current in field effect transistor (FET) switches by providing inductive drain and / or body ladders in an RF switch stack. (2) Background technology

[0005] As part of the receiver front-end design, RF switches are typically implemented in a stacked configuration due to the large RF power handling requirements of such switch stacks. FIG. 1A shows a prior art field effect transistor (FET) switch stack (100) comprising a series arrangement of transistors (T1, ..., Tn). The FET switch stack (100) implements a bias network, as shown, comprising a body resistor ladder (120), a drain-source resistor ladder (110), and a gate resistor structure on the gate side of the transistor, the body resistor ladder (120) comprising body resistors (RB1, ..., RBn+1), and the drain-source resistor ladder (110) comprising drain-source resistors (RD1, ..., RDn). Bias voltages (VB, VG) are applied to the gate side and the body side to bias the switch stack (100). The FET switch stack (100) is connected at one end to a node (N1) to which an RF signal is applied, and at the other end to a node (N2), which may be ground, a reference voltage, or the rest of the RF circuit based on a possible shunt or series implementation of the FET switch stack (100).

[0006] Under operating conditions, when the stacked switches experience RF swings during the off state, each transistor within the stack will generate an undesirable gate-induced drain / body leakage current (GIDL) that increases as the RF swing peak increases. As shown in FIG. 1A , the GIDL current flows through the drain-source resistor ladder (110) in the direction of arrow (101) and flows through the body resistor ladder (120) in the direction of arrow (102). Due to the flow of the undesirable GIDL current, the effective DC voltage distribution across the body resistor ladder is modified. In other words, various switch stack nodes within the body resistor ladder and the drain-source ladder will experience an undesirable DC bias voltage that is different from the DC bias voltage that the bias circuit would provide to such nodes in the absence of such leakage current. Throughout the disclosure, the undesirable effect of the GIDL current on the DC bias voltage distribution of the entire stack may be referred to as a "de-biasing" effect.

[0007] The de-biasing effect is further illustrated by the curves (103, 104) of FIG. 1B and FIG. 1C, respectively. Curve (103) represents an exemplary DC average voltage distribution of the drain terminals of transistors (T1, ..., Tn) of the switch stack (100) of FIG. 1A, which is drawn from the position of the transistors in the reference stack from the top (Tn) to the bottom (T1), while curve (104) represents the DC average distribution of the body terminals of such transistors compared to the position of the transistors in the stack from the top (Tn) to the bottom (T1). In this example, the switch stack (100) of FIG. 1A includes nine transistors, i.e., there are nine points on each of the curves (103, 104). Referring to FIG. 1B, the DC voltage at the drain terminal of the transistor in the middle of the stack reaches its minimum value, i.e., the de-biasing effect is more severe in the middle of the stack. On the other hand, the DC voltage at the body terminal of the FET decreases from the top to the bottom of the stack, as shown in FIG. 1C. In other words, due to the unbalanced voltage distribution caused by the undesired GIDL current, the voltage at the bulk terminal of the transistor (Tn) has the highest magnitude, and the voltage at the bulk terminal of the transistor (T1) has the lowest magnitude.

[0008] Body de-biasing as described above may result in early breakdown of transistors within a FET switch stack, especially for transistors disposed closer to the top of the stack. Summary of the invention

[0009] The disclosed method and device solve the above-mentioned problems.

[0010] According to a first aspect of the present disclosure, a switch stack is provided, comprising: a plurality of field effect transistors (FETs) arranged in series and connected to a first node at one end and to a second node at the other end; a drain bias ladder comprising one or more drain inductors coupled across drain terminals and source terminals of corresponding one or more first FETs among the plurality of FETs.

[0011] According to a second aspect of the present disclosure, a switch stack is provided, comprising: a plurality of field effect transistors (FETs) arranged in series and connected to a first node at one end and to a second node at the other end; and a body bias ladder comprising one or more individual inductors, wherein each of the one or more individual inductors is coupled across body terminals of a corresponding pair of first adjacent FETs.

[0012] According to a third aspect of the present disclosure, a method for balancing the drain voltage or body voltage in a switch stack is disclosed, wherein the switch stack includes a plurality of field effect transistors (FETs) connected in series and in an off state, each FET including a drain terminal and a source terminal, the method including: inductively coupling the drain terminal and the source terminal of at least one FET together to reduce drain de-biasing.

[0013] Further aspects of the disclosure are provided in the description, drawings and claims of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0014] FIG. 1A shows a prior art FET switch stack.

[0015] FIG. 1B shows a prior art graph representing the drain DC voltage distribution at the drain terminal of a FET within a switch stack versus the position of the FET in the stack.

[0016] FIG. 1C shows a prior art graph representing the bulk DC voltage distribution at the bulk terminals of FETs within a switch stack versus the position of the FETs in the stack.

[0017] Figure 2A An exemplary FET switch stack according to an embodiment of the present disclosure is shown.

[0018] Figure 2B An exemplary graph showing drain DC voltage distribution at the drain terminal of a FET within a switch stack versus the position of the FET in the stack is shown according to an embodiment of the present disclosure.

[0019] Figure 2CAn exemplary graph showing the bulk DC voltage distribution of the bulk terminals of FETs within a switch stack versus the position of the FETs in the stack is shown in accordance with an embodiment of the present disclosure.

[0020] FIG. 2D to FIG. 2I An exemplary FET switch stack according to an embodiment of the present disclosure is shown.

[0021] Figure 2J to Figure 2K An exemplary graph illustrating DC voltage distribution in a FET switch stack is shown in accordance with an embodiment of the present disclosure.

[0022] FIG. 3A to FIG. 3C An exemplary FET switch stack according to an embodiment of the present disclosure is shown.

[0023] Figure 4A An exemplary schematic diagram of a switch stack in an off state is shown according to an embodiment of the present disclosure.

[0024] Figure 4B An exemplary graph illustrating compensation of off capacitance of transistors of a switch stack according to an embodiment of the present disclosure is shown.

[0025] Figure 4C An exemplary schematic diagram of a switch stack in an off state is shown according to an embodiment of the present disclosure.

[0026] Figure 4D An exemplary graph illustrating compensation of off capacitance of transistors of a switch stack according to an embodiment of the present disclosure is shown.

[0027] Like reference numbers and designations in the various drawings indicate like elements. DETAILED DESCRIPTION

[0028] Referring to FIG. 1A , under operating conditions where the FET switch stack (100) is in the off state, a GIDL current including an RF (AC) component and a DC component will be generated due to the application of an RF voltage to the node (N1). The reason for the presence of a DC component in this current is that during a positive RF cycle, the GIDL current flows from the drain terminal to the source terminal of each transistor in the stack, and during a negative RF cycle, this current flows from the source terminal to the body terminal of each transistor. In other words, regardless of the RF cycle, the generated GIDL current always flows out of the body terminal of such a transistor. This means that the GIDL current will include a DC component, which is the cause of the above-mentioned de-biasing problem. According to the teachings of the present disclosure, a bias circuit that is as close to a short circuit as possible for DC and as close to an open circuit as possible for AC components will help overcome the de-biasing problem by reducing the undesirable effects of the DC component of the GIDL current. In other words, a bias network including an inductive element can be a solution to the de-biasing problem as described above. In the following, various embodiments that implement this teaching will be described in detail.

[0029] Figure 2A An exemplary FET switch stack (200A) according to an embodiment of the present disclosure is shown. As shown, the FET switch stack (200A) includes a series arrangement of transistors (T1, ..., Tn) and implements a bias network, which includes a body bias ladder (220A), a drain-source bias ladder (210A), and a gate resistor structure on the gate side of the transistor, the body bias ladder (220A) includes a body inductor (LB1, ..., LBn+1) and a series capacitor (CB1, CB2), and the drain-source bias ladder (210A) includes a drain-source inductor (LD1, ..., LDn). Bias voltages (VB, VG) are applied to the gate side and the body side to bias the switch stack (200A). The FET switch stack (200A) is connected at one end to a node (N1) to which an RF signal is applied, and at the other end to a node (N2), which may be ground, a reference voltage, or the rest of the RF circuit depending on a possible series or shunt implementation of the FET switch stack (200A).

[0030] The bias ladder (210A, 220A) includes an inductor which will act as a short circuit and an open circuit for the above-mentioned DC component and AC component, thereby reducing the negative impact of the GIDL current as previously described. To further demonstrate this, refer to Figure 2B to Figure 2C , Figure 2B to Figure 2C Compared with the resistor bias ladder shown in Figure 1A, Figure 2A The effect of an inductor bias ladder is shown. Figure 2B The curve (103) of is a reproduction of the curve (103) of Figure 1A and is shown for comparison purposes. Figure 2B The curve (203B) shows Figure 2A The DC average voltage distribution at the drain terminals of the transistors of the switch stack (200A) of FIG. 1 is also plotted with reference to the positions of the transistors in the stack. It can be noted that by implementing an inductor in the drain bias ladder (210A) instead of a resistor implemented in the drain resistor ladder (110) of FIG. 1A , the de-biasing of the drain terminal is significantly reduced. Similarly, referring now to Figure 2C , curve (204C) shows Figure 2A The DC average voltage distribution of the body terminals of the transistors of the switch stack (200A) of FIG. 1A is compared to the position of the transistors within the stack. Likewise, the de-biasing problem on the body terminals is significantly reduced compared to curve (104), a reproduction of curve (104) of FIG. 1C, which shows the body DC voltage distribution in the case of the switch stack (100) of FIG. 1A. According to an embodiment of the present disclosure, the inductor value of one or more of the inductors within the drain-source bias ladder (210A) is selected to resonate with the off capacitance of the corresponding one or more transistors of the switch stack within the operating frequency band.

[0031] Return to reference Figure 2A , some embodiments may not implement one or both of the series capacitors (CB1, CB2). Furthermore, the number of inductors implemented in any of the bias ladders (210A, 220A) may be any number greater than or equal to 1. To demonstrate this, refer to Figure 2D ,exist Figure 2D In the implementation with (with Figure 2A In addition, in implementing Figure 2D When implementing the method, do not use Figure 2A Capacitors (CB1, CB2) are provided. In some embodiments, capacitors (CB1, CB2) are used to provide a way to connect the RF voltage swing of the input signal to the bias ladder. In the absence of these capacitors, extreme voltages and uneven voltages and currents may occur due to the RF voltage difference between the switch stack drain / source voltage level and the DC level of the bias ladder.

[0032] Reference Figure 2A and Figure 2DAccording to the teachings of the present disclosure, instead of providing a one-to-one correspondence between inductors and FET transistors, some of the inductors within the drain-source bias ladder (210A, 210D) may be replaced by resistors or removed (e.g., there is no inductor across one or more of the FET transistors). In addition, some of the inductors within the body bias ladder (220A, 220D) may be replaced by resistors or short-circuited. In other words, the bias ladder (210A, 210D, 220A, 220D) may be designed using a hybrid approach in which one or more series-connected resistors and one or more series-connected inductors are implemented and arranged sequentially. The number of inductors used in this arrangement is also any number greater than or equal to 1. When designing the bias ladder, no resistors or any number of resistors (in addition to at least one inductor) may be used.

[0033] As is known in the art of RF design, implementing on-chip inductors for higher frequencies is a challenging task due to the inherently large size of such inductors. Therefore, the above-described implementation using a combination of resistors and inductors within the bias ladder will help reduce the actual footprint on the chip. However, since a smaller number of inductors are used, the amount of de-biasing may be compromised in this implementation. At the same time, by using resistors as part of the bias network in addition to the inductors, the design can ensure that the overall off resistance (Roff) requirements of the switch stack are met. In other words, the number of resistors and inductors used within the bias ladder is a trade-off between the footprint on the chip, the amount of de-biasing reduction, and the Roff resistance of the switch stack. Figure 2E An exemplary switch stack (200E) demonstrating the above teachings is shown, wherein a hybrid approach is employed in implementing the bias ladder. In other words, the drain-source bias ladder (210E) includes an inductor (LD) combined with resistors (RD1, ..., RDn-1). In addition, the body bias ladder (220E) includes a series arrangement of inductors (LB1, LB2) and resistors (RB1, ..., RBj+1). As previously described, the most severe drain de-biasing occurs in the middle of the stack, while the top of the stack is where the body de-biasing is most pronounced. Continued with reference to Figure 2E In the exemplary embodiment of FIG. 1 , it can be noted that the inductor (LD) is placed in the middle of the switch stack and coupled across the middle transistor (Tj) to counteract the maximum drain de-biasing. Similarly, the two inductors (LB1, LB2) are implemented towards the top of the stack to reduce the effects of the most severe body de-biasing. Figure 2E In a preferred embodiment, a resistor can be connected in parallel across the transistor (Tj) and the inductor (LD) to achieve ( Figure 2E). The presence of such a resistor will help maintain a frequency-independent impedance across the transistor (Tj). This feature will be described in more detail later by describing another embodiment of the present disclosure.

[0034] In other embodiments, any number of inductors (and resistors, in addition to at least one inductor) may be implemented within the bias ladder (210E, 220E) depending on requirements and applications. Furthermore, the location of such inductors (and resistors) may also vary from one embodiment to another, again depending on the application and design requirements.

[0035] To further clarify the teachings of the above disclosure, and to reiterate the design flexibility provided by the teachings according to the present disclosure, reference is now made to Figure 2F , Figure 2F A FET switch stack (200F) is shown including a drain bias ladder (210F) implemented using a series arrangement consisting of only resistors, while only inductors are used in implementing the body bias ladder (220F). Figure 2G Another exemplary FET switch stack (200G) is shown in accordance with an embodiment of the present disclosure, wherein each bias ladder (210G, 220G) is implemented using a series of alternating resistors and inductors arranged in series.

[0036] Figure 2H Another exemplary FET switch stack (200H) according to an embodiment of the present disclosure is shown. The structure and function of the FET switch stack (200H) are similar to those of the Figure 2A The structure and function of the FET switch stack (200A) described above are described, except that instead of direct connection, the body terminals of the transistors (T1, ..., Tn) are coupled to the corresponding inductors (LB1, ..., LBn) within the body bias ladder (220H) through corresponding "ladder" resistors (R1, ..., Rn). In addition, the drain terminals of the transistors (T1, ..., Tn-1) are coupled to the corresponding inductors (LD1, ..., LDn-1) within the body bias ladder (210H) through corresponding "ladder" resistors (R1', ..., Rn-1'). This coupling can be used in FIG. 2D to FIG. 2I In all the embodiments shown, and even more design flexibility is provided in terms of the desired setting of the DC bias point of the transistor, while also meeting the overall RF performance requirements of the switch stack. The number and position of the ladder resistors within each of the ladders (210H, 220H) are arbitrary and can be selected based on the application and related requirements.

[0037] Fig.2IThe FET switch stack (200I) shows another method of designing the bias ladder within the disclosed FET switch stack. As can be seen in this embodiment, the body terminals of one or more adjacent FET pairs are connected together. This method reduces the effective number of inductors implemented to save space on the chip.

[0038] Combination reference as mentioned above Figure 2A and for example Figure 2G , the hybrid approach of using a combination of inductors and resistors in the construction of the body bias ladder and / or drain bias ladder is a trade-off between i) reducing the footprint on the chip, ii) reducing the de-biasing effect, and iii) meeting the switch stack Roff requirement. To illustrate this trade-off, refer to Figure 2J ,in:

[0039] Curve (103) is shown here for comparison purposes Figure 2B 1A , and shows the drain DC voltage distribution of the exemplary prior art switch stack of FIG. 1A versus the transistor position within the stack,

[0040] Curve (203J) shows the above Figure 2A The distribution of the implementation method is the same as the distribution,

[0041] Curve (205J) shows the above Figure 2G It can be noted that the application of the disclosed teachings significantly reduces the drain de-biasing. Furthermore, the greater the number of inductors used as part of the drain bias ladder, the greater the effect of compensating for the negative effects of de-biasing.

[0042] Now refer to Figure 2K :

[0043] Curve (104) is shown here for comparison purposes Figure 2C 1A and shows the bulk DC voltage distribution of the exemplary prior art switch stack of FIG. 1A versus the transistor position within the stack,

[0044] · Curve (204K) represents the above Figure 2A The distribution of the implementation method is the same as the distribution,

[0045] · Curve (205K) shows the same as above Figure 2G It can be noted that the application of the disclosed teachings significantly reduces the body de-biasing. In addition, the greater the number of inductors used as part of the body bias ladder, the greater the compensation for the negative effects of de-biasing.

[0046] The disclosed teachings can be applied to RF switches that operate across a wide frequency range. As the frequency increases, the physical space required to create the same inductive impedance decreases. Implementations in the millimeter wave region of 30 GHz to 300 GHz can be more easily adopted. Figure 2A architecture, while lower frequencies will likely benefit from a hybrid implementation. Figure 2A as well as FIG. 2D to FIG. 2I The disclosed FET switch stack can be implemented in a shunt configuration, in which node (N2) is ground or a reference voltage. Such a FET switch can also be implemented in a series configuration, in which the FET switch stack is connected at node (N2) to the rest of the RF circuit including other RF nodes.

[0047] Those skilled in the art will appreciate that the above-described embodiments represent some exemplary implementations of the disclosed teachings and that other different implementations may also be contemplated. Figure 3A An exemplary FET switch stack (300A) according to an embodiment of the present disclosure is shown. Figure 2A Similar to the embodiment of , as shown, the FET switch stack (300A) includes a series arrangement of transistors (T1, ..., Tn) and implements a bias network including a drain-source bias ladder (310A) and a gate resistor structure on the gate side of the transistor, the drain-source bias ladder (310A) including a drain-source inductor (LD1, ..., LDn). In addition, Figure 2A In different embodiments, the FET switch stack (300A) further includes a drain-source resistance ladder (330A), and the drain-source resistance ladder (330A) includes drain-source resistors (RD1, ..., RDn). Figure 3A The configuration shown provides a way to present a uniform impedance across the drain-source terminals of the transistors (T1, ..., Tn) that is independent of frequency. In other words, this configuration effectively separates low-frequency behavior from high-frequency RF behavior by dedicating inductors to low frequencies and resistors to high frequencies. In another embodiment, a body bias ladder, such as Figure 2A The body step bias (220A) can also be realized as Figure 3A supplement to the implementation method.

[0048] Figure 3B Another exemplary FET switch stack (300B) according to an embodiment of the present disclosure is shown. The operating principle of the FET switch stack (300B) is similar to that of Figure 3AThe FET switch stack (300A) describes the principle of operation, except that instead of having a separate inductor connected across each individual transistor (T1, T2), the inductor (LDS12) is implemented in a series arrangement across the transistors (T1, T2). This will save space on the chip while benefiting from the presence of the inductor (LDS12).

[0049] Figure 3C Yet another exemplary FET switch stack (300C) according to an embodiment of the present disclosure is shown. As shown, in this embodiment, for example, there is no inductor across the transistors (T1, T2) to save more space, while still benefiting from the presence of the drain-source bias ladder (310C).

[0050] According to the teachings of the present disclosure, adding an inductive drain-source bias ladder as described above can also provide the benefit of detuning and compensating the off capacitance (Coff) of the transistors of the switch stack in the off state. To further illustrate this point, refer to Figure 4A , Figure 4A An exemplary schematic diagram (400A) of a switch stack in an off state is shown, wherein the transistors are each represented by their respective off capacitance (Coff1, ..., Coff7). Figure 4A Also shown are an inductive bias ladder (410A) and a resistive bias ladder (430A), respectively. Figure 4B A graph (400B) is shown which illustrates the detuning (compensation) of the off capacitance (Coff) of the transistors of the switch stack. FIG. 4A to FIG. 4B , Figure 4B The curve (451B) shows that when Figure 4A 4. The variation of the magnitude of the impedance (Zshunt) between nodes (N1, N2) with respect to frequency when the inductive bias ladder (410A) is not present, as seen. On the other hand, curve (452B) shows the variation of the magnitude of the impedance (Zshunt) with respect to frequency for a specific inductance value (e.g., 2nH) of the inductor within the inductive bias ladder (410A). It can be noted that the off-capacitive behavior of the switch stack is detuned at frequency (F1).

[0051] Figure 4C An exemplary schematic diagram (400C) is shown, which is similar to Figure 4A Schematic diagram (400A), except the inductors (L2, L4, L6) are removed to save on-chip space. Similar to Figure 4B , Figure 4D A graph (400D) is shown which shows that by implementing the inductors (L1, L3, L5, L7) Figure 4CThe detuning (compensation) of the off capacitance of the transistors in the stack. Curves (451D, 452D) are respectively Figure 4B It can be noted that the off capacitance behavior of the switch stack is detuned at frequency (F2).

[0052] As used in this disclosure, the term "MOSFET" includes any field effect transistor (FET) having an insulated gate whose voltage determines the conductivity of the transistor, and includes insulated gates having metal or metalloid, insulator and / or semiconductor structures. The terms "metal" or "metalloid" include at least one conductive material (e.g., aluminum, copper or other metal or highly doped polysilicon, graphene or other electrical conductors), "insulator" includes at least one insulating material (e.g., silicon oxide or other dielectric material), and "semiconductor" includes at least one semiconductor material.

[0053] As used in this disclosure, the term "radio frequency" (RF) refers to oscillation rates in the range of about 3 kHz to about 300 GHz. The term also includes frequencies used in wireless communication systems. RF frequencies can be the frequency of electromagnetic waves or the frequency of an alternating voltage or current in an electrical circuit.

[0054] With respect to the drawings cited in this disclosure, the sizes of the various elements are not to scale; some dimensions are greatly exaggerated in the vertical and / or horizontal directions for clarity or emphasis. In addition, references to orientations and directions (e.g., "top," "bottom," "above," "below," "lateral," "vertical," "horizontal," etc.) are relative to the exemplary drawings and are not necessarily absolute orientations or directions.

[0055] Various embodiments of the present invention can be implemented to meet various specifications. Unless otherwise specified above, selecting appropriate component values ​​is a matter of design choice. Various embodiments of the present invention can be implemented in any suitable integrated circuit (IC) technology (including but not limited to MOSFET structure) or hybrid or discrete circuit form. Any suitable substrate and process (including but not limited to standard bulk silicon, high resistivity bulk CMOS, silicon on insulator (SOI) and silicon on sapphire (SOS)) can be used to manufacture integrated circuit embodiments. Unless otherwise specified above, embodiments of the present invention can be implemented in other transistor technologies, such as bipolar transistors, BiCMOS, LDMOS, BCD, GaAs HBT, GaN HEMT, GaAspHEMT and MESFET technology. However, embodiments of the present invention are particularly useful when using SOI or SOS-based process manufacturing or when using processes with similar characteristics. The manufacture of SOI or SOS processes in CMOS enables circuits to have low power consumption, the ability to withstand high power signals during operation due to FET stacking, good linearity, and high frequency operation (i.e., up to and exceeding 300GHz radio frequency). Monolithic IC implementations are particularly useful because, through careful design, parasitic capacitances can generally be kept low (or at least consistent across all units, allowing them to be compensated for).

[0056] Voltage levels may be adjusted, and / or voltage and / or logic signal polarity may be reversed, depending on the particular specification and / or implementation technology (e.g., NMOS, PMOS, or CMOS, and enhancement mode or depletion mode transistor devices). Component voltage, current, and power handling capabilities may be adjusted as needed, such as by adjusting device size, "stacking" components (particularly FETs) in series to withstand higher voltages, and / or using multiple components in parallel to handle higher currents. Additional circuit components may be added to enhance the capabilities of the disclosed circuits and / or to provide additional functionality without significantly changing the functionality of the disclosed circuits.

[0057] Circuits and devices according to the present invention can be used alone or in combination with other components, circuits and devices. Embodiments of the present invention can be manufactured as integrated circuits (ICs), which can be packaged in IC packages and / or modules for ease of processing, manufacturing and / or improved performance. Specifically, IC embodiments of the present invention are often used in modules, wherein one or more of such ICs are combined into a package with other circuit blocks (e.g., filters, amplifiers, passive components, and possible additional ICs). Then, ICs and / or modules are typically combined with other components typically on a printed circuit board to form a part of a final product (e.g., a cellular phone, a laptop computer, or an electronic tablet), or to form a more advanced module that can be used in a variety of products (e.g., vehicles, test equipment, medical devices, etc.). Through various configurations of modules and components, such ICs are typically capable of implementing a communication mode, typically wireless communication.

[0058] A number of embodiments of the present invention have been described. It should be understood that various modifications may be made without departing from the spirit and scope of the present invention. For example, some of the above steps may be order-independent and thus may be performed in an order different from that described. In addition, some of the above steps may be optional. The various activities described with respect to the methods identified above may be performed in a repetitive, serial, and / or parallel manner.

[0059] It should be understood that the foregoing description is intended to illustrate, but not to limit, the scope of the invention, which is defined by the scope of the following claims, and that other embodiments are also within the scope of the claims. In particular, the scope of the invention includes any and all feasible combinations of one or more of the processes, machines, manufacture, or components of matter set forth in the following claims. (Note that parenthetical markings of claim elements are for convenience of reference to such elements and do not, by themselves, indicate a particular required order or enumeration of the elements; furthermore, such markings may be repeated in dependent claims as references to additional elements without being considered as starting a conflicting marking sequence).

Claims

1. A switch stack, comprising: a plurality of field effect transistors (FETs) arranged in series and connected at one end to a first node and at another end to a second node; A drain bias ladder includes one or more drain inductors coupled across drain terminals and source terminals of corresponding one or more first FETs of the plurality of FETs.

2. The switch stack according to claim 1 further includes one or more drain resistors connected in series with the one or more drain inductors, and the one or more drain resistors are coupled across the drain terminals and source terminals of corresponding one or more second FETs among the multiple FETs, and the one or more second FETs are different from the one or more first FETs.

3. The switch stack according to claim 1, wherein: The one or more first FETs include a first FET disposed in the middle of the switch stack.

4. The switch stack according to claim 1, wherein: The one or more first FETs include FETs other than a top FET closest to the first node or a bottom FET closest to the second node.

5. The switch stack according to claim 2, wherein: The one or more first FETs or the one or more second FETs include FETs other than a top FET closest to the first node or a bottom FET closest to the second node.

6. A switch stack comprising: a plurality of field effect transistors (FETs) arranged in series and connected at one end to a first node and at another end to a second node; as well as A body bias ladder includes one or more individual inductors, wherein each of the one or more individual inductors is coupled across body terminals of a corresponding pair of first adjacent FETs.

7. The switch stack of claim 6, wherein: The body bias ladder further includes one or more body resistors in series with the one or more body inductors; Each of the one or more body resistors is coupled across body terminals of a corresponding pair of second adjacent FETs, and Any two pairs of adjacent FETs, including one pair from the first adjacent FET and one pair from the second adjacent FET, have at most one common FET.

8. The switch stack of claim 6, wherein: The body terminals of one or more pairs of second adjacent FETs are connected together, and Any two pairs of adjacent FETs, including one pair from the first adjacent FET and one pair from the second adjacent FET, have at most one common FET.

9. The switch stack of claim 1 , further comprising a body bias ladder comprising one or more individual inductors, wherein: Each of the one or more individual inductors is coupled across body terminals of a corresponding pair of first adjacent FETs.

10. The switch stack of claim 1 implemented in a shunt or series configuration.

11. The switch stack of claim 1 , configured to operate in a frequency range of 30 GHz to 300 GHz.

12. The switch stack according to claim 6, wherein: A first end of each of the one or more individual inductors is coupled to a body terminal of a first corresponding FET via a first resistor, and a second end of each of the one or more individual inductors is connected to a body terminal of a second corresponding FET via a second resistor, and wherein the first corresponding FET and the second corresponding FET are adjacent FETs.

13. The switch stack of claim 1, wherein: The one or more drain inductors are coupled across drain terminals and source terminals of corresponding one or more first FETs of the plurality of FETs via respective resistors.

14. The switch stack according to claim 6, wherein: A series combination of a first body inductor and a first series capacitor among the one or more individual inductors is coupled across the first node and a body terminal of a top FET, the top FET being closest to the first node, or a series combination of a second body inductor and a second series capacitor among the one or more individual inductors is coupled across the second node and a body terminal of a bottom FET, the bottom FET being closest to the second node.

15. The switch stack of claim 1, wherein: One or more of the drain inductor values ​​are selected to resonate with the corresponding one or more first FET off capacitances within the operating frequency band.

16. A method of equalizing drain voltage or bulk voltage in a switch stack, the switch stack comprising a plurality of field effect transistors (FETs) connected in series and in an off state, each FET comprising a drain terminal and a source terminal, the method comprising: The drain terminal and the source terminal of at least one FET are inductively coupled together to reduce drain de-biasing.

17. The method according to claim 16, wherein: The inductive coupling comprises: The drain terminal and the source terminal of the at least one FET are coupled together inductively and resistance-free.

18. The method of claim 16, each FET further comprising a body terminal, the method further comprising: The body terminals of at least one pair of adjacent FETs are inductively coupled together.

19. The method according to claim 18, wherein: Inductively coupling the body terminals together comprises: The body terminals of the at least one pair of adjacent FETs are inductively and resistance-lessly coupled together.

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