Solid-state imaging element, imaging apparatus, and method of controlling solid-state imaging element

Abstract

The configuration of the imaging device is simplified, and manual operation is not needed when images are captured. In each pixel, a pre-stage circuit that sequentially generates a predetermined number of pixel signals and a pair of capacitive elements are provided. When the sensing mode is set, the scanning circuit causes the pair of capacitive elements to maintain respective signal levels of a pair of pixel signals among the predetermined number of pixel signals, and when switching from the sensing mode to a normal imaging mode is performed, the scanning circuit causes the pair of capacitive elements to maintain respective signal levels of the pair of pixel signals. The scanning circuit causes the pair of capacitive elements to hold a reset level and a signal level of any one of the predetermined number of pixel signals. When the sensing mode is set, the difference calculation circuit calculates a difference between respective signal levels in the pair of pixel signals. The mode control unit determines whether to perform switching from the sensing mode to the normal imaging mode based on the difference.

Description

Technical Field

[0001] The present technology relates to a solid-state imaging element. Specifically, the present technology relates to a solid-state imaging element that performs automatic imaging, an imaging device, and a method of controlling the solid-state imaging element. Background Art

[0002] Conventionally, an automatic imaging mode that does not require manual operation at the time of imaging is used in life recording cameras, surveillance cameras, etc. For example, an imaging device that recognizes a user's voice command and performs imaging according to the command has been proposed (for example, see Patent Document 1).

[0003] Reference List

[0004] Patent Literature

[0005] Patent Document 1: Japanese Patent Application Publication No. 2019-106694 Summary of the invention

[0006] Problems to be solved by the present invention

[0007] In the above conventional technology, imaging according to a user instruction is realized by performing imaging according to a voice command. However, in the above imaging device, a microphone for inputting voice and a circuit for performing voice recognition are required, and the configuration of the imaging device becomes complicated.

[0008] The present technology has been made in view of such circumstances, and an object thereof is to simplify the configuration of an imaging device that does not require manual operation at the time of imaging.

[0009] Solution to the problem

[0010] The present technology has been made to solve the above-mentioned problems, and its first aspect is a solid-state imaging element including: a pixel including a front-stage circuit and a pair of capacitance elements, the front-stage circuit sequentially generating a predetermined number of pixel signals; a scanning circuit that causes the pair of capacitance elements to maintain the signal level of each of a pair of pixel signals in a predetermined number of pixel signals when a sensing mode is set, and causes the pair of capacitance elements to maintain a reset level and the signal level of any one of the predetermined number of pixel signals when switching from the sensing mode to the normal imaging mode; a differential calculation circuit that calculates the difference between the signal levels of each of the pair of pixel signals when the sensing mode is set; and a mode control section that determines whether to switch from the sensing mode to the normal imaging mode based on the difference, and a control method thereof. This brings about the effect of simplifying the configuration of the solid-state imaging element.

[0011] In addition, in the first aspect, the mode control section may determine whether to switch from the sensing mode to the normal imaging mode based on a comparison result between the absolute value of the difference and a predetermined threshold value, thereby producing an effect of switching the mode according to the presence or absence of movement of the object.

[0012] Furthermore, in the first aspect, the solid-state imaging element may further include a focus control section that detects a focus position of the lens and moves the lens to the focus position, wherein the difference calculation circuit calculates the difference between the signal level before the lens moves to the focus position and the signal level when the lens has moved to the focus position, and when the lens has moved to the focus position, the mode control section determines whether to switch from the sensing mode to the normal imaging mode based on a comparison result between the absolute value of the difference and a predetermined threshold value. This brings about an effect of capturing focused image data.

[0013] In addition, in the first aspect, the front-stage circuit may include: a photoelectric conversion element; a transfer transistor that transfers charge from the photoelectric conversion element to the floating diffusion layer; and a front-stage amplifier transistor that amplifies the voltage of the floating diffusion layer. This brings about an effect of reading out a signal obtained by amplifying the voltage of the floating diffusion layer.

[0014] Furthermore, in the first aspect, when the sensing mode is set, the scanning circuit causes one of the pair of capacitive elements to maintain the first signal level at the end of odd-numbered exposure and causes the other of the pair of capacitive elements to maintain the second signal level at the end of even-numbered exposure, and when switching to the normal imaging mode, causes the pair of capacitive elements to maintain the reset level and the signal level at the end of exposure. This brings about the effect of switching the mode based on the difference between the signal levels.

[0015] Furthermore, in the first aspect, when the sensing mode is set, the scanning circuit causes one of the pair of capacitive elements to maintain the first signal level at the end of odd-numbered exposure and causes the other of the pair of capacitive elements to maintain the second signal level at the end of even-numbered exposure, and when switching to the normal imaging mode, causes one of the pair of capacitive elements to maintain the reset level at the end of exposure. This brings about the effect of increasing the frame rate.

[0016] In addition, in the first aspect, the front-stage circuit may include: a first photoelectric conversion element and a second photoelectric conversion element; a first transfer transistor that transfers charge from the first photoelectric conversion element to a floating diffusion layer; a second transfer transistor that transfers charge from the second photoelectric conversion element to the floating diffusion layer; and a front-stage amplifier transistor that amplifies the voltage of the floating diffusion layer; and the first photoelectric conversion element and the second photoelectric conversion element have exposure periods that partially overlap each other. This brings about an effect of increasing the frame rate.

[0017] Furthermore, in the first aspect, in the case where the sensing mode is set, the scanning circuit causes one of the pair of capacitance elements to maintain a first signal level according to the exposure amount of the first photoelectric conversion element, and causes the other of the pair of capacitance elements to maintain a second signal level according to the exposure amount of the second photoelectric conversion element, and in the case of switching to the normal imaging mode, causes the pair of capacitance elements to maintain a reset level and a signal level at the end of exposure. This brings about an effect of switching the mode based on the difference between the signal levels.

[0018] In addition, in the first aspect, the front-stage circuit may include: a photoelectric conversion element; a first transfer transistor, the first transfer transistor transfers the charge from the photoelectric conversion element to one of the pair of capacitors; a second transfer transistor, transfers the charge from the photoelectric conversion element to the other of the pair of capacitors; and a discharge transistor, the discharge transistor releases the charge from the photoelectric conversion element. This brings about the effect that the charge is transferred to each of the pair of capacitors through different transistors.

[0019] In addition, in the first aspect, the pixel may further include: a selection circuit, the selection circuit sequentially performs: control to connect one of the pair of capacitance elements to a predetermined subsequent node, control to disconnect both of the pair of capacitance elements from the subsequent node, and control to connect the other of the pair of capacitance elements to the subsequent node; a subsequent reset transistor, when both of the pair of capacitance elements are disconnected from the subsequent node, the subsequent reset transistor initializes the level of the subsequent node; and a subsequent circuit, the subsequent circuit reads the pixel signal from the pair of capacitance elements via the subsequent node and outputs the pixel signal. This brings about the effect of reducing noise.

[0020] In addition, a second aspect of the present technology is an imaging device including: a pixel including a front-stage circuit and a pair of capacitor elements, the front-stage circuit sequentially generating a predetermined number of pixel signals; a scanning circuit that causes the pair of capacitor elements to maintain the signal level of each of a pair of pixel signals in the predetermined number of pixel signals when the sensing mode is set, and causes the pair of capacitor elements to maintain the reset level and the signal level of any one of the predetermined number of pixel signals when switching from the sensing mode to the normal imaging mode; a differential calculation circuit that calculates the difference between the signal levels of each of the pair of pixel signals when the sensing mode is set; a mode control section that determines whether to switch from the sensing mode to the normal imaging mode based on the difference; and an image data processing section that processes image data arranged with the difference between the reset level and the signal level when switching to the normal imaging mode. This brings about an effect of simplifying the configuration of the imaging device. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] Figure 1 : is a block diagram showing a configuration example of an imaging device in a first embodiment of the present technology.

[0022] Figure 2 : is a block diagram showing a configuration example of a solid-state imaging element according to a first embodiment of the present technology.

[0023] Figure 3 is a circuit diagram showing a configuration example of a pixel according to a first embodiment of the present technology.

[0024] Figure 4 is a circuit diagram showing another example of the pixel according to the first embodiment of the present technology.

[0025] Figure 5 : is a block diagram showing a configuration example of a load metal oxide semiconductor (MOS) circuit block and a column signal processing section according to the first embodiment of the present technology.

[0026] Figure 6 : is a block diagram showing a configuration example of a digital signal processing section in the first embodiment of the present technology.

[0027] Figure 7 2 is a diagram for explaining the operation of the difference calculation circuit according to the first embodiment of the present technology.

[0028] Figure 8 : is a diagram illustrating an example of a state transition diagram of the solid-state imaging element according to the first embodiment of the present technology.

[0029] Fig. 9 : is a timing chart showing an example of a first global shutter operation when a sensing mode is set according to the first embodiment of the present technology.

[0030] Fig.10 : is a timing chart showing an example of the second global shutter operation when the sensing mode is set according to the first embodiment of the present technology.

[0031] Fig.11 : is a timing chart showing an example of a reading operation when the sensing mode is set according to the first embodiment of the present technology.

[0032] Fig.12 : is a timing chart showing an example of the global shutter operation when the normal imaging mode is set according to the first embodiment of the present technology.

[0033] Fig.13 is a timing chart showing an example of a reading operation when the normal imaging mode is set according to the first embodiment of the present technology.

[0034] Fig.14is a diagram showing an example of the waveform of the ramp signal according to the first embodiment of the present technology.

[0035] Fig.15 : is a diagram illustrating an example of the operation of the solid-state imaging element according to the first embodiment of the present technology.

[0036] Fig.16 is an example of an overall view of the solid-state imaging element according to the first embodiment of the present technology.

[0037] Fig.17 It is an example of an overall view of the solid-state imaging element in the first modification example of the first embodiment of the present technology.

[0038] Fig.18 : is a circuit diagram showing a configuration example of a pixel in the second modification example of the first embodiment of the present technology.

[0039] Fig.19 is a circuit diagram showing a configuration example of a pixel in a third modification example of the first embodiment of the present technology.

[0040] Fig. 20 is a timing chart showing an example of a reading operation when the mode is switched to the normal imaging mode according to the second embodiment of the present technology.

[0041] Fig.21 2 is a diagram for explaining the operation of the difference calculation circuit according to the second embodiment of the present technology.

[0042] Fig. 22 is a circuit diagram showing a configuration example of two pixels according to a third embodiment of the present technology.

[0043] Fig.23 : is a timing chart showing an example of a global shutter operation when a sensing mode is set according to the third embodiment of the present technology.

[0044] Fig.24 : is a timing chart showing an example of a global shutter operation when the mode is switched to the normal imaging mode according to the third embodiment of the present technology.

[0045] Fig.25 is a timing chart showing an example of a global shutter operation according to the fourth embodiment of the present technology.

[0046] Fig.26 is a timing chart showing an example of a read operation according to the fourth embodiment of the present technology.

[0047] Fig. 27 is a timing chart showing another example of the read operation according to the fourth embodiment of the present technology.

[0048] Fig.28 : is a circuit diagram showing a configuration example of a pixel in a first modification example of the fourth embodiment of the present technology.

[0049] Fig.29 : is a timing chart showing an example of the global shutter operation in the first modification example of the fourth embodiment of the present technology.

[0050] Fig.30 is a timing chart showing an example of a read operation in the first modification example of the fourth embodiment of the present technology.

[0051] Fig.31 This is a diagram showing an example of a stacked structure of a solid-state imaging element in a second modification of a fourth embodiment of the present technology.

[0052] Fig.32 : is a circuit diagram showing a configuration example of a pixel in a second modification example of the fourth embodiment of the present technology.

[0053] Fig.33 : is a diagram showing an example of a stacked structure of a solid-state imaging element in a third modification example of the fourth embodiment of the present technology.

[0054] Fig.34 is a circuit diagram showing a configuration example of a pixel according to a fifth embodiment of the present technology.

[0055] Fig.35 is a timing chart showing an example of a global shutter operation according to the fifth embodiment of the present technology.

[0056] Fig.36 is a circuit diagram showing a configuration example of a pixel according to a sixth embodiment of the present technology.

[0057] Fig.37 It is a diagram for explaining reset feedthrough in the sixth embodiment of the present technology.

[0058] Fig.38 is a diagram for explaining level change due to reset feedthrough in the sixth embodiment of the present technology.

[0059] Fig.39 : is a timing chart showing an example of voltage control according to the sixth embodiment of the present technology.

[0060] Fig.40 : is a timing chart showing an example of the global shutter operation of the odd-numbered frame according to the seventh embodiment of the present technology.

[0061] Fig.41 : is a timing chart showing an example of a read operation of an odd-numbered frame according to the seventh embodiment of the present technology.

[0062] Fig.42 : is a timing chart showing an example of the global shutter operation of the even-numbered frame according to the seventh embodiment of the present technology.

[0063] Fig.43 : is a timing chart showing an example of a read operation of an even-numbered frame according to the seventh embodiment of the present technology.

[0064] Fig.44 is a timing chart illustrating an example of a rolling shutter operation according to the eighth embodiment of the present technology.

[0065] Fig.45 : is a block diagram showing a configuration example of a solid-state imaging element according to a ninth embodiment of the present technology.

[0066] Fig.46 : is a circuit diagram showing a configuration example of a dummy pixel, a regulator, and a switching section according to a ninth embodiment of the present technology.

[0067] Fig.47 : is a timing chart showing an example of the operation of the dummy pixel and the adjuster according to the ninth embodiment of the present technology.

[0068] Fig.48 is a circuit diagram showing a configuration example of an effective pixel according to a ninth embodiment of the present technology.

[0069] Fig.49 : is a timing chart showing an example of a global shutter operation according to the ninth embodiment of the present technology.

[0070] Fig.50 : is a timing chart showing an example of a read operation according to the ninth embodiment of the present technology.

[0071] Fig.51 It is a diagram for explaining the effects in the ninth embodiment of the present technology.

[0072] Fig.52 This is a block diagram showing a schematic configuration example of a vehicle control system.

[0073] Fig.53 : is a diagram showing an example of the installation position of the imaging section. DETAILED DESCRIPTION

[0074] Hereinafter, a mode for carrying out the present technology (hereinafter, referred to as an embodiment) will be described. The description will be given in the following order.

[0075] 1. First Embodiment (Example of Switching Patterns Based on Difference in Signal Level)

[0076] 2. Second Embodiment (Example of Switching Mode Based on Difference in Signal Level and Reading Only Reset Level)

[0077] 3. Third Embodiment (Example in which a floating diffusion layer is shared by two pixels and the mode is switched based on a difference in signal level)

[0078] 4. Fourth Embodiment (Example of Changing Method of Driving Pixels)

[0079] 5. Fifth Embodiment (Example of adding a discharge transistor and causing the first and second capacitive elements to hold pixel signals)

[0080] 6. Sixth Embodiment (Example of Making the First Capacitance Element and the Second Capacitance Element Hold Pixel Signals and Controlling the Reset Power Supply Voltage)

[0081] 7. Seventh Embodiment (Example of Causing the First Capacitance Element and the Second Capacitance Element to Hold the Pixel Signal and Keep Switching Levels for Each Frame)

[0082] 8. Eighth Embodiment (Example of Making the First Capacitance Element and the Second Capacitance Element Hold Pixel Signals and Performing Rolling Shutter Operation)

[0083] 9. Ninth Embodiment (Example of Reducing Noise and Making the First Capacitance Element and the Second Capacitance Element Hold Pixel Signal)

[0084] 10. Application examples for mobile objects

[0085] <1. First Embodiment>

[0086] [Configuration Example of Imaging Device]

[0087] Figure 1 1 is a block diagram showing a configuration example of an imaging device 100 according to a first embodiment of the present technology. The imaging device 100 is a device that captures image data, and includes an imaging lens 110, a solid-state imaging element 200, a recording section 120, and an imaging control section 130. As the imaging device 100, a digital camera and an electronic device (smartphone, personal computer, etc.) having an imaging function are assumed.

[0088] The solid-state imaging element 200 captures image data under the control of the imaging control section 130. The solid-state imaging element 200 supplies the image data to the recording section 120 via the signal line 209.

[0089] The imaging lens 110 condenses light and guides the light to the solid-state imaging element 200. The imaging control section 130 controls the solid-state imaging element 200 to capture image data. For example, the imaging control section 130 provides an imaging control signal including a vertical synchronization signal VSYNC to the solid-state imaging element 200 via a signal line 139. The recording section 120 records image data.

[0090] Here, the vertical synchronization signal VSYNC is a signal indicating imaging timing, and a periodic signal of a constant frequency such as 60 Hz is used as the vertical synchronization signal VSYNC.

[0091] It is to be noted that although the imaging device 100 records the image data, the image data may be transmitted to the outside of the imaging device 100. In this case, an external interface for transmitting the image data is further provided. Alternatively, the imaging device 100 may further display the image data. In this case, a display section is further provided.

[0092] [Configuration Example of Solid-State Imaging Element]

[0093] Figure 2 1 is a block diagram showing a configuration example of a solid-state imaging element 200 according to a first embodiment of the present technology. The solid-state imaging element 200 includes a vertical scanning circuit 211, a pixel array section 220, a timing control circuit 212, a digital-to-analog converter (DAC) 213, a load MOS circuit block 250, and a column signal processing circuit 260. In the pixel array section 220, a plurality of pixels 300 are arranged in a two-dimensional grid pattern. In addition, each circuit in the solid-state imaging element 200 is provided in, for example, a single semiconductor chip.

[0094] Hereinafter, a group of pixels 300 arranged in the horizontal direction is referred to as a “row”, and a group of pixels 300 arranged in a direction perpendicular to the row is referred to as a “column”.

[0095] The timing control circuit 212 controls the operation timing of each of the vertical scanning circuit 211 , the DAC 213 , and the column signal processing circuit 260 in synchronization with the vertical synchronization signal VSYNC from the imaging control section 130 .

[0096] The DAC 213 generates a sawtooth-shaped ramp signal through digital-to-analog (DA) conversion and provides the generated ramp signal to the column signal processing circuit 260 .

[0097] The vertical scanning circuit 211 sequentially selects and drives the rows to output analog pixel signals. Each pixel 300 photoelectrically converts incident light to generate an analog pixel signal. The pixel 300 supplies the pixel signal to the column signal processing circuit 260 via the load MOS circuit block 250. Note that the vertical scanning circuit 211 is an example of a scanning circuit described in the claims.

[0098] In the load MOS circuit block 250, a MOS transistor that supplies a constant current is provided for each column.

[0099] The column signal processing circuit 260 performs signal processing such as analog-to-digital (AD) conversion processing and correlated double sampling (CDS) processing on the pixel signal of each column, and supplies image data including the processed signal to the recording section 120 .

[0100] [Pixel configuration example]

[0101] Figure 3 3 is a circuit diagram showing a configuration example of a pixel 300 according to a first embodiment of the present technology. The pixel 300 includes a previous stage circuit 310 , capacitance elements 321 and 322 , a selection circuit 330 , a subsequent stage reset transistor 341 , and a subsequent stage circuit 350 .

[0102] The previous-stage circuit 310 includes a photoelectric conversion element 311 , a transfer transistor 312 , a floating diffusion (FD) reset transistor 313 , an FD 314 , a previous-stage amplifier transistor 315 , and a current source transistor 316 .

[0103] The photoelectric conversion element 311 generates electric charge by photoelectric conversion. The transfer transistor 312 transfers the electric charge from the photoelectric conversion element 311 to the FD 314 according to the transfer signal trg from the vertical scanning circuit 211 .

[0104] The FD reset transistor 313 extracts charge from the FD 314 according to the FD reset signal rst from the vertical scanning circuit 211 to initialize the FD 314. The FD 314 accumulates the charge and generates a voltage corresponding to the amount of charge. The pre-stage amplifier transistor 315 amplifies the level of the voltage of the FD 314 and outputs the amplified voltage to the pre-stage node 320.

[0105] Furthermore, respective sources of the FD reset transistor 313 and the pre-stage amplifier transistor 315 are connected to the power supply voltage VDD. A current source transistor 316 is connected to the drain of the pre-stage amplifier transistor 315. The current source transistor 316 supplies a current id1 under the control of the vertical scanning circuit 211.

[0106] The capacitance elements 321 and 322 have their respective one ends commonly connected to the previous-stage node 320 and have their respective other ends connected to the selection circuit 330. Note that the capacitance elements 321 and 322 are examples of a pair of capacitance elements described in the claims.

[0107] The selection circuit 330 includes a selection transistor 331 and a selection transistor 332. The selection transistor 331 opens and closes the path between the capacitor element 321 and the subsequent node 340 according to the selection signal Φ1 from the vertical scanning circuit 211. The selection transistor 332 opens and closes the path between the capacitor element 322 and the subsequent node 340 according to the selection signal Φ2 from the vertical scanning circuit 211.

[0108] The post-stage reset transistor 341 initializes the level of the post-stage node 340 to a predetermined potential Vreg according to a post-stage reset signal rstb from the vertical scanning circuit 211. A potential different from the power supply voltage VDD (eg, a potential lower than VDD) is set as the potential Vreg.

[0109] The post-stage circuit 350 includes a post-stage amplifier transistor 351 and a post-stage selection transistor 352. The post-stage amplifier transistor 351 amplifies the level of the post-stage node 340. The post-stage selection transistor 352 outputs the signal of the level amplified by the post-stage amplifier transistor 351 to the vertical signal line 309 as a pixel signal according to the post-stage selection signal selb from the vertical scanning circuit 211.

[0110] Note that, for example, n-channel metal oxide semiconductor (nMOS) transistors are used as various transistors (the transfer transistor 312 and the like) in the pixel 300 .

[0111] The vertical scanning circuit 211 supplies a high-level FD reset signal rst and a transfer signal trg to all pixels, and sets the subsequent reset signal rstb to a high level at the start of exposure. Thus, the photoelectric conversion element 311 is initialized. Hereinafter, this control is referred to as "PD reset".

[0112] Then, the vertical scanning circuit 211 provides a high-level FD reset signal rst in the pulse period of all pixels immediately before the end of exposure. Therefore, the FD 314 is initialized, and the level corresponding to the level of the FD 314 at this time is held in the capacitor 321. This control is hereinafter referred to as "FD reset".

[0113] The level of the FD 314 at the time of FD reset and the level corresponding to the level of the FD 314 (the level held in the capacitive element 321 and the level of the vertical signal line 309 ) are hereinafter collectively referred to as “P phase” or “reset level”.

[0114] At the end of exposure, the vertical scanning circuit 211 supplies a high-level transfer signal trg to all pixels in a pulse period. Therefore, a signal charge corresponding to the exposure amount is transferred to the FD 314, and a level corresponding to the level of the FD 314 at this time is held in the capacitor 322.

[0115] The level of the FD 314 at the time of signal charge transfer and the level corresponding to the level of the FD 314 (the level held in the capacitance element 322 and the level of the vertical signal line 309 ) are hereinafter collectively referred to as “D phase” or “signal level”.

[0116] The exposure control that starts and ends exposure to all pixels at the same time in this way is called a global shutter method. Under this exposure control, the front-stage circuit 310 of all pixels generates a reset level and a signal level in sequence. These levels are maintained in the capacitor elements 321 and 322. After the exposure is completed, the vertical scanning circuit 211 selects the row in sequence and outputs the level (reset level or signal level) of the row.

[0117] Note that the circuit configuration of the pixel 300 is not limited to the structure shown in the figure, as long as a plurality of levels (reset level and signal level) can be generated and maintained. Figure 4 As shown, transfer transistors 312-1 and 312-2 may be provided instead of the transfer transistor 312. In this case, the FD reset transistor 313, the pre-stage amplifier transistor 315, and the current source transistor 316 are not arranged, and the discharge transistor 317 is added.

[0118] The transfer transistor 312-1 transfers the charge from the photoelectric conversion element 311 to the capacitor element 321 according to the transfer signal PDTG1 from the vertical scanning circuit 211. The transfer transistor 312-2 transfers the charge from the photoelectric conversion element 311 to the capacitor element 322 according to the transfer signal PDTG2 from the vertical scanning circuit 211. The discharge transistor 317 functions as an overflow drain for releasing the charge from the photoelectric conversion element 311 according to the discharge signal ofg from the vertical scanning circuit 211.

[0119] [Configuration Example of Column Signal Processing Circuit]

[0120] Figure 5 : is a block diagram showing a configuration example of the load MOS circuit block 250 and the column signal processing circuit 260 according to the first embodiment of the present technology.

[0121] In the load MOS circuit block 250, a vertical signal line 309 is wired for each column. When the number of columns is I (I is an integer), I vertical signal lines 309 are wired. In addition, a load MOS transistor 251 that supplies a constant current id2 is connected to each of the vertical signal lines 309.

[0122] In the column signal processing circuit 260, a plurality of ADCs 261 and a digital signal processing section 262 are arranged. Each ADC 261 is provided for each column. In the case where the number of columns is 1, 1 ADC 261 is provided.

[0123] The ADC 261 converts the analog pixel signal from the corresponding column into a digital signal using the ramp signal Rmp from the DAC 213. The ADC 261 supplies the digital signal to the digital signal processing section 262. As the ADC 261, for example, a single slope ADC including a comparator and a counter is provided.

[0124] The digital signal processing section 262 performs predetermined signal processing, such as CDS processing, on the digital signal of each column. The digital signal processing section 262 supplies image data including the processed digital signal to the recording section 120 .

[0125] Here, according to the user's operation, etc., a manual imaging mode or an automatic imaging mode is set in the solid-state imaging element 200. The manual imaging mode is a mode in which the solid-state imaging element 200 performs imaging according to the user's operation (such as pressing a shutter button). On the other hand, the automatic imaging mode is a mode that does not require user operation when imaging.

[0126] A flag F_auto indicating the manual imaging mode or the automatic imaging mode is input to the digital signal processing unit 262. The automatic driving mode includes a sensing mode and a normal imaging mode, and when the automatic driving mode is set, the digital signal processing unit 262 switches to the sensing mode.

[0127] The sensing mode is a mode in which the solid-state imaging element 200 detects the presence or absence of movement of an object. On the other hand, the normal imaging mode is a mode in which the solid-state imaging element 200 generates image data. In the presence of movement, the solid-state imaging element 200 switches from the sensing mode to the normal imaging mode and performs imaging. The digital signal processing section 262 generates a flag F_sense indicating the sensing mode or the normal imaging mode, and provides the flag F_sense to the vertical scanning circuit 211.

[0128] In the case of setting the manual imaging mode, the vertical scanning circuit 211 simultaneously exposes all pixels, generates a reset level and a signal level for each pixel, and maintains the reset level and the signal level for the capacitor elements 321 and 322. Then, the vertical scanning circuit 211 sequentially selects the row after exposure, and sequentially outputs the reset level and the signal level of each pixel in the row. The digital signal processing section 262 performs AD conversion and CDS processing to generate image data.

[0129] In the case where the mode is switched to the automatic drive mode and the sensing mode is set, the vertical scanning circuit 211 performs control to simultaneously expose all pixels a plurality of times.

[0130] At the end of odd-numbered exposure, the vertical scanning circuit 211 causes each of the pixels to generate a signal level and causes one of the capacitive elements 321 and 322 to hold the signal level. At the end of even-numbered exposure, the vertical scanning circuit 211 causes each of the pixels to generate a signal level and causes the other of the capacitive elements 321 and 322 to hold the signal level. Then, the vertical scanning circuit 211 sequentially selects a row after even-numbered exposure, and sequentially outputs a pair of signal levels for each pixel in the row.

[0131] Note that the odd-numbered exposure amount and the even-numbered exposure amount are controlled to be substantially the same. For example, in the solid-state imaging element 200, the aperture value and the International Organization for Standardization (ISO) sensitivity are substantially the same as the exposure time in each exposure.

[0132] In the sensing mode, the digital signal processing section 262 determines whether to switch to the normal imaging mode based on a comparison result between the absolute value of the difference between a pair of signal levels and a predetermined threshold value. For example, the digital signal processing section 262 determines the movement of the object when there are one or more pixels whose absolute value of the difference exceeds the threshold value, and switches the sensing mode to the normal imaging mode.

[0133] In the case where the mode is switched to the normal imaging mode, the vertical scanning circuit 211 generates image data by control similar to that in the manual imaging mode.

[0134] [Configuration example of digital signal processing section]

[0135] Figure 6 2 is a block diagram showing a configuration example of the digital signal processing section 262 according to the first embodiment of the present technology. The digital signal processing section 262 includes a plurality of difference calculation circuits 263, a mode control section 264, and an image data processing section 265. Each difference calculation circuit 263 is provided for each column.

[0136] The difference calculation circuit 263 calculates the difference between the levels held in the capacitive elements 321 and 322 in the corresponding column. In the manual imaging mode, the difference calculation circuit 263 performs CDS processing of calculating the difference between the signal level after AD conversion and the reset level as the net signal level, and supplies the processing result to the mode control section 264.

[0137] In the sensing mode in the automatic imaging mode, the difference calculation circuit 263 calculates the difference between a pair of signal levels after AD conversion and supplies the difference to the mode control section 264. In the normal imaging mode, the difference calculation circuit 263 performs the same CDS processing as in the manual imaging mode and supplies the processing result to the mode control section 264.

[0138] The mode control unit 264 determines whether to switch from the sensing mode to the normal imaging mode based on the difference in the sensing mode. For example, when the absolute value of the difference in one or more pixels among all pixels exceeds a threshold, the mode control unit 264 determines the movement of the object and switches to the normal imaging mode.

[0139] At this time, for example, in the case where the threshold is 2P, the mode control section 264 can determine whether the absolute value of the difference exceeds the threshold by referring to the P-th bit of the code indicating the absolute value of the difference. Then, the mode control section 264 generates a flag F_sense specifying the mode, and provides the flag F_sense to the difference calculation circuit 263 and the vertical scanning circuit 211 of each column. In the case of referring to the P-th bit of the code, for example, an OR gate that outputs the OR (logical product) of the P-th bit of each column as F_sense is used as the mode control section 264.

[0140] Furthermore, the mode control section 264 supplies the CDS processing result to the image data processing section 265 in the manual imaging mode or the normal imaging mode.

[0141] The image data processing section 265 performs various types of image processing on the image data in which the CDS processing results of the respective pixels are arranged, and supplies the processed image data to the recording section 120 .

[0142] Note that the mode control section 264 determines the presence or absence of movement of the object based on whether the absolute value of the difference in one or more pixels among all the pixels has exceeded the threshold value, but the method of determining the presence or absence of movement is not limited to this method. For example, in the case where a certain area is set as a monitoring target and the absolute value of the difference exceeds the threshold value of one or more pixels in the area, the mode control section 264 can also determine that there is movement. Alternatively, the mode control section 264 can count the number of pixels whose absolute value of the difference exceeds the threshold value, and determine that there is movement when the count value exceeds a specific value.

[0143] [Operation Example of Solid-State Imaging Element]

[0144] Figure 7 : is a diagram for explaining the operation of the differential calculation circuit 263 according to the first embodiment of the present technology. In the sensing mode, the signal level at the time of odd exposure is D1, and the signal level at the time of even exposure is D2. After the odd exposure, the signal level D1 is output from the pixel 300, and after the even exposure, the sum of the signal levels D1 and D2 is output from the pixel 300.

[0145] In the sensing mode, the differential calculation circuit 263 holds the signal level D1 in a memory, etc. Then, the differential calculation circuit 263 calculates D2 which is the difference between the sum of the signal levels D1 and D2 and the held signal level D1. The differential calculation circuit 263 calculates and outputs the difference between the signal level D2 and the held signal level D1.

[0146] In a mode other than the sensing mode (manual imaging mode or normal imaging mode), the difference calculation circuit 263 holds the reset level in a memory, etc. Then, the difference calculation circuit 263 calculates and outputs the difference between the signal level and the held reset level.

[0147] Figure 8 1 is a diagram showing an example of a state transition diagram of the solid-state imaging element 200 according to the first embodiment of the present technology. In the initial state, for example, the manual imaging mode 510 is set.

[0148] In the manual imaging mode 510 , when the flag F_auto is set to a high level, the mode switches to the automatic imaging mode 520 , and the sensing mode 521 is set.

[0149] In the sensing mode 521 , when the flag F_auto is set to a low level, the mode switches to the manual imaging mode 510 .

[0150] In the sensing mode 521, the solid-state imaging element 200 calculates the difference between the signal levels and determines for each pixel whether the absolute value of the difference exceeds the threshold value Th. When the absolute value of the difference exceeds the threshold value Th in one or more pixels, the sensing mode 521 switches to the normal imaging mode 522.

[0151] In the normal imaging mode 522, the solid-state imaging element 200 captures image data. After the imaging ends, the normal imaging mode 522 switches to the sensing mode 521.

[0152] [Operation Example of Solid-State Imaging Element]

[0153] Fig. 9 : is a timing chart showing an example of an odd-numbered global shutter operation when the sensing mode is set according to the first embodiment of the present technology.

[0154] When the sensing mode is set, the solid-state imaging element 200 performs control to simultaneously expose all pixels a plurality of times. The period from time T1 to T3 in the figure corresponds to an odd-numbered exposure period.

[0155] At timing T0 immediately before the odd-numbered exposure period, the vertical scanning circuit 211 sets the post-stage reset signal rstb of all rows (in other words, all pixels) to a high level. In addition, the vertical scanning circuit 211 supplies the high-level FD reset signal rst and the transfer signal trg to all pixels in the period from time T0 to time T1. Therefore, all pixels are reset by PD, and exposure is started simultaneously in all rows.

[0156] Here, rst_[n], trg_[n], and rstb_[n] in the figure indicate signals to pixels of the nth row among N rows. N is an integer indicating the total number of rows, and n is an integer from 1 to N.

[0157] Then, at the timing T2 immediately before the end of the exposure period, the vertical scanning circuit 211 supplies the high-level FD reset signal rst over the pulse period. Therefore, all pixels are FD reset.

[0158] At the exposure end time T3, the vertical scanning circuit 211 provides a high-level transfer signal trg within the pulse period, and at the same time sets the selection signal Φ1 to a high level in all pixels. As a result, the signal level according to the odd exposure amount is sampled and held. In addition, the level of the previous node 320 is reduced from the reset level to the signal level. The difference between them corresponds to the net signal level Vsig1. In addition, Φ1_[n] in the figure represents the signal for the pixel of the nth row.

[0159] At timing T4 after timing T3 , the vertical scanning circuit 211 returns the selection signal Φ1 to the low level.

[0160] Fig.10 1 is a timing chart showing an example of an even-numbered global shutter operation when setting a sensing mode according to the first embodiment of the present technology. The period from time T6 to T8 in the figure corresponds to an even-numbered exposure period.

[0161] The vertical scanning circuit 211 supplies the high-level FD reset signal rst and the transfer signal trg to all pixels in the period from the time T5 to the time T6. Therefore, all pixels are reset by PD, and exposure starts simultaneously in all rows.

[0162] Then, at the timing T7 immediately before the end of the exposure period, the vertical scanning circuit 211 supplies the high-level FD reset signal rst over the pulse period. Therefore, all pixels are FD reset.

[0163] At the exposure end timing T8, the vertical scanning circuit 211 provides a high-level transfer signal trg within the pulse period, and at the same time sets the selection signal Φ1 to a high level in all pixels. As a result, the signal level according to the even exposure amount is sampled and held. In addition, the level of the previous node 320 is reduced from the reset level to the signal level. The difference between them corresponds to the net signal level Vsig2. In addition, Φ2_[n] in the figure represents the signal for the pixel of the nth row.

[0164] At timing T9 after timing T8, the vertical scanning circuit 211 returns the selection signal Φ2 to the low level.

[0165] Fig.111 is a timing diagram showing an example of a read operation when a sensing mode is set according to the first embodiment of the present technology. Immediately after even exposure, rows are selected in sequence, and the signal level of each row is read. T10 to T14 in the figure represent the read operation of the nth row.

[0166] In the reading period of the nth row from timing T10 to timing T14, the vertical scanning circuit 211 sets the FD reset signal rst and the subsequent stage selection signal selb of the nth row to high level. Here, selb_[n] in the figure represents a signal to the pixel of the nth row.

[0167] From the timing T10 to the pulse period, the vertical scanning circuit 211 supplies the high-level subsequent-stage reset signal rstb to the n-th row. As a result, the subsequent-stage node 340 is initialized.

[0168] The vertical scanning circuit 211 supplies the high-level selection signal Φ1 to the n-th row in the period from timing T11 to timing T12 immediately after timing T10. The potential of the subsequent node 340 increases the signal level according to the odd exposure amount. The odd signal level is defined as D1.

[0169] The DAC 213 gradually decreases the ramp signal Rmp in the period from immediately after the timing T11 to the timing T12. The ADC 261 compares the ramp signal Rmp with the level of the vertical signal line 309 and counts the count value until the comparison result is inverted. Thus, the signal level D1 is read out.

[0170] Then, the vertical scanning circuit 211 supplies the high-level selection signal Φ2 to the n-th row in the period from timing T13 to timing T14 immediately after timing T12. The potential of the subsequent node 340 increases the signal level according to the even exposure amount. The odd signal level is defined as D2.

[0171] The DAC 213 gradually decreases the ramp signal Rmp in the period from immediately after the timing T13 to the timing T14. The ADC 261 compares the ramp signal Rmp with the level of the vertical signal line 309 and counts the count value until the comparison result is inverted. As a result, the sum of the signal levels D1 and D2 is read.

[0172] The mode control section 264 determines the presence or absence of movement of the object based on the difference between the signal levels D1 and D2 of each pixel, and switches from the sensing mode to the normal imaging mode if there is movement.

[0173] Fig.12 1 is a timing chart showing an example of the global shutter operation when the normal imaging mode is set according to the first embodiment of the present technology. Assume that at timing T20, the imaging mode is switched to the normal imaging mode.

[0174] At timing T20, the vertical scanning circuit 211 sets the post-stage reset signal rstb of all pixels to a high level. In addition, the vertical scanning circuit 211 provides the high-level FD reset signal rst and the transfer signal trg to all pixels during the period from time T20 to time T21. Therefore, all pixels are reset by PD, and exposure starts simultaneously in all rows.

[0175] At timing T22 immediately before the end of exposure, the vertical scanning circuit 211 provides a high-level FD reset signal rst within the pulse period, and sets the selection signal Φ1 to a high level in all pixels. Therefore, all pixels are reset by FD, and the reset level is sampled and held. At timing T23 after timing T22, the vertical scanning circuit 211 returns the selection signal Φ1 to a low level.

[0176] At the exposure end time T24, the vertical scanning circuit 211 provides a high-level transfer signal trg during the pulse, and sets the selection signal Φ2 to a high level in all pixels. As a result, the signal level is sampled and maintained in all pixels. In addition, the level of the previous node 320 is reduced from the reset level to the signal level. At the time T25 after the time T24, the vertical scanning circuit 211 returns the selection signal Φ2 to a low level.

[0177] Fig.13 is a timing chart showing an example of a reading operation when the normal imaging mode is set according to the first embodiment of the present technology.

[0178] In the reading period of the n-th row from the timing T30 to the timing T34 , the vertical scanning circuit 211 sets the FD reset signal rst and the subsequent-stage selection signal selb of the n-th row to the high level.

[0179] From the time T30 to the pulse period, the vertical scanning circuit 211 supplies the high-level subsequent-stage reset signal rstb to the n-th row. As a result, the subsequent-stage node 340 is initialized.

[0180] The vertical scanning circuit 211 supplies the high-level selection signal Φ1 to the n-th row in a period from time T31 to time T32 immediately after time T30. The potential of the subsequent-stage node 340 becomes a reset level.

[0181] The DAC 213 gradually decreases the ramp signal Rmp from immediately after the timing T31 to the period of the timing T32. The ADC 261 compares the ramp signal Rmp with the level of the vertical signal line 309 and counts the count value until the comparison result is inverted. Thus, the P-phase level (reset level) is read.

[0182] The vertical scanning circuit 211 supplies the high-level selection signal Φ2 to the n-th row during the period from the time T33 after the time T32 to the time T34. The potential of the subsequent-stage node 340 increases by the net signal level.

[0183] The DAC 213 gradually decreases the ramp signal Rmp from immediately after the timing T33 to the period of the timing T34. The ADC 261 compares the ramp signal Rmp with the level of the vertical signal line 309 and counts the count value until the comparison result is inverted. Thus, the D-phase level (signal level) is read.

[0184] The waveform of the ramp signal Rmp in the read cycle of the P phase level (reset level) is different from the waveform in the read cycle of the D phase level (signal level). For example, the change amount of the ramp signal Rmp in the read cycle of the P phase level is smaller than the change amount in the read cycle of the D phase level.

[0185] Fig.14 : is a diagram showing an example of the waveform of the ramp signal according to the first embodiment of the present technology. The drawing shows the waveform in the reading period. The ramp signal in the exposure period is constant, for example.

[0186] In the sensing mode, the odd-numbered D-phase level and the even-numbered D-phase level are sequentially read. The waveform of the ramp signal in the reading period of the odd-numbered D-phase level is the same as the waveform in the reading period of the even-numbered D-phase level.

[0187] On the other hand, in the normal imaging mode, the P-phase level and the D-phase level are read in sequence. The waveform of the ramp signal in the reading period of the P-phase level is different from that in the reading period of the D-phase level.

[0188] Fig.15 1 is a diagram showing an example of the operation of the solid-state imaging element 200 according to the first embodiment of the present technology. For example, when the automatic imaging mode is set, the operation is started.

[0189] First, the sensing mode is set. The vertical scanning circuit 211 performs odd exposure on all pixels (step S901) and even exposure on all pixels (step S902). Then, the ADC 261 performs AD conversion on D1 as the odd-numbered D-phase level and the sum (D1+D2) of D2 and D1 as the even-numbered D-phase level (step S903), and the differential calculation circuit 263 calculates the difference between D1 and D2 (step S904).

[0190] The mode control section 264 determines whether there is movement in the object based on whether the absolute value of the difference exceeds the threshold value in one or more pixels (step S905). If there is no movement (step S905: No), the solid-state imaging element 200 repeatedly performs steps S901 to S905.

[0191] In the case of movement (step S905: Yes), the mode is switched to the normal imaging mode, and the vertical scanning circuit 211 exposes all pixels (step S906). Then, the ADC 261 performs AD conversion on the P-phase level and the D-phase level (step S907), and the differential calculation circuit 263 calculates the difference between them (step S908). The image data processing unit 265 performs various types of image processing on the image data (step S909). After step S909, the solid-state imaging element 200 switches to the sensing mode, and repeats step S901 and subsequent steps.

[0192] Note that, although one piece of image data is captured in the normal imaging mode, two or more pieces of image data may be captured continuously. In addition, although the mode is switched to the sensing mode after imaging in the normal imaging mode, the mode may be switched to the manual imaging mode after imaging.

[0193] Fig.16 3 is an example of an overall view of the solid-state imaging element 200 according to the first embodiment of the present technology. Each pixel 300 is provided with a front-stage circuit 310 that sequentially generates a predetermined number of pixel signals, capacitance elements 321 and 322, a selection circuit 330, and a rear-stage circuit 350.

[0194] When the sensing mode is set, the vertical scanning circuit 211 causes the capacitor elements 321 and 322 to maintain the respective signal levels of the odd and even pixel signals. In addition, when the sensing mode is switched to the normal imaging mode, the vertical scanning circuit 211 causes the capacitor elements 321 and 322 to maintain the reset level and signal level of the pixel signal.

[0195] When the sensing mode is set, the difference calculation circuit 263 calculates the difference between the signal levels of the odd and even pixel signals. The mode control section 264 determines whether to switch from the sensing mode to the normal imaging mode based on the difference. For example, the mode control section 264 determines whether to switch the sensing mode to the normal imaging mode based on the comparison result between the absolute value of the difference and a predetermined threshold.

[0196] The automatic imaging mode can also be realized by recognizing a voice command and performing control of imaging according to the command as in Patent Document 1. However, in this configuration, a microphone for inputting voice and a circuit for performing voice recognition are required, and the configuration of the imaging device becomes complicated.

[0197] Furthermore, the presence or absence of movement of an object can be detected by an inter-frame difference method, but in this configuration, a frame memory for holding image data is required.

[0198] On the other hand, in the solid-state imaging element 200 shown in the drawings, the odd signal level and the even signal level are held by the capacitor elements 321 and 322, and the mode is switched based on the difference therebetween. Therefore, the resources and costs of the microphone, speech recognition processing, frame memory, etc. can be reduced.

[0199] As described above, according to the first embodiment of the present technology, the solid-state imaging element 200 holds the capacitance elements 321 and 322 at odd signal levels and even signal levels and switches the mode based on the difference therebetween, and therefore, the automatic imaging mode can be realized with a simple configuration.

[0200] [First Modification]

[0201] In the first embodiment described above, imaging is performed in the presence of movement of the object, but there is a situation where focusing is not achieved during imaging. The solid-state imaging element 200 according to the first variant of the first embodiment is different from the solid-state imaging element 200 of the first embodiment in that whether to switch to the normal imaging mode is determined based on the difference when the lens moves to the focus position.

[0202] Fig.17 1 is an example of an overall view of the solid-state imaging element 200 in the first modification of the first embodiment of the present technology. The solid-state imaging element 200 according to the first modification of the first embodiment is different from the solid-state imaging element of the first embodiment in that the phase difference pixel 305 is provided in the pixel array section 220, and the focus control section 266 is further provided in the column signal processing circuit 260.

[0203] The phase difference pixel 305 generates one of a pair of pupil-divided pixel signals. In the pixel array section 220, multiple pairs of phase difference pixels 305 are arranged along the direction of detecting the phase difference. Note that although a dedicated phase difference pixel 305 for detecting the phase difference is provided, the present invention is not limited to this configuration. For example, all pixels may be configured to detect the phase difference. For example, by providing a pair of photodiodes and an on-chip lens (OCL) for each pixel, phase difference detection in all pixels can be achieved. Alternatively, by providing 2×2 photodiodes and an OCL for each pixel, the phase difference can be detected in all pixels.

[0204] The focus control section 266 detects the pixel signal of each of the plurality of phase difference pixel pairs 305 and detects the focus position of the lens (focus lens) in the optical section 110. The focus control section 266 controls a driver (not shown) that drives the lens so that the lens moves to the detected focus position. In addition, the focus control section 266 notifies the difference calculation circuit 263 whether the lens of each column has moved to the focus position.

[0205] The difference calculation circuit 263 obtains the difference between the signal level D1 before the lens moves to the focus position in the sensing mode and the signal level D2 when the lens moves to the focus position. When the lens has moved to the focus position, the sum of D1 and D2 is read.

[0206] Therefore, similar to the first embodiment, the difference calculation circuit 263 holds the signal level D1 in a memory or the like, and calculates the difference (D2) between the sum of the signal levels D1 and D2 and the held signal level D1. Then, the difference calculation circuit 263 calculates and outputs the difference between the signal level D2 and the held signal level D1.

[0207] When the lens (such as a focus lens) has moved to the focus position, the mode control section 264 determines whether to switch the sensing mode to the normal imaging mode based on the difference. For example, when the absolute value of the difference exceeds a threshold in one or more pixels, the sensing mode is switched to the normal imaging mode.

[0208] In the case of movement of the focused object during the time period from detection to the movement of the lens to the focus position, there is a case where focusing is not achieved when moving to the focus position. In this case, since the absolute value of the difference is usually less than or equal to the threshold, the solid-state imaging element 200 does not switch to the normal imaging mode and does not perform imaging. On the other hand, if focusing is achieved when moving to the focus position, the absolute value of the difference usually exceeds the threshold, and at this time, the solid-state imaging element 200 switches to the normal imaging mode and performs imaging. As a result, imaging can be performed in a reliable focus state.

[0209] As described above, according to the first modification example of the first embodiment of the present technology, whether to switch from the sensing mode to the normal imaging mode is determined based on the difference when the lens moves to the focus position, and therefore, focused image data can be captured.

[0210] [Second Modification]

[0211] In the first embodiment described above, the selection transistors 331 and 332 are connected in parallel and inserted between the capacitor elements 321 and 322 and the subsequent node 340, but these transistors may be connected in series. The solid-state imaging element 200 in the second modification of the first embodiment is different from the solid-state imaging element 200 of the first embodiment in that the selection transistors 331 and 332 are connected in series.

[0212] Fig.18 3 is a circuit diagram showing a configuration example of a pixel 300 in a second modification of the first embodiment of the present technology. In the first modification of the first embodiment, selection transistors 332 and 331 are connected in series between the front-stage circuit 310 and the rear-stage circuit 350. In addition, a capacitor 322 is inserted between a connection node of the selection transistors 332 and 331 and a ground terminal. The capacitor 321 is inserted between a connection node of the selection transistor 331 and the rear-stage circuit 350 and a ground terminal. In addition, a rear-stage reset transistor 341 is not provided.

[0213] In modes other than the sensing mode, the vertical scanning circuit 211 closes both the selection transistors 331 and 332 by the selection signals S1 and S2 while the reset level is maintained in the capacitor 321. In addition, the vertical scanning circuit 211 opens the selection transistor 331 and closes the selection transistor 332 by the selection signals S1 and S2 while the signal level is maintained in the capacitor 322.

[0214] In the sensing mode, the vertical scanning circuit 211 closes both the selection transistors 331 and 332 by the selection signals S1 and S2, and keeps the capacitance element 321 at an odd signal level. In addition, the vertical scanning circuit 211 opens the selection transistor 331 and closes the selection transistor 332 by the selection signals S1 and S2, and keeps the capacitance element 322 at an even signal level.

[0215] For example, the details of the method of controlling the circuit in the accompanying drawings are described in “Chen Xu et al., A Stacked Global-Shutter CMOS Imager with SC-Type Hybrid-GS Pixel and Self-Knee Point Calibration Single-Frame HDR and On-ChipBinarization Algorithm for Smart Vision Applications ISSCC2019.”

[0216] As described above, according to the second modification example of the first embodiment of the present technology, since the selection transistors 331 and 332 are connected in series, the subsequent-stage reset transistor 341 can be reduced in size.

[0217] [Third Modification]

[0218] In the above-described first embodiment, the subsequent circuit 350 has one system, but the circuit may include two systems. The solid-state imaging element 200 in the third modification of the first embodiment is different from the first embodiment in that two systems of subsequent circuits are provided.

[0219] Fig.19 1 is a circuit diagram showing a configuration example of a pixel 300 in a third modification example of the first embodiment of the present technology. The pixel 300 according to the third modification example of the first embodiment is different from the pixel of the first embodiment in that a post-stage reset transistor 341 is not provided, and post-stage circuits 350-1 and 350-2 are provided instead of the post-stage circuit 350.

[0220] The selection transistor 331 opens and closes a path between the capacitance element 321 and the subsequent-stage circuit 350 - 1 , and the selection transistor 332 opens and closes a path between the capacitance element 322 and the subsequent-stage circuit 350 - 2 .

[0221] The post-stage circuit 350-1 includes a post-stage amplifier transistor 351-1 and a post-stage selection transistor 352-1, and the post-stage circuit 350-2 includes a post-stage amplifier transistor 351-2 and a post-stage selection transistor 352-2. In addition, two vertical signal lines are wired for each column, and the post-stage circuit 350-1 outputs a pixel signal to the vertical signal line 309-1, and the post-stage circuit 350-2 outputs a pixel signal to the vertical signal line 309-2. In addition, two ADCs 261 are provided for each column.

[0222] As shown in the figure, by providing two subsequent circuits, two ADCs 261 are provided for each column, and two levels (D1, D2, etc.) can be AD-converted at the same time. As a result, the reading speed is improved.

[0223] As described above, according to the third modification example of the first embodiment of the present technology, since the subsequent-stage circuit 350 includes two systems, the reading speed can be improved.

[0224] <2. Second Embodiment>

[0225] In the first embodiment described above, when switching to the normal imaging mode, the solid-state imaging element 200 reads the reset level and the signal level, but in this configuration, it is difficult to further increase the frame rate. The solid-state imaging element 200 according to the second embodiment is different from the solid-state imaging element of the first embodiment in that only the reset level is read when the mode is switched to the normal imaging mode.

[0226] Fig. 20 is a timing diagram showing an example of a read operation when switching to a normal imaging mode in a second embodiment of the present technology. The method of controlling the pixel 300 in the sensing mode according to the second embodiment is similar to the method according to the first example. However, the differential calculation circuit 263 according to the second embodiment holds the signal level D2 in a memory or the like and calculates the difference between the signal levels D1 and D2.

[0227] In addition, in the second embodiment, when the mode is switched to the normal imaging mode, only the reset level is read. For example, in the reading cycle of the nth row from timing T30 to timing T36, the vertical scanning circuit 211 sets the subsequent stage selection signal selb of the nth row to a high level. In addition, in the cycle from timing T30 to timing T33, the vertical scanning circuit 211 sets the subsequent stage reset signal rstb of the nth row to a high level.

[0228] From time T30 to the pulse period, the vertical scanning circuit 211 supplies the high-level FD reset signal rst to the nth row. Then, the vertical scanning circuit 211 supplies the high-level selection signal Φ1 to the nth row in the period from time T31 to time T32. As a result, the reset level is maintained.

[0229] The vertical scanning circuit 211 supplies the high-level subsequent-stage reset signal rstb to the n-th row in the pulse period from the timing T34 , and supplies the high-level selection signal Φ1 to the n-th row in the period from the timing T35 to the timing T36 .

[0230] DAC 213 gradually decreases the ramp signal Rmp in the time period from immediately after timing T35 to timing T36. ADC 261 compares the ramp signal Rmp with the level of the vertical signal line 309, and counts the count value until the comparison result is inverted. Therefore, the P phase level (reset level) is read. Then, the differential calculation circuit 263 calculates the difference between the signal level D2 and the reset level. In the sensing mode, since a plurality of D phase levels (signal levels) are read, the drive of the second embodiment is called DDP drive.

[0231] As shown in the figure, when switching to the normal imaging mode, the solid-state imaging element 200 only reads the reset level. Therefore, compared with the first embodiment in which both the reset level and the signal level are read, the amount of communication between the pixel 300 and the column signal processing circuit 260 can be reduced. Therefore, the frame rate can be increased.

[0232] Fig.21 2 is a diagram for explaining the operation of the difference calculation circuit 263 according to the second embodiment of the present technology.

[0233] In the sensing mode, the differential calculation circuit 263 holds the signal level D1 in a memory or the like. Then, the differential calculation circuit 263 calculates the difference (D2) between the sum of the signal levels D1 and D2 and the held signal level D1. The differential calculation circuit 263 holds the signal level D2 in a memory or the like, calculates the difference between the signal level D2 and the held signal level D1, and outputs the difference.

[0234] In the normal image pickup mode, the difference calculation circuit 263 calculates the difference between the hold signal level D2 and the reset level.

[0235] Furthermore, in the manual image pickup mode, the difference calculation circuit 263 holds the reset level in a memory, etc. Then, the difference calculation circuit 263 calculates and outputs the difference between the signal level and the held reset level.

[0236] Note that each of the first, second, and third modifications of the first embodiment can be applied to the second embodiment.

[0237] As described above, according to the second embodiment of the present technology, since the solid-state imaging element 200 reads only the reset level when switching to the normal imaging mode, the frame rate can be increased compared to the first embodiment.

[0238] <3. Third Embodiment>

[0239] In the first embodiment described above, even exposure starts after odd exposure ends, but in this configuration, it is difficult to further increase the frame rate. The solid-state imaging element 200 in the third embodiment differs from the solid-state imaging element in the first embodiment in that the exposure periods of two pixels partially overlap.

[0240] Fig. 22 3 is a circuit diagram showing a configuration example of two pixels according to a third embodiment of the present technology. The two pixels include a front-stage circuit 310, capacitance elements 321 and 322, a selection circuit 330, a rear-stage reset transistor 341, and a rear-stage circuit 350.

[0241] The previous-stage circuit 310 includes photoelectric conversion elements 311 - 1 and 311 - 2 , transfer transistors 312 - 1 and 312 - 2 , an FD reset transistor 313 , an FD 314 , a previous-stage amplifier transistor 315 , and a current source transistor 316 .

[0242] The transfer transistor 312-1 transfers charge from the photoelectric conversion element 311-1 to the FD 314 according to the transfer signal trg1 from the vertical scanning circuit 211. The transfer transistor 312-2 transfers charge from the photoelectric conversion element 311-2 to the FD 314 according to the transfer signal trg2 from the vertical scanning circuit 211.

[0243] The circuit configuration of the subsequent stage of the transfer transistors 312 - 1 and 312 - 2 is similar to that of the first embodiment.

[0244] In addition, a part of the exposure period of the photoelectric conversion element 311-1 overlaps with the exposure period of the photoelectric conversion element 311-2. The details of the exposure control of these elements will be described later. Note that the photoelectric conversion elements 311-1 and 311-2 are examples of the first photoelectric conversion element and the second photoelectric conversion element described in the claims.

[0245] As shown in the figure, by sharing the FD 314 by two pixels, the circuit scale of each pixel can be reduced. It should be noted that the FD 314 is shared by two pixels, but may be shared by three or more pixels (four pixels or eight pixels).

[0246] Fig.23 : is a timing chart showing an example of a global shutter operation when a sensing mode is set according to the third embodiment of the present technology.

[0247] At timing T0 immediately before the exposure period of all pixels, the vertical scanning circuit 211 sets the post-stage reset signal rstb of all rows (in other words, all pixels) to a high level. In addition, the vertical scanning circuit 211 provides the high-level FD reset signal rst and the transfer signals trg1 and trg2 to all pixels in the period from time T0 to time T1. Therefore, all pixels are reset by PD, and exposure starts simultaneously in all rows.

[0248] The exposure period of one of the two pixels sharing the FD 314 partially overlaps with the exposure period of the other pixel. In the example of the drawing, timings T1 to T3 correspond to the exposure period of one of the two pixels, and timings T1 to T6 correspond to the exposure period of the other pixel.

[0249] At timing T0 immediately before the exposure period, the vertical scanning circuit 211 sets the post-stage reset signal rstb of all pixels to a high level. In addition, the vertical scanning circuit 211 provides the high-level FD reset signal rst and the transfer signals trg1 and trg2 to all pixels in the period from time T0 to time T1. Therefore, all pixels are reset by PD, and exposure starts simultaneously in all rows.

[0250] Then, at the timing T2 immediately before the end of the shorter exposure period, the vertical scanning circuit 211 supplies the high-level FD reset signal rst over the pulse period. Therefore, one of the two pixels sharing the FD 314 is FD reset.

[0251] At the exposure end time T3 in the shorter exposure period, the vertical scanning circuit 211 provides the high-level transfer signal trg1 in the pulse period, and sets the selection signal Φ1 to the high level in all pixels. As a result, the signal level Vsig1 corresponding to the exposure amount is sampled and held in one of the two pixels. At the timing T4 after the timing T3, the vertical scanning circuit 211 returns the selection signal Φ1 to the low level.

[0252] Then, at timing T5 immediately before the end of the long exposure period, the vertical scanning circuit 211 supplies a high-level FD reset signal rst over a pulse period. As a result, the other of the two pixels sharing the FD 314 is reset.

[0253] At the exposure end timing T6 in the longer exposure period, the vertical scanning circuit 211 provides the high-level transfer signal trg1 in the pulse period, and at the same time sets the selection signal Φ2 to the high level in all pixels. As a result, the signal level Vsig2 corresponding to the exposure amount is sampled and held in the other of the two pixels. At the timing T7 after the timing T6, the vertical scanning circuit 211 returns the selection signal Φ2 to the low level.

[0254] The control of the reading cycle in the sensing mode in the third embodiment is similar to the control of the reading cycle in the first embodiment. During the reading cycle, one signal level Vsig1 and another signal level Vsig2 of two pixels sharing the FD are read. The digital signal processing section 262 determines whether to switch to the normal imaging mode based on the difference between the signal levels.

[0255] Here, since the exposure time of one of the two pixels sharing the FD is different from the exposure time of the other pixel, a difference occurs in the exposure amount of each of the two pixels regardless of the presence or absence of movement of the object. However, when the shorter exposure time is Ta, the difference in exposure time is dT, and dT / Ta is sufficiently reduced, when the illuminance is relatively low, the difference in exposure amount is reduced to a negligible level.

[0256] It should be noted that the digital signal processing section 262 may also correct the signal level of one of the two pixels according to the difference between the exposure amounts of the two pixels. In this case, for example, the shorter the exposure time may be, Ta, and the longer the exposure time may be, Tb, and it is only necessary to multiply the signal level of the shorter exposure time by Tb / Ta, or it is only necessary to multiply the signal level of the longer exposure time by Ta / Tb. After this correction, the mode is controlled based on the difference in the signal level.

[0257] As shown in the figure, since a part of the exposure period of one of the two pixels sharing the FD overlaps with the exposure period of the other, the frame rate can be increased compared with the first embodiment.

[0258] Fig.24 : is a timing chart showing an example of a global shutter operation when the mode is switched to the normal imaging mode according to the third embodiment of the present technology.

[0259] At timing T20, the vertical scanning circuit 211 sets the post-stage reset signal rstb of all pixels to a high level. In addition, the vertical scanning circuit 211 provides the high-level FD reset signal rst and the transfer signals trg1 and trg2 to all pixels during the period from time T20 to time T21. Therefore, all pixels are reset by PD, and exposure starts simultaneously in all rows.

[0260] At timing T22 immediately before the end of exposure, the vertical scanning circuit 211 provides a high-level FD reset signal rst within the pulse period, and sets the selection signal Φ1 to a high level in all pixels. Therefore, all pixels are reset by FD, and the reset level is sampled and held. At timing T23 after timing T22, the vertical scanning circuit 211 returns the selection signal Φ1 to a low level.

[0261] At the exposure end time T24, the vertical scanning circuit 211 provides high-level transfer signals trg1 and trg2 during the pulse, and sets the selection signal Φ2 to a high level in all pixels. As a result, the signal level is sampled and held. In addition, the level of the previous node 320 is reduced from the reset level to the signal level. At the time T25 after the time T24, the vertical scanning circuit 211 returns the selection signal Φ2 to a low level.

[0262] As shown in the figure, since the transmission signals trg1 and trg2 are supplied at the same time, the two pixels sharing the FD 314 are subjected to pixel addition. This is because, in the case where the FD 314 is shared by two pixels, there are only two capacitive elements per two pixels, and only one reset level and one signal level can be sampled and held. As a result, the resolution of the image data is halved compared to the first embodiment in which the FD 314 is not shared.

[0263] The control during reading in the normal imaging mode in the third embodiment is similar to the control during reading in the first embodiment.

[0264] Note that the first, second, and third modifications of the first embodiment as well as the second embodiment can be applied to the third embodiment.

[0265] As described above, according to the third embodiment of the present technology, the frame rate can be increased because the exposure periods of two pixels sharing the FD 314 overlap each other. In addition, because the FD 314 is shared by two pixels, the circuit scale of each pixel can be reduced.

[0266] <4. Fourth Embodiment>

[0267] In the first embodiment described above, the solid-state imaging element 200 is Figures 9 to 13 The driving method shown drives pixels, but is not limited to this driving method. The solid-state imaging element 200 of the fourth embodiment is different from the solid-state imaging element 200 of the first embodiment in that the timing of resetting the subsequent stage node is different.

[0268] Fig.25 is a timing chart showing an example of a global shutter operation according to a fourth embodiment of the present technology. The drawing shows control in an exposure period other than a sensing mode.

[0269] In the fourth embodiment, at the timing T2 when the FD reset signal rst is controlled to be high level, the subsequent stage reset signal rstb is controlled to be high level. Similarly, in the exposure period of the sensing mode, when the FD reset signal rst is controlled to be high level, the subsequent stage reset signal rstb is controlled to be high level.

[0270] In the sensing mode, since the subsequent node 340 is initialized after reading the odd signal level D1, the subsequent node 340 becomes D2 instead of D1+D2 in the even reading. Therefore, the differential calculation circuit 263 does not need to hold D1, and the configuration of the differential calculation circuit 263 can be simplified.

[0271] Fig.26 : is a timing chart showing an example of a reading operation according to a fourth embodiment of the present technology. The drawing shows control in a reading period other than the sensing mode.

[0272] In the fourth embodiment, the subsequent reset signal rstb is supplied in the pulse period from the timing T14 immediately after the timing T13 of reading the reset level. Similarly, in the sensing mode, the subsequent reset signal rstb is supplied from the timing immediately after the timing of reading the first signal level in the pulse period.

[0273] Note that the solid-state imaging element 200 reads the signal level after the reset level, but is not limited to this order. Fig. 27 As shown, the solid-state imaging element 200 can also read the reset level after the signal level. In this case, as shown in the figure, the vertical scanning circuit 211 provides a high-level selection signal Φ1 after the high-level selection signal Φ2. In addition, in this case, the gradient of the slope of the ramp signal must be reversed.

[0274] As described above, according to the fourth embodiment of the present technology, the pixel can be driven by a driving method different from that of the first embodiment.

[0275] [First Modification]

[0276] In the above-mentioned fourth embodiment, the front-stage circuit 310 reads the signal while being connected to the front-stage node 320, but with this configuration, the noise from the front-stage node 320 cannot be cut off when reading. The pixel 300 according to the first variant of the fourth embodiment is different from the pixel 300 of the fourth embodiment in that a transistor is inserted between the front-stage circuit 310 and the front-stage node 320.

[0277] Fig.28 : is a circuit diagram showing a configuration example of a pixel 300 in a first variant of the fourth embodiment of the present technology. The pixel 300 according to the first variant of the fourth embodiment is different from the pixel 300 of the fourth embodiment in that it further includes a front-stage reset transistor 323 and a front-stage selection transistor 324. In addition, the power supply voltage of the front-stage circuit 310 and the rear-stage circuit 350 of the first variant of the fourth embodiment is VDD1.

[0278] The previous stage reset transistor 323 initializes the level of the previous stage node 320 with the power supply voltage VDD2. It is desirable to set the power supply voltage VDD2 to a value satisfying the following formula.

[0279] VDD2 = VDD1 - Vgs...Equation 1

[0280] In the above formula, Vgs represents the gate-source voltage of the pre-stage amplifier transistor 315 .

[0281] By setting the value to a value satisfying Formula 1, the potential fluctuation between the previous stage node 320 and the next stage node 340 in darkness can be reduced. Therefore, the photo response non-uniformity (PRNU) can be improved.

[0282] The previous stage selection transistor 324 opens and closes a path between the previous stage circuit 310 and the previous stage node 320 according to the previous stage selection signal sel from the vertical scanning circuit 211 .

[0283] Fig.291 is a timing diagram showing an example of global shutter operation in the first variant of the fourth embodiment of the present technology. The accompanying drawings show controls other than the sensing mode. The timing diagram of the first variant of the fourth embodiment differs from the timing diagram of the fourth embodiment in that the vertical scanning circuit 211 also provides a front-stage reset signal rsta and a front-stage selection signal sel. In the accompanying drawings, rsta_[n] and sel_[n] indicate signals to pixels in the nth row.

[0284] The vertical scanning circuit 211 supplies the high-level previous-stage selection signal sel to all pixels in the period from the timing T2 immediately before the end of exposure to the time T5. The previous-stage reset signal rsta is controlled to be low level.

[0285] Fig.30 1 is a timing diagram showing an example of a read operation in a first variant of the fourth embodiment of the present technology. The accompanying drawings show controls other than the sensing mode. When reading each row, the front-stage selection signal sel is controlled to a low level. This control causes the front-stage selection transistor 324 to enter a disconnected state to disconnect the front-stage node 320 from the front-stage circuit 310. Therefore, noise from the front-stage node 320 can be blocked when reading.

[0286] Furthermore, in the reading period of the n-th row from the timing T10 to the timing T17 , the vertical scanning circuit 211 supplies the high-level previous-stage reset signal rsta to the n-th row.

[0287] Furthermore, during reading, the vertical scanning circuit 211 controls the current source transistors 316 of all pixels to stop supplying the current id1. The current id2 is supplied in the same manner as in the fourth embodiment. As described above, the control of the current id1 is simplified compared to the fourth embodiment.

[0288] As described above, according to the first modification of the fourth embodiment of the present technology, the previous stage selection transistor 324 turns to the off state at the time of reading, and the previous stage circuit 310 is disconnected from the previous stage node 320 , so that noise from the previous stage circuit 310 can be cut off.

[0289] [Second Modification]

[0290] In the fourth embodiment described above, the circuit in the solid-state imaging element 200 is arranged in a single semiconductor chip. However, with this configuration, there is a possibility that the element may not fit in the semiconductor chip when the pixel 300 is miniaturized. The solid-state imaging element 200 according to the second modification of the fourth embodiment is different from the solid-state imaging element 200 of the fourth embodiment in that the circuit in the solid-state imaging element 200 is dispersedly arranged on two semiconductor chips.

[0291] Fig.311 is a diagram showing an example of a stacked structure of a solid-state imaging element 200 in a second modification of the fourth embodiment of the present technology. The solid-state imaging element 200 according to the second modification of the fourth embodiment includes a circuit chip 201 and a pixel chip 201 stacked on the circuit chip 201. These chips are electrically connected by, for example, Cu-Cu bonding. Note that in addition to Cu-Cu bonding, vias or bumps can also be used for connection.

[0292] The upper pixel array section 221 is provided on the circuit chip 201. In the pixel chip 202, a lower pixel array section 222 and a column signal processing circuit 260 are provided. For each pixel in the pixel array section 220, a part of the pixels are provided in the upper pixel array section 221, and the remaining pixels are provided in the lower pixel array section 222.

[0293] Furthermore, in the circuit chip 202, a vertical scanning circuit 211, a timing control circuit 212, a DAC 213, and a load MOS circuit block 250 are also arranged. These circuits are not shown in the figure.

[0294] Furthermore, the pixel chip 201 is manufactured, for example, by a pixel-dedicated process, and the circuit chip 202 is manufactured, for example, by a complementary MOS (CMOS) process.

[0295] Fig.32 is a circuit diagram showing a configuration example of a pixel 300 in a second variant of the fourth embodiment of the present technology. In the pixel 300, the pre-stage circuit 310 is arranged on the pixel chip 201, and other circuits and elements (such as capacitor elements 321 and 322) are arranged on the circuit chip 202. Note that the current source transistor 316 may be further provided in the circuit chip 202. As shown in the figure, by dispersively arranging the elements in the pixel 300 on the stacked pixel chip 201 and the circuit chip 202, the area of ​​the pixel can be reduced, and the miniaturization of the pixel is facilitated.

[0296] As described above, according to the second modification example of the fourth embodiment of the present technology, since the circuits and elements in the pixel 300 are dispersedly arranged on two semiconductor chips, miniaturization of the pixel is facilitated.

[0297] [Third Modification]

[0298] In the second modification of the fourth embodiment described above, a part of the pixel 300 and the peripheral circuits (such as the column signal processing circuit 260) are provided in the lower circuit chip 202. However, with this configuration, the arrangement area of ​​the circuits and elements on the circuit chip 202 side is larger than the arrangement area of ​​the pixel chip 201 by the peripheral circuits, and there is a possibility that an unnecessary space without the circuits and elements is generated in the pixel chip 201. The solid-state imaging element 200 according to the third modification of the fourth embodiment is different from the second modification of the fourth embodiment in that the circuits in the solid-state imaging element 200 are dispersedly arranged on three semiconductor chips.

[0299] Fig.33 1 is a diagram showing an example of a stacked structure of a solid-state imaging element 200 in a third modification of the fourth embodiment of the present technology. The solid-state imaging element 200 according to the third modification of the fourth embodiment includes an upper pixel chip 203, a lower pixel chip 204, and a circuit chip 202. These chips are stacked and electrically connected by, for example, Cu-Cu bonding. Note that in addition to Cu-Cu bonding, vias or bumps can also be used for connection.

[0300] The upper pixel array section 221 is provided in the upper pixel chip 203. The lower pixel array section 222 is provided in the lower pixel chip 204. For each pixel in the pixel array section 220, a part of the pixels are provided in the upper pixel array section 221, and the remaining pixels are provided in the lower pixel array section 222.

[0301] Furthermore, in the circuit chip 202, a column signal processing circuit 260, a vertical scanning circuit 211, a timing control circuit 212, a DAC 213, and a load MOS circuit block 250 are arranged. Circuits other than the column signal processing circuit 260 are not shown in the drawing.

[0302] Compared to a two-layer configuration, adopting the three-layer configuration shown in the drawings allows for reduction of unnecessary space and allows for further pixel miniaturization. In addition, the lower pixel chip 204 as the second layer can be manufactured by a dedicated process for capacitors and switches.

[0303] As described above, in the third modification of the fourth example of the present technology, since the circuits in the solid-state imaging element 200 are dispersedly arranged on three semiconductor chips, the pixels can be further miniaturized compared to the case where the circuits are dispersedly arranged on two semiconductor chips.

[0304] <5. Fifth embodiment>

[0305] In the fourth embodiment described above, the reset level is sampled and held during the exposure period, but in this configuration, the exposure period cannot be made shorter than the sampling and holding period of the reset level. The solid-state imaging element 200 according to the fifth embodiment is different from the solid-state imaging element of the first embodiment in that a transistor that releases charge from the photoelectric conversion element is added to make the exposure period shorter.

[0306] Fig.34 3 is a circuit diagram showing a configuration example of a pixel 300 according to a fifth embodiment of the present technology. The pixel 300 of the fifth embodiment is different from the pixel 300 of the fourth embodiment in that a discharge transistor 317 is further provided in the previous stage circuit 310 .

[0307] The discharge transistor 317 functions as an overflow drain that discharges electric charge from the photoelectric conversion element 311 in accordance with a discharge signal ofg from the vertical scanning circuit 211. As the discharge transistor 317, for example, an nMOS transistor is used.

[0308] In the configuration in which the discharge transistor 317 is not provided in the fourth embodiment, blooming may occur for all pixels when the charge is transferred from the photoelectric conversion element 311 to the FD 314. Then, at the time of FD reset, the potential of the FD 314 and the potential of the previous node 320 drop. In response to the potential drop, the charging current and the discharging current of the capacitor elements 321 and 322 continue to occur, and the IR drop in the power supply or the ground changes from a stable state without blooming.

[0309] On the other hand, when the signal levels of all pixels are sampled and held, after the transfer of the signal charge, the photoelectric conversion element 311 has no charge, so that blooming does not occur, and the IR drop in the power supply or ground enters a stable state without blooming. Due to the difference in IR drop when sampling and holding the reset level and the signal level, tail noise occurs.

[0310] On the other hand, in the fifth embodiment in which the discharge transistor 317 is provided, the charge in the photoelectric conversion element 311 is discharged to the overflow drain side. Therefore, the IR drop and the signal level when sampling and holding the reset level become almost the same, so that the tail noise can be suppressed.

[0311] Fig.35 1 is a timing diagram showing an example of global shutter operation according to the fifth embodiment of the present technology. At timing T0 before starting exposure, the vertical scanning circuit 211 provides a high-level FD reset signal rst to all pixels during the pulse, and at the same time sets the discharge signal ofg to a high level for all pixels. Therefore, PD reset and FD reset are performed on all pixels. In addition, the reset level is sampled and held. Here, g_[n] in the figure represents a signal to a pixel in the nth row of N rows.

[0312] Then, at the timing T1 as the start of exposure, the vertical scanning circuit 211 returns the discharge signal ofg to the low level for all pixels. Then, the vertical scanning circuit 211 supplies the high-level transfer signal trg to all pixels in the period from the timing T2 immediately before the end of exposure to the timing T3 as the end of exposure. As a result, the signal level is sampled and held.

[0313] In a configuration where the discharge transistor 317 is not provided as in the fourth embodiment, both the transfer transistor 312 and the FD reset transistor 313 need to be turned on at the start of exposure (i.e., at the time of PD reset). Under this control, the FD 314 also needs to be reset at the time of PD reset. Therefore, it is necessary to perform FD reset again within the exposure period to sample and hold the reset level so that the exposure period cannot be made shorter than the sampling and holding period of the reset level. When the reset levels of all pixels are sampled and held, a certain waiting time is required until the voltage and current are stabilized, and, for example, a sampling and holding period of several microseconds (μs) to tens of microseconds (μs) is required.

[0314] On the other hand, in the fifth embodiment in which the discharge transistor 317 is provided, the PD reset and the FD reset can be performed separately from each other. Therefore, as shown in the figure, the reset level can be sampled and held by performing the FD reset before the cancellation of the PD reset (the start of exposure). Therefore, the exposure period can be made shorter than the sampling and holding period of the reset level.

[0315] Furthermore, the first to third modified examples of the fourth embodiment can also be applied to the fifth embodiment.

[0316] As described above, according to the fifth embodiment of the present technology, the discharge transistor 317 that discharges charge from the photoelectric conversion element 311 is provided, so that the reset level can be sampled and held by performing FD reset before starting exposure. Therefore, the exposure period can be made shorter than the sampling and holding period of the reset level.

[0317] <6. Sixth Implementation Method>

[0318] In the fourth embodiment described above, the FD 314 is initialized by the power supply voltage VDD. However, in this configuration, there is a possibility that the photoresponse non-uniformity (PRNU) deteriorates due to variations in the capacitance elements 321 and 322 and the parasitic capacitance. The solid-state imaging element 200 of the sixth embodiment is different from the solid-state imaging element 200 of the fourth example in that the PRNU is improved by reducing the power supply of the FD reset transistor 313 at the time of reading.

[0319] Fig.362 is a circuit diagram showing a configuration example of a pixel 300 according to a sixth embodiment of the present technology. The pixel 300 of the sixth embodiment is different from the pixel of the fourth embodiment in that the power supply of the FD reset transistor 313 is separated from the power supply voltage VDD of the pixel 300 .

[0320] The drain of the FD reset transistor 313 of the sixth embodiment is connected to a reset power supply voltage VRST. The reset power supply voltage VRST is controlled by, for example, the timing control circuit 212.

[0321] Here, we will refer to Fig.37 and 38 Consider the degradation of PRNU in the pixel 300 of the fourth embodiment. These figures show control other than the sensing mode. In the fourth embodiment, as Fig.37 As shown, at the timing T0 immediately before the exposure start time, the potential of the FD 314 decreases due to the reset feedthrough of the FD reset transistor 313. This change amount is set as Vft.

[0322] In the fourth embodiment, since the power supply voltage of the FD reset transistor 313 is VDD, the potential of the FD 314 changes from VDD to VDD-Vft at timing T0. In addition, the potential of the previous stage node 320 when exposed is VDD-Vft-Vgs.

[0323] Furthermore, in the fourth embodiment, if Fig.37 As shown in FIG. 3 , the FD reset transistor 313 is turned to the on state at the time of reading, and the FD 314 is fixed to the power supply voltage VDD. Due to the change Vft of the FD 314, the potential of the previous stage node 320 and the potential of the next stage node 340 are higher than approximately Vft at the time of reading. However, due to the change in the capacitance value or parasitic capacitance of the capacitance elements 321 and 322, the offset voltage amount varies for each pixel, which causes PRNU degradation.

[0324] The shift amount of the subsequent node 340 when the previous node 320 is shifted by Vft is expressed by, for example, the following formula.

[0325] {(Cs+δCs) / (Cs+δCs+Cp)}*Vft...Formula 2

[0326] In the above formula, Cs is the capacitance value of the capacitance element 322 on the signal level side, and δCs is the change in Cs. Cp is the capacitance value of the parasitic capacitance of the subsequent-stage node 340.

[0327] Formula 2 can be approximated by the following formula.

[0328] {1-(δCs / Cs)*(Cp / Cs)}*Vft...Formula 3

[0329] According to Formula 3, the change of the subsequent node 340 can be expressed by the following formula.

[0330] {(δCs / Cs)*(Cp / Cs)}*Vft...Formula 4

[0331] When (δCs / Cs) is set to 10 -2 , (Cp / Cs) is set to 10 -1 And when Vft is set to 400 millivolts (mV), according to Formula 4, PRNU is 400 μVrms, which is a relatively large value.

[0332] Specifically, in order to reduce the kTC noise when sampling and holding the input conversion capacitance, it is necessary to increase the charge-to-voltage conversion efficiency of FD 314. In order to increase the charge-to-voltage conversion efficiency, it is necessary to reduce the capacitance of FD 314, but the smaller the capacitance of FD 314, the greater the change Vft (which can be several hundred millivolts (mV)). In this case, according to Formula 4, the impact of PRNU may become too large to be ignored.

[0333] Fig.39 is a timing chart showing an example of voltage control according to the sixth embodiment of the present technology. The drawing shows control other than the sensing mode.

[0334] The timing control circuit 212 performs control so that the reset power supply voltage VRST during the row-by-row reading after the timing T9 is different from the reset power supply voltage VRST during the exposure period.

[0335] For example, for the exposure period, the timing control circuit 212 sets the reset power supply voltage VRST to be the same as the power supply voltage VDD. On the other hand, during the reading period, the timing control circuit 212 reduces the reset power supply voltage VRST to VDD-Vft. That is, during the reading period, the timing control circuit 212 reduces the reset power supply voltage VRST by an amount substantially equal to the change Vft caused by the reset feedthrough. This control allows the reset level of the FD 314 at the time of exposure and the reset level at the time of reading to be the same as each other.

[0336] As shown in the figure, controlling the reset power supply voltage VRST allows reduction of voltage variation of the FD 314 and the previous-stage node 320. Therefore, variation of the capacitance elements 321 and 322 and PRNU degradation due to parasitic capacitance can be suppressed.

[0337] Furthermore, the first to third modifications of the fourth embodiment and the fifth embodiment can also be applied to the sixth embodiment.

[0338] As described above, according to the sixth embodiment of the present technology, the timing control circuit 212 reduces the reset power supply voltage VRST by the change amount Vft caused by the reset feedthrough during reading so that the reset level during exposure and the reset level during reading can be equal to each other. Therefore, it is possible to suppress the degradation of the photoresponse non-uniformity (PRNU).

[0339] <7. Seventh Implementation Method>

[0340] In the above-mentioned fourth embodiment, in modes other than the sensing mode, the signal level is read next to the reset level for each frame. However, in this configuration, there is a possibility that the light response non-uniformity (PRNU) deteriorates due to the variation or parasitic capacitance of the capacitor elements 321 and 322. The solid-state imaging element 200 of the seventh embodiment is different from the solid-state imaging element 200 of the fourth embodiment in that the PRNU is improved by switching the level held in the capacitor element 321 and the level held in the capacitor element 322 for each frame.

[0341] The solid-state imaging element 200 according to the seventh embodiment continuously images a plurality of frames in synchronization with a vertical synchronization signal in a mode other than a sensing mode (such as a normal imaging mode). An odd-numbered frame is referred to as an "odd-numbered frame", and an even-numbered frame is referred to as an "even-numbered frame". Note that an odd-numbered frame and an even-numbered frame are examples of a pair of frames described in the claims.

[0342] Fig.40 1 is a timing diagram showing an example of global shutter operation of an odd-numbered frame in the seventh embodiment. The accompanying drawings show control other than the sensing mode. The front-stage circuit 310 in the solid-state imaging element 200 sets the selection signal Φ2 to a high level next to the selection signal Φ1 during the exposure period of the odd-numbered frame, thereby maintaining the capacitor element 321 at a reset level, and then maintaining the capacitor element 322 at a signal level.

[0343] Fig.41 1 is a timing diagram showing an example of the read operation of the odd frame according to the seventh embodiment of the present technology. The subsequent circuit 350 in the solid-state imaging element 200 sets the selection signal Φ2 to a high level next to the selection signal Φ1, and reads the signal level next to the reset level in the read cycle of the odd frame.

[0344] Fig.42 1 is a timing diagram illustrating an example of global shutter operation of an even-numbered frame in the seventh embodiment. The front-stage circuit 310 in the solid-state imaging element 200 sets the selection signal Φ1 followed by the selection signal Φ2 to a high level during the exposure period of the even-numbered frame, thereby maintaining the capacitor element 322 at a reset level, and then maintaining the capacitor element 321 at a signal level.

[0345] Fig.431 is a timing chart showing an example of the reading operation of the even-numbered frame according to the seventh embodiment of the present technology. The subsequent circuit 350 in the solid-state imaging element 200 sets the selection signal Φ1 to a high level next to the selection signal Φ2, and reads a signal level next to the reset level in the reading cycle of the even-numbered frame.

[0346] like Fig.40 and 42 As shown, the levels held in the capacitor elements 321 and 322 are inverted between the even frame and the odd frame. This also inverts the polarity of the PRNU between the even frame and the odd frame. The column signal processing circuit 260 in the subsequent stage obtains the average value of the odd frame and the even frame. Therefore, it is possible to eliminate the PRNU with the opposite polarity.

[0347] This control is effective when capturing moving images or accumulating frames. In addition, it is not necessary to add elements to the pixel 300, and it can be realized only by changing the drive system.

[0348] In addition, the first to third modified examples of the fourth embodiment, the fifth embodiment, and the sixth embodiment can also be applied to the seventh embodiment.

[0349] As described above, in the seventh embodiment of the present technology, in a mode other than the sensing mode, the level held in the capacitor 321 and the level held in the capacitor 322 are inverted between the odd frame and the even frame. Therefore, the polarity of the PRNU can be inverted between the odd frame and the even frame. The column signal processing circuit 260 adds the odd frame and the even frame, so that the PRNU degradation can be suppressed.

[0350] <8. Eighth Implementation Method>

[0351] In the fourth embodiment described above, the vertical scanning circuit 211 performs control (i.e., global shutter operation) to expose all rows (all pixels) at the same time. However, in the case where simultaneity of exposure is not required but low noise is required, such as when testing or analyzing, it is desirable to perform a rolling shutter operation. The solid-state imaging element 200 of the eighth embodiment is different from the solid-state imaging element 200 of the fourth embodiment in that a rolling shutter operation is performed when testing, etc.

[0352] Fig.44 2 is a timing chart showing an example of the rolling shutter operation according to the eighth embodiment of the present technology. The vertical scanning circuit 211 performs control to sequentially select a plurality of rows and start exposure. This figure shows exposure control of the n-th row.

[0353] During the period from timing T0 to T2, the vertical scanning circuit 211 provides a high-level subsequent selection signal selb, a selection signal Φ1, and a selection signal Φ2 to the nth row. In addition, at timing T0 as the start of exposure, the vertical scanning circuit 211 provides a high-level FD reset signal rst and a high-level subsequent reset signal rstb to the nth row within a pulse period. At timing T1 as the end of exposure, the vertical scanning circuit 211 supplies a transfer signal trg to the nth row. The rolling shutter operation in the figure allows the solid-state imaging element 200 to produce low-noise image data.

[0354] Note that the solid-state imaging element 200 of the eighth embodiment performs the global shutter operation similarly to the fourth embodiment except for the timing of the test.

[0355] Furthermore, the first to third modified examples of the fourth embodiment and the fifth to seventh embodiments can also be applied to the eighth embodiment.

[0356] As described above, according to the eighth embodiment of the present technology, the vertical scanning circuit 211 performs control (ie, rolling shutter operation) to sequentially select a plurality of rows and start exposure, and therefore, low-noise image data can be generated.

[0357] <9. Ninth Implementation Method>

[0358] In the above-mentioned fourth embodiment, the source of the front-stage source follower (the front-stage amplifier transistor 315 and the current source transistor 316) is connected to the power supply voltage VDD, and reading is performed row by row in the state where the source follower is turned on. However, there is a possibility that the driving method causes the circuit noise of the front-stage source follower to propagate to the subsequent stage when reading row by row, and the random noise increases accordingly. The solid-state imaging element 200 of the ninth embodiment is different from the solid-state imaging element of the fourth embodiment in that the noise is reduced by disconnecting the front-stage source follower during reading.

[0359] Fig.45 1 is a block diagram showing a configuration example of a solid-state imaging element 200 according to a ninth embodiment of the present technology. The solid-state imaging element 200 of the ninth embodiment differs from the solid-state imaging element of the fourth embodiment in that a regulator 420 and a switching section 440 are further included. In addition, in the pixel array section 220 of the ninth embodiment, a plurality of effective pixels 301 and a predetermined number of virtual pixels 430 are arranged. The virtual pixels 430 are arranged around the area where the effective pixels 301 are arranged.

[0360] In addition, the power supply voltage VDD is supplied to each dummy pixel 430, and the power supply voltage VDD and the source voltage Vs are supplied to each effective pixel 301. The figure does not show a signal line for supplying the power supply voltage VDD to the effective pixel 301. In addition, the power supply voltage VDD is supplied from the pad 410 located outside the solid-state imaging element 200.

[0361] The regulator 420 generates a constant generated voltage V based on the input voltage Vi from the virtual pixel 430. gen , and will generate a voltage V gen The switching section 440 selects the power supply voltage VDD from the pad 410 or the generated voltage VDD from the regulator 420. gen , and supplies the selected voltage as the source voltage Vs to each of the columns of the effective pixels 301.

[0362] Fig.46 1 is a circuit diagram showing a configuration example of a virtual pixel 430, a regulator 420, and a switch 440 according to a ninth embodiment of the present technology. In the drawings, a represents a circuit diagram of a virtual pixel 430 and a regulator 420, and b in the drawings represents a circuit diagram of a switch 440.

[0363] As shown in a of the accompanying drawings, the virtual pixel 430 includes a reset transistor 431, an FD 432, an amplifier transistor 433, and a current source transistor 434. The reset transistor 431 initializes the FD 432 according to the reset signal RST from the vertical scanning circuit 211. The FD 432 accumulates charge and generates a voltage according to the amount of charge. The amplifier transistor 433 amplifies the level of the voltage of the FD 432 and provides the amplified voltage as the input voltage Vi to the regulator 420.

[0364] Furthermore, the FD reset transistor 431 and the amplifier transistor 433 have respective sources connected to the power supply voltage VDD. The current source transistor 434 is connected to the drain of the amplifier transistor 433. The current source transistor 434 supplies the current id1 under the control of the vertical scanning circuit 211.

[0365] The regulator 420 includes a low-pass filter 421, a buffer amplifier 422, and a capacitor 423. The low-pass filter 421 passes a component in a low frequency band below a predetermined frequency in a signal of an input voltage Vi as an output voltage Vj.

[0366] The output voltage Vj is input to the non-inverting input terminal (+) of the buffer amplifier 422. The inverting input terminal (-) of the buffer amplifier 422 is connected to its output terminal. The capacitor element 423 maintains the voltage at the output terminal of the buffer amplifier 422 at V gen . The V genis provided to the switching unit 440 .

[0367] As shown in b in the figure, the switching section 440 includes an inverter 441 and a plurality of switching circuits 442. Each of the switch circuits 442 is provided for a corresponding one of the columns of the effective pixels 301.

[0368] The inverter 441 inverts the switching signal SW sent from the timing control circuit 212. The inverter 441 supplies an inverted signal to each switch circuit 442.

[0369] The switch circuit 442 selects the power supply voltage VDD or the generated voltage V gen , and provides the selected voltage as the source voltage Vs to the corresponding column in the pixel array section 220. The switch circuits 442 each include switches 443 and 444. The switch 443 opens and closes the path between the node of the power supply voltage VDD and the corresponding column according to the switching signal SW. The switch 444 opens and closes the generated voltage V according to the inverted signal of the switch signal SW. gen The path between the nodes and the corresponding columns.

[0370] Fig.47 is a timing diagram showing an example of the operation of the virtual pixel 430 and the regulator 420 according to the ninth embodiment of the present technology. At the timing T10 immediately before reading a specific row, the vertical scanning circuit 211 supplies a high-level reset signal RST (here, the power supply voltage VDD) to each virtual pixel 430. The potential Vfd of the FD 432 in the virtual pixel 430 is initialized to the power supply voltage VDD. Then, when the reset signal RST becomes a low level, the reset feedthrough causes a change to VDD-Vft.

[0371] In addition, the input voltage Vi is reduced to VDD-Vgs-Vsig after reset. By passing through the low-pass filter 421, Vj and V gen becomes an approximately constant voltage.

[0372] After the timing T20 immediately before reading the next row, similar control is performed for each row, and a constant generated voltage V gen .

[0373] Fig.48 : is a circuit diagram showing a configuration example of an effective pixel 301 according to a ninth embodiment of the present technology. The circuit configuration of the effective pixel 301 is similar to that of the pixel 300 of the fourth embodiment, but the source voltage Vs from the switch section 440 is supplied to the source of the pre-stage amplifier transistor 315.

[0374] Fig.491 is a timing diagram showing an example of global shutter operation according to the ninth embodiment of the present technology. In the ninth embodiment, when exposure is performed simultaneously in all pixels, the switching section 440 selects the power supply voltage VDD and provides the power supply voltage VDD as the source voltage Vs. In addition, the voltage of the previous node decreases from VDD-Vgs-Vth to VDD-Vgs-Vsig at timing T4. Here, Vth represents the threshold voltage of the transfer transistor 312.

[0375] Fig.50 1 is a timing chart showing an example of a reading operation according to a ninth embodiment of the present technology. The accompanying drawings show control other than the sensing mode. In the ninth embodiment, when reading, the switching unit 440 selects the power generation voltage V gen and provide a generating voltage V gen , as the source voltage Vs. Power generation voltage V gen is adjusted to VDD-Vgs-Vft. In addition, in the ninth embodiment, the vertical scanning circuit 211 controls the current source transistors 316 of all rows (all pixels) to stop the supply of the current id1.

[0376] Fig.51 3 is a diagram for explaining the effect in the ninth embodiment of the present technology. In the fourth embodiment, during the row-by-row reading, the source follower (the front-stage amplifier transistor 315 and the current source transistor 316) of the pixel 300 to be read is turned on. However, there is a possibility that the driving method causes the circuit noise of the front-stage source follower to propagate to the subsequent stage (the capacitor element, and the rear-stage source follower and ADC), and the read noise increases accordingly.

[0377] For example, in the fourth embodiment, as shown in the figure, the kTC noise generated in the pixel during the global shutter operation is 450 (μVrms). In addition, the noise generated in the previous source follower (pre-stage amplifier transistor 315 and current source transistor 316) during row-by-row reading is 380 (μVrms). The noise generated after the source follower in the subsequent stage is 160 (μVrms). Therefore, the total noise is 610 (μVrms). As described above, in the fourth embodiment, the contribution of the noise of the previous source follower to the total value of the noise becomes relatively large.

[0378] In order to reduce the noise of the front-stage source follower, in the ninth embodiment, as described above, an adjustable voltage (Vs) is supplied to the source of the front-stage source follower. During the global shutter (exposure) operation, the switching section 440 selects the power supply voltage VDD and provides the selected power supply voltage as the source voltage Vs. Then, after the exposure ends, the switching section 440 switches the source voltage Vs to VDD-Vgs-Vft. In addition, the timing control circuit 212 turns on the front-stage current source transistor 316 during the global shutter (exposure) operation, and turns off the front-stage current source transistor 316 after the exposure ends.

[0379] Using the above control, such as Fig.49 and 50 As shown in , the potential of the front-stage node is aligned when the global shutter is operated and when each row is read, and the PRNU can be improved. In addition, since the front-stage source follower is turned off when each row is read, the circuit noise of the source follower does not occur and becomes zero (μVrms), as shown in Fig.51 Note that in the previous source follower, the previous amplifier transistor 315 is in the on state.

[0380] As described above, according to the ninth embodiment of the present technology, since the preceding-stage source follower is turned off at the time of reading, noise generated in the source follower can be reduced.

[0381] <10. Application examples of mobile objects>

[0382] The technology according to the present disclosure (the present technology) can be applied to various products. For example, the technology of the present disclosure can be implemented in the form of a device installed on any kind of mobile body (such as, a car, an electric vehicle, a hybrid electric vehicle, a motorcycle, a bicycle, personal mobility, an airplane, a drone, a ship, or a robot).

[0383] Fig.52 is a block diagram showing a schematic configuration example of a vehicle control system, which is an example of a moving body control system to which the technology according to the present disclosure can be applied.

[0384] The vehicle control system 12000 includes a plurality of electronic control units connected to each other via a communication network 12001. Fig.52 In the example shown, the vehicle control system 12000 includes a drive system control unit 12010, a body system control unit 12020, an external information detection unit 12030, an internal information detection unit 12040, and an integrated control unit 12050. In addition, as a functional structure of the integrated control unit 12050, a microcomputer 12051, a sound / image output unit 12052, and an in-vehicle network interface (I / F) 12053 are exemplified.

[0385] The drive system control unit 12010 controls the operation of devices related to the drive system of the vehicle according to various programs. For example, the drive system control unit 12010 serves as a control device for a drive force generating device (such as an internal combustion engine, a drive motor, etc.) for generating a drive force of the vehicle, a drive force transmitting mechanism for transmitting the drive force to the wheels, a steering mechanism for adjusting the steering angle of the vehicle, a braking device for generating a braking force of the vehicle, and the like.

[0386] The body system control unit 12020 controls the operation of various devices provided on the vehicle body according to various programs. For example, the body system control unit 12020 is used as a control device for a keyless entry system, a smart key system, a power window device, or various lights such as a headlight, a backup light, a brake light, a turn signal, a fog light, etc. In this case, a radio wave transmitted from a mobile device as a substitute for a key or a signal of various switches may be input to the body system control unit 12020. The body system control unit 12020 receives these input radio waves or signals, and controls the door lock device, the power window device, the lights, etc. of the vehicle.

[0387] The vehicle exterior information detection unit 12030 detects information outside the vehicle including the vehicle control system 12000. For example, the vehicle exterior information detection unit 12030 is connected to an imaging unit 12031. The vehicle exterior information detection unit 12030 causes the imaging unit 12031 to capture an image outside the vehicle and receive the captured image. In addition, the vehicle exterior information detection unit 12030 may also detect objects such as people, vehicles, obstacles, signs, and text on the road surface, or detect their distances, based on the received image.

[0388] The imaging unit 12031 is an optical sensor that receives light and outputs an electrical signal corresponding to the amount of light received. The imaging unit 12031 may output the electrical signal as an image, or may output the electrical signal as information about the measured distance. In addition, the light received by the imaging unit 12031 may be visible light, or may be invisible light such as infrared rays.

[0389] The in-vehicle information detection unit 12040 detects information about the interior of the vehicle. The in-vehicle information detection unit 12040 is connected to, for example, a driver state detection unit 12041 that detects the state of the driver. The driver state detection unit 12041 includes, for example, a camera that photographs the driver. Based on the detection information input from the driver state detection unit 12041, the in-vehicle information detection unit 12040 can calculate the driver's fatigue or the driver's concentration, or can determine whether the driver is dozing off.

[0390] The microcomputer 12051 can calculate the control target value of the driving force generation device, the steering mechanism, or the braking device based on the information about the inside or outside of the vehicle obtained by the vehicle exterior information detection unit 12030 or the vehicle interior information detection unit 12040, and output a control command to the drive system control unit 12010. For example, the microcomputer 12051 can perform cooperative control aimed at realizing the functions of the advanced driver assistance system (ADAS), which includes collision prevention or shock absorption for the vehicle, follow-up driving based on the following distance, maintaining the vehicle speed for driving, warning of vehicle collision, warning of vehicle deviation from the lane, etc.

[0391] In addition, the microcomputer 12051 can perform collaborative control for automatic driving by controlling the driving force generating device, steering mechanism, braking device, etc. based on information about outside or inside the vehicle obtained by the outside information detection unit 12030 or the inside information detection unit 12040, thereby enabling the vehicle to travel automatically without relying on the driver's operation, etc.

[0392] In addition, the microcomputer 12051 can output a control command to the body system control unit 12020 based on the information about the outside of the vehicle obtained by the vehicle outside information detection unit 12030. For example, the microcomputer 12051 can perform cooperative control aimed at preventing glare by controlling the headlights to change from high beam to low beam according to the position of the front vehicle or the oncoming vehicle detected by the vehicle outside information detection unit 12030.

[0393] The sound / image output unit 12052 sends an output signal of at least one of sound and image to an output device, which can visually or auditorily notify the occupants of the vehicle or the outside of the vehicle of information. Fig.52 In the example of FIG. 1 , an audio speaker 12061, a display portion 12062, and a dashboard 12063 are shown as output devices. For example, the display portion 12062 may include at least one of an on-board display and a head-up display.

[0394] Fig.53 12031 is a diagram illustrating an example of the installation position of the imaging unit 12031.

[0395] exist Fig.53 In the imaging unit 12031, imaging units 12101, 12102, 12103, 12104 and 12105 are included.

[0396] The imaging units 12101, 12102, 12103, 12104, 12105 are provided, for example, at locations such as the front nose, side mirrors, rear bumper, rear door, and upper portion of the windshield in the interior of the vehicle 12100. The imaging unit 12101 provided at the front nose in the interior of the vehicle and the imaging unit 12105 provided at the upper portion of the windshield mainly obtain images in front of the vehicle 12100. The imaging units 12102 and 12103 provided to the side mirrors mainly obtain images of the sides of the vehicle 12100. The imaging unit 12104 provided to the rear bumper or rear door mainly obtains images of the rear portion of the vehicle 12100. The imaging unit 12105 provided at the upper portion of the windshield in the interior of the vehicle is mainly used to detect vehicles ahead, pedestrians, obstacles, signals, traffic signs, lanes, etc.

[0397] Please note that Fig.53 An example of the shooting range of the image capturing units 12101 to 12104 is shown. Imaging range 12111 represents the imaging range of the imaging unit 12101 set to the front nose. Imaging ranges 12112 and 12113 respectively represent the imaging ranges of the imaging units 12102 and 12103 set to the side mirrors. Imaging range 12114 represents the imaging range of the imaging unit 12104 set to the rear bumper or the rear door. For example, a bird's-eye view image of the vehicle 12100 viewed from above is obtained by superimposing image data imaged by the imaging units 12101 to 12104.

[0398] At least one of the imaging units 12101 to 12104 may have a function of obtaining distance information. For example, at least one of the imaging units 12101 to 12104 may be a stereo camera composed of a plurality of imaging elements, or may be an imaging element having pixels for phase difference detection.

[0399] For example, the microcomputer 12051 can determine the distance to each three-dimensional object within the imaging range 12111 to 12114 and the time change of the distance (relative speed relative to the vehicle 12100) based on the distance information obtained from the imaging units 12101 to 12104, thereby extracting a three-dimensional object that exists on the driving path of the vehicle 12100 and travels at a prescribed speed (for example, equal to or greater than 0 km / hour) in the same direction as the vehicle 12100 as the leading vehicle. In addition, the microcomputer 12051 can pre-set the following distance to keep in front of the leading vehicle, and perform automatic braking control (including follow-up stop control), automatic acceleration control (including follow-up start control), etc. As a result, coordinated control for automatic driving that allows the vehicle to automatically travel without relying on the driver's operation, etc., can be performed.

[0400] For example, the microcomputer 12051 can classify the three-dimensional object data related to the three-dimensional object into three-dimensional object data of a two-wheeled vehicle, a standard vehicle, a large vehicle, a pedestrian, a utility pole, and other three-dimensional objects based on the distance information obtained from the imaging units 12101 to 12104, extract the classified three-dimensional object data, and use the extracted three-dimensional object data for automatic obstacle avoidance. For example, the microcomputer 12051 identifies obstacles around the vehicle 12100 as obstacles that can be visually recognized by the driver of the vehicle 12100 and obstacles that are difficult for the driver of the vehicle 12100 to visually recognize. Then, the microcomputer 12051 determines a collision risk indicating the risk of collision with each obstacle. In the case where the collision risk is equal to or higher than the set value and therefore there is a possibility of collision, the microcomputer 12051 outputs a warning to the driver via the audio speaker 12061 or the display unit 12062, and performs forced deceleration or evasive steering via the drive system control unit 12010. The microcomputer 12051 can thereby assist driving to avoid collisions.

[0401] At least one of the imaging units 12101 to 12104 may be an infrared camera that detects infrared rays. The microcomputer 12051 may, for example, identify a pedestrian by determining whether a pedestrian exists in the captured images of the imaging units 12101 to 12104. This identification of a pedestrian is performed, for example, by a step of extracting feature points in the imaged images of the imaging units 12101 to 12104 as infrared cameras and a step of determining whether it is a pedestrian by performing pattern matching processing on a series of feature points representing the outline of an object. When the microcomputer 12051 determines that a pedestrian exists in the imaged images of the imaging units 12101 to 12104 and thus identifies the pedestrian, the sound / image output unit 12052 controls the display unit 12062 so that a square outline for emphasis is displayed as superimposed on the identified pedestrian. The sound / image output unit 12052 may also control the display unit 12062 so that an icon representing a pedestrian or the like is displayed at a desired position.

[0402] An example of a vehicle control system to which the technology according to the present disclosure can be applied has been described above. The technology according to the present disclosure can be applied to the imaging unit 12031 in the above configuration. Specifically, for example, Figure 1 The imaging device 100 in can be applied to the imaging section 12031. By applying the technology according to the present disclosure to the imaging section 12031, the system can be simplified.

[0403] It should be noted that the above-mentioned embodiments show examples for embodying the present technology, and the matters in the embodiments and the matters specifying the present invention in the claims have a corresponding relationship. Similarly, the matters specifying the present invention in the claims have a corresponding relationship with the matters with the same names in the embodiments of the present technology. However, the present technology is not limited to the embodiments, and can be embodied by applying various modifications to the embodiments without departing from the scope of the present technology.

[0404] It should be noted that the advantageous effects described in this specification are merely examples and are not limiting, and other advantageous effects may be provided.

[0405] It should be noted that the present technology may also have the following configurations.

[0406] (1) A solid-state imaging element comprising:

[0407] A pixel including a front-stage circuit and a pair of capacitor elements, wherein the front-stage circuit sequentially generates a predetermined number of pixel signals;

[0408] a scanning circuit that causes the pair of capacitive elements to maintain respective signal levels of a pair of pixel signals among a predetermined number of pixel signals when a sensing mode is set, and causes the pair of capacitive elements to maintain a reset level and a signal level of any one pixel signal among the predetermined number of pixel signals when a switching from the sensing mode to the normal imaging mode is performed;

[0409] a difference calculation circuit that calculates a difference between respective signal levels of the pair of pixel signals when the sensing mode is set; and

[0410] The mode control section determines whether to switch from the sensing mode to the normal imaging mode based on the difference.

[0411] (2) The solid-state imaging element according to (1), wherein

[0412] The mode control section determines whether to switch from the sensing mode to the normal imaging mode based on a comparison result between the absolute value of the difference and a predetermined threshold value.

[0413] (3) The solid-state imaging element according to (2), further comprising:

[0414] A focus control unit detects the focus position of the lens and moves the lens to the focus position,

[0415] wherein the difference calculation circuit calculates the difference between the signal level before the lens moves to the focus position and the signal level when the lens has moved to the focus position, and

[0416] When the lens has moved to the focus position, the mode control section determines whether to switch from the sensing mode to the normal imaging mode based on a comparison result between the absolute value of the difference and a predetermined threshold value.

[0417] (4) The solid-state imaging device according to any one of (1) to (3) above, wherein:

[0418] The pre-stage circuit includes:

[0419] Photoelectric conversion element;

[0420] a transfer transistor that transfers charges from the photoelectric conversion element to the floating diffusion layer; and

[0421] The front-stage amplifier transistor amplifies the voltage of the floating diffusion layer.

[0422] (5) The solid-state imaging element according to (4), wherein

[0423] When the sensing mode is set, the scanning circuit causes one of the pair of capacitors to maintain a first signal level at the end of odd-numbered exposure and causes the other of the pair of capacitors to maintain a second signal level at the end of even-numbered exposure, and when switching to the normal imaging mode, causes the pair of capacitors to maintain a reset level and a signal level at the end of exposure.

[0424] (6) The solid-state imaging element according to (4), wherein

[0425] When the sensing mode is set, the scanning circuit causes one of the pair of capacitors to maintain a first signal level at the end of odd-numbered exposure and causes the other of the pair of capacitors to maintain a second signal level at the end of even-numbered exposure, and when switching to the normal imaging mode, causes one of the pair of capacitors to maintain a reset level at the end of exposure.

[0426] (7) The solid-state imaging element according to (1), wherein

[0427] The pre-stage circuit includes:

[0428] a first photoelectric conversion element and a second photoelectric conversion element;

[0429] a first transfer transistor that transfers charges from the first photoelectric conversion element to the floating diffusion layer;

[0430] a second transfer transistor that transfers charges from the second photoelectric conversion element to the floating diffusion layer; and

[0431] a front-stage amplifier transistor that amplifies the voltage of the floating diffusion layer; and

[0432] The first photoelectric conversion element and the second photoelectric conversion element have exposure periods that partially overlap each other.

[0433] (8) The solid-state imaging element according to (7), wherein

[0434] When the sensing mode is set, the scanning circuit causes one of the pair of capacitors to maintain a first signal level according to the exposure amount of the first photoelectric conversion element, and causes the other of the pair of capacitors to maintain a second signal level according to the exposure amount of the second photoelectric conversion element, and when switching to the normal imaging mode, causes the pair of capacitors to maintain a reset level and a signal level at the end of exposure.

[0435] (9) The solid-state imaging element according to (1), wherein

[0436] The pre-stage circuit includes:

[0437] Photoelectric conversion element;

[0438] a first transfer transistor that transfers charge from the photoelectric conversion element to one of the pair of capacitive elements;

[0439] a second transfer transistor that transfers charge from the photoelectric conversion element to the other capacitance element of the pair of capacitance elements; and

[0440] A discharge transistor discharges electric charge from the photoelectric conversion element.

[0441] (10) The solid-state imaging element according to (1), wherein

[0442] Pixels also include:

[0443] a selection circuit that sequentially performs: control to connect one of the pair of capacitance elements to a predetermined subsequent node, control to disconnect both capacitance elements of the pair of capacitance elements from the subsequent node, and control to connect the other capacitance element of the pair of capacitance elements to the subsequent node;

[0444] a subsequent-stage reset transistor that initializes a level of the subsequent-stage node when both of the pair of capacitive elements are disconnected from the subsequent-stage node; and

[0445] A subsequent-stage circuit reads a pixel signal from the pair of capacitive elements via a subsequent-stage node and outputs the pixel signal.

[0446] (11) An imaging device comprising:

[0447] A pixel including a front-stage circuit and a pair of capacitor elements, wherein the front-stage circuit sequentially generates a predetermined number of pixel signals;

[0448] a scanning circuit that causes the pair of capacitive elements to maintain respective signal levels of a pair of pixel signals among a predetermined number of pixel signals when a sensing mode is set, and causes the pair of capacitive elements to maintain a reset level and a signal level of any one pixel signal among the predetermined number of pixel signals when a switching from the sensing mode to the normal imaging mode is performed;

[0449] a difference calculation circuit that calculates a difference between respective signal levels in the pair of pixel signals when a sensing mode is set;

[0450] a mode control section that determines whether to switch from the sensing mode to the normal imaging mode based on the difference; and

[0451] The image data processing unit processes the image data in which the difference between the reset level and the signal level is arranged when the mode is switched to the normal imaging mode.

[0452] (12) A method for controlling a solid-state imaging element, the solid-state imaging element including a pixel, the pixel including a front-stage circuit and a pair of capacitor elements, the front-stage circuit sequentially generating a predetermined number of pixel signals, the method comprising:

[0453] a scanning step, in which, when the sensing mode is set, the pair of capacitive elements in the pixel maintain respective signal levels of a pair of pixel signals among a predetermined number of pixel signals, and in which, when the sensing mode is switched to a normal imaging mode, the pair of capacitive elements maintain a reset level and a signal level of any one pixel signal among the predetermined number of pixel signals;

[0454] a difference calculation step of calculating a difference between respective signal levels of the pair of pixel signals when the sensing mode is set; and

[0455] A mode control step determines whether to switch from the sensing mode to the normal imaging mode based on the difference.

[0456] Reference Symbols List

[0457] 100 Imaging Device

[0458] 110 Optical Department

[0459] 120 Records Department

[0460] 130 Imaging Control Unit

[0461] 200 Solid-state imaging element

[0462] 201 pixel chip

[0463] 202 Circuit Chip

[0464] 203 Upper pixel chip

[0465] 204 Lower pixel chip

[0466] 211 vertical scanning circuit

[0467] 212 Timing Control Circuit

[0468] 213DAC

[0469] 220 Pixel Array Section

[0470] 221 upper pixel array portion

[0471] 222 lower pixel array portion

[0472] 250 load MOS circuit block

[0473] 251 Load MOS Transistor

[0474] 260 signal processing circuits

[0475] 261ADC

[0476] 262 Digital Signal Processing Department

[0477] 263 Differential Calculation Circuit

[0478] 264 Mode Control Unit

[0479] 265 Image Data Processing Unit

[0480] 266 Focus Control Unit

[0481] 300 pixels

[0482] 301 effective pixels

[0483] 305 Phase difference pixels

[0484] 310 Preamplifier Circuit

[0485] 311, 311-1, 311-2 Photoelectric conversion element

[0486] 312, 312-1, 312-2 transfer transistor

[0487] 313FD reset transistor

[0488] 314,432FD

[0489] 315 preamplifier transistor

[0490] 316, 434 current source transistors

[0491] 317 discharge transistor

[0492] 321, 322, 423 capacitor elements

[0493] 323 Pre-stage reset transistor

[0494] 324 Pre-select transistor

[0495] 330 Selection Circuit

[0496] 331, 332 select transistor

[0497] 341 Rear stage reset transistor

[0498] 350, 350-1, 350-2 rear stage circuit

[0499] 351, 351-1, 351-2 post-amplifier transistor

[0500] 352, 352-1, 352-2 rear stage selection transistor

[0501] 420 Regulator

[0502] 421 Low-pass filter

[0503] 422 Buffer Amplifier

[0504] 430 virtual pixels

[0505] 431 Reset transistor

[0506] 433 Amplifier Transistor

[0507] 440 Switching Department

[0508] 441 Inverter

[0509] 442 Switching Circuit

[0510] 443, 444 switch

[0511] 12031 Imaging Department.

Claims

1. A solid-state imaging element, comprising: A pixel including a front-stage circuit and a pair of capacitive elements, wherein the front-stage circuit sequentially generates a predetermined number of pixel signals; a scanning circuit that causes the pair of capacitive elements to maintain respective signal levels of a pair of pixel signals among the predetermined number of pixel signals when the sensing mode is set, and causes the pair of capacitive elements to maintain a reset level and a signal level of any one pixel signal among the predetermined number of pixel signals when the sensing mode is switched to a normal imaging mode; a difference calculation circuit, which calculates a difference between respective signal levels of the pair of pixel signals when the sensing mode is set; as well as A mode control section determines whether to switch from the sensing mode to the normal imaging mode based on the difference.

2. The solid-state imaging element according to claim 1, wherein The mode control section determines whether to switch from the sensing mode to the normal imaging mode based on a comparison result between an absolute value of the difference and a predetermined threshold value.

3. The solid-state imaging element according to claim 2, further comprising: a focus control unit that detects a focus position of the lens and moves the lens to the focus position, wherein the difference calculation circuit calculates the difference between the signal level before the lens moves to the focus position and the signal level when the lens has moved to the focus position, and When the lens has moved to the focus position, the mode control section determines whether to switch from the sensing mode to the normal imaging mode based on a comparison result between an absolute value of the difference and a predetermined threshold value.

4. The solid-state imaging element according to claim 1, wherein The front stage circuit comprises: Photoelectric conversion element; a transfer transistor that transfers charges from the photoelectric conversion element to a floating diffusion layer; and A front-stage amplifier transistor amplifies the voltage of the floating diffusion layer.

5. The solid-state imaging element according to claim 4, wherein When the sensing mode is set, the scanning circuit causes one of the pair of capacitors to maintain a first signal level at the end of odd-numbered exposure and causes the other of the pair of capacitors to maintain a second signal level at the end of even-numbered exposure, and when switching to the normal imaging mode, causes the pair of capacitors to maintain a reset level and a signal level at the end of exposure.

6. The solid-state imaging element according to claim 4, wherein When the sensing mode is set, the scanning circuit causes one of the pair of capacitors to maintain a first signal level at the end of odd-numbered exposure and causes the other of the pair of capacitors to maintain a second signal level at the end of even-numbered exposure, and when switching to the normal imaging mode, causes one of the pair of capacitors to maintain a reset level at the end of exposure.

7. The solid-state imaging element according to claim 1, wherein The front stage circuit comprises: a first photoelectric conversion element and a second photoelectric conversion element; a first transfer transistor that transfers charges from the first photoelectric conversion element to a floating diffusion layer; a second transfer transistor that transfers charge from the second photoelectric conversion element to the floating diffusion layer; and a front-stage amplifier transistor that amplifies a voltage of the floating diffusion layer; and The first photoelectric conversion element and the second photoelectric conversion element have exposure periods that partially overlap each other.

8. The solid-state imaging element according to claim 7, wherein When the sensing mode is set, the scanning circuit causes one of the pair of capacitors to maintain a first signal level according to the exposure amount of the first photoelectric conversion element, and causes the other of the pair of capacitors to maintain a second signal level according to the exposure amount of the second photoelectric conversion element, and when switching to the normal imaging mode, causes the pair of capacitors to maintain a reset level and a signal level at the end of exposure.

9. The solid-state imaging element according to claim 1, wherein The front stage circuit comprises: Photoelectric conversion element; a first transfer transistor that transfers charge from the photoelectric conversion element to one of the pair of capacitive elements; a second transfer transistor that transfers charge from the photoelectric conversion element to the other capacitance element of the pair of capacitance elements; and A discharge transistor discharges the charge from the photoelectric conversion element.

10. The solid-state imaging element according to claim 1, wherein The pixel also includes: a selection circuit that sequentially performs: control to connect one of the pair of capacitance elements to a predetermined subsequent node, control to disconnect both of the pair of capacitance elements from the subsequent node, and control to connect the other of the pair of capacitance elements to the subsequent node; a subsequent reset transistor that initializes the level of the subsequent node when both of the pair of capacitance elements are disconnected from the subsequent node; and A subsequent stage circuit reads the pixel signal from the pair of capacitive elements via the subsequent stage node and outputs the pixel signal.

11. An imaging device, comprising: A pixel including a front-stage circuit and a pair of capacitive elements, wherein the front-stage circuit sequentially generates a predetermined number of pixel signals; a scanning circuit that causes the pair of capacitive elements to maintain respective signal levels of a pair of pixel signals among the predetermined number of pixel signals when the sensing mode is set, and causes the pair of capacitive elements to maintain a reset level and a signal level of any one pixel signal among the predetermined number of pixel signals when the sensing mode is switched to a normal imaging mode; a difference calculation circuit, which calculates a difference between respective signal levels of the pair of pixel signals when the sensing mode is set; a mode control section that determines whether to switch from the sensing mode to the normal imaging mode based on the difference; as well as The image data processing unit processes the image data in which the difference between the reset level and the signal level is arranged when switching to the normal imaging mode.

12. A method for controlling a solid-state imaging element, the solid-state imaging element comprising a pixel, the pixel comprising a front-stage circuit and a pair of capacitor elements, the front-stage circuit sequentially generating a predetermined number of pixel signals, the method comprising: a scanning step, in which, when the sensing mode is set, the pair of capacitive elements in the pixel maintain respective signal levels of a pair of pixel signals among a predetermined number of pixel signals, and in which, when the sensing mode is switched to a normal imaging mode, the pair of capacitive elements maintain a reset level and a signal level of any one pixel signal among the predetermined number of pixel signals; a difference calculation step of calculating the difference between the respective signal levels of the pair of pixel signals when the sensing mode is set; as well as A mode control step of determining whether to switch from the sensing mode to the normal imaging mode based on the difference.

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