Display device and method of driving a display device

Abstract

A display device includes a display panel and a scan circuit configured to provide control signals to the display panel. A plurality of scan units are grouped into N groups, N being a positive integer greater than 2. Each scan unit group includes one or more scan units. The scan circuit further includes N control units respectively connected to the N scan unit groups, and N selection units connected to the N control units. Each control unit of the N control units is configured to provide a start signal to a respective scan unit group of the N scan unit groups. Each selection unit of the N selection units is configured to transmit one or more selection signals to a respective control unit.

Description

Technical Field

[0001] This invention relates to display technology, and more particularly to a display device and a method for driving the display device. Background Technology

[0002] The image display device includes a driver for controlling the image display of each of a plurality of pixels. The driver is a transistor-based circuit that includes gate drive circuitry and data drive circuitry. The gate drive circuitry consists of a plurality of shift register units cascaded together. Each shift register unit outputs a gate drive signal to one of a plurality of gate lines. The gate drive signal from the gate drive circuitry scans through the gate lines line by line, thereby controlling the transistors in each row to be in an on / off state. The gate drive circuitry can be integrated into a gate-on-array (GOA) circuitry, which can be directly formed in the array substrate of the display panel. Summary of the Invention

[0003] On one hand, this disclosure provides a display device, including a display panel and a scanning circuit, the scanning circuit being configured to provide control signals to the display panel; wherein the scanning circuit includes multiple stages, each of the multiple stages including a corresponding scanning unit among multiple scanning units; the multiple scanning units are grouped into N groups, where N is a positive integer greater than 2; each scanning unit group includes one or more scanning units; each scanning unit in the one or more scanning units in each scanning unit group is connected to one or more rows of sub-pixels in the display panel; wherein the scanning circuit further includes N control units respectively connected to the N scanning unit groups, and N selection units connected to the N control units; each control unit in the N control units is configured to provide a start signal to a corresponding scanning unit group in the N scanning unit groups; and each selection unit in the N selection units is configured to transmit one or more selection signals to a corresponding control unit.

[0004] Optionally, each of the N scanning unit groups is configured to receive the start signal from the corresponding control unit of the N control units; and each scanning unit group is configured to output control signals to the corresponding display area of ​​the display panel step by step, wherein the sub-pixel in the corresponding display area is configured to receive the control signals output from the corresponding scanning unit group.

[0005] Optionally, the plurality of selection units include N cascaded levels; the plurality of scanning units include (m×N) cascaded levels, where m is a positive integer; and each scanning unit group in the plurality of scanning unit groups includes m cascaded levels.

[0006] Optionally, the nth selection unit is configured to receive an output signal from the output terminal of the preceding selection unit, where n is an integer greater than 1; and the nth selection unit is configured to output an nth selection signal to the nth control unit among the plurality of control units.

[0007] Optionally, the display panel includes one or more first display areas and one or more second display areas; wherein the one or more first display areas are configured to display an image at a first refresh rate; the one or more second display areas are configured to display an image at a second refresh rate; and the second refresh rate is greater than the first refresh rate.

[0008] Optionally, the control signal is a disable signal, and when the disable signal is provided to one or more first control units among the plurality of control units, one or more selection signals from one or more first selection units do not pass through the one or more first control units, the one or more first control units are configured not to provide a start signal to one or more first scan unit groups; the scan units in the one or more first scan unit groups maintain a constant voltage output; and the one or more first display areas corresponding to the one or more first scan unit groups are configured to display an image at the first refresh rate.

[0009] Optionally, the plurality of scanning units include a latching circuit configured to maintain the constant voltage output in the scanning unit of the one or more first scanning unit groups.

[0010] Optionally, the control signal is an enable signal, and when the enable signal is provided to one or more second control units among the plurality of control units, one or more selection signals from one or more second selection units pass through the one or more second control units, the one or more second control units being configured to provide one or more start signals to one or more second scanning unit groups; and the one or more second display areas corresponding to the one or more second scanning unit groups being configured to display images at the second refresh rate.

[0011] Optionally, the display device further includes one or more enable signal lines configured to provide an enable signal or a disable signal to the plurality of control units.

[0012] On the other hand, this disclosure provides a method for driving a display device, wherein the display device includes a display panel and a scanning circuit, the scanning circuit being configured to provide control signals to the display panel; wherein the scanning circuit includes multiple stages, each of the multiple stages including a corresponding scanning unit among multiple scanning units; the multiple scanning units are grouped into N groups, where N is a positive integer greater than 2; each scanning unit group includes one or more scanning units; each scanning unit in the one or more scanning units in each scanning unit group is connected to one or more rows of sub-pixels in the display panel; wherein the scanning circuit further includes N control units respectively connected to the N scanning unit groups, and N selection units connected to the N control units; wherein the method includes: each control unit in the N control units providing a start signal to a corresponding scanning unit group in the N scanning unit groups; and each selection unit in the N selection units transmitting one or more selection signals to the corresponding control unit.

[0013] Optionally, the method further includes: each of the N scanning unit groups receiving the start signal from a corresponding control unit among the N control units; and each scanning unit group outputting control signals to a corresponding display area of ​​the display panel, wherein in the corresponding display area, the sub-pixel is configured to receive the control signals output from the corresponding scanning unit group.

[0014] Optionally, the method further includes: receiving an output signal from the output terminal of a preceding selection unit by the nth selection unit, where n is an integer greater than 1; and outputting an nth selection signal by the nth selection unit to the nth control unit among the plurality of control units.

[0015] Optionally, the display panel includes one or more first display areas and one or more second display areas; wherein, the method further includes: displaying an image in the one or more first display areas at a first refresh rate; and displaying an image in the one or more second display areas at a second refresh rate; wherein the second refresh rate is greater than the first refresh rate.

[0016] Optionally, the method further includes: providing a disable signal to one or more first control units among the plurality of control units; preventing one or more selection signals from one or more first selection units from passing through the one or more first control units; preventing the one or more first control units from providing a start signal to one or more first scan unit groups; maintaining a constant voltage output in the scan units of the one or more first scan unit groups; and displaying an image at the first refresh rate in the one or more first display areas corresponding to the one or more first scan unit groups.

[0017] Optionally, the method further includes: providing an enable signal to one or more second control units among the plurality of control units; allowing one or more selection signals from one or more second selection units to pass through the one or more second control units; providing one or more start signals from the one or more second control units to one or more second scanning unit groups; and displaying an image at the second refresh rate in the one or more second display areas corresponding to the one or more second scanning unit groups.

[0018] Optionally, the display panel includes one or more first display areas and one or more second display areas; the one or more first display areas are configured to display an image at a first refresh rate; the one or more second display areas are configured to display an image at a second refresh rate; the second refresh rate is greater than the first refresh rate; wherein the method includes: providing one or more selection signals from one or more first selection units to one or more first control units; providing a disable signal to one or more first control units to prevent the one or more selection signals from passing through the one or more first control units, the one or more first control units being configured not to provide a start signal to one or more first scanning unit groups; and displaying an image at the first refresh rate in one or more first display areas corresponding to the one or more first scanning unit groups.

[0019] Optionally, the method further includes: providing one or more selection signals from one or more second selection units to one or more second control units; providing an enable signal to one or more second control units to allow the one or more selection signals to pass through the one or more second control units; providing a start signal from the one or more second control units to one or more second scanning unit groups; and displaying an image at a second refresh rate in one or more second display areas corresponding to the one or more second scanning unit groups.

[0020] Optionally, in a frame of image, each of the one or more second selection units is configured to provide a plurality of selection signals to a corresponding second control unit in the one or more second control units.

[0021] Optionally, the display panel includes one or more first display areas and one or more second display areas; the one or more first display areas are configured to display an image at a first refresh rate; the one or more second display areas are configured to display an image at a second refresh rate; the second refresh rate is greater than the first refresh rate; wherein the method includes: providing multiple selection signals from multiple selection units to multiple control units respectively; providing enable signals to the multiple control units to allow the multiple selection signals to pass through the multiple control units respectively; providing start signals from the multiple control units to multiple scanning unit groups; and displaying an image at the second refresh rate in the display area of ​​the display panel.

[0022] Optionally, the display panel includes multiple regions; wherein the signal frequency of each selection unit is configured to be higher than the base frequency, thereby causing the refresh frequency of one or more regions among the multiple regions to be higher than the base frequency. Attached Figure Description

[0023] The following figures are merely illustrative examples based on various disclosed embodiments and are not intended to limit the scope of the invention.

[0024] Figure 1 This is a schematic diagram illustrating a method for driving a display panel according to some embodiments of the present disclosure.

[0025] Figure 2 This is a schematic diagram illustrating a method for driving a display panel according to some embodiments of the present disclosure.

[0026] Figure 3 This is a schematic diagram illustrating a method for driving a display panel according to some embodiments of the present disclosure.

[0027] Figure 4 This is a schematic diagram illustrating a method for driving a display panel according to some embodiments of the present disclosure.

[0028] Figure 5 This is a schematic diagram illustrating a method for driving a display panel according to some embodiments of the present disclosure.

[0029] Figure 6 This is a schematic diagram illustrating a method for driving a display panel according to some embodiments of the present disclosure.

[0030] Figure 7 It is a circuit diagram of a corresponding scanning unit or a corresponding selection unit according to some embodiments of this disclosure.

[0031] Figure 8 It is shown Figure 7 The timing diagram shows the operation of the corresponding scanning unit or the corresponding selection unit.

[0032] Figure 9 It is a circuit diagram of a corresponding scanning unit or a corresponding selection unit according to some embodiments of this disclosure.

[0033] Figure 10 It is a circuit diagram of a corresponding scanning unit or a corresponding selection unit according to some embodiments of this disclosure.

[0034] Figure 11 These are circuit diagrams of corresponding control units according to some embodiments of this disclosure.

[0035] Figure 12 These are circuit diagrams of corresponding control units according to some embodiments of this disclosure.

[0036] Figure 13 This is a schematic diagram illustrating a method for driving a display panel according to some embodiments of the present disclosure.

[0037] Figure 14A This is a schematic diagram illustrating the structure of a display device according to some embodiments of the present disclosure.

[0038] Figure 14B It is shown Figure 14A The timing diagram shown is for the operation of the display device.

[0039] Figure 15A This is a schematic diagram illustrating the structure of a display device according to some embodiments of the present disclosure.

[0040] Figure 15B It is shown Figure 15A The timing diagram shown is for the operation of the display device.

[0041] Figure 16A This is a schematic diagram illustrating the structure of a display device according to some embodiments of the present disclosure.

[0042] Figure 16B It is shown Figure 16A The timing diagram shown is for the operation of the display device. Specific Implementation

[0043] This disclosure will now be described in more detail with reference to the following embodiments. It should be noted that the following description of some embodiments presented herein is for illustrative and descriptive purposes only. It is not exhaustive or limited to the precise forms disclosed.

[0044] Generally, display panels (such as those in mobile phones) typically have only one refresh rate per frame. At a high refresh rate, the display panel refreshes from top to bottom at a high frequency; at a low refresh rate, it refreshes from top to bottom at a low frequency. However, high refresh rates result in high power consumption, which poses a challenge to battery capacity and lifespan. On the other hand, low refresh rates can cause display flickering or reduced smoothness.

[0045] The inventors of this disclosure have discovered that a high refresh rate distribution (HRD) can be used, in which the GOA (gate-on-array) circuitry divides the display panel into multiple regions. In regions where frequent refreshes are not required, power consumption when using a high refresh rate can be reduced, thereby improving battery life, while regions that do require frequent refreshes can maintain a high refresh rate. For example, the inventors of this disclosure have discovered that latches can be used to store the GOA output in low refresh regions without requiring GOA cascading; the time saved in the low refresh regions can be allocated to the high refresh regions, further increasing the refresh rate of the high refresh regions.

[0046] Figure 1 This is a schematic diagram illustrating a method for driving a display panel according to some embodiments of the present disclosure. (Refer to...) Figure 1 In some embodiments, the display device includes a scanning circuit SC and a display panel DP. The scanning circuit SC is configured to provide control signals to the display panel DP. (See also...) Figure 1 In some embodiments, the scanning circuit includes N stages. Each of the N stages includes a corresponding scanning unit. For example... Figure 1 As depicted, in some embodiments, the scanning circuit SC includes a first scanning unit SU1, a second scanning unit SU2, ..., an nth scanning unit SUn, a (n+1)th scanning unit SU(n+1), ..., a (N-1)th scanning unit SU(N-1), and an Nth scanning unit SUN. The N scanning units are configured to provide N control signals (e.g., gate signals, reset control signals, or emission control signals) to multiple rows of sub-pixels (e.g., N rows of sub-pixels). The nth scanning unit is configured to receive a start signal STV or an output signal from the output of a preceding scanning unit (e.g., the (n-1)th scanning unit SU(n-1), the (n-2)th scanning unit, or the (n-3)th scanning unit). As used herein, the term "preceding scanning unit" is not limited to the immediately preceding scanning unit (e.g., the (n-1)th scanning unit), but includes any suitable preceding scanning unit (e.g., the (n-2)th scanning unit or the (n-3)th scanning unit). Figure 1In this configuration, the first scanning unit SU1 is configured to receive the start signal STV as an input signal, the second scanning unit SU2 is configured to receive the output signal from the first scanning unit SU1 as an input signal, the nth scanning unit SUn is configured to receive the output signal from the (n-1)th scanning unit SU(n-1) as an input signal, the (n+1)th scanning unit SU(n+1) is configured to receive the output signal from the nth scanning unit as an input signal, the (N-1)th scanning unit SU(N-1) is configured to receive the output signal from the (N-2)th scanning unit as an input signal, and the Nth scanning unit is configured to receive the output signal from the (N-1)th scanning unit as an input signal. Figure 1 The scanning direction of the method for operating the scanning circuit is shown.

[0047] exist Figure 1 In this configuration, the first scanning unit SU1 is configured to output a first control signal to the display panel DP, the second scanning unit SU2 is configured to output a second control signal to the display panel DP, the nth scanning unit SUn is configured to output the nth control signal to the display panel DP, the (n+1)th scanning unit SU(n+1) is configured to output the (n+1)th control signal to the display panel DP, the (N-1)th scanning unit SU(N-1) is configured to output the (N-1)th control signal to the display panel DP, and the Nth scanning unit is configured to output the Nth control signal to the display panel DP.

[0048] Figure 2 This is a schematic diagram illustrating a method for driving a display panel according to some embodiments of the present disclosure. (Refer to...) Figure 2 In some embodiments, the display device includes a scanning circuit SC and a display panel DP. The scanning circuit SC is configured to provide control signals to the display panel DP. (See also...) Figure 2 In some embodiments, the scanning circuit SC includes N stages. Each of the N stages includes a corresponding scanning unit among multiple scanning units and a corresponding control unit among multiple control units CU. For example... Figure 2 As depicted, in some embodiments, the scanning circuit SC includes a first scanning unit SU1, a second scanning unit SU2, ..., an nth scanning unit SUn, a (n+1)th scanning unit SU(n+1), ..., a (N-1)th scanning unit SU(N-1), and an Nth scanning unit SUN. The N scanning units are configured to provide N control signals (e.g., gate signals, reset control signals, or emission control signals) to multiple rows of sub-pixels (e.g., N rows of sub-pixels). The nth scanning unit is configured to receive a start signal STV or an output signal from the output of a preceding scanning unit (e.g., the (n-1)th scanning unit SU(n-1), the (n-2)th scanning unit, or the (n-3)th scanning unit). Figure 2 In this configuration, the first scanning unit SU1 is configured to receive the start signal STV as an input signal, the second scanning unit SU2 is configured to receive the output signal from the first scanning unit SU1 as an input signal, the (n-1)th scanning unit SU(n-1) is configured to receive the output signal from the (n-2)th scanning unit as an input signal, the nth scanning unit SUn is configured to receive the output signal from the (n-1)th scanning unit SU(n-1) as an input signal, the (N-1)th scanning unit SU(N-1) is configured to receive the output signal from the (N-2)th scanning unit as an input signal, and the Nth scanning unit is configured to receive the output signal from the (N-1)th scanning unit as an input signal. Figure 2 The scanning direction of the method for operating the scanning circuit is shown.

[0049] To save power and achieve different display frequencies on the same display panel, a high refresh rate is used for dynamic content, such as animations and videos, to ensure smoother playback, while a low refresh rate is used for less important information, such as text and backgrounds, or for content that changes slowly. Figure 2 The scanning circuit SC includes multiple control units CUs respectively connected to multiple scanning units. In some embodiments, the first scanning unit SU1 is configured to output a first control signal to the first control unit among the multiple control units CU, the second scanning unit SU2 is configured to output a second control signal to the second control unit among the multiple control units CU, the nth scanning unit SUUn is configured to output an nth control signal to the nth control unit among the multiple control units CU, the (n+1)th scanning unit SU(n+1) is configured to output an (n+1)th control signal to the (n+1)th control unit among the multiple control units CU, the (N-1)th scanning unit SU(N-1) is configured to output an (N-1)th control signal to the (N-1)th control unit among the multiple control units CU, and the Nth scanning unit is configured to output an Nth control signal to the Nth control unit among the multiple control units CU.

[0050] Figure 3 This is a schematic diagram illustrating a method for driving a display panel according to some embodiments of the present disclosure. (Refer to...) Figure 3In some embodiments, the display device further includes one or more enable signal lines ENL configured to provide control signals to a plurality of control units to turn these control units on or off. In some embodiments, the display panel includes one or more first display areas A1 and one or more second display areas A2. The one or more first display areas A1 and one or more second display areas A2 are configured to display images at different refresh rates. In one example, one or more first display areas A1 are configured to display images at a first refresh rate, and one or more second display areas A2 are configured to display images at a second refresh rate, the first refresh rate and the second refresh rate being different from each other. Figure 3 The diagram shows the enable signals (e.g., the low-voltage portion of signal EN) provided by one or more enable signal lines ENL corresponding to one or more first display areas A1 and one or more second display areas A2.

[0051] In one example, the selection signal for controlling the control unit corresponding to one or more first display areas A1 has a low voltage level, and the selection signal for controlling the control unit corresponding to one or more second display areas A2 has a high voltage level. In another example, the control unit corresponding to one or more first display areas A1 is turned off, so that the control signal output from the scanning unit connected to the control unit corresponding to the one or more first display areas A1 is not provided to the one or more first display areas A1. In another example, the control unit corresponding to one or more second display areas A2 is turned on, such that the control signal output from the scanning unit connected to the control unit corresponding to the one or more second display areas A2 is provided to the one or more second display areas A2.

[0052] The simplest idea behind frequency division driving is to eliminate the scanning circuit, allowing the integrated circuit (IC) to provide control signals to the display panel for direct control, and then input the control signals to the display area. Figure 4 This is a schematic diagram illustrating a method for driving a display panel according to some embodiments of the present disclosure. (Refer to...) Figure 4 In some embodiments, the display device includes a plurality of control signal lines (CSLs). The plurality of control signal lines (CSLs) are configured to provide control signals to the display panel (DP) without a scanning circuit. In some embodiments, each control signal line of the plurality of control signal lines (CSLs) is connected to a corresponding row of sub-pixels in a multi-row sub-pixel array in the display panel. Each control signal line is configured to provide a control signal to the corresponding row of sub-pixels. However, without a scanning circuit, the display device requires not only a large number of IC pins but also places high demands on the bezel of the display device.

[0053] Figure 5This is a schematic diagram illustrating a method for driving a display panel according to some embodiments of the present disclosure. (Refer to...) Figure 5 In some embodiments, the display device includes a plurality of start signal lines (e.g., Sa, Sb, Sc, Sd, Se, and Sf) and a scanning circuit including a plurality of scanning units. In some embodiments, the plurality of scanning units are grouped into a plurality of scanning unit groups (e.g., SUa, SUb, SUc, SUd, SUe, and SUf). Each start signal line in the plurality of start signal lines is configured to provide a corresponding start signal to a corresponding scanning unit group in the plurality of scanning unit groups. In some embodiments, the display panel DP includes a plurality of display areas (e.g., a, b, c, d, e, and f). In some embodiments, the scanning units in each scanning unit group are configured to provide control signals to a corresponding display area in the plurality of display areas. The inventors of this disclosure have found that because the number of start signal lines is limited, Figure 5 The method and display device shown require a fixed number of frequency division zones (e.g., a to f). Arbitrary frequency division for display cannot be implemented. For example, if the display device includes six start signal lines, the display panel DP can only have six display zones for frequency division.

[0054] Therefore, this disclosure particularly provides a display device and a method for driving the display device, which substantially eliminates one or more problems caused by the limitations and disadvantages of the prior art. In one aspect, this disclosure provides a display device. In some embodiments, the display device includes a display panel and a scanning circuit configured to provide control signals to the display panel. Optionally, the scanning circuit includes multiple stages, each stage including a corresponding scanning unit among multiple scanning units. Optionally, the multiple scanning units are grouped into N groups, where N is a positive integer greater than 2. Optionally, each scanning unit group includes one or more scanning units. Optionally, each scanning unit in one or more scanning units in each scanning unit group is connected to one or more rows of sub-pixels in the display panel. Optionally, the scanning circuit further includes N control units respectively connected to the N scanning unit groups, and N selection units connected to the N control units. Optionally, each control unit among the N control units is configured to provide a start signal to a corresponding scanning unit group among the N scanning unit groups. Optionally, each selection unit among the N selection units is configured to transmit one or more selection signals to a corresponding control unit.

[0055] Figure 6 This is a schematic diagram illustrating a method for driving a display panel according to some embodiments of the present disclosure. (Refer to...) Figure 6 In some embodiments, the display device includes a scanning circuit SC and a display panel DP. The scanning circuit SC is configured to provide control signals to the display panel DP. (See also...) Figure 6In some embodiments, the scanning circuit SC includes multiple stages. Each stage of the multiple stages includes a corresponding scanning unit among multiple scanning units.

[0056] In some embodiments, the plurality of scanning units are grouped into N groups, including a first scanning unit group (e.g., SU1), ..., an nth scanning unit group (e.g., SUn), ..., and an Nth scanning unit group (e.g., SUN). Each scanning unit in the respective scanning unit group is connected to one or more rows of subpixels in the display panel DP.

[0057] In some embodiments, the scanning circuit SC further includes N control units (e.g., CU1, ..., CUn, ..., CUN) respectively connected to the N scanning unit groups. For example, the scanning unit in the first scanning unit group is denoted as SU1, the scanning unit in the nth scanning unit group is denoted as SUn, and the scanning unit in the Nth scanning unit group is denoted as SUN.

[0058] In some embodiments, each of the N control units is configured to provide a start signal to a corresponding scan unit group among the N scan unit groups. In some embodiments, when each scan unit group among the N scan unit groups receives a start signal from a corresponding control unit among the N control units, the corresponding scan unit group is configured to (e.g., in a cascaded manner) output control signals step by step to a corresponding display area of ​​the display panel DP, wherein a sub-pixel in the display panel DP is configured to receive the control signals output from the corresponding scan unit group.

[0059] In some embodiments, the scanning circuit SC further includes N selection units (e.g., SLU1, ..., SLUn, ..., SLUN), which are respectively connected to N control units (e.g., CU1, ..., CUn, ..., CUN). Each of the N selection units is connected to a corresponding control unit among the N control units. Each selection unit is configured to transmit one or more selection signals to the corresponding control unit. The one or more selection signals are configured to control the corresponding control unit to transmit one or more start signals to the corresponding scanning unit group.

[0060] Figure 6The multiple selection units depicted are equivalent to addressing units. Compared to existing display devices and driving methods, the display device and driving method according to this disclosure have the advantage that the display device (e.g., the integrated circuit of the display device) first determines the direction of the display by using multiple selection units and issues instructions to the corresponding row for high-frequency refresh or low-frequency hold. If high-frequency refresh is required, both the multiple selection units and the multiple scanning units operate normally for refresh. However, in low-frequency display, after the integrated circuit provides information, the multiple selection units handle refresh and cascading, while the multiple scanning units maintain their previous state.

[0061] Various suitable selection units can be implemented in this disclosure. Examples of suitable selection units include multiple cascaded units, each of which is a 10T3C, 12T3C, or 16T3C unit. Alternatively, a selection unit may include one or more transistors.

[0062] In some embodiments, the plurality of selection units comprises N cascaded levels. In some embodiments, the plurality of scan units comprises (m×N) cascaded levels, where m and N are positive integers. In some embodiments, each scan unit group in the plurality of scan unit groups comprises m cascaded levels. In one example, m = 2. In another example, m = 4. In another example, m = 6. In another example, m = 8. In another example, m = 10. In another example, m = 12. In another example, m = 14. In another example, m = 16. In another example, m = 18. In another example, m = 20.

[0063] In some embodiments, the plurality of selection units include a first selection unit SLU1, ..., an nth selection unit SLUn, ..., and an Nth selection unit SLUN. In some embodiments, the nth selection unit SLUn is configured to receive a start signal or an output signal from the output of a preceding selection unit (e.g., the (n-1)th selection unit, the (n-2)th scan unit, or the (n-3)th scan unit). As used herein, the term "preceding selection unit" is not limited to the immediately preceding selection unit (e.g., the (n-1)th selection unit), but includes any suitable preceding selection unit (e.g., the (n-2)th selection unit or the (n-3)th selection unit).

[0064] exist Figure 6In this configuration, the first selection unit SLU1 is configured to receive a start signal as an input signal, the second selection unit is configured to receive the output signal of the first selection unit SLU1 as an input signal, the nth selection unit SLUn is configured to receive the output signal of the (n-1)th selection unit as an input signal, the (n+1)th selection unit is configured to receive the output signal of the nth selection unit SLUn as an input signal, the (N-1)th selection unit is configured to receive the output signal of the (N-2)th selection unit as an input signal, and the Nth selection unit SLUN is configured to receive the output signal of the (N-1)th selection unit as an input signal.

[0065] exist Figure 6 In this configuration, the first selection unit SLU1 is configured to output a first selection signal to the first control unit among the plurality of control units, the second selection unit is configured to output a second selection signal to the second control unit among the plurality of control units, the nth selection unit SLUn is configured to output an nth selection signal to the nth control unit among the plurality of control units, the (n+1)th selection unit is configured to output an (n+1)th selection signal to the (n+1)th control unit among the plurality of control units, the (N-1)th selection unit is configured to output an (N-1)th selection signal to the (N-1)th control unit among the plurality of control units, and the Nth selection unit is configured to output an Nth selection signal to the Nth control unit among the plurality of control units.

[0066] Various suitable scanning units can be implemented in this disclosure.

[0067] Figure 7 This is a circuit diagram of a corresponding scanning unit or a corresponding selection unit according to some embodiments of this disclosure. (Refer to...) Figure 7 In some embodiments, each scanning unit or each selection unit includes an input sub-circuit ISC, an output sub-circuit OSC, a first processing sub-circuit PSC1, a second processing sub-circuit PSC2, and a third processing sub-circuit PSC3.

[0068] In some embodiments, the output sub-circuit OSC is configured to provide a first power supply signal VGL or a second power supply signal VGH to the output terminal TM4 in response to the voltages of the fourth node N4 and the first node N1. Optionally, the output sub-circuit OSC includes a ninth transistor T9 and a tenth transistor T10.

[0069] The ninth transistor T9 is coupled between the first power supply signal VGL and the output terminal TM4. The gate of the ninth transistor T9 is coupled to the fourth node N4. The ninth transistor T9 can be turned on or off according to the voltage of the fourth node N4. Optionally, when the ninth transistor T9 is turned on, the voltage of the first power supply signal VGL is provided to the output terminal TM4, which (in Figure 7The signal marked OUTc can be transmitted to the nth gate line and used as a gate drive signal with a gate on level.

[0070] The tenth transistor T10 is coupled between the output terminal TM4 and the second power supply signal VGH. The gate of the tenth transistor T10 is coupled to the first node N1. The tenth transistor T10 can be turned on or off according to the voltage of the first node N1. Optionally, when the tenth transistor T10 is turned on, the voltage of the second power supply signal VGH is provided to the output terminal TM4, and this voltage (in Figure 7 The signal marked OUTc can be provided to the nth gate line and used as a gate drive signal with a gate cutoff level. In one example, when the gate drive signal has a gate cutoff level, it can be understood that no gate drive signal is provided.

[0071] In some embodiments, the input sub-circuit ISC is configured to control the voltage of the first node N1 in response to signals provided to the first input terminal TM1 and the second input terminal TM2, respectively. Optionally, the input sub-circuit ISC includes a first transistor T1.

[0072] The first transistor T1 is coupled between the first input terminal TM1 and the first node N1. The gate of the first transistor T1 is coupled to the second input terminal TM2. When the first clock signal CK is provided to the second input terminal TM2, the first transistor T1 is turned on to electrically couple the first input terminal TM1 to the first node N1.

[0073] In some embodiments, the first processing sub-circuit PSC1 is configured to control the voltage of the fourth node N4 in response to the voltage of the first node N1. Optionally, the first processing sub-circuit PSC1 includes an eighth transistor T8 and a second capacitor C2.

[0074] The eighth transistor T8 is coupled between the first power supply signal VGL and the fourth node N4. The gate of the eighth transistor T8 is coupled to the first node N1. The eighth transistor T8 can be turned on or off according to the voltage of the first node N1. Optionally, when the eighth transistor T8 is turned on, the voltage of the first power supply signal VGL can be provided to the fourth node N4.

[0075] The second capacitor C2 is coupled between the first power supply signal VGL and the fourth node N4. Optionally, the second capacitor C2 is configured to charge the voltage to be applied to the fourth node N4. Optionally, the second capacitor C2 is configured to stably maintain the voltage of the fourth node N4.

[0076] In some embodiments, the second processing sub-circuit PSC2 is coupled to the fifth node N5 and configured to control the voltage of the fourth node N4 in response to a signal input to the third input terminal TM3. Optionally, the second processing sub-circuit PSC2 includes a sixth transistor T6, a seventh transistor T7, and a first capacitor C1.

[0077] The first terminal of the first capacitor C1 is coupled to the fifth node N5, and the second terminal of the first capacitor C1 is coupled to the third node N3. The third node N3 is the common node between the sixth transistor T6 and the seventh transistor T7.

[0078] The sixth transistor T6 is coupled between the third node N3 and the fifth node N5. The gate of the sixth transistor T6 is coupled to the fifth node N5. The sixth transistor T6 can be turned on according to the voltage of the fifth node N5, therefore, the voltage corresponding to the second clock signal CB provided to the third input terminal TM3 can be applied to the third node N3.

[0079] The seventh transistor T7 is coupled between the fourth node N4 and the third node N3. The gate of the seventh transistor T7 is coupled to the third input terminal TM3. The seventh transistor T7 can be turned on in response to the second clock signal CB provided to the third input terminal TM3, thus applying the voltage of the first power supply signal VGL to the third node N3.

[0080] In some embodiments, the third processing sub-circuit PSC3 is configured to control the voltage of the fifth node N5. Optionally, the third processing sub-circuit PSC3 includes a second transistor T2, a third transistor T3, a fourth transistor T4, and a fifth transistor T5.

[0081] The fifth transistor T5 is coupled between the first power supply signal VGL and the fourth transistor T4. The gate of the fifth transistor T5 is coupled to the fifth node N5. The fifth transistor T5 can be turned on or off according to the voltage of the fifth node N5.

[0082] The fourth transistor T4 is coupled between the fifth transistor T5 and the first node. The gate of the fourth transistor T4 is configured to receive a second clock signal CB, which is provided to the third input terminal TM3. The first electrode of the fourth transistor T4 is coupled to the first node N1. The second electrode of the fourth transistor T4 is coupled to the second electrode of the fifth transistor T5.

[0083] The second transistor T2 is coupled between the fifth node N5 and the second input terminal TM2. The gate of the second transistor T2 is coupled to the first node N1.

[0084] The third transistor T3 is coupled between the fifth node N5 and the second power supply signal VGH. The gate of the third transistor T3 is coupled to the second input terminal TM2. When the first clock signal CK is provided to the second input terminal TM2, the third transistor T3 can be turned on, so that the voltage of the second power supply signal VGH can be provided to the fifth node N5.

[0085] This disclosure can be implemented in scanning circuits having various types of transistors, including scanning circuits with p-type transistors, scanning circuits with n-type transistors, and scanning circuits with one or more p-type transistors and one or more n-type transistors. For p-type transistors, the active control signal (e.g., a turn-on control signal) is a low-voltage signal, while the inactive control signal (e.g., a turn-off control signal) is a high-voltage signal. For n-type transistors, the active control signal (e.g., a turn-on control signal) is a high-voltage signal, while the inactive control signal (e.g., a turn-off control signal) is a low-voltage signal.

[0086] In some embodiments, refer to Figure 7 Each of the first transistor T1 through the tenth transistor T10 may be formed of an n-type transistor, such as a metal-oxide-semiconductor transistor. In some embodiments, the gate on-voltage of the first transistor T1 through the tenth transistor T10 may be set to a high level, while its gate off-voltage may be set to a low level.

[0087] In an alternative embodiment, each of the first transistor T1 through the tenth transistor T10 may be formed of a p-type transistor. In some embodiments, the gate on-voltage of the first transistor T1 through the tenth transistor T10 may be set to a low level, while its gate off-voltage may be set to a high level.

[0088] Figure 8 It is shown Figure 7 The timing diagram shows the operation of the corresponding scanning unit or the corresponding selection unit. (Refer to...) Figure 8 In some embodiments, the operation of each scanning unit includes a first time period p1, a second time period p2, a third time period p3, a fourth time period p4, and a fifth time period p5.

[0089] In some embodiments, during the first time period p1, the first clock signal CK is provided to the second input terminal TM2. The first transistor T1 and the third transistor T3 are turned on. Furthermore, during the first time period p1, the second clock signal CB is not provided to the third input terminal TM3, and the fourth transistor T4 and the seventh transistor T7 are turned off.

[0090] In some embodiments, during the first time period p1, the start signal STV provided to the first input terminal TM1 or the output signal OUTp from the output terminal of the preceding scan unit has a high level, and a high voltage (e.g., the voltage of the second power supply signal VGH) can be applied to the first node N1. When the first node N1 is set to a high voltage, the second transistor T2, the eighth transistor T8, and the tenth transistor T10 are turned on.

[0091] In some embodiments, when the second transistor T2 is turned on, the voltage of the first clock signal CK is provided to the second node N2. The fifth transistor T5 and the sixth transistor T6 are turned on.

[0092] In some embodiments, when the third transistor T3 is turned on, the voltage of the second power supply signal VGH is provided to the second node N2. The fifth transistor T5 and the sixth transistor T6 are turned on.

[0093] In some embodiments, when the eighth transistor T8 is turned on, the voltage of the first power supply signal VGL is provided to the fourth node N4. The ninth transistor T9 is turned off.

[0094] In some embodiments, when the tenth transistor T10 is turned on, the voltage of the second power supply signal VGH is provided to the output terminal TM4. During the first time period p1, the gate drive signal is not provided to the nth gate line.

[0095] In some embodiments, during the second time period p2, the supply of the first clock signal CK to the second input terminal TM2 is interrupted. The first transistor T1 and the third transistor T3 are turned off. The first node N1 maintains the voltage of the previous time period. Because the first node N1 remains at a high voltage, the second transistor T2, the eighth transistor T8, and the tenth transistor T10 remain on. When the eighth transistor T8 remains on, the voltage of the first power supply signal VGL is supplied to the fourth node N4. Because the fourth node N4 remains at a low voltage, the ninth transistor T9 remains off.

[0096] In some embodiments, during the second time period p2, a second clock signal CB is provided to the third input terminal TM3. The fourth transistor T4 and the seventh transistor T7 are turned on by the second clock signal CB, which is provided to the third input terminal TM3. When the seventh transistor T7 is turned on, the fourth node N4 and the third node N3 are electrically coupled to each other. The third node N3 is set to a low voltage.

[0097] In some embodiments, during the third time period p3, the supply of the second clock signal CB to the third input terminal TM3 is interrupted. When the supply of the second clock signal CB is interrupted, the seventh transistor T7 is turned off.

[0098] In some embodiments, during the third time period p3, the start signal STV or the output signal OUTp from the output terminal of the preceding scan unit is provided to the first input terminal TM1, and the first clock signal CK is provided to the second input terminal TM2. When the first clock signal CK is provided to the second input terminal TM2, the first transistor T1 and the third transistor T3 are turned on.

[0099] In some embodiments, when the first transistor T1 is turned on, the first input terminal TM1 is electrically coupled to the first node N1. The first node N1 is set to a low voltage by a start signal STV or an output signal OUTp from the output terminal of the preceding scan unit, wherein the start signal STV or the output signal OUTp is provided to the first input terminal TM1. When the first node N1 is set to a low voltage, the second transistor T2, the eighth transistor T8, and the tenth transistor T10 are turned off.

[0100] In some embodiments, when the sixth transistor T6 is turned on, the third input terminal TM3 is electrically coupled to the third node N3. Since the second clock signal CB is not provided to the third input terminal TM3 during the third time period p3, the third node N3 remains at a low voltage. Because the seventh transistor T7 remains off, the voltage of the third node N3 does not affect the voltage of the fourth node N4. The first capacitor C1 is configured to store the voltage corresponding to the on-level of the sixth transistor T6.

[0101] In some embodiments, during the fourth time period p4, the second clock signal CB can be provided to the third input terminal TM3. When the second clock signal CB is provided to the third input terminal TM3, the seventh transistor T7 is turned on.

[0102] In some embodiments, when the seventh transistor T7 is turned on, the fourth node N4 and the third node N3 are electrically coupled to each other. A high voltage of the second clock signal CB, provided to the third input terminal TM3 via the sixth transistor T6 which remains on, is supplied to the third node N3 and the fourth node N4. When the high voltage is supplied to the fourth node N4, the ninth transistor T9 is turned on.

[0103] In some embodiments, when the ninth transistor T9 is turned on, the voltage of the first power supply signal VGL is provided to the output terminal TM4. The voltage of the first power supply signal VGL provided to the output terminal TM4 is provided to the nth gate line as a gate drive signal.

[0104] In some embodiments, during the fifth time period p5, the supply of the second clock signal CB to the third input terminal TM3 is interrupted. When the supply of the second clock signal CB is interrupted, the seventh transistor T7 is turned off. The fourth node N4 is stably maintained at a high voltage through the second capacitor C2. The ninth transistor T9 remains on, and the voltage of the first power supply signal VGL is provided as a gate drive signal to the nth gate line.

[0105] The supply of the second clock signal CB is interrupted during the fifth period p5, which keeps the fourth transistor T4 off. Therefore, the voltage of the second clock signal CB does not affect the voltage of the first node N1.

[0106] Figure 9 This is a circuit diagram of a corresponding scanning unit or a corresponding selection unit according to some embodiments of this disclosure. (Refer to...) Figure 9 In some embodiments, each scanning unit or each selection unit includes an input sub-circuit ISC, an output sub-circuit OSC, a first processing sub-circuit PSC1, a second processing sub-circuit PSC2, a third processing sub-circuit PSC3, a first stabilizing sub-circuit SSC1, and a second stabilizing sub-circuit SSC2.

[0107] In some embodiments, the output sub-circuit OSC is configured to provide a second power supply signal VGH or a first power supply signal VGL to the output terminal TM4 in response to the voltage of the fourth node N4. Optionally, the output sub-circuit OSC includes a ninth transistor T9 and a tenth transistor T10.

[0108] The ninth transistor T9 is coupled between the second power supply signal VGH and the output terminal TM4. The gate of the ninth transistor T9 is coupled to the fourth node N4. The ninth transistor T9 can be turned on or off according to the voltage of the fourth node N4. Optionally, when the ninth transistor T9 is turned on, the voltage of the second power supply signal VGH is provided to the output terminal TM4, and this voltage (in...) Figure 9 The signal marked OUTc can be transmitted to the nth gate line and used as a gate drive signal with a gate on level.

[0109] The tenth transistor T10 is coupled between the output terminal TM4 and the first power supply signal VGL. The gate of the tenth transistor T10 is coupled to the first node N1. The tenth transistor T10 can be turned on or off according to the voltage of the first node N1. Optionally, when the tenth transistor T10 is turned on, the voltage of the first power supply signal VGL is provided to the output terminal TM4, and this voltage (in Figure 9 The signal marked OUTc can be provided to the nth gate line and used as a gate drive signal with a gate cutoff level. In one example, when the gate drive signal has a gate cutoff level, it can be understood that no gate drive signal is provided.

[0110] In some embodiments, the input sub-circuit ISC is configured to control the voltage of the first node N1 in response to signals provided to the first input terminal TM1 and the second input terminal TM2, respectively. Optionally, the input sub-circuit ISC includes a first transistor T1.

[0111] The first transistor T1 is coupled between the first input terminal TM1 and the first node N1. The gate of the first transistor T1 is coupled to the second input terminal TM2. When the first clock signal CK is provided to the second input terminal TM2, the first transistor T1 is turned on to electrically couple the first input terminal TM1 to the first node N1.

[0112] In some embodiments, the first processing sub-circuit PSC1 is configured to control the voltage of the fourth node N4 in response to the voltage of the first node N1. Optionally, the first processing sub-circuit PSC1 includes an eighth transistor T8 and a second capacitor C2.

[0113] The eighth transistor T8 is coupled between the second power supply signal VGH and the fourth node N4. The gate of the eighth transistor T8 is coupled to the first node N1. The eighth transistor T8 can be turned on or off according to the voltage of the first node N1. Optionally, when the eighth transistor T8 is turned on, the voltage of the second power supply signal VGH can be provided to the fourth node N4.

[0114] The second capacitor C2 is coupled between the second power supply signal VGH and the fourth node N4. Optionally, the second capacitor C2 is configured to charge the voltage to be applied to the fourth node N4. Optionally, the second capacitor C2 is configured to stably maintain the voltage of the fourth node N4.

[0115] In some embodiments, the second processing sub-circuit PSC2 is coupled to the fifth node N5 and configured to control the voltage of the fourth node N4 in response to a signal input to the third input terminal TM3. Optionally, the second processing sub-circuit PSC2 includes a sixth transistor T6, a seventh transistor T7, and a first capacitor C1.

[0116] The first terminal of the first capacitor C1 is coupled to the fifth node N5, and the second terminal of the first capacitor C1 is coupled to the third node N3. The third node N3 is the common node between the sixth transistor T6 and the seventh transistor T7.

[0117] The sixth transistor T6 is coupled between the third node N3 and the fifth node N5. The gate of the sixth transistor T6 is coupled to the fifth node N5. The sixth transistor T6 can be turned on according to the voltage of the fifth node N5, therefore, the voltage corresponding to the second clock signal CB provided to the third input terminal TM3 can be applied to the third node N3.

[0118] The seventh transistor T7 is coupled between the fourth node N4 and the third node N3. The gate of the seventh transistor T7 is coupled to the third input terminal TM3. The seventh transistor T7 can be turned on in response to the second clock signal CB provided to the third input terminal TM3, thus applying the voltage of the second power supply signal VGH to the third node N3.

[0119] In some embodiments, the third processing sub-circuit PSC3 is configured to control the voltage of the second node N2. Optionally, the third processing sub-circuit PSC3 includes a second transistor T2, a third transistor T3, a fourth transistor T4, a fifth transistor T5, and a third capacitor C3.

[0120] The fifth transistor T5 is coupled between the second power supply signal VGH and the fourth transistor T4. The gate of the fifth transistor T5 is coupled to the second node N2. The fifth transistor T5 can be turned on or off according to the voltage of the second node N2.

[0121] The fourth transistor T4 is coupled between the fifth transistor T5 and the third input terminal TM3. The first electrode of the fourth transistor T4 is configured to provide a second clock signal CB to the third input terminal TM3. The gate of the fourth transistor T4 is coupled to the gate of the tenth transistor T10. The second electrode of the fourth transistor T4 is coupled to the second electrode of the fifth transistor T5.

[0122] The second transistor T2 is coupled between the second node N2 and the second input terminal TM2. The gate of the second transistor T2 is coupled to the first node N1.

[0123] The third transistor T3 is coupled between the second node N2 and the first power supply signal VGL. The gate of the third transistor T3 is coupled to the second input terminal TM2. When the first clock signal CK is provided to the second input terminal TM2, the third transistor T3 can be turned on, so that the voltage of the first power supply signal VGL can be provided to the second node N2.

[0124] The third capacitor C3 is coupled between the tenth transistor T10 and the fifth transistor T5. The first capacitor electrode of the third capacitor C3 is coupled to the second electrode of the fifth transistor T5 and the second electrode of the fourth transistor T4. The second capacitor electrode of the third capacitor C3 is coupled to the gate of the fourth transistor T4 and the gate of the tenth transistor T10.

[0125] In some embodiments, a first stabilizing subcircuit SSC1 is coupled between a second processing subcircuit PSC2 and a third processing subcircuit PSC3. Optionally, the first stabilizing subcircuit SSC1 is configured to limit the voltage drop width of the second node N2. Optionally, the first stabilizing subcircuit SSC1 includes an eleventh transistor T11.

[0126] The eleventh transistor T11 is coupled between the second node N2 and the fifth node N5. The gate of the eleventh transistor T11 is coupled to the first power supply signal VGL. Since the first power supply signal VGL has a gate conduction level voltage, the eleventh transistor T11 can always remain on. Therefore, the second node N2 and the fifth node N5 can maintain the same voltage and operate essentially as the same node.

[0127] In some embodiments, the second stabilizing sub-circuit SSC2 is coupled between the first node N1 and the output sub-circuit OSC. Optionally, the second stabilizing sub-circuit SSC2 is configured to limit the voltage drop width of the first node N1. Optionally, the second stabilizing sub-circuit SSC2 includes a twelfth transistor T12.

[0128] The twelfth transistor T12 is coupled between the first node N1 and the gate of the tenth transistor T10. The gate of the twelfth transistor T12 is coupled to the first power supply signal VGL. Since the first power supply signal VGL has a gate conduction level voltage, the twelfth transistor T12 can always remain on. Therefore, the gates of the first node N1 and the tenth transistor T10 can be maintained at the same voltage.

[0129] In some embodiments, refer to Figure 9 Each of the first transistor T1 to the twelfth transistor T12 may be formed of an n-type transistor. In some embodiments, the gate on-voltage of the first transistor T1 to the twelfth transistor T12 may be set to a high level, while its gate off-voltage may be set to a low level.

[0130] In an alternative embodiment, each of the first transistor T1 through the twelfth transistor T12 may be formed of a p-type transistor. In some embodiments, the gate on-voltage of the first transistor T1 through the twelfth transistor T12 may be set to a low level, while its gate off-voltage may be set to a high level.

[0131] Figure 10 This is a circuit diagram of a corresponding scanning unit or a corresponding selection unit according to some embodiments of this disclosure. (Refer to...) Figure 10In some embodiments, each scanning unit or each selection unit includes a first control transistor GT1 to an eighth control transistor GT8, a first control capacitor GC1, and a second control capacitor GC2. In some embodiments, the gate of the first control transistor GT1 is electrically connected to a first clock signal terminal GCK1, the first electrode of the first control transistor GT1 is electrically connected to the input terminal GIN, and the second electrode of the first control transistor GT1 is electrically connected to a first node G1; the gate of the second control transistor GT2 is electrically connected to the first node G1, the first electrode of the second control transistor GT2 is electrically connected to the first clock signal terminal GCK1, and the second electrode of the second control transistor GT2 is electrically connected to a second node G2; the gate of the third control transistor GT3 is electrically connected to the first clock signal terminal GCK1, the first electrode of the third control transistor GT3 is electrically connected to a first power supply signal VGL, and the second electrode of the third control transistor GT3 is electrically connected to the second node G2; the gate of the fourth control transistor GT4 is electrically connected to the second node G2, the first electrode of the fourth control transistor GT4 is electrically connected to a second power supply signal VGH, and the second electrode of the fourth control transistor GT4 is electrically connected to the output terminal GOUT; the gate of the fifth control transistor GT5 is electrically connected to the third node G3, and the first electrode of the fifth control transistor GT5 is electrically connected to a second clock signal... Terminal GCK2 is used as the terminal for the fifth control transistor GT5. The second electrode of the fifth control transistor GT5 is electrically connected to the output terminal GOUT. The gate of the sixth control transistor GT6 is electrically connected to the second node G2, the first electrode of the sixth control transistor GT6 is electrically connected to the second power supply signal VGH, and the second electrode of the sixth control transistor GT6 is electrically connected to the first electrode of the seventh control transistor GT7. The gate of the seventh control transistor GT7 is electrically connected to the second clock signal terminal GCK2, and the second electrode of the seventh control transistor GT7 is electrically connected to the first node G1. The gate of the eighth control transistor GT8 is electrically connected to the first power supply signal VGL, the first electrode of the eighth control transistor GT8 is electrically connected to the first node G1, and the second electrode of the eighth control transistor GT8 is electrically connected to the third node G3. The first electrode plate GC11 of the first control capacitor GC1 is electrically connected to the second node G2, and the second electrode plate GC12 of the first control capacitor GC1 is electrically connected to the second power supply signal VGH. The first electrode plate GC21 of the second control capacitor GC2 is electrically connected to the third node G3, and the second electrode plate GC22 of the second control capacitor GC2 is electrically connected to the output terminal GOUT. In one example, the first control transistor GT1 to the eighth control transistor GT8 can be p-type transistors or n-type transistors. In another example, the second power signal VGH provides a continuous high-level signal, and the first power signal VGL provides a continuous low-level signal.

[0132] Various suitable control units can be implemented in this disclosure.

[0133] Figure 11 This is a circuit diagram of a corresponding control unit according to some embodiments of this disclosure. (Refer to...) Figure 11 In some embodiments, each control unit includes a transistor having a gate configured to receive a control signal CS. The control signal CS is configured to turn on the transistor, thereby allowing one or more selection signals to reach the corresponding scan unit group through the respective control unit.

[0134] Figure 12 This is a circuit diagram of a corresponding control unit according to some embodiments of this disclosure. (Refer to...) Figure 12 In some embodiments, each control unit includes an inverter gating circuit. In some embodiments, each control unit includes a first transistor T1, a second transistor T2, and a third transistor T3. The gate of the first transistor T1 is configured to receive a control signal CS. The gates of the second transistor T2 and the third transistor T3 are configured to receive selection signals SS from corresponding selection units. The second electrodes of the second transistor T2 and the third transistor T3 are configured to output corresponding start signals RSTV to corresponding scan unit groups. The first electrode of the first transistor T1 is configured to receive a second power supply signal VGH. The first electrode of the third transistor T3 is configured to receive a first power supply signal VGL. The first electrode of the second transistor T2 is connected to the second electrode of the first transistor T1.

[0135] In some embodiments, when the control signal CS is a low-voltage signal (enable signal), the selection signal SS passes through a corresponding control unit, which is configured to provide a corresponding start signal to a corresponding scan unit group. The corresponding display area corresponding to the corresponding scan unit group is configured to display an image at a second refresh rate (e.g., a high refresh rate).

[0136] In some embodiments, when the control signal CS is a high-voltage signal (disable signal), the selection signal SS does not pass through the corresponding control unit, and the corresponding control unit is configured not to provide the corresponding start signal to the corresponding scan unit group. The corresponding display area corresponding to the corresponding scan unit group is configured to display the image at a first refresh rate (e.g., a low refresh rate).

[0137] The inventors of this disclosure have discovered that in the display device of this disclosure, multiple selection units perform normal cascading without bearing the load of the display area, thereby resulting in lower power consumption. In the display device of this disclosure, the ratio of the number of selection units to the number of scanning units is 1:m (e.g., 1:4, 1:8, 1:12, or 1:16), where m is a positive integer.

[0138] Figure 13 This is a schematic diagram illustrating a method for driving a display panel according to some embodiments of the present disclosure. (Refer to...) Figure 13In some embodiments, the display panel includes one or more first display areas A1 and one or more second display areas A2. The one or more first display areas A1 and the one or more second display areas A2 are configured to display images at different refresh rates. In one example, the one or more first display areas A1 are configured to display images at a first refresh rate, and the one or more second display areas A2 are configured to display images at a second refresh rate, wherein the first refresh rate and the second refresh rate are different from each other. In one example, the second refresh rate is greater than the first refresh rate.

[0139] In some embodiments, when an enable signal is provided to the nth control unit CUn among a plurality of control units, a selection signal from the nth selection unit SLUn passes through the nth control unit, and the nth control unit CUn is configured to provide a start signal to the nth scan unit group. One or more second display areas A2 corresponding to the nth scan unit group are configured to display an image at a second refresh rate (e.g., a high refresh rate).

[0140] In some embodiments, when a disable signal is provided to the first control unit CU1 among a plurality of control units, the selection signal from the first selection unit SLU1 does not pass through the first control unit CU1, and the first control unit CU1 is configured not to provide a start signal to the first scan unit group. The scan units in the first scan unit group maintain a constant voltage output. One or more first display areas A1 corresponding to the first scan unit group are configured to display an image at a first refresh rate (e.g., a low refresh rate).

[0141] In some embodiments, when a disable signal is provided to the Nth control unit CUN among multiple control units, the selection signal from the Nth selection unit SLUN does not pass through the Nth control unit CUN, and the Nth control unit CUN is configured not to provide a start signal to the Nth scan unit group. The scan units in the Nth scan unit group maintain a constant voltage output. One or more first display areas A1 corresponding to the Nth scan unit group are configured to display an image at a first refresh rate (e.g., a low refresh rate).

[0142] The time saved in one or more first display areas A1 is allocated to one or more second display areas A2. By increasing the frequency of the selection units, one or more second display areas A2 can achieve higher frequency operation. For example, in a display panel with 2400 grid lines divided into first, second, and third areas, multiple scanning unit groups corresponding to the first and third areas are invalid, and only the second area with 800 grid lines is valid. The second area can use the extra time for ultra-high frequency operation, such as 240Hz or 360Hz (with a base frequency of 120Hz). Ultra-low power multi-frequency display is achieved in the first and third areas, while smooth ultra-high frequency display is achieved in the second area.

[0143] In some embodiments, the display panel includes multiple regions. Optionally, the signal frequency of each selection unit is configured to be higher than the base frequency, thereby causing one or more regions among the multiple regions to have a refresh frequency higher than the base frequency. As used herein, the term "base frequency" refers to the frequency at which the display panel operates during normal refresh. When no special or enhanced refresh operation is applied, the base frequency serves as the default or fundamental frequency for refreshing all regions of the display. This frequency ensures consistent and stable performance across the entire display under typical usage conditions.

[0144] Figure 14A This is a schematic diagram illustrating the structure of a display device according to some embodiments of the present disclosure. Figure 14B It is shown Figure 14A The timing diagram for the operation of the display device is shown below. (Refer to...) Figure 14A and Figure 14B In some embodiments, the display panel includes one or more first display areas A1 and one or more second display areas A2. The one or more first display areas A1 and the one or more second display areas A2 are configured to display images at different refresh rates. In one example, the one or more first display areas A1 are configured to display images at a first refresh rate, and the one or more second display areas A2 are configured to display images at a second refresh rate, wherein the first refresh rate and the second refresh rate are different from each other. In one example, the second refresh rate is greater than the first refresh rate.

[0145] In some embodiments, a method of driving a display device includes: in a first mode, receiving signals from one or more first selection units (e.g., ...). Figure 14A One or more selection signals of SLU1 or SLUN in the SLU1 or SLUN are provided to one or more first control units (e.g., Figure 14A CU1 or CUN in the middle); to one or more first control units (e.g., Figure 14AThe CU1 or CUN in the control unit provides a disable signal (e.g., a high-voltage portion of the control signal CS provided by one or more enable signal lines ENL), disallowing one or more selection signals from passing through one or more first control units, which are configured not to send signals to one or more first scan unit groups (e.g., ...). Figure 14A The system provides a start signal (SU1 or SUN in the first display area); and displays an image at a first refresh frequency (e.g., a low refresh frequency) in one or more first display areas A1 corresponding to one or more first scan unit groups. The scan units in the one or more first scan unit groups maintain a constant voltage output, for example, through a latching circuit.

[0146] Various suitable latching circuits can be implemented in this disclosure. Latching circuits are configured to allow certain areas of the display to maintain a constant voltage on subpixels without requiring continuous refresh. In some embodiments, the latching circuit is configured to store the last voltage state of a subpixel in a display area (e.g., one or more first display areas) operating at a low refresh rate. Once a subpixel is set to a specific voltage level (e.g., to display a specific brightness or color), the latching circuit ensures that the voltage remains constant even without an additional refresh signal. Examples of latching circuits include trigger circuits and capacitors. These circuits can maintain or “latch” the voltage applied to the subpixel after the last refresh, effectively preventing the voltage from decaying over time, which would otherwise cause the display to fade or flicker.

[0147] In some embodiments, in the first mode, the method further includes: selecting from one or more second selection units (e.g., Figure 14A One or more selection signals of SLUn are provided to one or more second control units (e.g., Figure 14A (CUn in the middle); to one or more second control units (e.g., Figure 14A The CUn in the control unit provides an enable signal (e.g., a low-voltage portion of the control signal CS provided by one or more enable signal lines ENL), thereby allowing one or more selection signals to pass through one or more second control units; and provides a start signal from one or more second control units to one or more second scan unit groups (e.g., Figure 14A The image is displayed in one or more second display areas A2 corresponding to one or more second scan unit groups at a second refresh rate (e.g., a high refresh rate).

[0148] In some embodiments, in a frame of an image, in a first mode, one or more second selection units (e.g., ...) Figure 14A Each of the SLUn in the above is configured to send to a corresponding second control unit in one or more second control units (e.g., Figure 14AThe CUn in the middle provides a single selection signal.

[0149] Figure 15A This is a schematic diagram illustrating the structure of a display device according to some embodiments of the present disclosure. Figure 15B It is shown Figure 15A The timing diagram for the operation of the display device is shown below. (Refer to...) Figure 15A and Figure 15B In some embodiments, the display panel includes one or more first display areas A1 and one or more second display areas A2. The one or more first display areas A1 and the one or more second display areas A2 are configured to display images at different refresh rates. In one example, the one or more first display areas A1 are configured to display images at a first refresh rate, and the one or more second display areas A2 are configured to display images at a second refresh rate, wherein the first refresh rate and the second refresh rate are different from each other. In one example, the second refresh rate is greater than the first refresh rate.

[0150] In some embodiments, the method of driving the display device includes: in a second mode, receiving signals from one or more first selection units (e.g., ...). Figure 15A One or more selection signals of SLU1 or SLUN in the SLU1 or SLUN are provided to one or more first control units (e.g., Figure 15A CU1 or CUN in the middle); to one or more first control units (e.g., Figure 15A The CU1 or CUN in the control unit provides a disable signal (e.g., a high-voltage portion of the control signal CS provided by one or more enable signal lines ENL), disallowing one or more selection signals from passing through one or more first control units, which are configured not to send signals to one or more first scan unit groups (e.g., ...). Figure 15A The system provides a start signal (SU1 or SUN in the first display area); and displays an image at a first refresh frequency (e.g., a low refresh frequency) in one or more first display areas A1 corresponding to one or more first scan unit groups. The scan units in the one or more first scan unit groups maintain a constant voltage output, for example, through a latching circuit.

[0151] In some embodiments, in the second mode, the method further includes: selecting from one or more second selection units (e.g., Figure 15A One or more selection signals of SLUn are provided to one or more second control units (e.g., Figure 15A (CUn in the middle); to one or more second control units (e.g., Figure 15AThe CUn in the control unit provides an enable signal (e.g., a low-voltage portion of the control signal CS provided by one or more enable signal lines ENL), thereby allowing one or more selection signals to pass through one or more second control units; and provides a start signal from one or more second control units to one or more second scan unit groups (e.g., Figure 15A The image is displayed in one or more second display areas A2 corresponding to one or more second scan unit groups at a second refresh rate (e.g., a high refresh rate).

[0152] In some embodiments, in a frame of an image, in the second mode, one or more second selection units (e.g., Figure 15A Each of the SLUn in the above is configured to send to a corresponding second control unit in one or more second control units (e.g., Figure 15A The CUn in the system provides multiple (e.g., 2) selection signals.

[0153] Figure 16A This is a schematic diagram illustrating the structure of a display device according to some embodiments of the present disclosure. Figure 16B It is shown Figure 16A The timing diagram for the operation of the display device is shown below. (Refer to...) Figure 16A and Figure 16B In some embodiments, the display panel includes one or more first display areas A1 and one or more second display areas A2. The one or more first display areas A1 and the one or more second display areas A2 are configured to display images at different refresh rates. In one example, the one or more first display areas A1 are configured to display images at a first refresh rate, and the one or more second display areas A2 are configured to display images at a second refresh rate, wherein the first refresh rate and the second refresh rate are different from each other. In one example, the second refresh rate is greater than the first refresh rate.

[0154] In some embodiments, the method of driving the display device includes: in a third mode, selecting from a plurality of selection units (e.g., Figure 16A Multiple selection signals (SLU1 to SLUN) are provided to multiple control units (e.g., Figure 16A (CU1 to CUN); to multiple control units (e.g., Figure 16A The CU1 to CUN units provide enable signals, thereby allowing multiple selection signals to pass through multiple control units respectively; and provide start signals from multiple control units to multiple scan unit groups (e.g., ...). Figure 16A The images are displayed at a second refresh rate (e.g., a high refresh rate) in a display area (e.g., the entire display area) of a display panel (e.g., the entire display area).

[0155] Examples of suitable display devices include, but are not limited to, electronic paper, mobile phones, tablet computers, televisions, monitors, laptop computers, digital photo albums, GPS devices, etc. Optionally, the display device is an organic light-emitting diode (OLED) display device. Optionally, the display device is a miniature OLED display device. Optionally, the display device is a micro-LED display device.

[0156] For illustrative and descriptive purposes, the foregoing description of embodiments of the invention has been provided. It is not exhaustive, nor is it intended to limit the invention to the precise forms or exemplary embodiments disclosed. Therefore, the foregoing description should be considered illustrative rather than restrictive. Clearly, many modifications and variations will be apparent to those skilled in the art. The embodiments were chosen and described to explain the principles of the invention and its best mode of practical application, thereby enabling those skilled in the art to understand the various embodiments of the invention and the various modifications suitable for the particular use or implementation contemplated. The scope of the invention is intended to be defined by the appended claims and their equivalents, wherein, unless otherwise stated, all terms are to be interpreted in their broadest reasonable sense. Therefore, the terms “the invention,” “the present invention,” etc., do not necessarily limit the scope of the claims to the specific embodiments, and references to exemplary embodiments of the invention do not imply limitation of the invention, nor should such limitation be inferred. The invention is defined only by the spirit and scope of the appended claims. Furthermore, these claims may involve the use of “first,” “second,” etc., followed by nouns or elements. These terms should be understood as nomenclature and should not be construed as limiting the number of elements modified by these nomenclatures unless a specific number has been given. Any advantages and benefits described may not apply to all embodiments of the invention. It should be understood that changes to the described embodiments can be made by those skilled in the art without departing from the scope of the invention as defined by the appended claims. Furthermore, the elements and components in this disclosure are not intended for public distribution, whether or not they are expressly recited in the appended claims.

Claims

1. A display device comprising a display panel and a scanning circuit, the scanning circuit being configured to provide a control signal to the display panel; in, The scanning circuit includes multiple stages, and each of the multiple stages includes a corresponding scanning unit among multiple scanning units; The plurality of scanning units are grouped into N groups, where N is a positive integer greater than 2; Each scan unit group includes one or more scan units; Each scanning unit in one or more scanning units of each scanning unit group is connected to one or more rows of sub-pixels in the display panel; The scanning circuit further includes N control units respectively connected to the N scanning unit groups, and N selection units connected to the N control units; Each of the N control units is configured to provide a start signal to a corresponding scan unit group in the N scan unit groups; and Each of the N selection units is configured to transmit one or more selection signals to the corresponding control unit.

2. The display device according to claim 1, wherein, Each of the N scanning unit groups is configured to receive the start signal from the corresponding control unit of the N control units; as well as Each scanning unit group is configured to output control signals to a corresponding display area of ​​the display panel step by step, and in the corresponding display area, the sub-pixel is configured to receive the control signals output from the corresponding scanning unit group.

3. The display device according to claim 1, wherein, The plurality of selection units include N cascaded levels; The plurality of scanning units comprises cascaded (m×N) stages, where m is a positive integer; and Each of the plurality of scanning unit groups comprises m cascaded levels.

4. The display device according to any one of claims 1 to 3, wherein, The nth selection unit is configured to receive the output signal from the output terminal of the preceding selection unit, where n is an integer greater than 1; as well as The nth selection unit is configured to output the nth selection signal to the nth control unit among the plurality of control units.

5. The display device according to any one of claims 1 to 4, wherein, The display panel includes one or more first display areas and one or more second display areas; The one or more first display areas are configured to display an image at a first refresh rate; The one or more second display areas are configured to display an image at a second refresh rate; and The second refresh rate is greater than the first refresh rate.

6. The display device according to claim 5, wherein, The control signal is a disable signal. When the disable signal is provided to one or more first control units among the plurality of control units, one or more selection signals from one or more first selection units do not pass through the one or more first control units, and the one or more first control units are configured not to provide a start signal to one or more first scan unit groups. The scanning units in the one or more first scanning unit groups maintain a constant voltage output; as well as The one or more first display areas corresponding to the one or more first scanning unit groups are configured to display images at the first refresh rate.

7. The display device according to claim 6, wherein, The plurality of scan units include a latch circuit configured to maintain the constant voltage output in the scan unit of the one or more first scan unit groups.

8. The display device according to claim 5, wherein, The control signal is an enable signal. When the enable signal is provided to one or more second control units among the plurality of control units, one or more selection signals from one or more second selection units pass through the one or more second control units, which are configured to provide one or more start signals to one or more second scan unit groups. as well as The one or more second display areas corresponding to the one or more second scanning unit groups are configured to display images at the second refresh rate.

9. The display device of claim 5, further comprising one or more enable signal lines configured to provide an enable signal or a disable signal to the plurality of control units.

10. A method for driving a display device, in, The display device includes a display panel and a scanning circuit, wherein the scanning circuit is configured to provide control signals to the display panel; The scanning circuit includes multiple stages, and each stage includes a corresponding scanning unit among multiple scanning units; The plurality of scanning units are grouped into N groups, where N is a positive integer greater than 2; Each scan unit group includes one or more scan units; Each scanning unit in one or more scanning units of each scanning unit group is connected to one or more rows of sub-pixels in the display panel; The scanning circuit further includes N control units respectively connected to the N scanning unit groups, and N selection units connected to the N control units; The method includes: Each of the N control units provides a start signal to the corresponding scan unit group in the N scan unit groups; and Each of the N selection units transmits one or more selection signals to the corresponding control unit.

11. The method of claim 10, further comprising: The start signal is received by each of the N scanning unit groups from the corresponding control unit of the N control units; as well as Each scanning unit group outputs control signals to the corresponding display area of ​​the display panel in turn, and in the corresponding display area, the sub-pixel is configured to receive the control signals output from the corresponding scanning unit group.

12. The method of claim 10, further comprising: The nth selection unit receives the output signal from the output terminal of the preceding selection unit, where n is an integer greater than 1; as well as The nth selection unit outputs the nth selection signal to the nth control unit among the plurality of control units.

13. The method according to claim 10, wherein, The display panel includes one or more first display areas and one or more second display areas; The method further includes: The image is displayed in one or more first display areas at a first refresh rate; and The image is displayed at a second refresh rate in one or more second display areas; The second refresh frequency is greater than the first refresh frequency.

14. The method of claim 13, further comprising: A disable signal is provided to one or more first control units among the plurality of control units; Prevent one or more selection signals from one or more first selection units from passing through the one or more first control units; Prevent the one or more first control units from providing start signals to one or more first scan unit groups; Maintain a constant voltage output in the scanning units of the one or more first scanning unit groups; as well as An image is displayed at the first refresh rate in one or more first display areas corresponding to the one or more first scanning unit groups.

15. The method of claim 13, further comprising: Provide an enable signal to one or more second control units among the plurality of control units; Allow one or more selection signals from one or more second selection units to pass through the one or more second control units; The one or more second control units provide one or more start signals to one or more second scanning unit groups; as well as The image is displayed at the second refresh rate in the one or more second display areas corresponding to the one or more second scanning unit groups.

16. The method of claim 10, wherein, The display panel includes one or more first display areas and one or more second display areas; The one or more first display areas are configured to display an image at a first refresh rate; The one or more second display areas are configured to display images at a second refresh rate; The second refresh rate is greater than the first refresh rate; The method includes: One or more selection signals from one or more first selection units are provided to one or more first control units; a disable signal is provided to one or more first control units to prevent the one or more selection signals from passing through the one or more first control units, the one or more first control units being configured not to provide a start signal to one or more first scan unit groups; and An image is displayed at a first refresh rate in one or more first display areas corresponding to the one or more first scanning unit groups.

17. The method of claim 16, further comprising: One or more selection signals from one or more second selection units are provided to one or more second control units; An enable signal is provided to one or more second control units, thereby allowing the one or more selection signals to pass through the one or more second control units; A start signal from one or more second control units is provided to one or more second scan unit groups; as well as An image is displayed at a second refresh rate in one or more second display areas corresponding to the one or more second scanning unit groups.

18. The method according to claim 16, wherein, In a frame of image, each of the one or more second selection units is configured to provide a plurality of selection signals to a corresponding second control unit in the one or more second control units.

19. The method according to claim 10, wherein, The display panel includes one or more first display areas and one or more second display areas; The one or more first display areas are configured to display an image at a first refresh rate; The one or more second display areas are configured to display images at a second refresh rate; The second refresh rate is greater than the first refresh rate; The method includes: Multiple selection signals from multiple selection units are provided to multiple control units respectively; Enable signals are provided to multiple control units, thereby allowing the multiple selection signals to pass through the multiple control units respectively; The start signal from the plurality of control units is provided to the plurality of scan unit groups; and The image is displayed at a second refresh rate in the display area of ​​the display panel.

20. The method of claim 10, wherein, The display panel includes multiple areas; The signal frequency of each selection unit is configured to be higher than the base frequency, thereby making the refresh frequency of one or more regions in the plurality of regions higher than the base frequency.

Images