Array substrate and liquid crystal display device

Abstract

The invention provides an array substrate and a liquid crystal display device, and belongs to the technical field of display, the array substrate comprises a plurality of sub-pixel units, each sub-pixel unit comprises a substrate, a thin film transistor, a pixel electrode and a common electrode, the thin film transistor comprises an active layer, and the active layer comprises a channel region; the pixel electrode is connected with the first electrode of the thin film transistor and comprises a plurality of electrode strips, and at least one end of each electrode strip comprises at least one first corner; the common electrode is located on the side, close to the substrate, of the pixel electrode. The orthographic projection of the common electrode on the substrate is overlapped with the orthographic projection of the pixel electrode on the substrate. Wherein the common electrode in at least one sub-pixel unit comprises at least one second corner, and the orthographic projection, on the substrate, of the second corner is located in the orthographic projection, on the substrate, of the area, where the first corner is located, of the electrode strip; and at least one sub-pixel unit further comprises a shielding layer, and the orthographic projection of the shielding layer on the substrate covers the orthographic projection of the channel region on the substrate.

Description

Technical Field

[0001] The present disclosure relates to the field of display technology, and in particular to an array substrate and a liquid crystal display device. Background Art

[0002] Liquid crystal display, or LCD (Liquid CryS1tal DiS1play), is a flat ultra-thin display device. Among them, the liquid crystal display generally includes a backlight panel, an array substrate (also called a TFT substrate), a color film substrate, and liquid crystal located between the color film substrate and the array substrate. Among them, the brightness of the liquid crystal display has always been an important display indicator of the product. However, when the brightness of the liquid crystal display is increased, the product often suffers from crosstalk. Summary of the invention

[0003] Based on the background technology, the present disclosure proposes an array substrate and a liquid crystal display device.

[0004] In a first aspect of the present disclosure, an array substrate is provided, comprising a plurality of sub-pixel units, wherein the sub-pixel units include:

[0005] substrate;

[0006] A thin film transistor, located on the substrate and comprising an active layer, wherein the active layer comprises a channel region;

[0007] A pixel electrode, comprising a plurality of electrode strips, at least one end of each of the electrode strips comprising at least one first corner; and

[0008] A common electrode, located on a side of the pixel electrode close to the substrate, wherein an orthographic projection of the common electrode on the substrate overlaps with an orthographic projection of the pixel electrode on the substrate;

[0009] The common electrode in at least one of the sub-pixel units comprises at least one second corner, and the orthographic projection of the second corner on the substrate is located within the orthographic projection of the region where the first corner is located in the electrode strip on the substrate;

[0010] Furthermore, at least one of the sub-pixel units further includes a shielding layer, and an orthographic projection of the shielding layer on the substrate at least covers an orthographic projection of the channel region on the substrate.

[0011] Exemplarily, the angle of the first corner is the same as the angle of the second corner.

[0012] Exemplarily, the electrode strip comprises a first end and a second end opposite to each other, and the first corner is located at the first end;

[0013] Wherein, a first vertical distance between the orthographic projection of the vertex of the first corner on the substrate and the orthographic projection of the second end on the substrate is greater than or equal to a second vertical distance between the orthographic projection of the vertex of the second corner on the substrate and the orthographic projection of the second end on the substrate.

[0014] Exemplarily, the first vertical distance is greater than the second vertical distance, wherein the vertex of the second corner is located at the reverse extension line of the vertex of the first corner.

[0015] Exemplarily, the electrode strip comprises a first end and a second end opposite to each other, and the first corner is located at the first end; the plurality of electrode strips comprise an edge electrode strip located at an edge and an intermediate electrode strip adjacent to the edge electrode strip, and an orthographic projection of the second corner on the substrate is located within an orthographic projection of a region of the edge electrode strip where the first corner is located on the substrate;

[0016] Among them, the orthographic projection of the target endpoint of the common electrode connected to the second corner and close to the first endpoint on the substrate has a lateral distance from the orthographic projection of the intermediate electrode strip on the substrate, and the lateral distance increases as the vertical distance from the second corner to the second end decreases.

[0017] Exemplarily, one end of the electrode strip includes at least one of the first corners;

[0018] The orthographic projections of the electrode strips in two adjacent sub-pixel units on the substrate are centrally symmetrical.

[0019] Exemplarily, the shielding layer includes a first shielding layer located on a side of the channel region close to the substrate, and / or includes a second shielding layer located on a side of the channel region away from the substrate.

[0020] Exemplarily, the blocking layer includes the first blocking layer, and the thin film transistor includes:

[0021] A gate layer, located on a side of the channel region close to the substrate;

[0022] Part or all of the first shielding layer is the gate layer, and the orthographic projection of the first shielding layer on the substrate covers the orthographic projection of the active layer on the substrate.

[0023] Exemplarily, one side of the substrate includes a plurality of gate lines, the active layer includes a source region and a drain region located on opposite sides of the channel region, and the source region, the channel region and the drain region are arranged in an extending direction of the gate lines;

[0024] Wherein, in the extending direction of the data line, there is a third vertical distance between the outer contour of the orthographic projection of the first shielding layer on the substrate and the outer contour of the orthographic projection of the active layer on the substrate, and in the extending direction of the gate line, there is a fourth vertical distance between the outer contour of the orthographic projection of the first shielding layer on the substrate and the outer contour of the orthographic projection of the active layer on the substrate;

[0025] Wherein, the third vertical distance is greater than the fourth vertical distance.

[0026] Exemplarily, the third vertical distance is 4 μm to 5 μm, and the fourth vertical distance is 2.7 to 3 μm.

[0027] Exemplarily, one side of the substrate includes a plurality of data lines, the active layer includes a source region and a drain region located on opposite sides of the channel region, and the source region, the channel region and the drain region are arranged in an extending direction of the data lines;

[0028] Wherein, a vertical distance between an outer contour of an orthographic projection of the first shielding layer on the substrate and an outer contour of an orthographic projection of the active layer on the substrate is 2.7 μm to 3 μm.

[0029] Exemplarily, the blocking layer includes the first blocking layer and the second blocking layer, and the thin film transistor includes:

[0030] A first gate layer, located on one side of the substrate;

[0031] A first gate insulating layer is located on a side of the first gate layer away from the substrate, and the active layer is located on a side of the first gate insulating layer away from the substrate;

[0032] A second gate insulating layer, located on a side of the active layer away from the substrate;

[0033] A second gate layer, located on a side of the second gate insulating layer facing away from the substrate;

[0034] Part or all of the first shielding layer is the first gate layer, and part or all of the second shielding layer is the second gate layer.

[0035] Exemplarily, the shielding layer includes the second shielding layer, and the second shielding layer includes:

[0036] an organic insulating layer, wherein an orthographic projection of the organic insulating layer on the substrate covers an orthographic projection of the channel region on the substrate;

[0037] Wherein, the refractive index of the organic insulating layer is smaller than the refractive index of the liquid crystal.

[0038] Exemplarily, a preset relationship is satisfied among the size of the organic insulating layer on the normal line of the substrate, the size of the channel region on the plane of the substrate, the refractive index of the organic insulating layer, and the refractive index of the liquid crystal.

[0039] Exemplarily, the array substrate includes a display area, the plurality of sub-pixel units are located in the display area, and the display area includes a plurality of sub-display areas;

[0040] Wherein, the shielding layers located in the sub-pixel units of the plurality of sub-display areas have different spatial positions and / or shielding sizes;

[0041] The spatial position represents the upper and lower positions of the blocking layer and the channel layer relative to the substrate, and the blocking size includes the vertical distance between the outer contour of the orthographic projection of the blocking layer on the substrate and the outer contour of the orthographic projection of the channel region on the substrate.

[0042] According to a second aspect of the present disclosure, there is provided a liquid crystal display device, comprising:

[0043] A color filter substrate, and an array substrate as described in any exemplary embodiment of the first aspect;

[0044] The color filter substrate and the array substrate are arranged in a box-type arrangement, and liquid crystal is filled between the color filter substrate and the array substrate.

[0045] Exemplarily, a spacer column is further provided between the color filter substrate and the array substrate;

[0046] The array substrate includes an organic insulating layer, the spacer column is located on a side of the organic insulating layer away from the substrate, and an orthographic projection of the spacer column on the substrate overlaps with an orthographic projection of the organic insulating layer on the substrate.

[0047] Exemplarily, the organic insulating layer includes a plurality of first grooves, the spacer column includes first protrusions respectively matching the plurality of first grooves, and the plurality of first protrusions are respectively embedded in the first grooves;

[0048] Alternatively, the spacer column includes a plurality of second grooves, the organic insulating layer includes second protrusions respectively matching the plurality of second grooves, and the plurality of second protrusions are respectively embedded in the second grooves.

[0049] The array substrate proposed in the present disclosure includes a plurality of sub-pixel units, wherein the sub-pixel units include: a substrate, a thin film transistor, a pixel electrode and a common electrode, wherein the thin film transistor includes an active layer, and the active layer includes a channel region; the pixel electrode is connected to the first electrode of the thin film transistor and includes a plurality of electrode strips, and at least one end of the electrode strip includes at least one first corner; the common electrode is located on a side of the pixel electrode close to the substrate, and the orthographic projection of the common electrode on the substrate overlaps with the orthographic projection of the pixel electrode on the substrate; wherein the common electrode in at least one sub-pixel unit includes at least one second corner, and the orthographic projection of the second corner on the substrate is located within the orthographic projection of the region where the first corner is located in the electrode strip on the substrate; and, at least one sub-pixel unit also includes a shielding layer, and the orthographic projection of the shielding layer on the substrate covers the orthographic projection of the channel region on the substrate. Among them, by adding a second corner in the common electrode, an electric field can be formed between the second corner and the first corner, so that the electric field at the end of the pixel electrode is improved, and then the light output of the sub-pixel unit is increased, thereby improving the light efficiency of the product; wherein, by adding a shielding layer to block the channel area, it is possible to avoid changes in the characteristics of the thin film transistor when the high-brightness backlight irradiates the channel area, such as improving the phenomenon of increasing Ioff of the thin film transistor, thereby causing CroS1S1talk defects in the product. In summary, the design of the shielding layer and the second corner can ensure that the product has a higher display brightness while avoiding CroS1S1talk defects caused by the use of high-brightness backlight.

[0050] The above description is only an overview of the technical solution of the present disclosure. In order to more clearly understand the technical means of the present disclosure, it can be implemented according to the contents of the specification. In order to make the above and other purposes, features and advantages of the present disclosure more obvious and easy to understand, the specific implementation methods of the present disclosure are listed below. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or related technologies, the following is a brief introduction to the drawings required for use in the embodiments or related technical descriptions. Obviously, the drawings described below are some embodiments of the present disclosure. For ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. It should be noted that the proportions in the drawings are only for illustration and do not represent the actual proportions.

[0052] Figure 1 A schematic top view of an array substrate is shown;

[0053] Figure 2 Shows Figure 1 A schematic diagram of the cross-sectional structure of a sub-pixel unit in the AA direction;

[0054] Figure 3 Shows Figure 1 An enlarged schematic diagram of the S1 region of the sub-pixel unit in FIG.

[0055] Figure 4 Shows Figure 1 Schematic diagram of the working principle of the occlusion layer in the image;

[0056] Figure 5-Figure 9 Schematic diagrams of enlarged partial areas S1 of several sub-pixel units are shown respectively;

[0057] Fig.10 Shows Fig. 9 An enlarged schematic diagram of the circled area H in FIG.

[0058] Fig.11 A schematic plan view of another array substrate is shown;

[0059] Fig.12 Shows Fig.11 A schematic diagram of the layout of the common electrode in FIG.

[0060] Fig.13 Shows Figure 1 A magnified schematic diagram of the middle S2 region;

[0061] Fig.14 A schematic diagram showing the covering relationship between the first shielding layer and the active layer is shown;

[0062] Fig.15 and Fig.18 Schematic diagrams of the layout of two array substrates are shown respectively;

[0063] Fig.16 Shows Fig.15 A magnified schematic diagram of the middle S2 region;

[0064] Fig.17 A schematic cross-sectional structure diagram of a thin film transistor in yet another embodiment is shown;

[0065] Fig.19 yes Fig.18 A magnified schematic diagram of the middle S2 region;

[0066] Fig. 20 A schematic diagram showing the light path between the backlight reflected by the cover plate and the organic insulating layer;

[0067] Fig.21 Several different division diagrams of the display area are shown;

[0068] Fig. 22 A schematic cross-sectional structure diagram of a liquid crystal display device is shown;

[0069] Fig.23 Schematic diagrams showing shapes of various complementary designs of organic insulating layers and spacer pillars.

[0070] Description of reference numerals:

[0071] 100, array substrate; 200, color filter substrate; 300, spacer column; 11, substrate; 12, thin film transistor; 13, electrode strip; 14, common electrode; 121, gate layer; 122, gate insulating layer; 123, active layer; 124, drain electrode; 125, source electrode; 15, shielding layer; 16, flat layer; 17, data line; 18, gate line; 131, first corner; 141, second corner; 20, opening area; 13a, first end of electrode strip; 13b, the second end of the electrode strip; 132, the middle electrode strip; 133, the edge electrode strip; 1231, the channel region; 1233, the source region; 1232, the drain region; 151, the sub-shielding layer; 1211, the first gate layer; 1212, the second gate layer; 1221, the first gate insulating layer; 1222, the second gate insulating layer; 1213, the via; 110, the sub-display region; 21, the black matrix layer; 22, the color filter layer; 23, the OC layer; 24, the transparent substrate. DETAILED DESCRIPTION

[0072] In order to make the above-mentioned purposes, features and advantages of the present disclosure more obvious and understandable, the technical solutions in the embodiments of the present disclosure will be clearly and completely described below in conjunction with the drawings in the embodiments of the present disclosure. Obviously, the described embodiments are part of the embodiments of the present disclosure, rather than all the embodiments. Based on the embodiments in the present disclosure, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of the present disclosure.

[0073] As the demand for LCD products continues to expand, the brightness of LCD products needs to be improved. For example, in products such as smart phones, outdoor billboards, car instruments, navigation equipment and outdoor billboards, display brightness is an important quality indicator. Among them, the brightness improvement solutions for LCD products include the following:

[0074] 1. Optimize pixel design, increase the number of pixel electrode strips, and improve light efficiency; 2. Increase pixel aperture ratio; 3. Replace CF color resist raw materials; 4. Replace liquid crystal raw materials; 5. Use high-brightness backlight panel;

[0075] In general, the above five solutions can be used as appropriate according to the use environment of the liquid crystal display product, such as using a high-brightness backlight panel in outdoor display. However, each of the above solutions has its own disadvantages. For example, although increasing the number of pixel electrode strips can improve the product transmittance, it requires a significant improvement in process capabilities under a certain aperture ratio, and the product's VOP will also increase accordingly, thereby increasing the actual IC capability requirements; secondly, in order to increase the pixel aperture ratio, the usual approach is to reduce the wrapping distance of the black matrix to the structure that needs to be shielded on the array substrate. In this way, for high-brightness / high-transmittance products, the strong light incident on the backlight panel will be reflected and irradiated to the active layer (mainly the channel area) of the thin film transistor. The active layer is affected by the strong light and generates charge drift, which increases Ioff and causes serious CroS1S1talk defects; similarly, for high-brightness backlight panels, the backlight is deflected after the birefringence effect of the liquid crystal, and after deflection, it also irradiates the active layer (mainly the channel area) in the thin film transistor TFT, thereby causing CroS1S1talk defects (abbreviated as CT defects).

[0076] Thirdly, the replacement of liquid crystal raw materials is limited by the supplier's new material development and verification and is generally not used in actual production.

[0077] It can be seen that in the related technology, if the display brightness is to be improved, high-brightness backlight is used or the pixel aperture ratio is increased, which will cause the product to have poor CT. If the CT poor is to be avoided, it is necessary to increase the wrapping of the active layer, such as increasing the wrapping distance of the black matrix to the active layer. This will reduce the aperture ratio and affect the display brightness, making how to avoid CT poor and improve display brightness a very difficult problem in actual production.

[0078] In view of this, the inventors have proposed an optimization scheme for the sub-pixel structure. By optimizing the pixel electrode and the common electrode in the sub-pixel structure, the inventors aim to start from the structural characteristics of the pixel electrode and the common electrode to optimize the display light efficiency and improve the product transmittance and brightness without increasing the actual product production requirements. On this basis, a shielding layer can also be used to shield the channel area of ​​the active layer to improve CT poorness. In this way, the wrapping distance of the black matrix to the active layer can be reduced, the aperture ratio can be increased, and the overall display brightness of the product can be improved.

[0079] First, before formally introducing the embodiment of the array substrate proposed in the present disclosure, the technical terms used in the embodiment are explained accordingly:

[0080] Corner: refers to a point and the figure formed by two non-parallel line segments connected by the point. The point is called the intersection of two straight lines, and the point is generally called the vertex of the corner. The degree of the corner refers to the angle formed by the two line segments at the intersection. In this embodiment, the two line segments constituting the corner can be both straight line segments or both circular arc segments, or one of the two line segments is a straight line segment and the other is a circular arc segment.

[0081] Parallel: It means that the angle formed between two straight lines is 0~5o, the angle formed between the two straight lines is 0o, and the angle formed between the two straight lines is 5o. In other words, the angle formed between two straight lines is within the range of 0~5o, and they can be called orthogonal.

[0082] Please combine Figure 1-Figure 4 As shown, Figure 1 1 shows a schematic top view of an array substrate, Figure 2 Shows Figure 1 A schematic diagram of the cross-sectional structure of a sub-pixel unit in the AA direction, Figure 3 Shows Figure 1 An enlarged schematic diagram of the S1 region of the sub-pixel unit in FIG. Figure 4 Shows Figure 1 Schematic diagram of the working principle of the occlusion layer in Figure 1-Figure 4 As shown, in this embodiment, the array substrate includes a plurality of sub-pixel units, wherein each sub-pixel unit may include the following structure:

[0083] Substrate 11;

[0084] The thin film transistor 12 is located on the substrate 11 and includes an active layer 123 , wherein the active layer 123 includes a channel region 1231 ;

[0085] A pixel electrode, comprising a plurality of electrode strips 13, wherein at least one end of the electrode strip 13 comprises at least one first corner 131; and

[0086] The common electrode 14 is located on a side of the pixel electrode close to the substrate, and the orthographic projection of the common electrode 14 on the substrate 11 overlaps with the orthographic projection of the pixel electrode on the substrate 11;

[0087] The common electrode 14 in at least one sub-pixel unit includes at least one second corner 141, and the orthographic projection of the second corner on the substrate 11 is located within the orthographic projection of the region where the first corner 131 of the electrode strip 13 is located on the substrate 11;

[0088] Furthermore, at least one sub-pixel unit further includes a shielding layer 15 , and an orthographic projection of the shielding layer on the substrate covers an orthographic projection of the channel region 1231 on the substrate.

[0089] In this embodiment, the substrate of the sub-pixel unit may be a flexible substrate or a non-flexible substrate. Specifically, the substrate may be a transparent substrate, such as a glass substrate or a silicon-based substrate; for example, it may be a 50-1000 μm thick Corning or Asahi glass or other materials such as quartz glass. The substrate may be divided into a display area and a non-display area, the non-display area may enclose the display area, or partially enclose the display area, and a plurality of sub-pixel units may be located in the display area.

[0090] Among them, multiple sub-pixel units can be arranged in an array in the display area, for example, arranged in an array in the row direction and the column direction, and the area occupied by the orthographic projection of each sub-pixel unit on the substrate can be called a sub-pixel area.

[0091] The thin film transistor may be a bottom-gate thin film transistor, so that the light irradiated from the backlight panel to the array substrate can be shielded by the gate layer, thereby reducing the irradiation of the backlight to the active layer. Figure 2 As shown, the bottom-gate thin film transistor may include a gate layer 121, a gate insulating layer 122, an active layer 123, and a first electrode 124 and a second electrode 125 overlapped with the active layer 123. Specifically, the gate layer is located on one side of the substrate, the gate insulating layer is located on the side of the gate layer away from the substrate, the active layer is located on the side of the gate insulating layer away from the substrate, the active layer includes a channel region 1231, one of the two opposite side regions of the channel region 1231 is a source region 1232, a first electrode thereof overlaps with the source region 1232, and the other side region is a drain region 1233, a second electrode thereof overlaps with the drain region 1233, then the first electrode may be the source of the thin film transistor, and the second electrode may be the drain of the thin film transistor.

[0092] The active layer may be a low-temperature polysilicon material, such as an A-Si material. The process of forming the active layer is: forming a pattern of an A-Si layer on a substrate, and then using excimer laser annealing to crystallize the A-Si layer to form an active layer.

[0093] The pixel electrode may be connected to the first electrode or the second electrode of the thin film transistor, and the pixel electrode may include a plurality of electrode strips, the plurality of electrode strips are arranged at intervals, and the orthographic projections of the plurality of electrode strips on the substrate may be located in the sub-pixel region. Figure 1 and Figure 2 As shown, the pixel electrode includes a connecting portion and a plurality of electrode strips connected to the connecting portion, and the connecting portion is connected to the first electrode or the second electrode of the thin film transistor through a via hole.

[0094] One end of each electrode strip may include at least one first corner, or both opposite ends of each electrode strip may include at least one first corner, that is, a first corner is provided at one end or both ends of the electrode strip, and for a certain end of the electrode strip, the end may include one first corner or multiple first corners. Figure 3 As shown, a first corner is provided at one end of the electrode strip, and specifically, a first corner is provided at one end of the electrode strip close to the thin film transistor connected thereto.

[0095] As described above, the first corner may be a corner formed by an arc segment and a straight line segment, or may be a corner formed by two straight line segments.

[0096] Among them, the common electrode can be arranged in the same layer as the active layer of the thin film transistor, or can be arranged in the same layer as the first electrode and the second electrode. The common electrode is located on the side of the pixel electrode close to the substrate and overlaps with the pixel electrode. The overlap can include the orthographic projection of the common electrode on the substrate being located within the orthographic projection of the pixel electrode on the substrate, and the orthographic projection of the common electrode on the substrate being staggered with the orthographic projection of the pixel electrode on the substrate, such as the orthographic projection of a part of the common electrode on the substrate being located within the orthographic projection of the pixel electrode on the substrate, and the orthographic projection of the remaining part of the common electrode on the substrate having no overlap with the orthographic projection of the pixel electrode on the substrate. For example, Figure 1 and Figure 3 As shown, the orthographic projection of the common electrode on the substrate is located within the orthographic projection of the pixel electrode on the substrate.

[0097] Among them, Figure 1 and Figure 3 As shown, the pixel electrode includes a plurality of electrode strips, which may include two edge electrode strips located at the edge and an intermediate electrode strip located between the two edge electrode strips. The outer contour of the positive projection of the common electrode on the substrate may overlap with the positive projection of the two edge electrode strips on the substrate.

[0098] In this embodiment, there is at least one sub-pixel unit, and the common electrode in the sub-pixel unit includes at least one second corner. The second corner can be formed by bending the edge of the common electrode, that is, the edge of the common electrode is bent at at least one place, thereby forming a second corner.

[0099] The orthographic projection of the second corner on the substrate may be located within the orthographic projection of the region where the first corner is located in the electrode strip on the substrate; specifically, the orthographic projections of the second corner and the first corner on the substrate may be located at the same end of the electrode strip. For example, if the first end of the electrode strip has the first corner, the orthographic projection of the second corner on the substrate may also be located at the first end of the electrode strip. As described above, the outer contour of the orthographic projection of the second corner on the substrate may overlap with the orthographic projections of the two edge electrode strips on the substrate. Figure 3 As shown, the orthographic projection of the second corner of the common electrode on the substrate may be located within the orthographic projection of the edge electrode strip on the substrate.

[0100] Among them, the common electrode may include a second corner, and the orthographic projection of the second corner on the substrate may be located within the orthographic projection of an edge electrode strip on the substrate; or, the common electrode may include multiple second corners, and the orthographic projections of the multiple second corners on the substrate may be located within the orthographic projection of the same edge electrode strip on the substrate; or, the common electrode may include multiple second corners, and the orthographic projections of the multiple second corners on the substrate may be located within the orthographic projections of two edge electrode strips on the substrate, respectively. In this case, the common electrode may form second corners at the opposite side edges.

[0101] In this embodiment, the first corner and the second corner may have the same corner orientation, for example, Figure 3 As shown, both the first corner and the second corner can be facing the direction where the middle electrode strip is located, the degree of the first corner can be 10~90°, and the degree of the second corner can be 10~90°; or, the degree of the first corner can be 90~170°, and the degree of the second corner can be 0~170°; or, the first corner can be an acute angle, and the second corner can be an obtuse angle, or, the first corner can be an obtuse angle, and the second corner can be an acute angle.

[0102] The region where the first corner of the electrode strip is located may include a plurality of second corners, or include one first corner in the orthographic projection on the substrate. Specifically, the number of the second corners may be the same as the number of the first corners included on one end of the electrode strip. For example, if one end of the electrode strip includes a first corner, then the common electrode includes a second corner at a position corresponding to the first corner of the electrode strip. Alternatively, the number of the second corners may be different from the number of the first corners included on one end of the electrode strip. For example, Figure 3 As shown, one end of the electrode strip includes a plurality of first corners, and the common electrode includes a second corner at a position corresponding to the first corner of the electrode strip.

[0103] Since the second corner on the common electrode and the first corner on the electrode strip are located at the same end of the electrode strip, the common electrode and the pixel electrode can form a more complex electric field at the two corners (the first corner and the second corner). Under the action of this electric field, the transmittance of light here can be improved, thereby improving the display brightness.

[0104] In this embodiment, there is at least one sub-pixel unit, and the sub-pixel unit may further include a shielding layer 15, the orthographic projection of the shielding layer 15 on the substrate at least covers the orthographic projection of the channel region 1231 on the substrate. Figure 4 As shown, the shielding layer can be arranged on the side of the active layer close to the substrate, that is, the shielding layer can be located between the active layer and the backlight; or, the shielding layer can be arranged on the side of the active layer away from the substrate, that is, the shielding layer can be located between the active layer and the light emitting surface; or, the shielding layer is arranged on the side of the active layer away from the substrate and on the side of the active layer close to the substrate.

[0105] The shielding layer may be formed of a light-proof material, specifically, it may be a metal material or a non-metal material. When it is a non-metal material, it may be an organic material or an inorganic material.

[0106] like Figure 4 As shown in (a), when the shielding layer is arranged on the side of the active layer close to the substrate, the shielding layer can block the backlight from directly irradiating the channel area. As the area of ​​the channel area covered by the shielding layer increases, the brightness of the reflected light reflected by the plate on the side of the light emitting surface to the array substrate can be further reduced, thereby further reducing the risk of changes in TFT characteristics and improving CT defects.

[0107] like Figure 4 As shown in (b), when the shielding layer is arranged on the side of the active layer away from the substrate, the shielding layer can block the reflected light reflected by the plate on the side of the light emitting surface to the array substrate from irradiating the channel area. In this way, the shielding layer blocks the channel area. When the aperture ratio of the sub-pixel is increased, the reflected light reflected by the plate on the side of the light emitting surface to the array substrate can be completely blocked above the channel area. Therefore, while ensuring the aperture ratio and improving the display brightness, the CT defect can be further improved.

[0108] In an example, the common electrode of each sub-pixel unit may include a second corner, and the channel region of each sub-pixel unit may have a shielding layer.

[0109] The array substrate of this embodiment has the following advantages:

[0110] On the one hand, the second corner included in the common electrode in the sub-pixel unit can cooperate with the first corner to improve the light transmittance and increase the display brightness of the product. Therefore, the sub-pixel unit can also improve the display brightness under the same aperture ratio. In practice, it is allowed to increase the wrapping distance of the black matrix to the active layer. By increasing the wrapping distance, the active layer is protected from being irradiated and CT poor is avoided. Therefore, CT poor can be improved while ensuring the improvement of display brightness.

[0111] On the other hand, the sub-pixel unit includes a shielding layer for shielding the channel area. The shielding layer can prevent high-brightness backlight or reflected backlight from irradiating the channel area, thereby preventing poor CT. As a result, it is possible to reduce the wrapping distance of the black matrix to the active layer, thereby increasing the aperture ratio of the sub-pixel. When the aperture ratio increases, the light transmittance can be increased, thereby improving the display brightness. Therefore, it is possible to improve the display brightness while improving the poor CT.

[0112] On the other hand, the sub-pixel unit includes a blocking layer that blocks the channel region, which can allow the black matrix to reduce the wrapping distance of the active layer and increase the aperture ratio of the sub-pixel; the second corner of the common electrode in the sub-pixel unit can further increase the light transmittance and improve the display brightness when the aperture ratio is increased, so that the display brightness is doubled, thereby further improving the display brightness while improving the CT poor.

[0113] In an example of this embodiment, the degree of the first corner may be the same as the degree of the second corner, and the same may include a case where the difference between the degree of the first corner and the degree of the second corner is 1 to 2°.

[0114] For example, reference may be made to Figure 5 As stated, Figure 5 FIG. 4 shows an enlarged schematic diagram of a partial area S1 of another sub-pixel unit, as shown in FIG. Figure 5 As shown, the second corner and the first corner have the same orientation, wherein the first corner and the second corner are both obtuse angles, and the degree of the first corner and the degree of the second corner are the same.

[0115] When this embodiment is adopted, the first corner and the second corner at the edge of the electrode strip are designed to be parallel, which can reduce the dark area of ​​the edge of the sub-pixel, thereby increasing the brightness of the edge, thereby further improving the display brightness.

[0116] In another example of this embodiment, the display brightness can be further improved by adjusting the relative position between the second corner and the first corner. For example, the second corner can be closer to the opening area of ​​the sub-pixel than the first corner to improve the display brightness. The opening area refers to the area in the sub-pixel unit that is not blocked by the black matrix (the black matrix on the color filter substrate).

[0117] In this example, the first corner of the first end of the electrode strip is used as an example for explanation. The electrode strip includes a first end and a second end opposite to each other, and the first corner is located at the first end; wherein a first vertical distance between the orthographic projection of the vertex of the first corner on the substrate and the orthographic projection of the second end on the substrate is greater than or equal to a second vertical distance between the orthographic projection of the vertex of the second corner on the substrate and the orthographic projection of the second end on the substrate.

[0118] In this embodiment, please refer to Figure 6 and Figure 7 As shown, Figure 6 and Figure 7 Two schematic layout diagrams of a partial area S1 of a pixel unit are shown respectively, as Figure 6 and Figure 7 As shown, the electrode strip includes a first end 13a and a second end 13b relative to each other, wherein, taking the first corner located at the first end as an example, the first vertical distance between the first corner and the second end may be greater than the second vertical distance between the second corner and the second end, wherein the first vertical distance may be a perpendicular line from the vertex of the first corner to the horizontal line L where the second end is located, and the straight-line distance D1 between the focus between the perpendicular line and the horizontal line and the vertex of the first corner is the first vertical distance; similarly, the second vertical distance may be a perpendicular line from the vertex of the second corner to the horizontal line L where the second end is located, and the straight-line distance D2 between the focus between the perpendicular line and the horizontal line and the vertex of the second corner is the second vertical distance.

[0119] The first vertical distance may be the same as the second vertical distance, for example, Figure 6 As shown, the line between the vertex of the first corner and the vertex of the second corner can be parallel to the horizontal line L where the second end is located. Figure 6 As shown, the vertex of the first corner can be located at the edge of the opening area of ​​the sub-pixel, and the vertex of the second corner can also be located at the edge of the opening area of ​​the sub-pixel, and be on the same edge of the opening area of ​​the sub-pixel as the vertex of the first corner.

[0120] The first vertical distance may be greater than the second vertical distance, for example, Figure 7 As shown, the line between the vertex of the first corner and the vertex of the second corner may not be parallel to the horizontal line L where the second end is located, and the vertex of the second corner is closer to the second end of the electrode strip, that is, the vertex of the second corner is farther away from the edge of the opening area of ​​the sub-pixel.

[0121] In one example, if Figure 7As shown in FIG. 1 , when the first vertical distance is greater than the second vertical distance, the orthographic projection of the first corner on the substrate does not overlap with the opening area of ​​the sub-pixel, and the orthographic projection of the second corner on the substrate can be located within the opening area of ​​the sub-pixel. For example, the first corner can be located outside the opening area of ​​the sub-pixel, and the second corner can be located within the opening area of ​​the sub-pixel. For another example, Figure 7 As shown, the vertex of the first corner may be located on the edge of the opening area of ​​the sub-pixel, and the second corner may be located within the opening area of ​​the sub-pixel.

[0122] In some other examples, when the first vertical distance is greater than or equal to the second vertical distance, the first corner and the second corner may both be located outside or inside the opening area of ​​the sub-pixel (not shown in the figure).

[0123] By adopting this embodiment, the degrees of the first corner and the second corner can be the same or different. In the same situation, the second corner is closer to the opening area of ​​the sub-pixel than the first corner. Then, the second corner not only forms an electric field with the first corner parallel to it, but also can form a complex electric field with the edge of the electrode strip, thereby further increasing the light transmittance and the light effect.

[0124] Of course, in some other embodiments, the first vertical distance corresponding to the first corner may also be smaller than the second vertical distance corresponding to the second corner. For example, Figure 5 As shown, in this case, the first corner is closer to the opening area of ​​the sub-pixel than the second corner. The orthographic projections of the first corner and the second corner on the substrate do not overlap with the opening area of ​​the sub-pixel. For example, the first corner and the second corner are located outside the opening area of ​​the sub-pixel. For example, Figure 5 As shown, the vertex of the first corner is located on the edge of the opening area of ​​the sub-pixel, and the second corner is located outside the opening area of ​​the sub-pixel.

[0125] In some further embodiments, when the second vertical distance between the vertex of the second corner and the second end is continuously reduced, the target endpoint of the common electrode connected to the second corner may be continuously close to the electrode strip at the edge.

[0126] Specifically, it can be combined Figure 8 As shown, Figure 8 Schematic diagram showing the comparison of the second corner designs of two common electrodes, as shown in Figure 8 As shown, the plurality of electrode strips include edge electrode strips located at the edge and middle electrode strips adjacent to the edge electrode strips, and the orthographic projection of the second corner on the substrate is located within the orthographic projection of the region where the first corner is located in the edge electrode strips on the substrate. Specifically, the orthographic projection of the target endpoint of the common electrode connected to the second corner and close to the first endpoint on the substrate has a lateral distance from the orthographic projection of the middle electrode strip on the substrate, and the lateral distance increases as the second vertical distance decreases.

[0127] like Figure 8 As shown, the lateral distance may refer to the vertical distance D3 between the target endpoint and the middle electrode strip; wherein the target endpoint may refer to endpoint A of the second end of the common electrode adjacent to the second corner and close to the edge electrode strip, and the vertex of the second corner continuously approaches the opening area of ​​the sub-pixel, that is, when the second vertical continuously decreases, the target endpoint continuously moves away from the middle electrode strip.

[0128] Combination Figure 8 As shown, Figure 8 The second vertical distance corresponding to the second corner of the common electrode 14 shown by the solid line is greater than the second vertical distance corresponding to the second corner of the common electrode 14' shown by the dotted line, that is, the second corner of the common electrode shown by the dotted line is closer to the opening area; the lateral distance between the target end point A of the common electrode 14 and the middle electrode strip is smaller than the lateral distance between the target end point A' of the common electrode 14' and the middle electrode strip. Figure 8 As can be seen, the target endpoint A' is further to the right. In this way, as the target endpoint continues to move away from the middle electrode strip, it can form a more complex electric field with the peripheral edge of the pixel electrode, thereby continuously enhancing the light effect.

[0129] In a further example of this example, the position of the vertex of the second corner and the angle of the second corner can be set with the extreme position of the target endpoint as the maximum limit, and the extreme position of the target endpoint can be the position of the first electrode or the second electrode of the thin film transistor.

[0130] Specifically, the thin film transistor further includes a second electrode, and the first electrode and the second electrode overlap with regions of the active layer located on opposite sides of the channel region; wherein the orthographic projection of the target endpoint on the substrate can intersect with the orthographic projection of the first electrode or the second electrode on the substrate. Figure 8 As shown, when the target endpoint continuously moves rightward to the junction of the first electrode and the second electrode, the light effect can reach the maximum.

[0131] In another example of this embodiment, when the second vertical distance corresponding to the second corner is smaller than the first vertical distance corresponding to the first corner, there is a target structural feature between the second corner and the first corner, and the target structural feature can enable the sub-pixel to achieve the maximum light effect at the same aperture ratio. Fig. 9 and Fig.10 As shown, Fig. 9 A schematic diagram showing a partial area S1 of another sub-pixel unit is shown. Fig.10 Shows Fig. 9 An enlarged schematic diagram of the circled area H in FIG. Fig. 9 and Fig.10As shown, the vertex of the second corner is located at the reverse extension line of the vertex of the first corner.

[0132] The common electrode may include only one second corner, the electrode strip includes a first corner corresponding to the position of the second corner, and the vertex of the second corner is located on the reverse extension line of the first corner. In this case, the perpendicular line from the vertex of the second corner to the common electrode, the straight line segment between the vertex of the second corner and the vertex of the first corner, and the line segment between the intersection of the perpendicular line from the vertex of the first corner to the common electrode and the vertex of the second corner form a right triangle.

[0133] For example, Fig. 9 and Fig.10 For example, the first end of the electrode strip may include multiple first corners, and the common electrode may include multiple second corners; in the direction from the first end to the second end, the multiple first corners include a target first corner located at the end position, and the multiple second corners include a target second corner located at the starting position; wherein the vertex of the target second corner may be located on the reverse extension line of the vertex of the target first corner.

[0134] Among them, in the plane direction of the substrate, a perpendicular line is drawn from the first corner of the target to the common electrode, the perpendicular line has an intersection with the edge of the common electrode, the perpendicular distance from the first corner of the target to the common electrode, the straight-line distance between the second corner of the target and the first corner of the target, and the straight-line distance between the second corner of the target and the intersection satisfy the Pythagorean theorem.

[0135] In this embodiment, the common electrode may include a plurality of second corners, and the edge electrode strip may include a plurality of first corners, wherein the plurality of second corners may be continuously connected, and the orthographic projections of the plurality of second corners on the substrate may all be located on the side where the first end of the edge electrode strip is located. Fig. 9 As shown, the plurality of second corners are continuous, and their orthographic projections on the substrate can all be located within the orthographic projections of the edge electrode strips on the substrate.

[0136] The plurality of first corners and the plurality of second corners may be sequentially distributed in the direction from the first end to the second end. In one example, the second vertical distances corresponding to the plurality of second corners may be smaller than the first vertical distances corresponding to the first corners. Fig. 9 As shown, the second vertical distance corresponding to the target second corner at the starting position among the multiple second corners is smaller than the first vertical distance corresponding to the target first corner at the ending position among the multiple first corners, that is, each second corner among the multiple second corners is closer to the opening area of ​​the sub-pixel than any first corner.

[0137] For example, Fig. 9As shown, the plurality of second corners are all located within the opening area of ​​the sub-pixel, and the plurality of first corners may all be located outside the opening area of ​​the sub-pixel. Alternatively, in some other examples, the plurality of second corners are all located within the opening area of ​​the sub-pixel, and the plurality of first corners may include corners located outside the opening area of ​​the sub-pixel, and corners located within the opening area of ​​the sub-pixel. Alternatively, the plurality of second corners may include corners located within the opening area of ​​the sub-pixel and corners located outside the opening area, and the plurality of first corners may include corners located outside the opening area of ​​the sub-pixel, and corners located within the opening area of ​​the sub-pixel.

[0138] In this embodiment, the multiple first corners include a target first corner located at the end position, and the multiple second corners include a target second corner located at the starting position, wherein the vertex D of the target first corner can be made perpendicular to the common electrode, and the perpendicular has an intersection G with the edge of the common electrode, and the target second corner has a vertex E, wherein the vertical distance D4 from the vertex D of the target first corner to the common electrode, the straight-line distance D5 between the vertex E of the target second corner and the vertex D of the target first corner, and the straight-line distance D6 between the vertex E of the target second corner and the intersection G satisfy the Pythagorean theorem.

[0139] It should be noted that the straight line segment D6 between the vertex E of the target second corner and the intersection point G coincides with the edge of the common electrode, thereby forming a right triangle between the vertex D of the target first corner, the vertex E of the target second corner and the intersection point; wherein, the straight line segment between the vertex E of the target second corner and the vertex D of the target first corner is the hypotenuse of the right triangle.

[0140] With this setting, the lighting effect of the product can be maximized.

[0141] It should be noted that Figure 5-Figure 9 For the sake of clarity, the electrode strips and common electrode strips are not pattern filled.

[0142] In some other embodiments, the electrode strip may include at least one of the first corners at only one end; wherein the patterns of the orthographic projections of the electrode strips in two adjacent sub-pixel units on the substrate are centrally symmetrical.

[0143] Reference Fig.11 As shown, Fig.11 A schematic plan view of another array substrate is shown. Fig.11 As shown, the electrode strip in each sub-pixel unit on the array substrate is provided with a first corner at only one end, wherein the second corner on the common electrode corresponds to the position of the first corner of the electrode strip. Fig.12 As shown, Fig.12 Shows Fig.11 The schematic diagram of the layout of the common electrode in FIG. Fig.12As shown, the common electrode is provided with a second corner at a position corresponding to the first corner of the edge electrode strip, and the second corners in different sub-pixel units are located at different positions of the common electrode.

[0144] The orthographic projections of the electrode strips in two adjacent sub-pixel units on the substrate are centrally symmetrical, and the central symmetry may mean that one electrode strip is mirror-symmetrical to another electrode strip, for example, one electrode strip is obtained by vertically flipping another electrode strip. The two adjacent sub-pixel units may refer to sub-pixel units adjacent in the lateral direction (the extension direction of the gate line), or may refer to sub-pixel units adjacent in the longitudinal direction (the extension direction of the data line); or, as Fig.12 As shown, it may refer to every two adjacent sub-pixel units.

[0145] With this embodiment, one end of the electrode strip has a first corner, while the other end does not have the first corner. Thus, the aperture ratio of the sub-pixel can be increased, the transmittance can be improved, and thus the overall brightness of the product can be increased. In addition, the electrode strip adopts a single-sided corner design, which can also avoid trace mura (scratch marks).

[0146] The above is an exemplary description of the design of the electrode strips of the common electrode and the pixel electrode of the present disclosure. Next, the shielding layer for shielding the channel region is introduced.

[0147] In some embodiments, the blocking layer may include a first blocking layer located on a side of the channel region close to the substrate and / or a second blocking layer located on a side of the channel region away from the substrate.

[0148] Specifically, the shielding layer may be a first shielding layer, or the shielding layer may be a second shielding layer, or the shielding layer may include a first shielding layer and a second shielding layer. Wherein, in the case of including the first shielding layer and the second shielding layer, the first shielding layer may block the backlight from directly irradiating the channel region, and the second shielding layer may block the reflected light reflected from the plate on the light-emitting surface side to the array substrate above the channel region, thereby preventing strong light from irradiating the TFT from the upper and lower sides of the channel region, thereby reducing the risk of TFT characteristic changes and improving CT failure.

[0149] Specifically, in one example, the shielding layer may include a first shielding layer, and the first shielding layer may be disposed at the same layer as the gate layer and connected to the gate layer. Figure 2 As shown, in this example, the thin film transistor may include a gate layer, which may be located on a side of the channel region close to the substrate; wherein part or all of the first shielding layer is the gate layer, and the orthographic projection of the first shielding layer on the substrate covers the orthographic projection of the active layer on the substrate.

[0150] In this example, the entire area of ​​the first shielding layer may be the gate layer, that is, the gate layer may serve as a shielding layer for shielding the channel region. The orthographic projection of the gate layer on the substrate may cover the channel region. Specifically, Figure 2 and Figure 1 As shown, the orthographic projection of the gate layer on the substrate can cover the active layer, thereby preventing the entire active layer from being illuminated.

[0151] When the first blocking layer covers the active layer, the distance that the first blocking layer wraps the active layer can be determined according to the positional relationship between the active layer, the first electrode and the second electrode, wherein the positional relationship between the active layer, the first electrode and the second electrode can be understood as the placement direction of the thin film transistor on the substrate.

[0152] Illustratively, in one example, the placement direction of the thin film transistor on the substrate may be based on the gate line 18 and the data line 17 on the substrate.

[0153] In an exemplary embodiment, one side of the substrate includes a plurality of gate lines, and the active layer includes a source region and a drain region located on opposite sides of the channel region, and the source region, the channel region and the drain region are arranged in the extension direction of the gate line. Then, in the extension direction of the data line, there is a third vertical distance between the outer contour of the orthographic projection of the first shielding layer on the substrate and the outer contour of the orthographic projection of the active layer on the substrate, and there is a fourth vertical distance between the outer contour of the orthographic projection of the first shielding layer on the substrate and the outer contour of the orthographic projection of the active layer on the substrate in the extension direction of the gate line; wherein the third vertical distance is greater than the fourth vertical distance.

[0154] Please combine Figure 1 as well as Fig.13 As shown, Fig.13 Shows Figure 1 The enlarged schematic diagram of the S2 region is shown in Figure 2. Fig.13 and Figure 2 As shown, the source region, channel region and drain region of the entire thin film transistor are arranged in the extension direction of the gate line, so that the source region and the drain region are located on the opposite sides of the channel region in the extension direction of the gate line, that is, the source region and the drain region are located on the opposite sides of the channel region in the lateral direction, so that the thin film transistor is arranged horizontally on the array substrate, wherein the lateral direction is the extension direction of the gate line, and the longitudinal direction can be the extension direction of the data line.

[0155] Generally speaking, when displaying, the high-brightness backlight mainly illuminates the active layer from both sides of the array substrate in the longitudinal direction, that is, from both sides of the extension direction of the data line, after the liquid crystal birefringence, resulting in changes in the characteristics of the TFT. In order to eliminate the longitudinal influence, the first shielding layer can be added to wrap the active layer in the longitudinal direction. Specifically, please combine Fig.13As shown, in the lateral direction, there is a third vertical distance A between the outer contour of the orthographic projection of the first blocking layer on the substrate and the outer contour of the orthographic projection of the active layer on the substrate; in the longitudinal direction, there is a fourth vertical distance B between the outer contour of the orthographic projection of the first blocking layer on the substrate and the outer contour of the orthographic projection of the active layer on the substrate, wherein the third vertical distance A is greater than the fourth vertical distance B, thereby blocking the reflected light emitted to the TFT from the longitudinal sides of the array substrate.

[0156] In a further example of this embodiment, the third vertical distance may be 4 μm to 5 μm, and the fourth vertical distance may be 2.7 to 3 μm. For example, the third vertical distance may be 4 μm, 4.2 μm, 4.2 μm, 4.4 μm, 4.5 μm, 4.6 μm, 4.8 μm and 5 μm, and the fourth vertical distance may be 2.7 μm, 2.8 μm, 2.9 μm and 3 μm.

[0157] In this embodiment, the entire area of ​​the first shielding layer can be a gate layer, or the first shielding layer includes a gate layer and a shielding sublayer connected to the gate layer, and the orthographic projection of the shielding sublayer on the substrate can be connected to the outer edge of the orthographic projection of the gate layer on the substrate, wherein the shielding sublayer can be made of the same metal as the gate layer, or the shielding sublayer can be made of organic insulating material or inorganic insulating material.

[0158] Wherein, in the case where the first shielding layer includes a gate layer and a shielding sublayer connected to the gate layer, the orthographic projection of the gate layer on the substrate covers the orthographic projection of the channel region on the substrate, and the orthographic projection of the shielding sublayer on the substrate covers the region of the active layer except the channel region. Fig.14 As shown, Fig.14 A schematic diagram showing the covering relationship between the first shielding layer and the active layer is shown, as Fig.14 As shown, the first shielding layer includes a gate layer and a shielding sublayer, the orthographic projection of the gate layer on the substrate covers the orthographic projection of the channel region on the substrate, and the orthographic projection of the shielding sublayer on the substrate covers the region of the active layer except the channel region and has no overlap with the channel region. Specifically, in the lateral direction, there is a third vertical distance A between the outer contour of the orthographic projection of the shielding sublayer on the substrate and the outer contour of the orthographic projection of the active layer on the substrate; in the longitudinal direction, there is a fourth vertical distance B between the outer contour of the orthographic projection of the shielding sublayer on the substrate and the outer contour of the orthographic projection of the active layer on the substrate, wherein the third vertical distance A is greater than the fourth vertical distance B.

[0159] In another embodiment, the thin film transistor can be placed vertically, in which case it is blocked by the gate layer in the lateral direction and blocked by the first electrode and the second electrode in the longitudinal direction. Specifically, the source region, the channel region and the drain region are arranged in the extending direction of the data line; wherein the vertical distance between the outer contour of the orthographic projection of the first shielding layer on the substrate and the outer contour of the orthographic projection of the channel region on the substrate is 2.7 μm to 3 μm.

[0160] Please combine this embodiment with Fig.15 and Fig.16 As shown, Fig.15 A schematic diagram of the layout of another array substrate is shown. Fig.16 Shows Fig.15 The enlarged schematic diagram of the S2 region is shown in Figure 2. Fig.15 and Fig.16 As shown, the source region, channel region and drain region of the entire thin film transistor are arranged in the extension direction of the data line, so that the source region and the drain region are located on the opposite sides of the channel region in the extension direction of the data line, that is, the source region and the drain region are located on the opposite sides in the longitudinal direction of the channel region, so that the thin film transistor is arranged longitudinally on the array substrate.

[0161] In this arrangement, the first electrode and the second electrode, that is, the source metal and the drain metal of the thin film transistor, shield the channel region in the vertical direction, and the gate layer shields in the horizontal direction. In this case, compared with the horizontal placement, the first shielding layer can have a smaller wrapping distance to the active layer. For example, the vertical distance between the outer contour of the orthographic projection of the first shielding layer on the substrate and the outer contour of the orthographic projection of the active layer on the substrate is 2.7μm to 3μm.

[0162] In this setting, Fig.16 As shown, in the lateral direction, there is a third vertical distance A between the outer contour of the orthographic projection of the first shielding layer on the substrate and the outer contour of the orthographic projection of the active layer on the substrate; in the longitudinal direction, there is a fourth vertical distance B between the outer contour of the orthographic projection of the first shielding layer on the substrate and the outer contour of the orthographic projection of the active layer on the substrate, wherein the third vertical distance A and the fourth vertical distance B may be the same, or the difference between the two may be controlled within 1 μm. Specifically, the third vertical distance A and the fourth vertical distance B may both be 2.7 μm to 3 μm.

[0163] For example, when the thin film transistor is disposed vertically, the third vertical distance may be 2.7 μm, 2.8 μm, 2.9 μm, and 3 μm, and the fourth vertical distance may be 2.7 μm, 2.8 μm, 2.9 μm, and 3 μm.

[0164] In specific implementation, the third vertical distance and the fourth vertical distance can be adjusted according to the backlight brightness. Generally speaking, the higher the backlight brightness, the larger the third vertical distance and the fourth vertical distance can be. In other words, the third vertical distance and the fourth vertical distance are positively correlated with the backlight brightness.

[0165] In this embodiment, when the thin film transistor is placed vertically, the entire area of ​​the first shielding layer can be the gate layer, that is, the gate layer serves as a shielding layer for the active layer. Alternatively, the first shielding layer can include the gate layer and a shielding sublayer surrounding the gate layer. The positional relationship between the shielding sublayer and the gate layer can be combined with Fig.14 The introduction has been described above and will not be repeated here.

[0166] In some other embodiments, the shielding layer may include a first shielding layer and a second shielding layer. In this case, the thin film transistor may be a gate type thin film transistor. Fig.17 As shown, Fig.17 A schematic cross-sectional structure diagram of a thin film transistor in another embodiment is shown. Fig.17 As shown, the thin film transistor includes:

[0167] A first gate layer 1211 is located on one side of the substrate;

[0168] A first gate insulating layer 1221 is located on a side of the first gate layer away from the substrate, and an active layer is located on a side of the first gate insulating layer away from the substrate;

[0169] A second gate insulating layer 1222 is located on a side of the active layer facing away from the substrate;

[0170] A second gate layer 1212, located on a side of the second gate insulating layer facing away from the substrate;

[0171] Part or all of the first shielding layer is the first gate layer, and part or all of the second shielding layer is the second gate layer.

[0172] The first gate layer and the second gate layer are connected via via holes 1213 on the first gate insulating layer and the second gate insulating layer.

[0173] In this embodiment, the first gate layer can be used as the first shielding layer, and the second gate layer can be used as the second shielding layer, or the first shielding layer includes the first gate layer and the sub-shielding layer 151 surrounding the first gate layer 121, and the second shielding layer includes the second gate layer and the sub-shielding layer surrounding the second gate layer, wherein the positional relationship between the sub-shielding layer and the gate layer can be Fig.14 The introduction has been described above and will not be repeated here.

[0174] In this example, when a dual-gate thin film transistor is used, the plan view of the array substrate can be referred to as Fig.18 and Fig.19 As shown, Fig.19 yes Fig.18 The enlarged schematic diagram of the S2 region is shown in Figure 2. Fig.18 and Fig.19 As shown, there are metal layers shielding the upper and lower sides of the thin film transistor, so the first shielding layer and the second shielding layer can directly use the corresponding first gate layer and the second gate layer.

[0175] Among them, the vertical distance between the outer contour of the orthographic projection of the first blocking layer on the substrate and the outer contour of the orthographic projection of the active layer on the substrate can be 2.7μm~3μm, and the vertical distance between the outer contour of the orthographic projection of the second blocking layer on the substrate and the outer contour of the orthographic projection of the active layer on the substrate can be 2.7μm~3μm.

[0176] In this embodiment, since the thin film transistor adopts a dual-gate structure, the Ioff of the dual-gate thin film transistor is smaller than that of the single-gate thin film transistor, which is approximately half of that of the single-gate thin film transistor. Therefore, CT failure can be improved. Furthermore, the first shielding layer and the second shielding layer still wrap the active layer, which can block the irradiation of the high-brightness backlight, so that CT failure will not occur.

[0177] In some embodiments, the second shielding layer may be made of an organic insulating layer material, for example, Figure 4 As shown, the second shielding layer includes an organic insulating layer, the orthographic projection of the organic insulating layer on the substrate covers the orthographic projection of the active layer on the substrate; wherein the refractive index of the organic insulating layer is smaller than the refractive index of the liquid crystal.

[0178] In this embodiment, the refractive index of the liquid crystal is 1.4, and the refractive index of the organic insulating layer is less than 1.4, for example, its refractive index may be 1.3, 1.2, 1.1, etc. The organic insulating layer is located above the active layer, and can block the backlight reflected by the cover plate on the light-emitting surface side. When the refractive index of the organic insulating layer is less than the refractive index of the liquid crystal, the organic insulating layer can refract the backlight refracted by the liquid crystal back to the liquid crystal, thereby preventing the backlight refracted by the liquid crystal from irradiating the thin film transistor.

[0179] The material of the organic insulating layer may be a resin material.

[0180] In this embodiment, the organic insulating layer may only cover the channel region. Specifically, the orthographic projection of the organic insulating layer on the substrate may cover the orthographic projection of the channel region on the substrate and be covered by the orthographic projection of the active layer on the substrate. Or, in some other examples, the orthographic projection of the organic insulating layer on the substrate may cover the orthographic projection of the active layer on the substrate.

[0181] In a further example of this embodiment, the thickness of the organic insulating layer is related to the backlight reflected by the cover plate of the light emitting surface irradiating the channel. Specifically, the size of the organic insulating layer on the normal line of the substrate, the size of the channel region on the plane of the substrate, the refractive index of the organic insulating layer, and the refractive index of the liquid crystal satisfy a preset relationship.

[0182] In this embodiment, the size of the organic insulating layer on the normal line of the substrate is the thickness of the organic insulating layer, which can also be called the height of the organic insulating layer. The size of the channel region on the plane of the substrate can refer to the size of the channel region in the extension direction of the gate line, or the size of the channel region in the direction of the data line. Specifically, when the thin film transistor is arranged horizontally, the size of the channel region on the plane of the substrate can be the size of the channel region in the extension direction of the gate line; when the thin film transistor is arranged vertically, the size of the channel region on the plane of the substrate can be the size of the channel region in the extension direction of the data line.

[0183] Among them, combined Fig. 20 As shown, Fig. 20 FIG. 4 shows a schematic diagram of the optical path between the backlight reflected by the cover plate and the organic insulating layer. Fig. 20 As shown, i is the incident angle of the backlight reflected by the cover plate, n1: the refractive index of the liquid crystal, n2: the refractive index of the organic insulating layer, L: the channel length, H: the height of the organic insulating layer; wherein, L≤L1+L2; L1 is the boundary of the backlight reflected by the cover plate when it is incident on the organic insulating layer and refracted by the organic insulating layer. The dotted line L' in the figure can be regarded as the limit boundary of the channel area that the light refracted by the organic insulating layer can avoid.

[0184]

[0185] When H satisfies the following preset relationship, the protection of the thin film transistor can be improved, and the effect of improving CT is better:

[0186]

[0187] When this example is used, the backlight reflected by the cover plate can deviate from the channel area, eliminating CT defects. In this example, the wrapping of the black matrix can be reduced, the aperture ratio of the sub-pixel can be increased, and the transmittance can be improved. Of course, when H does not satisfy the above preset relationship, crosstalk defects can also be alleviated to a certain extent.

[0188] In combination with the above shielding layer design, in some embodiments, the display area can be divided into a plurality of sub-display areas 110 according to the backlight brightness or according to the difference between the required display brightness and the actual display brightness. Fig.21 As shown, Fig.21 Schematic diagrams showing different ways of dividing the display area are shown. Fig.21 As shown, the division method can be regular division such as four-grid, nine-grid, etc., or can be irregular division. In practice, the display area can be divided into sub-display areas according to the analog value of the backlight brightness, and the number of sub-display areas is greater than or equal to 2.

[0189] Therein, the shielding layers of sub-pixel units located in different sub-display areas have different designs, which is mainly reflected in that the shielding layers of sub-pixel units located in multiple sub-display areas have different spatial positions and / or shielding sizes.

[0190] The spatial position represents the upper and lower positions of the shielding layer and the channel layer relative to the substrate, and the shielding size includes the vertical distance between the outer contour of the orthographic projection of the shielding layer on the substrate and the outer contour of the orthographic projection of the channel region on the substrate.

[0191] In this embodiment, the shielding layers of the sub-pixel units in the same sub-display area may have the same setting mode. Among them, the shielding layers located in multiple sub-display areas may have different spatial positions. For example, the shielding layer of the sub-pixel unit in one sub-display area is located on the side of the channel area away from the substrate, that is, the shielding layers of all sub-pixel units in the sub-display area include the second shielding layer; while the shielding layer of the sub-pixel unit in another sub-display area is located on the side of the channel area close to the substrate, that is, the shielding layers of all sub-pixel units in the sub-display area include the first shielding layer.

[0192] Alternatively, the blocking layers located in multiple sub-display areas may have different blocking sizes. For example, the blocking layer of the sub-pixel unit in one sub-display area wraps the active layer at a distance of 4 to 5 μm; while the blocking layer of the sub-pixel unit in another sub-display area wraps the active layer at a distance of 2.7 to 3 μm, where the wrapping distance is the vertical distance between the outer contour of the orthographic projection of the blocking layer on the substrate and the outer contour of the orthographic projection of the active layer on the substrate.

[0193] Alternatively, the shielding layers located in multiple sub-display areas may have different spatial positions and different shielding sizes. For example, the shielding layer of the sub-pixel unit in one sub-display area includes a first shielding layer, and the first shielding layer wraps the active layer to a wrapping distance of 4 to 5 μm; while the shielding layer of the sub-pixel unit in another sub-display area includes a second shielding layer, but the second shielding layer wraps the active layer to a wrapping distance of 2.7 to 3 μm. For another example, the shielding layer of the sub-pixel unit in one sub-display area includes a first shielding layer, the first shielding layer is a gate layer, and the first shielding layer wraps the active layer to a wrapping distance of 4 to 5 μm; while the shielding layer of the sub-pixel unit in another sub-display area includes a second shielding layer, the second shielding layer is an organic insulating layer, but the second shielding layer only wraps the channel area, not the active layer.

[0194] For example, taking the case where the blocking layer in the sub-pixel unit includes a first blocking layer, the vertical distance between the outer contour of the orthographic projection of the first blocking layer of the sub-pixel units located in different sub-display areas on the substrate and the outer contour of the orthographic projection of the active layer on the substrate can vary within 2.7 to 5 μm.

[0195] In this exemplary embodiment, the first shielding layer of the sub-pixel units located in different sub-display areas has different wrapping distances. For example, for a sub-display area with a higher backlight brightness, the third vertical distance of the first shielding layer in the longitudinal direction can be larger, such as a larger value of 4μm to 5μm, and at the same time, the fourth vertical distance of the first shielding layer in the transverse direction can be larger; for a sub-display area with a lower backlight brightness, the third vertical distance of the first shielding layer in the longitudinal direction can be smaller, such as a smaller value of 4μm to 5μm, or even 2.7 to 3μm, and at the same time, the fourth vertical distance of the first shielding layer in the transverse direction can be smaller.

[0196] By adopting this example, the thin film transistors in each sub-display area of ​​the display area are wrapped to different degrees, and the wrapping adjustment range is 2.7 to 5 um, thereby solving the high brightness CT problem and reducing the load at the same time.

[0197] Based on the same inventive concept, the present disclosure also provides a liquid crystal display device. Fig. 22 As shown, Fig. 22 Schematic diagram of the cross-sectional structure of a liquid crystal display device is shown. Fig. 22 As shown, the liquid crystal display device may include a color filter substrate 200 and the array substrate 100 described in any of the above array substrate embodiments; wherein the color filter substrate and the array substrate are arranged in a box, and liquid crystal is filled between the color filter substrate and the array substrate.

[0198] Among them, the color filter substrate includes an OC layer 23, which can be a planarization layer, which can be made of organic material or inorganic material, a color filter layer 22 and a black matrix layer 21 located on the side of the OC layer away from the array substrate, and a transparent substrate 24 located on the side of the black matrix layer away from the array substrate.

[0199] In this embodiment, a black matrix layer can be set on the color filter substrate, and the black matrix layer includes multiple opening areas 20, each opening area corresponds to a sub-pixel unit on the array substrate, and a color filter layer is set in the opening area, which may include a red color filter layer, a blue color filter layer and a green color filter layer.

[0200] The aperture ratio of the sub-pixel described in the above embodiment may refer to the opening area of ​​the opening zone. A plurality of spacer columns 300 are supported between the array substrate and the color film. The orthographic projection of the spacer columns 300 may overlap with the orthographic projection of the active layer in the array substrate on the substrate. That is to say, a plurality of spacer columns 300 may be arranged at the position of the active layer of the thin film transistor. The spacer columns 300 may also block the backlight reflected by the cover plate from irradiating the active layer.

[0201] In an example of this embodiment, the shielding layer on the array substrate for shielding the active layer may be an organic insulating layer located on the side of the channel region facing away from the substrate, and the spacer column may be located on the side of the organic insulating layer facing away from the substrate, wherein the orthographic projection of the spacer column on the substrate overlaps with the orthographic projection of the organic insulating layer on the substrate.

[0202] Please continue to refer to Fig. 22 As shown, the spacer column is stacked on the organic insulating layer, thereby improving the shielding effect on the active layer. The spacer column can be made of a low refractive index material, such as the refractive index of the spacer column can be less than the refractive index of the liquid crystal.

[0203] In an example of this embodiment, the embedding manner between the spacer column and the organic insulating layer may include: contact between the surface of the spacer column facing away from the substrate and the surface of the organic insulating layer facing away from the substrate, and embedding design between the spacer column and the organic insulating layer.

[0204] In a specific implementation, the organic insulating layer may include a plurality of first grooves, the spacer column includes a first protrusion that matches the plurality of first grooves, and the plurality of first protrusions are respectively embedded in the first grooves; or the spacer column may include a plurality of second grooves, the organic insulating layer includes a second protrusion that matches the plurality of second grooves, and the plurality of second protrusions are respectively embedded in the second grooves.

[0205] In this embodiment, the shape of the first groove is adapted to the shape of the first protrusion, and the shape of the second groove is adapted to the shape of the second protrusion. Specifically, the adaptation may mean that the orthographic projection of the first protrusion on the substrate is the same as the orthographic projection of the first groove on the substrate. For example, the orthographic projection of the first protrusion on the substrate is circular, and the orthographic projection of the first groove on the substrate is also circular; for another example, the orthographic projection of the first protrusion on the substrate is triangular, and the orthographic projection of the first groove on the substrate is also triangular; for another example, the orthographic projection of the first protrusion on the substrate is cross-shaped, and the orthographic projection of the first groove on the substrate is also cross-shaped.

[0206] Reference Fig.23 As shown, Fig.23 Schematic diagrams of shapes of various complementary designs of organic insulating layers and spacer columns are shown, wherein when the organic insulating layer and the spacer column are complementary and embedded, the shapes of the first protrusion and the second protrusion are not limited, such as Fig.23As shown, the shapes of the first protrusion and the second protrusion can be rectangular, trapezoidal, polygonal, cylindrical, triangular pyramidal, etc.

[0207] Using this example, an embedded fixing design is adopted between the spacer column and the organic insulating layer. The embedded design satisfies the complementary design of the spacer column and the organic insulating layer. When the array substrate and the color film substrate are aligned, the two can be embedded in each other. In this way, on the one hand, the alignment accuracy can be improved, and on the other hand, the connection stability between the two can be improved.

[0208] The various embodiments in this specification are described in a progressive manner, and each embodiment focuses on the differences from other embodiments. The same or similar parts between the various embodiments can be referenced to each other.

[0209] Finally, it should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, commodity or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, commodity or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, commodity or device including the elements.

[0210] The display method, device, system and medium provided by the present disclosure are introduced in detail above. Specific examples are used in this article to illustrate the principles and implementation methods of the present disclosure. The description of the above embodiments is only used to help understand the method of the present disclosure and its core idea. At the same time, for those skilled in the art, according to the idea of ​​the present disclosure, there will be changes in the specific implementation methods and application scope. In summary, the content of this specification should not be understood as a limitation on the present disclosure.

[0211] Those skilled in the art will readily appreciate other embodiments of the present disclosure after considering the specification and practicing the invention disclosed herein. The present disclosure is intended to cover any variations, uses or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art that are not disclosed in the present disclosure. The description and examples are to be considered exemplary only, and the true scope and spirit of the present disclosure are indicated by the following claims.

[0212] It should be understood that the present disclosure is not limited to the exact structures that have been described above and shown in the drawings, and that various modifications and changes may be made without departing from the scope thereof. The scope of the present disclosure is limited only by the appended claims.

[0213] References herein to "one embodiment," "embodiment," or "one or more embodiments" mean that a particular feature, structure, or characteristic described in conjunction with the embodiment is included in at least one embodiment of the present disclosure. In addition, please note that examples of the term "in one embodiment" do not necessarily all refer to the same embodiment.

[0214] In the description provided herein, a large number of specific details are described. However, it is understood that the embodiments of the present disclosure can be practiced without these specific details. In some instances, well-known methods, structures and techniques are not shown in detail so as not to obscure the understanding of this description.

[0215] In the claims, any reference signs placed between brackets shall not be construed as limiting the claims. The word "comprising" does not exclude the presence of elements or steps not listed in the claims. The word "a" or "an" preceding an element does not exclude the presence of a plurality of such elements. The present disclosure may be implemented by means of hardware comprising a number of different elements and by means of a suitably programmed computer. In a unit claim enumerating a number of means, several of these means may be embodied by the same item of hardware. The use of the words first, second, and third, etc. does not indicate any order. These words may be interpreted as names.

[0216] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present disclosure, rather than to limit them. Although the present disclosure has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the embodiments of the present disclosure.

Claims

1. An array substrate, characterized in that: The method comprises a plurality of sub-pixel units, wherein the sub-pixel units include: substrate; A thin film transistor, located on the substrate and comprising an active layer, wherein the active layer comprises a channel region; A pixel electrode, comprising a plurality of electrode strips, at least one end of each of the electrode strips comprising at least one first corner; and A common electrode, located on a side of the pixel electrode close to the substrate, wherein an orthographic projection of the common electrode on the substrate overlaps with an orthographic projection of the pixel electrode on the substrate; The common electrode in at least one of the sub-pixel units comprises at least one second corner, and the orthographic projection of the second corner on the substrate is located within the orthographic projection of the region where the first corner is located in the electrode strip on the substrate; Furthermore, at least one of the sub-pixel units further includes a shielding layer, and an orthographic projection of the shielding layer on the substrate at least covers an orthographic projection of the channel region on the substrate.

2. The array substrate according to claim 1, characterized in that: The angle of the first corner is the same as the angle of the second corner.

3. The array substrate according to claim 1 or 2, characterized in that: The electrode strip comprises a first end and a second end opposite to each other, and the first corner is located at the first end; Wherein, a first vertical distance between the orthographic projection of the vertex of the first corner on the substrate and the orthographic projection of the second end on the substrate is greater than or equal to a second vertical distance between the orthographic projection of the vertex of the second corner on the substrate and the orthographic projection of the second end on the substrate.

4. The array substrate according to claim 3, characterized in that: The first vertical distance is greater than the second vertical distance, wherein the vertex of the second corner is located at the reverse extension line of the vertex of the first corner.

5. The array substrate according to claim 1, 2 or 4, characterized in that: The electrode strip comprises a first end and a second end opposite to each other, and the first corner is located at the first end; the plurality of electrode strips comprise an edge electrode strip located at an edge and an intermediate electrode strip adjacent to the edge electrode strip, and the orthographic projection of the second corner on the substrate is located within the orthographic projection of the region where the first corner is located in the edge electrode strip on the substrate; Among them, the orthographic projection of the target endpoint of the common electrode connected to the second corner and close to the first endpoint on the substrate has a lateral distance from the orthographic projection of the intermediate electrode strip on the substrate, and the lateral distance increases as the vertical distance from the second corner to the second end decreases.

6. The array substrate according to any one of claims 1 to 4, characterized in that: One end of the electrode strip includes at least one of the first corners; The orthographic projections of the electrode strips in two adjacent sub-pixel units on the substrate are centrally symmetrical.

7. The array substrate according to claim 1, characterized in that: The shielding layer includes a first shielding layer located on a side of the channel region close to the substrate, and / or includes a second shielding layer located on a side of the channel region away from the substrate.

8. The array substrate according to claim 7, characterized in that: The shielding layer includes the first shielding layer, and the thin film transistor includes: A gate layer, located on a side of the channel region close to the substrate; Part or all of the first shielding layer is the gate layer, and the orthographic projection of the first shielding layer on the substrate covers the orthographic projection of the active layer on the substrate.

9. The array substrate according to claim 8, characterized in that: One side of the substrate includes a plurality of gate lines, the active layer includes a source region and a drain region located at opposite sides of the channel region, and the source region, the channel region and the drain region are arranged in the extending direction of the gate lines; Wherein, in the extending direction of the data line, there is a third vertical distance between the outer contour of the orthographic projection of the first shielding layer on the substrate and the outer contour of the orthographic projection of the active layer on the substrate, and in the extending direction of the gate line, there is a fourth vertical distance between the outer contour of the orthographic projection of the first shielding layer on the substrate and the outer contour of the orthographic projection of the active layer on the substrate; Wherein, the third vertical distance is greater than the fourth vertical distance.

10. The array substrate according to claim 9, characterized in that: The third vertical distance is 4 μm to 5 μm, and the fourth vertical distance is 2.7 to 3 μm.

11. The array substrate according to claim 8, characterized in that: One side of the substrate includes a plurality of data lines, the active layer includes a source region and a drain region located at opposite sides of the channel region, and the source region, the channel region and the drain region are arranged in an extending direction of the data lines; Wherein, a vertical distance between an outer contour of an orthographic projection of the first shielding layer on the substrate and an outer contour of an orthographic projection of the active layer on the substrate is 2.7 μm to 3 μm.

12. The array substrate according to claim 8, characterized in that: The shielding layer includes the first shielding layer and the second shielding layer, and the thin film transistor includes: A first gate layer, located on one side of the substrate; A first gate insulating layer is located on a side of the first gate layer away from the substrate, and the active layer is located on a side of the first gate insulating layer away from the substrate; A second gate insulating layer, located on a side of the active layer facing away from the substrate; A second gate layer, located on a side of the second gate insulating layer facing away from the substrate; Part or all of the first shielding layer is the first gate layer, and part or all of the second shielding layer is the second gate layer.

13. The array substrate according to claim 8, characterized in that: The shielding layer includes the second shielding layer, and the second shielding layer includes: an organic insulating layer, wherein an orthographic projection of the organic insulating layer on the substrate covers an orthographic projection of the channel region on the substrate; Wherein, the refractive index of the organic insulating layer is smaller than the refractive index of the liquid crystal.

14. The array substrate according to claim 13, characterized in that: A preset relationship is satisfied among the size of the organic insulating layer on the normal line of the substrate, the size of the channel region on the plane of the substrate, the refractive index of the organic insulating layer, and the refractive index of the liquid crystal.

15. The array substrate according to any one of claims 1 or 8-14, characterized in that: The array substrate comprises a display area, a plurality of sub-pixel units are located in the display area, and the display area comprises a plurality of sub-display areas; Wherein, the shielding layers located in the sub-pixel units of the plurality of sub-display areas have different spatial positions and / or shielding sizes; The spatial position represents the upper and lower positions of the blocking layer and the channel layer relative to the substrate, and the blocking size includes the vertical distance between the outer contour of the orthographic projection of the blocking layer on the substrate and the outer contour of the orthographic projection of the channel region on the substrate.

16. A liquid crystal display device, characterized in that: include: A color filter substrate, and an array substrate as claimed in any one of claims 1 to 15; The color filter substrate and the array substrate are arranged in a box-type arrangement, and liquid crystal is filled between the color filter substrate and the array substrate.

17. The liquid crystal display device according to claim 16, characterized in that: A spacer column is also provided between the color filter substrate and the array substrate; The array substrate includes an organic insulating layer, the spacer column is located on a side of the organic insulating layer away from the substrate, and an orthographic projection of the spacer column on the substrate overlaps with an orthographic projection of the organic insulating layer on the substrate.

18. The liquid crystal display device according to claim 17, characterized in that: The organic insulating layer includes a plurality of first grooves, the spacer column includes first protrusions respectively matching the plurality of first grooves, and the plurality of first protrusions are respectively embedded in the first grooves; Alternatively, the spacer column includes a plurality of second grooves, the organic insulating layer includes second protruding portions respectively matching the plurality of second grooves, and the plurality of second protruding portions are respectively embedded in the second grooves.

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