Bandgap reference circuit, ferroelectric memory and electronic device

Abstract

The application discloses a band gap reference circuit, a ferroelectric memory and an electronic device, and can be applied to the technical field of electronic circuits. The application sets a starting circuit, an error amplification circuit, a bias circuit, a mirror circuit, a stability coefficient control circuit and a voltage division circuit in the band gap reference circuit. The temperature coefficient of the circuit during the working process can be adjusted by the band gap reference circuit through the temperature coefficient control circuit. The error amplification circuit clamps the voltage of the bias circuit and then the bias circuit outputs a bias current. The mirror circuit mirrors the bias current and then performs voltage division on the bias current through the voltage division circuit to obtain a reference current that meets the current working temperature of the ferroelectric memory, so that the storage effect of the ferroelectric memory chip can be effectively maintained under high temperature.

Description

Technical Field

[0001] This application relates to the field of electronic circuit technology, and more particularly to a bandgap reference circuit, a ferroelectric memory, and an electronic device. Background Technology

[0002] In related technologies, in analog integrated circuits, the voltage reference magnitude is primarily dependent on temperature. This dependency is precisely defined, ensuring the reliability and consistency of the circuit under various temperature conditions. Simultaneously, this temperature-sensitive characteristic provides a reliable reference point for analog integrated circuits, thus guaranteeing the circuit's performance and stability under different temperature environments. The core design of a bandgap reference circuit lies in creating a stable reference source whose temperature changes have negligible impact. This circuit cleverly utilizes the characteristics of semiconductor devices: some devices exhibit a positive temperature coefficient as their voltage increases with temperature, while others exhibit a negative temperature coefficient as their voltage decreases. Currently, most bandgap reference circuits have non-adjustable temperature coefficients, with the output reference remaining almost unchanged within a temperature range of -40℃ to 125℃. However, because current ferroelectric memory chips gradually lose their ferroelectric properties at high temperatures, existing bandgap reference circuits cannot effectively maintain the storage performance of ferroelectric memory chips at high temperatures.

[0003] In summary, the technical problems existing in the relevant technologies need to be improved. Summary of the Invention

[0004] The main objective of this application is to provide a bandgap reference circuit, a ferroelectric memory, and an electronic device that can maintain the storage performance of the ferroelectric memory chip under high temperature conditions.

[0005] To achieve the above objectives, one aspect of this application provides a bandgap reference circuit, the bandgap reference circuit comprising:

[0006] A startup circuit is connected to an external input voltage and generates an output current based on the input voltage.

[0007] Error amplifier circuit;

[0008] A bias circuit, wherein the error amplifier circuit clamps the voltage of the bias circuit; the bias circuit is connected to the error amplifier circuit and is used to output a bias current;

[0009] A mirror circuit, connected to the bias circuit, is used to mirror the bias current and output a reference voltage.

[0010] A temperature coefficient control circuit is connected to the error amplifier circuit, the bias circuit and the mirror circuit respectively, and is used to adjust the temperature coefficient during the mirroring process of the mirror circuit.

[0011] A voltage divider circuit, the output of which is connected to a ferroelectric memory, is used to divide the reference voltage and then provide a reference current to the ferroelectric memory.

[0012] In some embodiments, the startup circuit includes a first PMOS transistor, a twelfth PMOS transistor, and a first NMOS transistor;

[0013] The external input voltage to the gate of the first NMOS transistor;

[0014] The drain of the first NMOS transistor and the drain of the first PMOS transistor are both connected to the gate of the twelfth PMOS transistor.

[0015] The source of the first PMOS transistor is connected to the source of the twelfth PMOS transistor.

[0016] The gate of the first PMOS transistor is connected to the first connection point, which is the connection point between the bias circuit and the mirror circuit.

[0017] In some embodiments, the mirror circuit includes a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, and an eleventh PMOS transistor;

[0018] The source terminals of the second PMOS transistor, the fourth PMOS transistor, the ninth PMOS transistor, and the tenth PMOS transistor are all connected to the source terminal of the first PMOS transistor.

[0019] The gate of the second PMOS transistor, the drain of the second PMOS transistor, the gate of the fourth PMOS transistor, the gate of the ninth PMOS transistor, and the gate of the tenth PMOS transistor are all connected to the source of the third PMOS transistor.

[0020] The drain of the fourth PMOS transistor is connected to the source of the fifth PMOS transistor.

[0021] The drain of the ninth PMOS transistor is connected to the source of the eighth PMOS transistor.

[0022] The drain of the tenth PMOS transistor is connected to the source of the eleventh PMOS transistor.

[0023] The drain of the third PMOS transistor, the gate of the third PMOS transistor, the gate of the fifth PMOS transistor, the gate of the eighth PMOS transistor, and the gate of the eleventh PMOS transistor are all connected to the first connection point.

[0024] In some embodiments, the error amplifier circuit includes a sixth PMOS transistor, a seventh PMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor;

[0025] The gate of the sixth PMOS transistor is connected to the drain of the fifth PMOS transistor;

[0026] The gate of the seventh PMOS transistor is connected to the drain of the eighth PMOS transistor.

[0027] The source of the sixth PMOS transistor is connected to the source of the seventh PMOS transistor.

[0028] The drain of the sixth PMOS transistor is connected to the drain of the third NMOS transistor, the gate of the third NMOS transistor, the gate of the second NMOS transistor, the gate of the fourth NMOS transistor, and the gate of the fifth NMOS transistor, respectively.

[0029] The drain of the seventh PMOS transistor is connected to the drain of the fourth NMOS transistor.

[0030] The source of the third NMOS transistor is connected to the drain of the second NMOS transistor;

[0031] The source of the fourth NMOS transistor is connected to the drain of the fifth NMOS transistor;

[0032] The source of the second NMOS transistor is connected to the source of the fifth NMOS transistor and then grounded.

[0033] In some embodiments, the bias circuit includes a sixth NMOS transistor;

[0034] The drain of the sixth NMOS transistor is connected to the first connection point;

[0035] The gate of the sixth NMOS transistor is connected to the drain of the seventh PMOS transistor.

[0036] The source of the sixth NMOS transistor is grounded.

[0037] In some embodiments, the temperature coefficient control circuit includes a positive temperature coefficient control circuit and a negative temperature coefficient control circuit;

[0038] The negative temperature coefficient control circuit includes a first transistor;

[0039] The emitter of the first transistor is connected to the voltage divider circuit;

[0040] The collector and base of the first transistor are both grounded;

[0041] The positive temperature coefficient control circuit includes a second resistor, a second transistor, and a third transistor;

[0042] The first end of the second resistor is connected to the drain of the eighth PMOS transistor and the gate of the seventh PMOS transistor, respectively.

[0043] The second end of the second resistor is connected to the emitter of the second transistor;

[0044] The base and collector of the second transistor are both grounded;

[0045] The emitter of the third transistor is connected to the gate of the sixth NMOS transistor;

[0046] The base and collector of the third transistor are both grounded.

[0047] In some embodiments, the voltage divider circuit includes a third resistor and a fourth resistor;

[0048] The first end of the third resistor is connected to the drain of the eleventh PMOS transistor;

[0049] The reference current is output at the connection point between the second end of the third resistor and the first end of the fourth resistor;

[0050] The second end of the fourth resistor is connected to the collector of the first transistor.

[0051] In some embodiments, the bandgap reference circuit further includes a first resistor, the first end of which is connected to the drain of the twelfth PMOS transistor.

[0052] To achieve the above objectives, another aspect of the embodiments of this application proposes a ferroelectric memory, including the bandgap reference circuit described above.

[0053] To achieve the above objectives, another aspect of the embodiments of this application proposes an electronic device including the aforementioned ferroelectric memory.

[0054] The embodiments of this application include at least the following beneficial effects: This application provides a bandgap reference circuit, a ferroelectric memory, and an electronic device. By setting a startup circuit, an error amplifier circuit, a bias circuit, a mirror circuit, a temperature coefficient control circuit, and a voltage divider circuit in the bandgap reference circuit, the temperature coefficient of the circuit during operation can be adjusted by the temperature coefficient control circuit through the bandgap reference circuit. After the error amplifier circuit clamps the voltage of the bias circuit, the bias circuit outputs a bias current. After the mirror circuit mirrors the bias current, it is then divided by the voltage divider circuit to obtain a reference current that conforms to the ferroelectric memory at the current operating temperature, thereby effectively maintaining the storage effect of the ferroelectric memory chip under high temperature conditions. Attached Figure Description

[0055] Figure 1 This is a schematic diagram of the bandgap reference circuit provided in the embodiments of this application. Detailed Implementation

[0056] To make the objectives, technical solutions, and advantages of this application clearer, the following detailed description is provided in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are merely illustrative of this application and are not intended to limit it. In the following description, when referring to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The embodiments described in the following exemplary embodiments do not represent all embodiments consistent with those of this application; they are merely examples of apparatuses and methods consistent with some aspects of the embodiments of this application.

[0057] It is understood that the terms “first,” “second,” etc., used in this application may be used herein to describe various concepts, but unless otherwise stated, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of the embodiments of this application, first information may also be referred to as second information, and similarly, second information may also be referred to as first information. Depending on the context, the words “if,” “when,” or “in response to a determination” as used herein may be interpreted as “when…” or “when…” or “in response to a determination.”

[0058] As used in this application, the terms "at least one", "multiple", "each", "any", etc., "at least one" includes one, two or more, "multiple" includes two or more, "each" refers to each of the corresponding multiples, and "any" refers to any one of the multiples.

[0059] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by one of ordinary skill in the art to which this application belongs. The terminology used herein is for the purpose of describing embodiments of this application only and is not intended to limit this application.

[0060] This application provides a bandgap reference circuit, which includes a startup circuit, an error amplifier circuit, a bias circuit, a mirror circuit, a temperature coefficient control circuit, and a voltage divider circuit. The startup circuit receives an external input voltage and starts the bandgap reference circuit when the input voltage exceeds a threshold voltage, generating an output current based on the input voltage. The temperature coefficient control circuit is connected to the error amplifier circuit, the bias circuit, and the mirror circuit, respectively. After the bandgap reference circuit starts, it adjusts the temperature coefficient during the mirroring process of the mirror circuit. The error amplifier circuit clamps the voltage of the bias circuit using its "virtual short" characteristic. The bias circuit is connected to the error amplifier circuit to output the bias current. The mirror circuit is connected to the bias circuit and, based on the Cascode mirroring principle, mirrors the bias current to output a constant reference voltage. The output of the voltage divider circuit is connected to a ferroelectric memory to divide the reference voltage and provide a reference current to the ferroelectric memory. Specifically, the bandgap reference circuit provided in this embodiment can provide a reference current with a zero temperature coefficient at room temperature and a reference current with a positive temperature coefficient at high temperatures.

[0061] In the embodiments of this application, such as Figure 1 As shown, the startup circuit includes a first PMOS transistor PM1, a twelfth PMOS transistor PM12, and a first NMOS transistor NM1. The gate of the first NMOS transistor NM1 is connected to an external input voltage; the drains of both the first NMOS transistor NM1 and the first PMOS transistor PM1 are connected to the gate of the twelfth PMOS transistor PM12; the source of the first NMOS transistor NM1 is grounded; the source of the first PMOS transistor PM1 is connected to the source of the twelfth PMOS transistor PM12; the gate of the first PMOS transistor PM1 is connected to a first connection point, which is the connection point between the bias circuit and the mirror circuit. Specifically, this embodiment, by setting a first PMOS transistor, a twelfth PMOS transistor, and a first NMOS transistor in the startup circuit, can break the degeneracy state when the input voltage VDD rises, thereby reducing energy loss during circuit operation.

[0062] In the embodiments of this application, such as Figure 1As shown, the mirror circuit includes the second PMOS transistor PM2, the third PMOS transistor PM3, the fourth PMOS transistor PM4, the fifth PMOS transistor PM5, the eighth PMOS transistor PM8, the ninth PMOS transistor PM9, the tenth PMOS transistor PM10, and the eleventh PMOS transistor PM11. The source of the second PMOS transistor PM2, the source of the fourth PMOS transistor PM4, the source of the ninth PMOS transistor PM9, and the source of the tenth PMOS transistor PM10 are all connected to the source of the first PMOS transistor PM1; the gate and drain of the second PMOS transistor PM2, the gate of the fourth PMOS transistor PM4, the gate of the ninth PMOS transistor PM9, and the gate of the tenth PMOS transistor PM10 are all connected to the source of the third PMOS transistor PM3; the drain of the fourth PMOS transistor PM4 is connected to the source of the fifth PMOS transistor PM5; the drain of the ninth PMOS transistor PM9 is connected to the source of the eighth PMOS transistor PM8; the drain of the tenth PMOS transistor PM10 is connected to the source of the eleventh PMOS transistor PM11; the drain and gate of the third PMOS transistor PM3, the gate of the fifth PMOS transistor PM5, the gate of the eighth PMOS transistor PM8, and the gate of the eleventh PMOS transistor PM11 are all connected to the first connection point. Specifically, this embodiment improves the stability of circuit operation by setting up a mirror circuit, thereby providing constant current or constant voltage under different temperature coefficients.

[0063] In the embodiments of this application, such as Figure 1As shown, the error amplifier circuit includes a sixth PMOS transistor PM6, a seventh PMOS transistor PM7, a second NMOS transistor NM2, a third NMOS transistor NM3, a fourth NMOS transistor NM4, and a fifth NMOS transistor NM5. The gate of the sixth PMOS transistor PM6 is connected to the drain of the fifth PMOS transistor PM5; the gate of the seventh PMOS transistor PM7 is connected to the drain of the eighth PMOS transistor PM8; the source of the sixth PMOS transistor PM6 is connected to the source of the seventh PMOS transistor PM7; the drain of the sixth PMOS transistor PM6 is connected to the drain of the third NMOS transistor, the gate of the third NMOS transistor NM3, the gate of the second NMOS transistor NM2, the gate of the fourth NMOS transistor NM4, and the gate of the fifth NMOS transistor NM5, respectively; the drain of the seventh PMOS transistor NM7 is connected to the drain of the fourth NMOS transistor NM4; the source of the third NMOS transistor NM3 is connected to the drain of the second NMOS transistor NM2; the source of the fourth NMOS transistor NM4 is connected to the drain of the fifth NMOS transistor NM5; the source of the second NMOS transistor NM2 is connected to the source of the fifth NMOS transistor NM5 and then grounded. Specifically, in this embodiment, the temperature coefficient of the sixth and seventh PMOS transistors is 0 at room temperature by using their gates as inputs; then, the positive temperature coefficient under high temperature conditions is adjusted by using the inverse ratios of the second, third, fourth, and fifth NMOS transistors.

[0064] In the embodiments of this application, such as Figure 1 As shown, the bias circuit includes a sixth NMOS transistor NM6; the drain of the sixth NMOS transistor NM6 is connected to the first connection point; the gate of the sixth NMOS transistor NM6 is connected to the drain of the seventh PMOS transistor PM7; and the source of the sixth NMOS transistor NM6 is grounded. In this embodiment, the bias current output by the bias circuit is controlled by the output of the error amplifier circuit.

[0065] The temperature coefficient control circuit includes a positive temperature coefficient control circuit and a negative temperature coefficient control circuit. In the embodiments of this application, such as... Figure 1As shown, the negative temperature coefficient control circuit includes a first transistor Q1; the emitter of the first transistor Q1 is connected to a voltage divider circuit; the collector and base of the first transistor Q1 are both grounded; the positive temperature coefficient control circuit includes a second resistor R2, a second transistor Q2, and a third transistor Q3; the first end of the second resistor R2 is connected to the drain of the eighth PMOS transistor PM8 and the gate of the seventh PMOS transistor PM7, respectively; the second end of the second resistor R2 is connected to the emitter of the second transistor Q2; the base and collector of the second transistor Q2 are both grounded; the emitter of the third transistor Q3 is connected to the gate of the sixth NMOS transistor NM6; the base and collector of the third transistor Q3 are both grounded. Specifically, in this embodiment, by setting the first transistor as a negative temperature coefficient transistor, setting the second and third transistors as positive temperature coefficient transistors, and controlling the positive temperature coefficient ratio through the second resistor, the bandgap reference circuit can output a reference current that conforms to the ferroelectric memory at the current operating temperature.

[0066] In the embodiments of this application, such as Figure 1 As shown, the voltage divider circuit includes a third resistor R3 and a fourth resistor R4; the first terminal of the third resistor R3 is connected to the drain of the eleventh PMOS transistor PM11; the connection point between the second terminal of the third resistor R3 and the first terminal of the fourth resistor R4 outputs a reference current; the second terminal of the fourth resistor R4 is connected to the collector of the first transistor Q1. In this embodiment, by setting up the voltage divider circuit, the voltage corresponding to a specific temperature coefficient can be output by adjusting the resistor ratio in the voltage divider circuit.

[0067] And, as Figure 1 As shown, the bandgap reference circuit in this embodiment of the application further includes a first resistor R1. The first end of the first resistor R1 is connected to the drain of the twelfth PMOS transistor PM12, thereby preventing the capacitor C1 in the circuit from being damaged during startup, and thus improving the circuit's operating life.

[0068] In summary, the bandgap reference circuit provided in this application has the following beneficial effects:

[0069] First, the output voltage exhibits different temperature coefficients in different temperature ranges, thus eliminating the need for two reference circuits with different temperature coefficients, effectively reducing circuit area and cost.

[0070] Secondly, by selecting a specific size load RC, the output anti-interference capability can maintain a psrr of over 45 even below 1GHz, demonstrating ultra-high anti-interference capability.

[0071] Third, conventional bandgap reference circuits directly control the PMOS gate voltage with their op-amp output to regulate current, which cannot finely adjust the current magnitude at different temperatures. In this application, the op-amp output controls the NMOS gate, and the current is then regulated via a current mirror. Under high-temperature conditions, the operating state of the fifth NMOS transistor changes, and the current surge strengthens the positive temperature coefficient, achieving a zero temperature coefficient at room temperature and a positive temperature coefficient at high temperatures.

[0072] Fourth, existing bandgap circuits use three bipolar junction transistors (BJTs) to output a zero-temperature coefficient current, which is then mirrored to the fourth branch. This application achieves the same effect without the fourth branch, effectively reducing the circuit area.

[0073] Furthermore, embodiments of this application also provide a ferroelectric memory and an electronic device. The ferroelectric memory includes the aforementioned bandgap reference circuit, and the electronic device includes the ferroelectric memory. It is understood that the ferroelectric memory may include, but is not limited to, a ferroelectric chip and a bandgap reference circuit. The bandgap reference circuit is used to provide a reference current or reference voltage for the ferroelectric chip.

[0074] It is understood that the content of the above-described bandgap reference circuit embodiments is applicable to the present ferroelectric memory and electronic device embodiments, and the beneficial effects achieved by the present ferroelectric memory and electronic device embodiments are the same as those achieved by the above-described bandgap reference circuit embodiments.

[0075] The embodiments described in this application are for the purpose of more clearly illustrating the technical solutions of the embodiments of this application, and do not constitute a limitation on the technical solutions provided by the embodiments of this application. As those skilled in the art will know, with the evolution of technology and the emergence of new application scenarios, the technical solutions provided by the embodiments of this application are also applicable to similar technical problems.

[0076] Those skilled in the art will understand that the technical solutions shown in the figures do not constitute a limitation on the embodiments of this application, and may include more or fewer steps than shown, or combine certain steps, or different steps.

[0077] The device embodiments described above are merely illustrative. The units described as separate components may or may not be physically separate; that is, they may be located in one place or distributed across multiple network units. Some or all of the modules can be selected to achieve the purpose of this embodiment according to actual needs.

[0078] Those skilled in the art will understand that all or some of the steps in the methods disclosed above, as well as the functional modules / units in the systems and devices, can be implemented as software, firmware, hardware, or suitable combinations thereof.

[0079] The terms “first,” “second,” “third,” “fourth,” etc. (if present) in the specification and accompanying drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence. It should be understood that such data can be interchanged where appropriate so that the embodiments of this application described herein can be implemented in orders other than those illustrated or described herein. Furthermore, the terms “comprising” and “having,” and any variations thereof, are intended to cover non-exclusive inclusion; for example, a process, method, system, product, or apparatus that comprises a series of steps or units is not necessarily limited to those steps or units explicitly listed, but may include other steps or units not explicitly listed or inherent to such processes, methods, products, or apparatus.

[0080] It should be understood that in this application, "at least one (item)" means one or more, and "more than" means two or more. "And / or" is used to describe the relationship between related objects, indicating that three relationships can exist. For example, "A and / or B" can represent three cases: only A exists, only B exists, and both A and B exist simultaneously, where A and B can be singular or plural. The character " / " generally indicates that the preceding and following related objects are in an "or" relationship. "At least one (item) of the following" or similar expressions refer to any combination of these items, including any combination of single or plural items. For example, at least one (item) of a, b, or c can represent: a, b, c, "a and b", "a and c", "b and c", or "a and b and c", where a, b, and c can be single or multiple.

[0081] In the several embodiments provided in this application, it should be understood that the disclosed apparatus and methods can be implemented in other ways. For example, the apparatus embodiments described above are merely illustrative; for instance, the division of the units described above is only a logical functional division, and in actual implementation, there may be other division methods. For example, multiple units or components may be combined or integrated into another system, or some features may be ignored or not executed. Furthermore, the coupling or direct coupling or communication connection shown or discussed may be through some interfaces; the indirect coupling or communication connection between apparatuses or units may be electrical, mechanical, or other forms.

[0082] The units described above as separate components may or may not be physically separate. The components shown as units may or may not be physical units; that is, they may be located in one place or distributed across multiple network units. Some or all of the units can be selected to achieve the purpose of this embodiment according to actual needs.

[0083] Furthermore, the functional units in the various embodiments of this application can be integrated into one processing unit, or each unit can exist physically separately, or two or more units can be integrated into one unit. The integrated unit can be implemented in hardware or as a software functional unit.

[0084] If the integrated unit is implemented as a software functional unit and sold or used as an independent product, it can be stored in a computer-readable storage medium. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, or all or part of the technical solution, can be embodied in the form of a software product. This computer software product is stored in a storage medium and includes multiple instructions to cause a computer device (which may be a personal computer, server, or network device, etc.) to execute all or part of the steps of the methods of the various embodiments of this application. The aforementioned storage medium includes various media capable of storing programs, such as USB flash drives, portable hard drives, read-only memory (ROM), random access memory (RAM), magnetic disks, or optical disks.

[0085] The preferred embodiments of the present application have been described above with reference to the accompanying drawings, but this does not limit the scope of the claims of the present application. Any modifications, equivalent substitutions, and improvements made by those skilled in the art without departing from the scope and substance of the embodiments of the present application shall be within the scope of the claims of the present application.

Claims

1. A bandgap reference circuit, characterized in that, The bandgap reference circuit includes: A startup circuit is connected to an external input voltage and generates an output current based on the input voltage. Error amplifier circuit; A bias circuit is included, wherein the error amplifier circuit clamps the voltage of the bias circuit; the bias circuit is connected to the error amplifier circuit; and the bias circuit is used to output a bias current. A mirror circuit, connected to the bias circuit, is used to mirror the bias current and output a reference voltage. A temperature coefficient control circuit is connected to the error amplifier circuit, the bias circuit and the mirror circuit respectively, and is used to adjust the temperature coefficient during the mirroring process of the mirror circuit. A voltage divider circuit, the output of which is connected to a ferroelectric memory, is used to divide the reference voltage and then provide a reference current to the ferroelectric memory. The temperature coefficient control circuit includes a positive temperature coefficient control circuit and a negative temperature coefficient control circuit. The negative temperature coefficient control circuit includes a first transistor; The emitter of the first transistor is connected to the voltage divider circuit; The collector and base of the first transistor are both grounded; The positive temperature coefficient control circuit includes a second resistor, a second transistor, and a third transistor; The first terminal of the second resistor is connected to both the mirror circuit and the error amplifier circuit. The second end of the second resistor is connected to the emitter of the second transistor; The base and collector of the second transistor are both grounded; The emitter of the third transistor is connected to the bias circuit; The base and collector of the third transistor are both grounded.

2. The bandgap reference circuit according to claim 1, characterized in that, The startup circuit includes a first PMOS transistor, a twelfth PMOS transistor, and a first NMOS transistor; The external input voltage to the gate of the first NMOS transistor; The drain of the first NMOS transistor and the drain of the first PMOS transistor are both connected to the gate of the twelfth PMOS transistor. The source of the first PMOS transistor is connected to the source of the twelfth PMOS transistor; The gate of the first PMOS transistor is connected to the first connection point, which is the connection point between the bias circuit and the mirror circuit. The bandgap reference circuit further includes a first resistor and a capacitor. The first end of the first resistor is connected to the drain of the twelfth PMOS transistor, the second end of the first resistor is connected to the first end of the capacitor, and the connection point between the second end of the capacitor and the source of the first NMOS transistor is connected to the bias circuit and the temperature coefficient control circuit, respectively.

3. The bandgap reference circuit according to claim 2, characterized in that, The mirror circuit includes a second PMOS transistor, a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, and an eleventh PMOS transistor; The source of the second PMOS transistor, the source of the fourth PMOS transistor, the source of the ninth PMOS transistor, and the source of the tenth PMOS transistor are all connected to the source of the first PMOS transistor. The gate of the second PMOS transistor, the drain of the second PMOS transistor, the gate of the fourth PMOS transistor, the gate of the ninth PMOS transistor, and the gate of the tenth PMOS transistor are all connected to the source of the third PMOS transistor. The drain of the fourth PMOS transistor is connected to the source of the fifth PMOS transistor; The drain of the ninth PMOS transistor is connected to the source of the eighth PMOS transistor. The drain of the tenth PMOS transistor is connected to the source of the eleventh PMOS transistor. The drain of the third PMOS transistor, the gate of the third PMOS transistor, the gate of the fifth PMOS transistor, the gate of the eighth PMOS transistor, and the gate of the eleventh PMOS transistor are all connected to the first connection point. The drains of the fifth PMOS transistor and the eighth PMOS transistor are both connected to the temperature coefficient control circuit. The drain of the eleventh PMOS transistor is connected to the voltage divider circuit.

4. The bandgap reference circuit according to claim 3, characterized in that, The error amplifier circuit includes a sixth PMOS transistor, a seventh PMOS transistor, a second NMOS transistor, a third NMOS transistor, a fourth NMOS transistor, and a fifth NMOS transistor; The gate of the sixth PMOS transistor is connected to the drain of the fifth PMOS transistor; The gate of the seventh PMOS transistor is connected to the drain of the eighth PMOS transistor. The source of the sixth PMOS transistor is connected to the source of the seventh PMOS transistor. The drain of the sixth PMOS transistor is connected to the drain of the third NMOS transistor, the gate of the third NMOS transistor, the gate of the second NMOS transistor, the gate of the fourth NMOS transistor, and the gate of the fifth NMOS transistor, respectively. The drain of the seventh PMOS transistor is connected to the drain of the fourth NMOS transistor. The source of the third NMOS transistor is connected to the drain of the second NMOS transistor; The source of the fourth NMOS transistor is connected to the drain of the fifth NMOS transistor; The source of the second NMOS transistor is connected to the source of the fifth NMOS transistor and then grounded.

5. The bandgap reference circuit according to claim 4, characterized in that, The bias circuit includes a sixth NMOS transistor; The drain of the sixth NMOS transistor is connected to the first connection point; The gate of the sixth NMOS transistor is connected to the drain of the seventh PMOS transistor. The source of the sixth NMOS transistor is grounded.

6. The bandgap reference circuit according to claim 5, characterized in that, The first end of the second resistor is connected to the drain of the eighth PMOS transistor and the gate of the seventh PMOS transistor, respectively. The emitter of the third transistor is connected to the gate of the sixth NMOS transistor.

7. The bandgap reference circuit according to claim 6, characterized in that, The voltage divider circuit includes a third resistor and a fourth resistor; The first end of the third resistor is connected to the drain of the eleventh PMOS transistor; The reference current is output at the connection point between the second end of the third resistor and the first end of the fourth resistor; The second end of the fourth resistor is connected to the collector of the first transistor.

8. A ferroelectric memory, characterized in that, Includes the bandgap reference circuit as described in any one of claims 1-7.

9. An electronic device, characterized in that, Including the ferroelectric memory as described in claim 8.

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