Memory voltage processing method and device, storage medium and electronic equipment

Abstract

The embodiment of the application provides a memory voltage processing method and device, a storage medium and an electronic device, relates to the field of computers, and comprises the following steps: acquiring a first standard voltage output by a target power supply chip based on a substrate management controller integrated on a server mainboard, wherein the first standard voltage provides a memory voltage for a group of memory modules of the server; in response to a first triggering operation of a voltage adjustment instruction, transmitting the first standard voltage to a target operating system; determining N preset voltages based on the first standard voltage; performing a memory performance test based on the N preset voltages to obtain a target test result, wherein the target test result comprises N performance indexes corresponding to the N preset voltages; determining a target preset voltage from the N preset voltages based on the N performance indexes; and modifying a power supply voltage output by the target power supply chip from the first standard voltage to the target preset voltage.

Description

Technical Field

[0001] This application relates to the field of computers, and more specifically, to a method and apparatus for processing memory voltage, a storage medium, and an electronic device. Background Technology

[0002] With the rapid development of cloud computing and big data technologies, the trend of informatization and intelligentization in society is accelerating. As the core equipment of information systems, servers are facing increasingly higher performance requirements. Memory is one of the core components of a server system, playing a crucial role in ensuring efficient server operation, data integrity, and performance.

[0003] The key to memory interface design lies in the bus signals and power supply. In related technologies, server memory voltage is typically designed to be a fixed value, such as a standard value (1.2V). However, due to differences in materials and manufacturing processes between different manufacturers, variations can occur between different batches of memory. Therefore, it cannot be guaranteed that the aforementioned standard voltage value is the optimal value for different server memory voltages, thus affecting the tuning of server memory performance parameters and leading to technical problems such as poor flexibility in server memory performance tuning.

[0004] There is currently no effective solution to the problem of poor flexibility in server memory performance tuning in related technologies. Summary of the Invention

[0005] This application provides a method and apparatus for processing memory voltage, a storage medium, and an electronic device to at least solve the problem of poor flexibility in the process of optimizing server memory performance.

[0006] According to one embodiment of this application, a method for processing memory voltage is provided, comprising: acquiring a first standard voltage output by a target power chip based on a baseboard management controller integrated on a server motherboard, wherein the first standard voltage provides memory voltage for a group of memory modules of the server; transmitting the first standard voltage to the target operating system in response to a first trigger operation of a voltage adjustment command; determining N preset voltages based on the first standard voltage, wherein the voltage difference between any two adjacent preset voltages in the N preset voltages is the same, and N is a positive integer greater than or equal to 1; performing a memory performance test based on the N preset voltages to obtain a target test result, wherein the target test result includes N performance indicators corresponding to the N preset voltages; determining a target preset voltage from the N preset voltages based on the N performance indicators; and modifying the power supply voltage output by the target power chip from the first standard voltage to the target preset voltage.

[0007] In an exemplary embodiment, determining N preset voltages based on the first standard voltage includes: determining n preset voltages less than the first standard voltage based on the voltage difference, where n is a positive integer greater than or equal to 1 and less than or equal to N; determining m preset voltages greater than the first standard voltage based on the voltage difference, where m is a positive integer greater than or equal to 1 and less than or equal to N, and the sum of n and m equals N; and determining the n preset voltages and the m preset voltages as the N preset voltages.

[0008] In an exemplary embodiment, the above-described memory performance test based on the N preset voltages to obtain a target test result includes: performing the following processing on the i-th preset voltage among the N preset voltages to obtain the i-th performance index, where i is a positive integer greater than or equal to 1 and less than or equal to N; performing M memory performance tests based on the i-th preset voltage to obtain M test data, where M is a positive integer greater than or equal to 1; and performing an averaging operation on the M test data to obtain the i-th performance index, wherein the target test result includes the i-th performance index.

[0009] In an exemplary embodiment, determining the target preset voltage from the N preset voltages based on the N performance indicators includes: sorting the N performance indicators in ascending order according to their values ​​to obtain a target sorting result; determining the target performance indicator with the highest sorting value from the N performance indicators based on the target sorting result; and determining a preset voltage corresponding to the target performance indicator as the target preset voltage.

[0010] In an exemplary embodiment, modifying the power supply voltage output by the target power chip from the first standard voltage to the target preset voltage includes: sending the target preset voltage to the target power chip via the substrate management controller; generating a target control signal in response to the received target preset voltage, wherein the target control signal represents control logic for modifying the registers of the target power chip based on the target preset voltage; modifying specific bits of the registers based on the control logic to obtain modified register state information; and adjusting the first standard voltage output by the target power chip to the target preset voltage based on the modified register state information.

[0011] In an exemplary embodiment, the above-described acquisition of the first standard voltage output by the target power chip based on the baseboard management controller integrated on the server motherboard includes: activating the target power chip in response to configuring a general-purpose input / output signal pin to a high level; reading the current register state information of the target power chip based on the target serial interface of the baseboard management controller, wherein the current register state information represents the encoding information of the power supply voltage output by the target power chip; and converting the encoding information of the power supply voltage into the first standard voltage.

[0012] In an exemplary embodiment, the above-described method of transmitting the first standard voltage to the target operating system in response to a first trigger operation of a voltage adjustment command includes: generating the voltage adjustment command when the target memory module is first connected to the server motherboard; transmitting the first standard voltage to the target operating system in response to the first trigger operation of the voltage adjustment command; or obtaining the first memory model of a first memory module inserted into a target memory slot connected to a memory controller on the server motherboard; generating the voltage adjustment command when it is detected that the memory model of the memory module inserted into the target memory slot has changed from the first memory model to a second memory model, wherein the second memory model is the memory model of the second memory module; transmitting the first standard voltage to the target operating system in response to the first trigger operation of the voltage adjustment command; or generating the voltage adjustment command in response to a second trigger operation of the memory performance tuning control when a memory performance tuning control is configured on the management interface of the baseboard manager; and obtaining the first standard voltage of a group of memory modules inserted into a pre-selected group of memory slots in response to the first trigger operation of the voltage adjustment command, and transmitting the first standard voltage to the target operating system.

[0013] According to another embodiment of this application, a memory voltage processing apparatus is also provided, comprising: a first acquisition unit, configured to acquire a first standard voltage output by a target power chip based on a baseboard management controller integrated on a server motherboard, wherein the first standard voltage provides memory voltage for a group of memory modules of the server; a transmission unit, configured to transmit the first standard voltage to the target operating system in response to a first trigger operation of a voltage adjustment command; a first processing unit, configured to determine N preset voltages based on the first standard voltage, wherein the voltage difference between any two adjacent preset voltages among the N preset voltages is the same, and N is a positive integer greater than or equal to 1; a second processing unit, configured to perform a memory performance test based on the N preset voltages to obtain a target test result, wherein the target test result includes N performance indicators corresponding to the N preset voltages; a third processing unit, configured to determine a target preset voltage from the N preset voltages based on the N performance indicators; and a fourth processing unit, configured to modify the power supply voltage output by the target power chip from the first standard voltage to the target preset voltage.

[0014] According to yet another embodiment of this application, a computer-readable storage medium is also provided, in which a computer program is stored, wherein the computer program is configured to perform the steps in any of the above method embodiments when it is run.

[0015] According to yet another embodiment of this application, an electronic device is also provided, including a memory and a processor, wherein a computer program is stored in the memory and the processor is configured to run the computer program to perform the steps in any of the above method embodiments.

[0016] According to yet another embodiment of this application, a computer program product is also provided, which includes a computer program that, when executed by a processor, implements the steps in any of the above method embodiments.

[0017] Using the embodiments provided in this application, a first standard power supply output from the target power chip on the server motherboard is obtained through a baseboard management controller. Within the target operating system, memory performance is tested at N preset voltages based on the first standard power supply. By comparing memory performance indicators under different preset power supplies, the optimal voltage value (target preset voltage) corresponding to the current motherboard is determined, thereby modifying the power supply voltage output by the target power chip to the target preset voltage. In other words, the embodiments of this application intelligently perform memory performance tests at N preset voltages based on the obtained first standard voltage, and then dynamically determine the optimal voltage value for each server memory based on the test results, achieving the technical effect of improving the flexibility of memory tuning. Attached Figure Description

[0018] The accompanying drawings, which are included to provide a further understanding of this application and form part of this application, illustrate exemplary embodiments and are used to explain this application, but do not constitute an undue limitation of this application. In the drawings:

[0019] Figure 1 This is a hardware structure block diagram of a server device according to an embodiment of the present application of a memory voltage processing method;

[0020] Figure 2 This is a flowchart of an optional memory voltage processing method according to an embodiment of this application;

[0021] Figure 3 This is a schematic diagram of an optional process for obtaining a standard voltage according to an embodiment of this application;

[0022] Figure 4 This is a flowchart of an optional memory performance tuning method according to an embodiment of this application;

[0023] Figure 5 This is a structural block diagram of a software decoding function verification device according to an embodiment of this application;

[0024] Figure 6 This is a schematic diagram of the structure of an optional electronic device according to an embodiment of this application. Detailed Implementation

[0025] The embodiments of this application will be described in detail below with reference to the accompanying drawings and examples.

[0026] It should be noted that the terms "first," "second," etc., in the specification, claims, and drawings of this application are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0027] The memory voltage processing method provided in this application can be executed in a server device or similar computing device. Taking running on a server device as an example, Figure 1 This is a hardware structure block diagram of a server device for a memory voltage processing method according to an embodiment of this application. Figure 1 As shown, the server device may include one or more ( Figure 1 Only one is shown in the diagram. A processor 102 (which may include, but is not limited to, a microprocessor MCU or a programmable logic device FPGA, etc.) and a memory 104 for storing data are also shown. The server device may further include a transmission device 106 for communication functions and an input / output device 108. Those skilled in the art will understand that... Figure 1The structure shown is for illustrative purposes only and does not limit the structure of the server equipment described above. For example, the server equipment may also include components that are more... Figure 1 The more or fewer components shown, or having the same Figure 1 The different configurations shown.

[0028] Memory 104 can be used to store computer programs, such as application software programs and modules, like the computer program corresponding to the memory voltage processing method in this embodiment. Processor 102 executes various functional applications and data processing by running the computer program stored in memory 104, thus implementing the aforementioned method. Memory 104 may include high-speed random access memory (RAM) and non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memories. In some instances, memory 104 may further include memory remotely located relative to processor 102, and these remote memories can be connected to server devices via a network. Examples of such networks include, but are not limited to, the Internet, corporate intranets, local area networks (LANs), mobile communication networks, and combinations thereof.

[0029] The transmission device 106 is used to receive or send data via a network. Specific examples of the network described above may include a wireless network provided by a communication provider for the server device. In one example, the transmission device 106 includes a Network Interface Controller (NIC), which can connect to other network devices via a base station to communicate with the Internet. In another example, the transmission device 106 may be a Radio Frequency (RF) module used for wireless communication with the Internet.

[0030] To better understand the above memory voltage processing method, the following is a brief introduction to the Baseboard Management Controller (BMC), power chip (which can also be understood as VR chip), memory (which can also be understood as memory module) and other components integrated on the server motherboard in this application embodiment, and the interaction process between the various components is explained.

[0031] like Figure 3 As shown, each server motherboard integrates a CPLD (Complex Programmable Logic Device), a BMC (Baseboard Management Controller), a memory VR, and multiple memory modules.

[0032] Among them, the output voltage of the VR chip (which can also be understood as a power chip) can, but is not limited to, provide power voltage for a group of memory, i.e., memory voltage; complex programmable logic devices are used to implement specific digital logic functions, such as timing control, logic function control, performance optimization, hardware monitoring and management, etc. The CPLD is mainly responsible for the power timing control of the motherboard, and controls the on or off state of the memory VR chip by controlling the high and low levels of the GPIO (general purpose input / output) pins; the baseboard management controller is one of the key components in server hardware. It is an embedded controller whose function is to monitor and manage the hardware status of the server to ensure the normal operation of the hardware.

[0033] To address the aforementioned problems in related technologies, this embodiment provides a method for processing memory voltage, the execution of which includes, but is not limited to, client and server motherboards, etc. Figure 2 As shown, the process includes the following steps S202-S212:

[0034] Step S202: Based on the baseboard management controller integrated on the server motherboard, obtain the first standard voltage output by the target power chip, wherein the first standard voltage provides memory voltage for a group of memory modules of the server;

[0035] Step S204: In response to a first trigger operation of a voltage adjustment command, the first standard voltage is transmitted to the target operating system;

[0036] Step S206: Based on the first standard voltage, determine N preset voltages, wherein the voltage difference between any two adjacent preset voltages among the N preset voltages is the same, and N is a positive integer greater than or equal to 1;

[0037] Step S208: Based on the N preset voltages, perform memory performance testing to obtain target test results, wherein the target test results include N performance indicators corresponding to the N preset voltages;

[0038] Step S210: Based on the N performance indicators, determine the target preset voltage from the N preset voltages;

[0039] Step S212: Modify the power supply voltage output by the target power chip from the first standard voltage to the target preset voltage.

[0040] like Figure 3 As shown, by connecting the I2C communication protocol of the baseboard management controller to the memory VR chip, the power supply voltage output by the target power chip can be read through the baseboard management controller after the server is powered on. The power supply voltage output by the target power chip is the currently set standard voltage (or standard voltage value), such as 1.2V.

[0041] I2C (Inter-Integrated Circuit) is a serial communication protocol used for communication between devices on a server motherboard. I2C allows multiple devices to communicate with one or more hosts through a set of shared serial lines. This communication method can be used to monitor and control hardware status, such as temperature, voltage, fan speed, etc.

[0042] It should be noted that in this embodiment, the baseboard management controller communicates with other chips or devices on the server motherboard via I2C to monitor and manage the hardware. This communication method is crucial for ensuring the stable operation of the server and timely response to hardware problems.

[0043] For ease of understanding, in this embodiment, the power supply for server memory is based on the current mainstream DDR4 memory, which has three power supply voltages (VDDQ, VPP, VTT: 1 / 2VDDQ). The VDDQ voltage range is generally 1.16V-1.26V, with a standard voltage of 1.2V. The VPP voltage range is generally 2.14V-2.75V, with a standard voltage of 2.5V. These voltages may vary slightly depending on the memory manufacturer.

[0044] like Figure 3 As shown, taking a single-socket motherboard as an example, a CPU can support the installation of 16 memory modules. Among them, every 8 memory modules share a power supply. Currently, the commonly used VR for DDR4 platforms is the 2-Loop (4+1) scheme. The voltage values ​​of VPP and VDDQ can be adjusted separately through the I2C bus. The voltage of VTT is 1 / 2 of that of VDDQ, so no separate adjustment is required.

[0045] In other words, this embodiment uses the power supply voltage output by a VR chip as the adjustment target to explain how to adjust the memory voltage of a group (8*DDR4) of memory or a group of memory modules. For example, the power supply voltage output by memory VR1 provides memory voltage for the 8 memory modules.

[0046] If it is determined that the first standard voltage output by the target power chip needs to be adjusted or optimized, the first standard voltage output by the target power chip is transmitted to the target operating system through the baseboard management controller, and memory performance testing is performed within the operating system. The target operating system may be, but is not limited to, an operating system installed on the target client. The following will explain whether adjustment of the first standard voltage output by the target power chip is necessary, using specific embodiments as examples.

[0047] The basic process of memory performance testing is as follows: Based on the obtained first standard voltage, N preset voltages are manually set, for example, according to a preset voltage difference of 5mV or 10mV. Memory performance tests are then performed on each of these N preset voltages to obtain the corresponding test data. Finally, based on the test data, the target preset voltage that optimizes the performance of the current group of memory modules is determined from the N preset voltages.

[0048] The baseboard management controller sends the target preset voltage, determined through memory performance testing, to the target power chip and modifies the voltage output by the target power chip from the current first standard voltage to the target preset voltage.

[0049] For example, suppose the first standard voltage output by the target power chip read by the baseboard management controller is 1.2V. Four preset voltages are manually set as 1.18V, 1.19V, 1.21V and 1.22V. Then, through memory performance testing, the performance indicators corresponding to the 44 preset voltages are determined as C1, C2, C3 and C4. Based on C1, C2, C3 and C4, 1.21V is determined as the target preset voltage.

[0050] The target preset voltage is sent to the target power chip through the baseboard management controller, and the first standard voltage output by the target power chip is modified to obtain the voltage output by the target power chip as the target preset voltage, so that the power supply voltage provided to a group of memory is the target preset voltage.

[0051] In practical applications, servers allow voltage fluctuations within a certain range to adapt to different working conditions or to optimize performance. For example, some servers may allow memory voltage to be adjusted within a certain range to optimize performance or reduce power consumption. Based on this, the embodiments of this application read the first standard voltage output by the target power chip through the baseboard management controller and transmit it to the target operating system. The performance indicators under different preset voltages are obtained through a pre-configured memory performance testing system, thereby determining the optimal memory voltage.

[0052] Using the above method, the first standard power supply output from the target power chip on the server motherboard is obtained through the baseboard management controller. Within the target operating system, memory performance is tested at N preset voltages based on the first standard power supply. By comparing memory performance indicators under different preset power supplies, the optimal voltage value (target preset voltage) corresponding to the current motherboard is determined, thereby modifying the power supply voltage output by the target power chip to the target preset voltage. In other words, this embodiment intelligently performs memory performance tests at N preset voltages based on the obtained first standard voltage, and then dynamically determines the optimal voltage value for each server memory based on the test results, achieving the technical effect of improving the flexibility of memory tuning.

[0053] In one example embodiment, determining N preset voltages based on the first standard voltage includes:

[0054] Based on the voltage difference, n preset voltages that are less than the first standard voltage are determined sequentially, where n is a positive integer greater than or equal to 1 and less than or equal to N;

[0055] Based on the voltage difference, m preset voltages greater than the first standard power supply are determined sequentially, where m is a positive integer greater than or equal to 1 and less than or equal to N, and the sum of n and m is equal to N;

[0056] The n preset voltages and the m preset voltages are determined as the N preset voltages.

[0057] Assuming the first standard voltage is 1.2V, the voltage difference needs to be determined according to the power supply chip's own parameters, for example, 5mV or 10mV. Based on the determined voltage difference, N preset voltages are manually set, for example, n preset voltages that are larger than the first standard voltage, such as 1.21V and 1.22V, and m preset voltages that are smaller than the first standard voltage, such as 1.18V, 1.19V, etc.

[0058] Memory performance tests are performed sequentially within the target operating system for each preset voltage to obtain the performance indicators corresponding to each preset voltage, thereby determining the target preset voltage.

[0059] In other words, through the instruction interaction between the baseboard management controller and the target power chip, real-time monitoring of memory voltage can be achieved, ensuring optimal memory performance and guaranteeing stable server operation.

[0060] In one example embodiment, the memory performance test performed based on the N preset voltages to obtain the target test results includes:

[0061] The following processing is performed on the i-th preset voltage among the N preset voltages to obtain the i-th performance index, where i is a positive integer greater than or equal to 1 and less than or equal to N:

[0062] Based on the i-th preset voltage, perform M memory performance tests to obtain M test data, where M is a positive integer greater than or equal to 1;

[0063] The average of the M test data is calculated to obtain the i-th performance index, wherein the target test result includes the i-th performance index.

[0064] In other words, for each preset voltage, M memory performance tests are performed, and the average of the M test data is taken. The server memory performance test includes, but is not limited to, the following aspects:

[0065] (1) Memory bandwidth test: Test the data transfer rate of the memory, that is, how much data the memory can process per second;

[0066] (2) Read / write response test: Use attacks, such as streams, to test memory read / write speed and response time;

[0067] (3) Memory latency test: Test the latency of memory access, that is, the time from issuing a memory access request to receiving a response;

[0068] (4) Memory capacity test: Evaluate the maximum memory capacity that the server can support;

[0069] (5) Memory stability test: Run memory-intensive tasks for a long time to ensure that the memory remains stable under high load;

[0070] (6) Error rate test: Test the probability of memory errors occurring during long-term operation;

[0071] (7) Concurrent User Test: Simulate multiple users accessing the server simultaneously to test performance under high memory concurrency conditions.

[0072] In other words, for each preset voltage, M memory performance tests are performed to obtain test data from the above-mentioned multiple aspects. Then, the test data from the multiple aspects are weighted and averaged to obtain a performance index X1 corresponding to the current preset voltage.

[0073] Through multiple performance tests, the impact of memory voltage on performance can be more comprehensively evaluated, improving the accuracy and reliability of memory tuning results. Especially during the deep tuning phase of servers, the optimal memory voltage value can be determined by analyzing the data from the aforementioned M tests to meet the needs of high-performance computing or big data processing.

[0074] In one example embodiment, determining the target preset voltage from the N preset voltages based on the N performance indicators includes:

[0075] Based on the values ​​of the performance indicators, the N performance indicators are sorted in ascending order to obtain the target ranking result;

[0076] Based on the target ranking results, the target performance index with the highest ranking is determined from the N performance indicators.

[0077] A preset voltage corresponding to the target performance index is determined as the target preset voltage.

[0078] In this embodiment, N performance indicators can be sorted, but are not limited to, and the performance indicator X with the largest value can be determined based on the sorting result. max and will be with X max The corresponding preset voltage is determined as the target preset voltage.

[0079] The adjustment range of memory voltage needs to be determined based on actual needs and material support, and the accuracy of voltage adjustment depends on the parameters of the power chip (VR chip) itself.

[0080] The specific values ​​of N and M can be selected based on the precision and efficiency requirements of the tuning, ensuring the efficiency and accuracy of the memory tuning process, and making it suitable for server environments of different sizes and performance requirements.

[0081] The above performance tests can quantify the impact of different preset voltages on memory performance, making it easier to find the optimal balance between performance and energy consumption, and further improve the overall performance of the server or reduce energy consumption.

[0082] In one example embodiment, modifying the power supply voltage output by the target power chip from the first standard voltage to the target preset voltage includes:

[0083] The target preset voltage is sent to the target power chip via the substrate management controller;

[0084] In response to the received target preset voltage, a target control signal is generated, wherein the target control signal represents control logic for modifying the registers of the target power chip based on the target preset voltage;

[0085] Based on the control logic, specific bits of the register are modified to obtain the modified register status information;

[0086] Based on the modified register state information, the first standard voltage output by the target power chip is adjusted to the target preset voltage.

[0087] Specifically, after the target preset voltage, determined by the target operating system test, is sent to the target power chip on the server motherboard via the baseboard management controller, the steps to modify the first standard voltage output by the target power chip to the target preset voltage by changing the value of the status bit in the register of the target power chip are as follows:

[0088] S11, determine the target register;

[0089] First, identify the specific register that controls the voltage output, usually by consulting the VR chip's datasheet or technical documentation.

[0090] S12, Read the current configuration;

[0091] The current voltage setting can be obtained by reading the value of the current register through interfaces such as I2C or PMBus.

[0092] The registers of a memory VR chip typically refer to the storage components inside the memory VR chip, which are used to store various parameters and status information that control memory operations.

[0093] S13, based on the target preset voltage to be adjusted, determine how to implement the control logic for this voltage change through register settings;

[0094] The register stores an 8-bit binary value. Control logic generates a control signal indicating the type of modification operation, including but not limited to setting, clearing, or toggling a specific bit. Based on this control signal, the specific bit in the register is modified without changing the values ​​of other bits.

[0095] S14, Write the configuration pins or program;

[0096] Write a script or program to modify the value of a register (at least some of the 8 bits) to modify the value at a specific bit in the register.

[0097] S15, send a command through the programming interface to update the value of the register;

[0098] This mainly involves the communication protocol with the VR chip, such as I2C or PMBus.

[0099] S16, verify the changed register value;

[0100] After changing the register value, it is necessary to verify whether the voltage output meets expectations. This can be done, but is not limited to, by reading the register value or using an external voltage measuring device.

[0101] S17, Monitoring and Adjustment.

[0102] After changing the voltage, monitor the system stability and performance, and make further adjustments if necessary.

[0103] Finally, based on the modified register value, the current first standard voltage adaptability is modified to the target preset voltage, for example, from 1.2V to 1.21V.

[0104] Through the coordinated operation of components such as the aforementioned baseboard management controller and target power chip, the automation of memory performance tuning is improved, and the flexibility and efficiency of memory tuning are enhanced.

[0105] In one example embodiment, the above-described acquisition of the first standard voltage output by the target power chip based on the baseboard management controller integrated on the server motherboard includes:

[0106] The target power supply chip is activated in response to configuring a general-purpose input / output signal pin to a high level.

[0107] Based on the target serial interface of the baseboard management controller, the current register status information of the target power chip is read, wherein the current register status information represents the encoding information of the power supply voltage output by the target power chip;

[0108] The encoded information of the power supply voltage is converted into the first standard voltage.

[0109] After the server motherboard is powered on, the CPLD is responsible for the power timing control of the motherboard. By controlling the GPIO to output a high level, the memory VR chip (target power chip) is turned on. After the server is powered on, the register status of the memory VR chip is read through the I2C interface of the baseboard management controller. Based on the read register status, the current set voltage value is obtained.

[0110] The specific steps are as follows:

[0111] (1) Reading register values: First, it is necessary to read the register values ​​related to voltage output in the VR chip through an appropriate interface (such as I2C, SPI, PMBus, etc.);

[0112] (2) Decoding Register Values: The values ​​in the registers typically contain encoded information about the voltage settings. This requires referring to the VR chip's datasheet to understand how to convert the encoded values ​​into actual voltage values. For example, some registers may directly contain a digital representation of the voltage value, while others may contain control bits for the voltage settings.

[0113] (3) Calculate the voltage: Calculate the corresponding voltage value based on the register value and the information in the datasheet.

[0114] By connecting the baseboard management controller (BMC) to the target power chip via I2C and communicating with the BMC, real-time monitoring of memory voltage is possible. Furthermore, by adhering to the voltage output settings configured in the firmware (FW) file, the accuracy and consistency of the memory voltage are ensured. This is particularly beneficial during server hardware upgrades or memory replacements, enabling rapid adaptation to the voltage requirements of the new memory and ensuring stable server operation.

[0115] In one example embodiment, the above-described response to a first triggering operation on a voltage adjustment command, transmitting the first standard voltage to the target operating system, includes:

[0116] When the target memory module is first connected to the server motherboard, the voltage adjustment command is generated;

[0117] In response to the first trigger operation of the voltage adjustment command, the first standard voltage is transmitted to the target operating system; or

[0118] Obtain the first memory model of the first memory module inserted into the target memory slot connected to the memory controller on the server motherboard;

[0119] If the memory model of the memory module inserted into the target memory slot is detected to have changed from the first memory model to the second memory model, the voltage adjustment command is generated, wherein the second memory model is the memory model of the second memory module;

[0120] In response to the first trigger operation of the voltage adjustment command, the first standard voltage is transmitted to the target operating system; or

[0121] When a memory performance tuning control is configured on the management interface of the baseboard manager, the voltage adjustment command is generated in response to the second trigger operation of the memory performance tuning control;

[0122] In response to the first trigger operation of the voltage adjustment command, the first standard voltage of a set of memory modules inserted in a pre-selected set of memory slots is obtained, and the first standard voltage is transmitted to the target operating system.

[0123] It is easy to understand that the above memory performance tuning methods are not necessary during normal server operation. Typically, the above memory performance tuning process will be initiated under the following three circumstances.

[0124] The first method: When the memory is used for the first time on the corresponding server motherboard interface, the fixed voltage (i.e. the default standard voltage) of the memory is obtained. The above memory performance test method is used to set N preset voltages from the preset voltage range, and the performance of each preset voltage is tested to obtain N performance indicators. Based on the N performance indicators, the target preset voltage that matches the memory used for the first time is determined.

[0125] It should be noted that before starting the above memory performance test method, it is necessary to manually determine whether voltage adjustment is required. If it is determined that voltage adjustment is required, the above voltage adjustment instruction is generated, and the first standard voltage obtained is transmitted to the target operating system through the BMC.

[0126] The second method is to generate the above voltage adjustment command when the memory model corresponding to the motherboard interface is changed.

[0127] After manually determining that the memory model of the motherboard interface has changed, the above-mentioned voltage adjustment instruction is generated and transmitted to the target power chip. The target power chip can then transmit the real-time monitored power supply voltage to the target operating system to perform the above-mentioned memory performance test within the target operating system.

[0128] The third method involves setting a memory performance tuning button on the BMC interface and triggering the button to generate the aforementioned voltage adjustment command.

[0129] For example, after manually selecting memory operations, a voltage matching action can be performed. The specific memory performance tuning process is as follows: Figure 4 As shown, it includes:

[0130] S402 performs parameter tuning on a set of memory modules across the entire system.

[0131] S404 obtains the current set voltage output by a set of memory-connected VR chips through the BMC;

[0132] For example, such as Figure 3 As shown, the power supply voltage output by VR1 provides the memory voltage for a group (8 memory modules). Through I2C, BMC reads the registers of the memory VR chip and obtains the status value of the registers. Based on the status value of the registers, it determines the current set voltage value and uses it as the current set voltage output by the VR chip.

[0133] S406, use the current voltage value to perform memory performance tests and record the test results;

[0134] For details, please refer to the description in the above embodiments, which will not be repeated here.

[0135] S408 takes N values ​​above and below the current voltage value, performs M memory performance tests for each value, and records the average value of the M memory performance tests for each value.

[0136] A single value (a preset voltage) is used to perform M memory performance tests, and the average of the M test data is calculated to obtain a performance index. Therefore, N values ​​correspond to N performance indices.

[0137] S410 sorts N performance indicators and uses the preset voltage value corresponding to the performance indicator with the largest value as the final target voltage value set for the memory VR chip.

[0138] As can be seen from the description in the above embodiments, by adjusting the memory voltage in real time through the BMC and combining it with the memory performance testing function under the system, the memory performance of each server can be optimized. The hardware and software architecture is simple and easy to implement, highly feasible, and low in cost.

[0139] As can be seen from the description of the above embodiments, compared with the prior art, the technical solutions in the embodiments of this application have at least the following beneficial effects:

[0140] (1) Through the I2C bus of the baseboard management controller, the instruction interaction between the baseboard management controller and the memory VR chip is realized, and the memory voltage is adjusted in real time;

[0141] (2) Utilize the memory performance testing function under the target operating system, and flexibly configure the voltage of the memory VR chip through I2C to adapt to the optimal value and improve memory performance;

[0142] (3) While retaining the monitoring function of the baseboard management controller in the existing solution, a new memory performance tuning function is added. The memory performance tuning process can be triggered under necessary conditions according to actual needs and application scenarios, thereby improving product competitiveness.

[0143] Through the above description of the embodiments, those skilled in the art can clearly understand that the methods according to the above embodiments can be implemented by means of software plus necessary general-purpose hardware platforms. Of course, they can also be implemented by hardware, but in many cases the former is a better implementation method. Based on this understanding, the technical solution of this application, in essence, or the part that contributes to the prior art, can be embodied in the form of a software product. This computer software product is stored in a storage medium (such as ROM / RAM, magnetic disk, optical disk) and includes several instructions to cause a terminal device (which may be a mobile phone, computer, server, or network device, etc.) to execute the methods of the various embodiments of this application.

[0144] This embodiment also provides a memory voltage processing device for implementing the above embodiments and preferred embodiments; details already described will not be repeated. As used below, the term "module" can refer to a combination of software and / or hardware that performs a predetermined function. Although the modules described in the following embodiments are preferably implemented in software, hardware implementation, or a combination of software and hardware, is also possible and contemplated.

[0145] Figure 5 This is a structural block diagram of a memory voltage processing apparatus according to an embodiment of this application. The apparatus includes:

[0146] The first acquisition unit 502 is used to acquire a first standard voltage output by the target power chip based on the baseboard management controller integrated on the server motherboard, wherein the first standard voltage provides memory voltage for a group of memory modules of the server.

[0147] Transmission unit 504 is configured to transmit the first standard voltage to the target operating system in response to a first trigger operation of a voltage adjustment command;

[0148] The first processing unit 506 is used to determine N preset voltages based on the first standard voltage, wherein the voltage difference between any two adjacent preset voltages among the N preset voltages is the same, and N is a positive integer greater than or equal to 1.

[0149] The second processing unit 508 is used to perform memory performance testing based on the N preset voltages to obtain target test results, wherein the target test results include N performance indicators corresponding to the N preset voltages.

[0150] The third processing unit 510 is used to determine the target preset voltage from the N preset voltages based on the N performance indicators;

[0151] The fourth processing unit 512 is used to modify the power supply voltage output by the target power chip from the first standard voltage to the target preset voltage.

[0152] In an exemplary embodiment, the first processing unit 506 described above includes:

[0153] The first processing module is used to determine n preset voltages that are less than the first standard voltage in sequence based on the voltage difference, where n is a positive integer greater than or equal to 1 and less than or equal to N;

[0154] The second processing module is used to determine m preset voltages that are greater than the first standard power supply based on the voltage difference, where m is a positive integer greater than or equal to 1 and less than or equal to N, and the sum of n and m is equal to N.

[0155] The third processing module is used to determine the n preset voltages and the m preset voltages as the N preset voltages.

[0156] In an exemplary embodiment, the second processing unit 508 described above includes:

[0157] The fourth processing module is used to perform the following processing on the i-th preset voltage among the N preset voltages to obtain the i-th performance index, where i is a positive integer greater than or equal to 1 and less than or equal to N:

[0158] Based on the i-th preset voltage, perform M memory performance tests to obtain M test data, where M is a positive integer greater than or equal to 1;

[0159] The average of the M test data is calculated to obtain the i-th performance index, wherein the target test result includes the i-th performance index.

[0160] In an exemplary embodiment, the third processing unit 510 described above includes:

[0161] The fifth processing module is used to sort the N performance indicators in ascending order according to their values ​​to obtain the target sorting result.

[0162] The sixth processing module is used to determine the highest-ranked target performance index from the N performance indicators based on the target ranking result.

[0163] The seventh processing module is used to determine a preset voltage corresponding to the target performance index as the target preset voltage.

[0164] In an exemplary embodiment, the fourth processing unit 512 described above includes:

[0165] The transmitting module is used to transmit the target preset voltage to the target power chip through the baseboard management controller;

[0166] The eighth processing module is used to generate a target control signal in response to the received target preset voltage, wherein the target control signal represents control logic for modifying the registers of the target power chip based on the target preset voltage;

[0167] The modification module is used to modify specific bits of the register based on the control logic to obtain the modified register status information;

[0168] The adjustment module is used to adjust the first standard voltage output by the target power chip to the target preset voltage based on the modified register state information.

[0169] In an exemplary embodiment, the first acquisition unit 502 described above includes:

[0170] A startup module is used to start the target power chip in response to configuring a general-purpose input / output signal pin to a high level;

[0171] The reading module is used to read the current register status information of the target power chip based on the target serial interface of the baseboard management controller, wherein the current register status information represents the encoding information of the power supply voltage output by the target power chip;

[0172] A conversion module is used to convert the encoded information of the power supply voltage into the first standard voltage.

[0173] In an exemplary embodiment, the transmission unit 504 includes:

[0174] The ninth processing module is used to generate the voltage adjustment command when the target memory module is first connected to the server motherboard;

[0175] In response to the first trigger operation of the voltage adjustment command, the first standard voltage is transmitted to the target operating system; or

[0176] Obtain the first memory model of the first memory module inserted into the target memory slot connected to the memory controller on the server motherboard;

[0177] If the memory model of the memory module inserted into the target memory slot is detected to have changed from the first memory model to the second memory model, the voltage adjustment command is generated, wherein the second memory model is the memory model of the second memory module;

[0178] In response to the first trigger operation of the voltage adjustment command, the first standard voltage is transmitted to the target operating system; or

[0179] When a memory performance tuning control is configured on the management interface of the baseboard manager, the voltage adjustment command is generated in response to the second trigger operation of the memory performance tuning control;

[0180] In response to the first trigger operation of the voltage adjustment command, the first standard voltage of a set of memory modules inserted in a pre-selected set of memory slots is obtained, and the first standard voltage is transmitted to the target operating system.

[0181] The aforementioned apparatus instructs the acquisition of a first standard power supply output from a target power chip on a server motherboard via a baseboard management controller. Within the target operating system, memory performance is tested at N preset voltages based on the first standard power supply. By comparing memory performance indicators under different preset power supplies, the optimal voltage value (target preset voltage) corresponding to the current motherboard is determined, thereby modifying the power supply voltage output by the target power chip to the target preset voltage. In other words, this embodiment intelligently performs memory performance tests at N preset voltages based on the acquired first standard voltage, and then dynamically determines the optimal voltage value for each server memory module based on the test results, achieving the technical effect of improving the flexibility of memory tuning.

[0182] It should be noted that the above modules can be implemented by software or hardware. For the latter, they can be implemented in the following ways, but are not limited to: all the above modules are located in the same processor; or, the above modules are located in different processors in any combination.

[0183] Embodiments of this application also provide a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps in any of the above method embodiments when run.

[0184] Optionally, in this embodiment, the computer program described above can be configured to perform the following steps:

[0185] S1, Based on the baseboard management controller integrated on the server motherboard, obtain the first standard voltage output by the target power chip, wherein the first standard voltage provides memory voltage for a group of memory modules of the server;

[0186] S2, in response to a first trigger operation of a voltage adjustment command, transmits the first standard voltage to the target operating system;

[0187] S3, based on the first standard voltage, determine N preset voltages, wherein the voltage difference between any two adjacent preset voltages among the N preset voltages is the same, and N is a positive integer greater than or equal to 1;

[0188] S4. Based on the N preset voltages, perform memory performance testing to obtain target test results, wherein the target test results include N performance indicators corresponding to the N preset voltages;

[0189] S5, Based on the N performance indicators, determine the target preset voltage from the N preset voltages;

[0190] S6, modify the power supply voltage output by the target power chip from the first standard voltage to the target preset voltage.

[0191] In one exemplary embodiment, the aforementioned computer-readable storage medium may include, but is not limited to, various media capable of storing computer programs, such as a USB flash drive, read-only memory (ROM), random access memory (RAM), portable hard disk, magnetic disk, or optical disk.

[0192] Embodiments of this application also provide an electronic device, such as... Figure 6 As shown, the electronic device includes a memory 602 and a processor 604. The memory 602 stores a computer program, and the processor 604 is configured to execute the steps in any of the above method embodiments via the computer program.

[0193] Optionally, in this embodiment, the processor 604 can be configured to perform the following steps via a computer program:

[0194] S1, Based on the baseboard management controller integrated on the server motherboard, obtain the first standard voltage output by the target power chip, wherein the first standard voltage provides memory voltage for a group of memory modules of the server;

[0195] S2, in response to a first trigger operation of a voltage adjustment command, transmits the first standard voltage to the target operating system;

[0196] S3, based on the first standard voltage, determine N preset voltages, wherein the voltage difference between any two adjacent preset voltages among the N preset voltages is the same, and N is a positive integer greater than or equal to 1;

[0197] S4. Based on the N preset voltages, perform memory performance testing to obtain target test results, wherein the target test results include N performance indicators corresponding to the N preset voltages;

[0198] S5, Based on the N performance indicators, determine the target preset voltage from the N preset voltages;

[0199] S6, modify the power supply voltage output by the target power chip from the first standard voltage to the target preset voltage.

[0200] Specific examples in this embodiment can be found in the examples described in the above embodiments and exemplary implementations, and will not be repeated here.

[0201] Alternatively, as those skilled in the art will understand, Figure 6 The structure shown is for illustrative purposes only. Figure 6This does not limit the structure of the aforementioned electronic devices. For example, the electronic device may also include components that are more... Figure 6 The more or fewer components shown (such as network interfaces, etc.), or having the same Figure 6 The different configurations shown.

[0202] The memory 602 can be used to store software programs and modules, such as the program instructions / modules corresponding to the memory voltage processing method and memory voltage processing device in this embodiment. The processor 604 executes various functional applications and data processing by running the software programs and modules stored in the memory 602, thereby implementing the aforementioned memory voltage processing method. The memory 602 may include high-speed random access memory, and may also include non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some instances, the memory 602 may further include memory remotely located relative to the processor 604, and these remote memories can be connected to the terminal via a network. Examples of such networks include, but are not limited to, the Internet, enterprise intranets, local area networks, mobile communication networks, and combinations thereof. Specifically, the memory 602 may be used, but is not limited to, to store information such as a first standard voltage, N preset voltages, and N performance indicators. As an example, such as... Figure 6 As shown, the memory 602 may include, but is not limited to, the first acquisition unit 502, transmission unit 504, first processing unit 506, second processing unit 508, third processing unit 510, and fourth processing unit 512 in the memory voltage processing device described above. Furthermore, it may include, but is not limited to, other module units in the verification device for the soft decoding function described above, which will not be elaborated upon in this example.

[0203] Optionally, the transmission device 606 described above is used to receive or send data via a network. Specific examples of the network described above may include wired networks and wireless networks. In one example, the transmission device 606 includes a Network Interface Controller (NIC), which can be connected to other network devices and routers via a network cable to communicate with the Internet or a local area network. In another example, the transmission device 606 is a radio frequency (RF) module, used for wireless communication with the Internet.

[0204] In addition, the above-mentioned electronic device also includes: a display 608; and a connection bus 610 for connecting the various module components in the above-mentioned electronic device.

[0205] In other embodiments, the aforementioned electronic device can be a node in a distributed system, which can be a blockchain system. This blockchain system is formed by connecting multiple nodes through network communication. The nodes can form a peer-to-peer (P2P) network, and any type of computing device, such as a server or terminal, can become a node in the blockchain system by joining this peer-to-peer network.

[0206] Embodiments of this application also provide a computer program product, which includes a computer program that, when executed by a processor, implements the steps in any of the above method embodiments.

[0207] Embodiments of this application also provide another computer program product, including a non-volatile computer-readable storage medium storing a computer program that, when executed by a processor, implements the steps in any of the above method embodiments.

[0208] The embodiments described herein also provide a computer program that includes computer instructions stored in a computer-readable storage medium; a processor of a computer device reads the computer instructions from the computer-readable storage medium and executes the computer instructions, causing the computer device to perform the steps in any of the above method embodiments.

[0209] Obviously, those skilled in the art should understand that the modules or steps of this application described above can be implemented using general-purpose computing devices. They can be centralized on a single computing device or distributed across a network of multiple computing devices. They can be implemented using computer-executable program code, and thus can be stored in a storage device for execution by a computing device. In some cases, the steps shown or described can be performed in a different order than those presented here, or they can be fabricated as separate integrated circuit modules, or multiple modules or steps can be fabricated as a single integrated circuit module. Thus, this application is not limited to any particular combination of hardware and software.

[0210] The above are merely preferred embodiments of this application and are not intended to limit this application. Various modifications and variations can be made to this application by those skilled in the art. Any modifications, equivalent substitutions, improvements, etc., made within the principles of this application should be included within the protection scope of this application.

Claims

1. A method for processing memory voltage, characterized in that, include: Based on the baseboard management controller integrated on the server motherboard, the first standard voltage output by the target power chip is obtained, wherein the first standard voltage provides memory voltage for a group of memory modules of the server; Obtain the first memory model of the first memory module inserted into the target memory slot connected to the memory controller on the server motherboard; if it is detected that the memory model of the memory module inserted into the target memory slot has changed from the first memory model to the second memory model, generate a voltage adjustment command, and in response to a first trigger operation of the voltage adjustment command, transmit the first standard voltage to the target operating system, and perform a memory performance test through a memory performance test system pre-configured in the target operating system, wherein the second memory model is the memory model of the second memory module; Based on the first standard voltage, N preset voltages are determined, wherein the voltage difference between any two adjacent preset voltages among the N preset voltages is the same, and N is a positive integer greater than or equal to 1; Based on the N preset voltages, the memory performance test is performed on the second memory module of the current second memory model to obtain the target test result. The target test result includes N performance indicators corresponding to the N preset voltages. The N preset voltages include preset voltages that are greater than and less than the first standard voltage. The memory performance test includes memory bandwidth test, memory latency test, memory capacity test, and error rate test. The memory bandwidth test includes testing the data transfer rate of the memory. The memory latency test includes the memory access latency time. The memory capacity test includes testing the maximum memory capacity supported by the server. The error rate test includes testing the probability of errors occurring in the memory during long-term operation. Based on the N performance indicators, the target preset voltage is determined from the N preset voltages; The baseboard management controller sends the target preset voltage, determined by the memory performance test, to the target power chip, and modifies the power supply voltage output by the target power chip from the first standard voltage to the target preset voltage. The target preset voltage is the optimal voltage value that enables the memory performance of the second memory module of the second memory model to reach its optimal level. The N performance indicators corresponding to the N preset voltages include: for each preset voltage, performing M memory performance tests to obtain multiple test data corresponding to the memory bandwidth test, the memory latency test, the memory capacity test, and the error rate test; and performing a weighted average of the multiple test data to obtain a performance indicator corresponding to each preset voltage, where M is a positive integer greater than or equal to 1. The method of acquiring the first standard voltage output by the target power chip based on the baseboard management controller integrated on the server motherboard includes: activating the target power chip in response to configuring a general-purpose input / output signal pin to a high level; reading the current register status information of the target power chip based on the target serial interface of the baseboard management controller, wherein the current register status information represents the encoding information of the power supply voltage output by the target power chip; and converting the encoding information of the power supply voltage into the first standard voltage. The step of modifying the power supply voltage output by the target power chip from the first standard voltage to the target preset voltage includes: sending the target preset voltage to the target power chip through the substrate management controller; generating a target control signal in response to the received target preset voltage, wherein the target control signal represents control logic for modifying the registers of the target power chip based on the target preset voltage; modifying specific bits of the register based on the control logic to obtain modified register status information; and adjusting the first standard voltage output by the target power chip to the target preset voltage based on the modified register status information.

2. The method according to claim 1, characterized in that, The step of determining N preset voltages based on the first standard voltage includes: Based on the voltage difference, n preset voltages that are less than the first standard voltage are determined sequentially, where n is a positive integer greater than or equal to 1 and less than or equal to N; Based on the voltage difference, m preset voltages that are greater than the first standard voltage are determined sequentially, where m is a positive integer greater than or equal to 1 and less than or equal to N, and the sum of n and m is equal to N; The n preset voltages and the m preset voltages are determined as the N preset voltages.

3. The method according to claim 1, characterized in that, The process of performing memory performance tests based on the N preset voltages to obtain target test results includes: The following processing is performed on the i-th preset voltage among the N preset voltages to obtain the i-th performance index, where i is a positive integer greater than or equal to 1 and less than or equal to N: Based on the i-th preset voltage, perform M memory performance tests to obtain M test data; The average of the M test data is calculated to obtain the i-th performance index, wherein the target test result includes the i-th performance index.

4. The method according to claim 1, characterized in that, The step of determining the target preset voltage from the N preset voltages based on the N performance indicators includes: Based on the values ​​of the performance indicators, the N performance indicators are sorted in ascending order to obtain the target sorting result; Based on the target ranking results, the target performance index with the highest ranking is determined from the N performance indicators. A preset voltage corresponding to the target performance index is determined as the target preset voltage.

5. The method according to any one of claims 1 to 4, characterized in that, The first trigger operation in response to a voltage adjustment command, transmitting the first standard voltage to the target operating system, includes: When the target memory module is first connected to the server motherboard, the voltage adjustment command is generated; In response to the first trigger operation of the voltage adjustment command, the first standard voltage is transmitted to the target operating system; or When a memory performance tuning control is configured on the management interface of the baseboard management controller, the voltage adjustment command is generated in response to the second trigger operation of the memory performance tuning control; In response to the first trigger operation of the voltage adjustment command, the first standard voltage of a set of memory modules inserted in a pre-selected set of memory slots is obtained, and the first standard voltage is transmitted to the target operating system.

6. A memory voltage processing device, characterized in that, include: The first acquisition unit is used to acquire a first standard voltage output by the target power chip based on the baseboard management controller integrated on the server motherboard, wherein the first standard voltage provides memory voltage for a group of memory modules of the server. A transmission unit is configured to acquire the first memory model of a first memory module inserted into a target memory slot connected to a memory controller on the server motherboard; upon detecting that the memory model of the memory module inserted into the target memory slot has changed from the first memory model to a second memory model, a voltage adjustment command is generated; in response to a first trigger operation of the voltage adjustment command, the first standard voltage is transmitted to the target operating system, and a memory performance test is performed through a memory performance test system pre-configured within the target operating system, wherein the second memory model is the memory model of the second memory module; The first processing unit is configured to determine N preset voltages based on the first standard voltage, wherein the voltage difference between any two adjacent preset voltages among the N preset voltages is the same, and N is a positive integer greater than or equal to 1. The second processing unit is configured to perform the memory performance test on the second memory module of the current second memory model based on the N preset voltages to obtain a target test result. The target test result includes N performance indicators corresponding to the N preset voltages, the N preset voltages including preset voltages greater than and less than the first standard voltage, the memory performance test including memory bandwidth test, memory latency test, memory capacity test, and error rate test, the memory bandwidth test including testing the data transfer rate of the memory, the memory latency test including the memory access latency time, the memory capacity test including testing the maximum memory capacity supported by the server, and the error rate test including testing the probability of errors occurring in the memory during long-term operation. The third processing unit is used to determine the target preset voltage from the N preset voltages based on the N performance indicators; The fourth processing unit is configured to send the target preset voltage determined by the memory performance test to the target power chip through the baseboard management controller, and modify the power supply voltage output by the target power chip from the first standard voltage to the target preset voltage, wherein the target preset voltage is the optimal voltage value that enables the memory performance of the second memory module of the second memory model to reach the optimal level. The device is further configured to perform M memory performance tests for each preset voltage, obtaining multiple test data corresponding to the memory bandwidth test, memory latency test, memory capacity test, and error rate test; perform a weighted average of the multiple test data to obtain a performance index corresponding to each preset voltage, where M is a positive integer greater than or equal to 1; activate the target power chip in response to configuring a general-purpose input / output signal pin to a high level; read the current register state information of the target power chip based on the target serial interface of the baseboard management controller, wherein the current register state information represents the encoded information of the power supply voltage output by the target power chip; convert the encoded information of the power supply voltage into the first standard voltage; send the target preset voltage to the target power chip through the baseboard management controller; generate a target control signal in response to the received target preset voltage, wherein the target control signal represents control logic for modifying the registers of the target power chip based on the target preset voltage; modify specific bits of the register based on the control logic to obtain modified register state information; and adjust the first standard voltage output by the target power chip to the target preset voltage based on the modified register state information.

7. A computer-readable storage medium, characterized in that, The computer-readable storage medium stores a computer program, wherein the computer program, when executed by a processor, implements the steps of the method described in any one of claims 1 to 5.

8. An electronic device comprising a memory, a processor, and a computer program stored in the memory and executable on the processor, characterized in that, When the processor executes the computer program, it implements the steps of the method described in any one of claims 1 to 5.

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