Test vector file compiling method and device and chip test system

Abstract

The invention relates to a compiling method and device of a test vector file and a chip test system.The method comprises the steps that time sequence data, pin data and test vector data in the test vector file are read, and the test vector data comprise a plurality of test vectors; based on the time sequence data, obtaining the sequence of the multiple test board cards in the test vector and corresponding time sequence configuration information; based on the sequence and the pin data, pin level information corresponding to each test vector is obtained, and the pin level information comprises level values of pins, connected with the multiple test board cards, of the tested chip; and based on the pin level information and the time sequence configuration information corresponding to the plurality of test board cards, generating compilation data of the test vectors corresponding to the plurality of test board cards, thereby solving the problem that the test vector file does not support expression of a plurality of test time sequences of the same test vector. Therefore, the problem that the test instruction corresponding to the test time sequence of the multi-type test board card cannot be generated after the test vector file is compiled is solved.

Description

Technical Field

[0001] The present application relates to the field of semiconductor testing, and in particular to a test vector file compilation method, device and chip testing system. Background Art

[0002] LCD (Liquid Crystal Display) chips are used to drive the image display of liquid crystal screens and have been widely used in recent years. In the field of LCD chip testing, some test equipment manufacturers test LCD chips through a single type of test board. Due to the large number of pins of LCD chips and the low data transmission rate of the test board, there are problems of low test efficiency and slow test speed; some test equipment manufacturers test LCD chips through a combination of test vectors of multiple types of test boards, but due to the different test timings of different types of test boards, and the existing test vector files do not support the expression of multiple test timings of the same test vector, the test instructions corresponding to the test timings of multiple types of test boards cannot be generated after the test vector files are compiled. Summary of the invention

[0003] In this embodiment, a test vector file compilation method, device and chip testing system are provided to solve the problem that the test vector file existing in the related technology does not support the expression of multiple test timings of the same test vector, resulting in the inability to generate test instructions corresponding to the test timings of multiple types of test boards after the test vector file is compiled.

[0004] In a first aspect, a method for compiling a test vector file is provided in this embodiment. The method is applied to a chip test system, wherein the chip test system includes a plurality of test boards connected to a chip under test, and the method includes:

[0005] Reading timing data, pin data and test vector data in a test vector file, wherein the test vector data includes a plurality of test vectors;

[0006] Based on the timing data, obtaining the order of the multiple test boards in the test vector and the timing configuration information corresponding to the multiple test boards;

[0007] Based on the sorting and the pin data, pin level information corresponding to each test vector in the test vector data is obtained, wherein the pin level information includes level values ​​of each pin of each of which the chip under test is connected to the multiple test boards respectively;

[0008] Based on the pin level information and the timing configuration information corresponding to the multiple test boards, compilation data of the test vectors respectively corresponding to the multiple test boards are generated.

[0009] In some embodiments, the timing data includes timing combination data and board timing data, and obtaining the order of the multiple test boards in the test vector and the timing configuration information corresponding to the multiple test boards based on the timing data includes:

[0010] Based on the order of the timing names of the multiple test boards in the timing combination data, obtaining the order of the multiple test boards in the test vector;

[0011] Based on the timing names of the multiple test boards in the timing combination data, the board timing data is queried to obtain timing configuration information corresponding to the timing names.

[0012] In some embodiments, obtaining the order of the multiple test boards in the test vector and the timing configuration information corresponding to the multiple test boards based on the timing data includes:

[0013] Based on the timing names of the multiple test boards in the timing combination data, acquiring the types of the multiple test boards;

[0014] Based on the types of the multiple test boards, a corresponding relationship between the time lengths of the test cycles of the multiple test boards is obtained.

[0015] In some embodiments, acquiring the pin level information corresponding to each test vector in the test vector data based on the sorting and the pin data includes:

[0016] Reading the board identification in the test vector data;

[0017] Query the pin data based on the board identifier to obtain the pin sequences of the chip under test corresponding to the multiple test boards;

[0018] Reading each test vector in the test vector data in sequence, and acquiring a level value sequence corresponding to the multiple test boards in the test vector based on the sorting;

[0019] The pin sequences corresponding to the multiple test boards are correspondingly combined with the level value sequences to obtain pin level information corresponding to the test vectors.

[0020] In some embodiments, sequentially reading each test vector in the test vector data and obtaining a level value sequence corresponding to the multiple test boards in the test vector based on the sorting includes:

[0021] The level value sequence in the test vector is read row by row, each row of the level value sequence corresponds to a test board, and each row of the level value sequence is arranged according to the order.

[0022] In some embodiments, generating the compiled data of the test vectors respectively corresponding to the multiple test boards based on the pin level information and the timing configuration information corresponding to the multiple test boards includes:

[0023] Reading each test vector in the test vector data in sequence to obtain a level value sequence of a target test board corresponding to the test vector;

[0024] Traversing and matching the level value sequence with the level value sequence in the test vector mapping table of the target test board;

[0025] In the case that the level value sequence exists in the test vector mapping table, the number of the level value sequence in the test vector mapping table is recorded in the compiled data corresponding to the test vector instead of the level value sequence.

[0026] In some embodiments, after traversing and matching the level value sequence with the level value sequence in the test vector mapping table of the target test board, the method further includes:

[0027] In the case that the level value sequence does not exist in the test vector mapping table, recording the level value sequence in the test vector mapping table and generating a corresponding number;

[0028] The number is recorded in the compiled data corresponding to the test vector data.

[0029] In some embodiments, generating the compiled data of the test vectors respectively corresponding to the multiple test boards based on the pin level information and the timing configuration information corresponding to the multiple test boards includes:

[0030] Based on the compilation data corresponding to each test vector in the test vector data, a compilation file corresponding to the test vector file is generated, and the compilation file includes the test vector compilation data corresponding to the multiple test boards and the test vector mapping table.

[0031] In a second aspect, a compiling device for a test vector file is provided in this embodiment, and the device is applied to a chip testing system, and the chip testing system includes a plurality of test boards connected to the chip under test, and the device includes:

[0032] A reading module, used to read timing data, pin data and test vector data in a test vector file, wherein the test vector data includes a plurality of test vectors;

[0033] A first acquisition module, configured to acquire, based on the timing data, the order of the multiple test boards in the test vector and the timing configuration information corresponding to the multiple test boards;

[0034] A second acquisition module is used to acquire pin level information corresponding to each test vector in the test vector data based on the sorting and the pin data, wherein the pin level information includes level values ​​of each pin of each of which the chip under test is connected to the multiple test boards respectively;

[0035] A generation module is used to generate compilation data of the test vectors corresponding to the multiple test boards respectively based on the pin level information and the timing configuration information corresponding to the multiple test boards.

[0036] In a third aspect, a chip testing system is provided in this embodiment, wherein the chip testing system includes a host computer and a plurality of test boards connected to the chip under test, and the host computer is used to execute the compiling method of the test vector file described in the first aspect.

[0037] Compared with the related art, the compiling method of the test vector file provided in the present embodiment obtains the timing information and pin information corresponding to each of the multiple test boards, and the test vectors that need to be compiled by reading the timing data, pin data and test vector data in the test vector file; obtains the sorting of the multiple test boards in the test vector and the timing configuration information corresponding to the multiple test boards based on the timing data, obtains the timing parameters of each test board in each test vector, and the sorting of the level information corresponding to each test board in the test vector; obtains the pin level information corresponding to each test vector in the test vector data based on the sorting and pin data, obtains the level value corresponding to the pin connected to the chip of each test board in each test vector; generates the compilation data of the test vectors corresponding to the multiple test boards respectively based on the pin level information and the timing configuration information corresponding to the multiple test boards, solves the problem that the test vector file does not support the expression of multiple test timings of the same test vector, and generates the test instructions corresponding to the test timings of multiple types of test boards through the compilation of the test vector file.

[0038] Details of one or more embodiments of the present application are set forth in the following drawings and description to make other features, objects, and advantages of the present application more readily apparent. BRIEF DESCRIPTION OF THE DRAWINGS

[0039] The drawings described herein are used to provide a further understanding of the present application and constitute a part of the present application. The illustrative embodiments of the present application and their descriptions are used to explain the present application and do not constitute an improper limitation on the present application. In the drawings:

[0040] Figure 1It is a computer hardware structure block diagram of a method for compiling a test vector file in some embodiments of the present application;

[0041] Figure 2 is a flow chart of a method for compiling a test vector file in some embodiments of the present application;

[0042] Figure 3 is a flowchart of obtaining the sequencing and timing configuration information of the test board in some embodiments of the present application;

[0043] Figure 4 is a flowchart of obtaining the corresponding relationship of the test cycles of the test board in some embodiments of the present application;

[0044] Figure 5 is a flowchart of obtaining pin level information corresponding to a test vector in some embodiments of the present application;

[0045] Figure 6 is a schematic diagram of test vector data of some embodiments of the present application;

[0046] Figure 7 is a flow chart of generating compiled data in some embodiments of the present application;

[0047] Figure 8 is a flow chart of generating compiled data in some other embodiments of the present application;

[0048] Fig. 9 is a flow chart of a method for compiling a test vector file of some preferred embodiments of the present application;

[0049] Fig.10 It is a structural block diagram of a compiling device for a test vector file in some embodiments of the present application. DETAILED DESCRIPTION

[0050] In order to more clearly understand the purpose, technical solutions and advantages of the present application, the present application is described and illustrated below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0051] Unless otherwise defined, the technical terms or scientific terms involved in this application shall have the general meaning understood by people with ordinary skills in the technical field to which this application belongs. The words "one", "a", "a", "the", "these" and the like in this application do not represent quantitative restrictions, and they can be singular or plural. The terms "include", "comprise", "have" and any variants thereof involved in this application are intended to cover non-exclusive inclusions; for example, a process, method and system, product or device comprising a series of steps or modules (units) is not limited to the listed steps or modules (units), but may include unlisted steps or modules (units), or may include other steps or modules (units) inherent to these processes, methods, products or devices. The words "connect", "connected", "coupled" and the like involved in this application are not limited to physical or mechanical connections, but may include electrical connections, whether directly or indirectly. The "multiple" involved in this application refers to two or more. "And / or" describes the association relationship of associated objects, indicating that there can be three relationships. For example, "A and / or B" can mean: A exists alone, A and B exist at the same time, and B exists alone. Usually, the character " / " indicates that the objects associated with each other are in an "or" relationship. The terms "first", "second", "third", etc. involved in this application are only used to distinguish similar objects and do not represent a specific ordering of the objects.

[0052] The test vector file compilation method provided in the embodiment of the present application can be executed in the host computer of the chip test system. The chip test system includes a host computer and multiple test boards connected to the chip under test, and the host computer is in communication connection with the multiple test boards. The host computer can be a server, a computer or a similar computing device. When the method is applied to a computer, Figure 1 1 is a hardware structure diagram of a computer for compiling a test vector file in some embodiments of the present application. Figure 1 As shown, the computer may include one or more ( Figure 1 The computer may include a processor 102 and a memory 104 for storing data, wherein the processor 102 may include but is not limited to a processing device of a central processing unit (CPU). The number of CPUs may be one or more, and this embodiment does not limit this. The computer may also include a transmission device 106 and an input / output device 108 for communication functions. A person skilled in the art will understand that Figure 1 The structure shown is only for illustration and does not limit the structure of the above-mentioned computer. Figure 1 More or fewer components as shown, or with Figure 1 Different configurations shown.

[0053] The memory 104 can be used to store computer programs, for example, software programs and modules of application software, such as the computer program corresponding to the compilation method of the test vector file in the present embodiment. The processor 102 executes various functional applications and data processing by running the computer program stored in the memory 104, that is, to implement the above method. The memory 104 may include a high-speed random access memory, and may also include a non-volatile memory, such as one or more magnetic storage devices, flash memory, or other non-volatile solid-state memory. In some embodiments, the memory 104 may further include a memory remotely arranged relative to the processor 102, and these remote memories may be connected to the computer via a network. Examples of the above-mentioned network include, but are not limited to, the Internet, an intranet, a local area network, a mobile communication network, and combinations thereof.

[0054] The transmission device 106 is used to receive or send data via a network. The above network includes a wireless network provided by a communication provider of the computer. In one example, the transmission device 106 includes a network adapter (Network Interface Controller, referred to as NIC), which can be connected to other network devices through a base station so as to communicate with the Internet. In one example, the transmission device 106 can be a radio frequency (RF) module, which is used to communicate with the Internet wirelessly.

[0055] In this embodiment, a method for compiling a test vector file is provided. Figure 2 is a flowchart of a method for compiling a test vector file in some embodiments of the present application, such as Figure 2 As shown, the process includes the following steps:

[0056] Step S201, reading timing data, pin data and test vector data in a test vector file, wherein the test vector data includes a plurality of test vectors.

[0057] Chip testing implements functional testing of the device under test by applying stimulus to the chip under test and detecting whether the response of the chip is consistent with expectations. The stimulus and response of the test can be represented by a test vector. A test vector includes the stimulus value and response value of each pin of the chip under test in a test cycle. The stimulus value and response value are reflected as the input and output level values ​​of the pin. A test item can include multiple test cycles, and a chip test can include multiple test items.

[0058] The test vector file is a file used to store the test vector, timing data, pin data and other related information of the device under test, and in this embodiment, it is a file in CAP format. The test vector data includes multiple test vectors.

[0059] Timing data refers to the timing configuration information of each type of test board in a test cycle, such as the duration of the test cycle, drive delay time, offset time, comparison time, etc. The timing configuration information of different types of test boards can be the same or different. Each type of test board can have a variety of pre-set timing configuration information, and use different timing configuration information in different test cycles. Different timing configuration information can be distinguished by different timing names.

[0060] Pin data refers to the chip pin sequence corresponding to each type of test board. When a test item is tested on the chip under test through multiple test boards, the multiple test boards can be connected to different pins of the chip under test respectively. In the same test time period, multiple test boards can execute the same test vector (pattern) according to their own timing configuration information to input and output the pin stimulus value and response value corresponding to each test board.

[0061] Since the timing configuration information of different types of test boards is different, and the CAP file does not support the expression of multiple test timings for the same test vector, in this embodiment, the timing data, pin data and test vector data in the CAP file are read, and the CAP file is compiled to generate a compilation file with a preset format. The compilation file includes test instructions generated for the same test vector based on the timing configuration information and pin sequences of different types of test boards.

[0062] Specifically, the compiled file may be composed of a plurality of data blocks, each of which is used to store different types of data. In a specific embodiment, the compiled file may include a pin information data block, a timing configuration data block, a test instruction data block, etc. Different types of test boards may correspond to different test instruction data blocks, respectively. The compiled file may be in binary format.

[0063] Step S202: Based on the timing data, the order of the various test boards in the test vector and the timing configuration information corresponding to the various test boards are obtained.

[0064] According to the timing data in the CAP file, the order of different types of test boards in the test vector and the timing configuration information corresponding to each test board can be obtained. The order is used to match the level value in the test vector with the type of test board. The timing configuration information is used to apply the time length, drive delay time, offset time, comparison time and other parameters of the test cycle of each test board to each test cycle, and generate the test instructions corresponding to the test cycle. The same test board can use the same or different timing configuration information in different test cycles.

[0065] Step S203, based on the sorting and the pin data, obtaining the pin level information corresponding to each test vector in the test vector data, wherein the pin level information includes the level values ​​of the pins to which the chip under test is respectively connected to the various test boards.

[0066] According to the order of multiple test boards in the test vector, the level values ​​in the test vector are matched with the types of test boards; then, according to the chip pin sequence corresponding to each type of test board, the level values ​​in the test vector are matched with the specific pins of this type of test board, and the level values ​​of each pin connected to each test board in the test vector are obtained.

[0067] Step S204 , generating compilation data of test vectors corresponding to the various test boards respectively based on the pin level information and the timing configuration information corresponding to the various test boards.

[0068] According to the level values ​​of the pins connected to the test boards in each test vector and the timing configuration information corresponding to the test cycle of the test vector, the compilation data of each test board for the test vector is generated, and the compilation data is written into the test instruction data block corresponding to the test board in the compilation file. Based on the compilation data, the test board can run the corresponding test vector according to the time length of each test cycle and the configuration value of the timing parameters, and input or output the corresponding level value to the corresponding pin.

[0069] Through steps S201 to S204, by reading the timing data, pin data and test vector data in the test vector file, the timing information and pin information corresponding to each of the multiple test boards and the test vectors that need to be compiled are obtained; by obtaining the order of the multiple test boards in the test vector and the timing configuration information corresponding to the multiple test boards based on the timing data, the timing parameters of each test board in each test vector and the order of the level information corresponding to each test board in the test vector are obtained; by obtaining the pin level information corresponding to each test vector in the test vector data based on the order and the pin data, the level value corresponding to the pin connected to the chip of each test board in each test vector is obtained; by generating the compilation data of the test vectors corresponding to the multiple test boards based on the pin level information and the timing configuration information corresponding to the multiple test boards, the problem that the test vector file does not support the expression of multiple test timings of the same test vector is solved, and the test instructions corresponding to the test timings of multiple types of test boards are generated through the compilation of the test vector file.

[0070] In some embodiments, the timing data includes timing combination data and board timing data. Figure 3 is a flowchart of obtaining the sequencing and timing configuration information of the test board in some embodiments of the present application, such as Figure 3 As shown, the process includes the following steps:

[0071] Step S301, based on the order of the timing names of the various test boards in the timing combination data, obtain the order of the various test boards in the test vector.

[0072] The timing combination data may include a combination name and a combination sequence. The combination name is used to distinguish different combinations of timing configuration information of multiple test boards. The combination sequence is a string composed of the timing names of multiple test boards arranged in a certain order. The timing names of each test board can be connected by the character +.

[0073] In a specific embodiment, it is assumed that the test boards are divided into three types: digital board DIO, LCD screen driver board LCD, and high-speed board HSD. Each type of test board has two types of timing configuration information. The timing configuration information of DIO is DIOTS1 and DIOTS2, the timing configuration information of LCD is LCDTS3 and LCDTS4, and the timing configuration information of HSD is HSDTS5 and HSDTS6. The timing combination data used by each test vector in the test vector file is as follows:

[0074] Group Name Combination Sequence TSGroup1 DIOTS1+LCDTS3+HSDTS6 TSGroup2 DIOTS2+LCDTS3+HSDTS6 TSGroup3 DIOTS2+LCDTS3+HSDTS5 TSGroup4 DIOTS2+LCDTS4+HSDTS6

[0075] The order of each test board in the string of the above combination sequence is the order of each test board in the test vector. That is, in the test vector file, the level value corresponding to each test vector is arranged in the order of DIO, LCD, and HSD.

[0076] In this embodiment, a corresponding combination sequence is determined according to a combination name in the test vector data, and the combination sequence is applicable to a plurality of test vectors included in the test vector data.

[0077] Step S302, based on the timing names of the various test boards in the timing combination data, query the board timing data to obtain the timing configuration information corresponding to the timing names.

[0078] The board timing data includes the preset timing names of each test board and the corresponding timing configuration information. Each test board can be preset with multiple timing configuration information and selected for use according to the requirements of each test vector. According to the timing names corresponding to each test board in the above combination sequence, the board timing data is queried to obtain the corresponding timing configuration information. That is, in the multiple test vectors contained in the test vector data, each test board performs timing configuration according to the corresponding timing configuration information.

[0079] Through steps S301 to S302, by sorting the timing names of multiple test boards in the timing combination data, the sorting of multiple test boards in the test vector is obtained, providing necessary information for the subsequent correspondence between the test boards and the level values; by querying the board timing data based on the timing names of multiple test boards in the timing combination data, the timing configuration information corresponding to the timing names is obtained, providing necessary data for the compilation of the test vector.

[0080] In some embodiments, Figure 4 is a flowchart of obtaining the corresponding relationship of the test cycle of the test board in some embodiments of the present application, such as Figure 4 As shown, the process includes the following steps:

[0081] Step S401, obtaining types of multiple test boards based on the timing names of the multiple test boards in the timing combination data.

[0082] In this embodiment, the timing name of each test board complies with a preset naming rule, that is, timing name = test board type name + timing number. Therefore, the timing name can be parsed based on the naming rule to obtain the type of the test board.

[0083] Step S402: based on the types of the various test boards, obtain the corresponding relationship between the time lengths of the test cycles of the various test boards.

[0084] Different test board types have different test cycle time lengths Period. In a specific embodiment, Period_DIO=Period_LCD=16*Period_HSD. The test cycle time length of the high-speed board HSD is shorter, and more chip data can be collected in the same time. When the test cycle time length of one type of test board is determined, the test cycle time length of other types of test boards can be obtained according to the above correspondence.

[0085] Through steps S401 to S402, the types of multiple test boards are obtained based on the timing names of the multiple test boards in the timing combination data, and based on the types of the multiple test boards, the corresponding relationship between the time lengths of the test cycles of the multiple test boards is obtained, providing a reference for setting timing configuration information for each type of test board.

[0086] In some embodiments, Figure 5 is a flowchart of obtaining pin level information corresponding to a test vector in some embodiments of the present application, such as Figure 5 As shown, the process includes the following steps:

[0087] Step S501, read the board identification in the test vector data.

[0088] Step S502 , querying pin data based on the board identification to obtain pin sequences of the chip under test corresponding to the various test boards.

[0089] The pin data is queried based on the board identification to obtain the pin sequence of the chip under test corresponding to different types of test boards.

[0090] Step S503, reading each test vector in the test vector data in sequence, and obtaining level value sequences corresponding to multiple test boards in the test vector based on the sorting.

[0091] Figure 6 Schematic diagram of test vector data of some embodiments of the present application. The test vector data includes a combination name 65, a board identifier 63 and multiple test vectors 61 (5 are shown in the figure). The board identifier is the identifier corresponding to the various types of test boards in the pin data. The board identifiers are also arranged in the order of the board types in the timing combination. Specifically, Figure 6 The board identifiers of the three test boards in the illustrated embodiment are ChaGS, LCDGS and HSIFGS respectively.

[0092] Each test vector 61 is read in sequence, and each test vector 61 includes identifiers and level values ​​corresponding to each test board arranged in order. Figure 6 In the illustrated embodiment, the identifier corresponding to DIO is ^, the identifier corresponding to LCD is *, and the identifier corresponding to HSD is &.

[0093] Step S504 , combining the pin sequences corresponding to the various test boards with the level value sequences to obtain the pin level information corresponding to the test vectors.

[0094] By making a one-to-one correspondence between the level value sequence following the identifier and the pin sequence of the corresponding test board, the pin level information of different types of test boards in the test vector can be obtained.

[0095] Through steps S501 to S504, based on the pre-set format of the test vector data, the board identification in the test vector data is read, and the pin data is queried based on the board identification to obtain the pin sequences of the chip under test corresponding to the multiple test boards; by reading each test vector in turn, the level value sequences corresponding to the multiple test boards are obtained based on the sorting, and the pin sequences corresponding to the multiple test boards are combined with the level value sequences to obtain the pin level information corresponding to the test vector, thereby providing the necessary pin level data for the subsequent compilation of the test vector.

[0096] Furthermore, in some embodiments, a specific method for obtaining level value sequences corresponding to multiple test boards based on sorting is also provided, and the method includes:

[0097] The level value sequence in the test vector is read line by line, each line of the level value sequence corresponds to a test board, and the level value sequences in each line are arranged according to the order.

[0098] In this embodiment, the level value sequences corresponding to different types of test boards in the test vector are arranged row by row, and the arrangement order is consistent with the sorting of each test board in the timing combination. Therefore, the level value sequence can be read row by row and corresponded to the pin sequence of each test board to obtain the pin level information corresponding to the test vector.

[0099] The test vector file compilation method of this embodiment reads the level value sequence line by line based on the arrangement of the level value sequence in the pre-set test vector, providing another reading method for obtaining the level value sequence corresponding to each test board in the test vector.

[0100] In some embodiments, Figure 7 is a flow chart of generating compiled data in some embodiments of the present application, such as Figure 7 As shown, the process includes the following steps:

[0101] Step S701, read each test vector in the test vector data in turn to obtain a level value sequence of a target test board corresponding to the test vector.

[0102] In actual chip testing, there may be some test boards with small storage space and large test vector data volume, resulting in insufficient storage space. The test vector corresponding to the test board can be compressed and stored by establishing a test vector mapping table. The test board is the target test board.

[0103] Specifically, each test vector in the test vector data is read in sequence, and according to the order of the target test board in the plurality of test boards, a level value sequence corresponding to the target test board in each test vector is obtained.

[0104] Step S702: traverse and match the level value sequence with the level value sequence in the test vector mapping table of the target test board.

[0105] According to the pre-established test vector mapping table, the level value sequence is traversed and matched with the level value sequence in the test vector mapping table of the target test board.

[0106] Step S703: if the level value sequence exists in the test vector mapping table, the number of the level value sequence in the test vector mapping table is recorded in the compiled data corresponding to the test vector instead of the level value sequence.

[0107] If there is a level value sequence in the test vector mapping table, the compilation data does not directly record the level value sequence, but records the number of the level value sequence in the test vector mapping table, thereby compressing and storing the level value sequence of the target test board.

[0108] Through steps S701 to S703, each test vector in the test vector data is read in turn to obtain the level value sequence of the target test board corresponding to the test vector, and the level value sequence is traversed and matched with the level value sequence in the test vector mapping table of the target test board. When the level value sequence exists in the test vector mapping table, the number of the level value sequence in the test vector mapping table is recorded in the compiled data corresponding to the test vector instead of the level value sequence, thereby realizing compressed storage of the level value sequence of the target test board, reducing the storage space occupied by the test vector, and solving the problem of insufficient storage space of the target test board.

[0109] In some embodiments, Figure 8 is a flow chart of generating compiled data in some other embodiments of the present application, such as Figure 8 As shown, the process includes the following steps:

[0110] Step S801: If the level value sequence does not exist in the test vector mapping table, the level value sequence is recorded in the test vector mapping table and a corresponding number is generated.

[0111] In the case that the level value sequence does not exist in the test vector mapping table, the level value sequence is recorded in the test vector mapping table, and a corresponding number is automatically generated.

[0112] Step S802: record the number in the compiled data corresponding to the test vector data.

[0113] Through steps S801 to S802, when the level value sequence does not exist in the test vector mapping table, the level value sequence is recorded in the test vector mapping table, and a corresponding number is generated, and the number is recorded in the compiled data corresponding to the test vector data. The level value sequence of the target test board is stored in a compressed encoding manner, thereby reducing the storage space occupied by the test vector.

[0114] In some embodiments, a specific method for generating a compilation file corresponding to a test vector file is also provided, the method comprising:

[0115] Based on the compilation data corresponding to each test vector in the test vector data, a compilation file corresponding to the test vector file is generated, and the compilation file includes test vector compilation data corresponding to multiple test boards and a test vector mapping table.

[0116] The compilation file in this embodiment is composed of multiple data blocks. In a specific embodiment, the compilation file may include a pin information data block, a timing configuration data block, a timing combination data block, a test instruction data block, etc. Different types of test boards may correspond to different test instruction data blocks, for example, a DIO board corresponds to a vector scan record data block VSR and a non-vector scan record data block VNR; an HSD board corresponds to a high-speed vector record VHR; and an LCD board corresponds to an LCD vector record VLR and a test vector mapping table VLMR.

[0117] The compiling method of the test vector file of the present embodiment generates a compilation file corresponding to the test vector file based on the compilation data corresponding to each test vector in the test vector data. The compilation file includes test vector compilation data corresponding to multiple test boards and a test vector mapping table, thereby realizing separate storage of test vector compilation data corresponding to multiple test boards, and facilitating the corresponding transmission of test instructions for multiple test boards.

[0118] The present embodiment is described and illustrated below through preferred embodiments. Fig. 9 is a flowchart of a method for compiling a test vector file in some preferred embodiments of the present application, such as Fig. 9 As shown, the process includes the following steps:

[0119] Step S901, read the board timing data from the test vector file, and write the board timing data into the timing configuration data block TSR of the compilation file (CBP file);

[0120] Step S902, reading the timing combination data from the test vector file, and writing the timing combination data into the timing combination data block TSGR of the compilation file;

[0121] Step S903, reading the pin data from the test vector file and verifying the pin data; writing the pin data into the pin information data block SIR of the compiled file;

[0122] Step S904, reading test vector data from the test vector file, the test vector data including a combination name, a board identifier and a plurality of test vectors;

[0123] Step S905, querying the timing combination data according to the combination name, obtaining the order of the multiple test boards in the test vector and the timing name of each test board;

[0124] Step S906, querying the board timing data according to the timing name of each test board to obtain the timing configuration information corresponding to each test board;

[0125] Step S907, querying the pin data based on the board identification to obtain the pin sequences of the chips under test corresponding to the various test boards;

[0126] Step S908, reading each test vector in the test vector data in sequence, and reading the level value sequence in the test vector row by row;

[0127] Step S909, according to the order of the various test boards in the test vector, the level value sequence of each row is matched with the test board;

[0128] Step S910, matching the level value sequence corresponding to the test board with the pin sequence of the chip under test one by one, and obtaining the pin level information corresponding to each test board in the test vector;

[0129] Step S911, based on the pin level information and timing configuration information corresponding to each test board, generate a test instruction corresponding to each test board in each test vector;

[0130] Step S912, writing the test instructions corresponding to each test board into the corresponding test instruction data block, wherein the DIO board corresponds to VSR and VNR; the HSD board corresponds to VHR; and the LCD board corresponds to VLR and VLMR;

[0131] Step S913, when the test board includes an LCD board, traverse and match the level value sequence corresponding to the LCD board in each test vector with the VLMR;

[0132] Step S914, determining whether the level value sequence exists in the VLMR;

[0133] Step S915, if the level value sequence exists, record the number of the level value sequence in the VLMR in the VLR;

[0134] Step S916: if the level value sequence does not exist in the VLMR, the level value sequence is recorded in the VLMR, a corresponding number is generated, and the number is recorded in the VLR;

[0135] Step S917, write tag information into the LIR data block of the compiled file, and write comment information into the AIR data block;

[0136] Step S918, write the end mark EMR data block into the compilation file, and the compilation ends.

[0137] Through steps S901 to S918, the timing data, pin data and test vector data respectively stored in the test vector file are read, compiled and stored in the corresponding data block of the compiled file according to a preset format; according to the combination name and board identification in the test vector data, the timing data and pin data are queried, and the timing configuration information and pin level information corresponding to each test board are obtained in combination with the level value sequence in the test vector; the test instructions corresponding to each test board are generated according to the timing configuration information and the pin level information, and stored in the data block corresponding to each test board, which solves the problem that the test vector file does not support the expression of multiple test timings of the same test vector; the level value sequence of the LCD board is stored in a mode encoding manner, which reduces the storage space occupied by the test vector.

[0138] In some embodiments, the present application also provides a test vector file compilation device, which is applied to a chip test system, and the chip test system includes a variety of test boards connected to the chip under test. The test vector file compilation device is used to implement the above-mentioned embodiments and preferred implementations, and the descriptions that have been made will not be repeated. The terms "module", "unit", "sub-unit", etc. used below can be a combination of software and / or hardware that can implement predetermined functions. In some embodiments, Fig.10 : is a structural block diagram of the compiling device of the test vector file of this embodiment, such as Fig.10 As shown, the device comprises:

[0139] A reading module 1001 is used to read timing data, pin data and test vector data in a test vector file, wherein the test vector data includes a plurality of test vectors;

[0140] A first acquisition module 1002 is used to acquire the order of multiple test boards in the test vector and the timing configuration information corresponding to the multiple test boards based on the timing data;

[0141] A second acquisition module 1003 is used to acquire pin level information corresponding to each test vector in the test vector data based on the sorting and the pin data, wherein the pin level information includes level values ​​of each pin of the chip under test and the plurality of test boards respectively connected thereto;

[0142] The generating module 1004 is used to generate the compilation data of the test vectors corresponding to the various test boards respectively based on the pin level information and the timing configuration information corresponding to the various test boards.

[0143] The compiling device of the test vector file of the present embodiment reads the timing data, pin data and test vector data in the test vector file through the reading module 1001, and obtains the timing information and pin information corresponding to each of the multiple test boards, as well as the test vectors that need to be compiled; obtains the sorting of the multiple test boards in the test vector and the timing configuration information corresponding to the multiple test boards based on the timing data through the first acquisition module 1002, and obtains the timing parameters of each test board in each test vector, as well as the sorting of the level information corresponding to each test board in the test vector; obtains the pin level information corresponding to each test vector in the test vector data based on the sorting and pin data through the second acquisition module 1003, and obtains the level value corresponding to the pin connected to the chip of each test board in each test vector; generates the compilation data of the test vectors corresponding to the multiple test boards based on the pin level information and the timing configuration information corresponding to the multiple test boards through the generation module 1004, thereby solving the problem that the test vector file does not support the expression of multiple test timings of the same test vector, and generates the test instructions corresponding to the test timings of multiple types of test boards through the compilation of the test vector file.

[0144] In some embodiments, the present application also provides a chip testing system, which includes a host computer and multiple test boards connected to the chip under test, and the host computer is used to execute the compiling method of the test vector file described in the above embodiment.

[0145] The chip testing system of this embodiment compiles the test vector file through the host computer to obtain the corresponding compilation file, and generates test instructions corresponding to the test timings of multiple types of test boards and cards, thereby solving the problem that the test vector file does not support the expression of multiple test timings for the same test vector, and improving the compilation efficiency of the test vector file that supports multiple types of test boards and cards.

[0146] It should be noted that the specific examples in this embodiment can refer to the examples described in the above embodiments and optional implementation modes, and will not be repeated in this embodiment.

[0147] It should be understood that the specific embodiments described herein are only used to explain the application, rather than to limit it. Based on the embodiments provided in this application, all other embodiments obtained by ordinary technicians in this field without creative work are within the protection scope of this application.

[0148] Obviously, the drawings are only some examples or embodiments of the present application. For ordinary technicians in the field, the present application can also be applied to other similar situations based on these drawings without creative work. In addition, it is understandable that although the work done in this development process may be complicated and lengthy, for ordinary technicians in the field, certain changes in design, manufacturing or production based on the technical content disclosed in this application are only conventional technical means and should not be regarded as insufficient content disclosed in this application.

[0149] The term "embodiment" in this application refers to a specific feature, structure or characteristic described in conjunction with the embodiment that can be included in at least one embodiment of the present application. The appearance of this phrase in various locations in the specification does not necessarily mean the same embodiment, nor does it mean that it is mutually exclusive with other embodiments and is independent or optional. It is clearly or implicitly understood by those of ordinary skill in the art that the embodiments described in this application can be combined with other embodiments without conflict.

[0150] The above-mentioned embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of patent protection. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the scope of protection of the present application. Therefore, the scope of protection of the present application shall be subject to the attached claims.

Claims

1. A method for compiling a test vector file, characterized in that: The method is applied to a chip testing system, wherein the chip testing system includes a plurality of testing boards connected to the chip under test, and the method includes: Reading timing data, pin data and test vector data in a test vector file, wherein the test vector data includes a plurality of test vectors; Based on the timing data, obtaining the order of the multiple test boards in the test vector and the timing configuration information corresponding to the multiple test boards; Based on the sorting and the pin data, pin level information corresponding to each test vector in the test vector data is obtained, wherein the pin level information includes level values ​​of each pin of each of which the chip under test is connected to the multiple test boards respectively; Based on the pin level information and the timing configuration information corresponding to the multiple test boards, compilation data of the test vectors respectively corresponding to the multiple test boards are generated.

2. The method according to claim 1, characterized in that The timing data includes timing combination data and board timing data, and obtaining the order of the multiple test boards in the test vector and the timing configuration information corresponding to the multiple test boards based on the timing data includes: Based on the order of the timing names of the multiple test boards in the timing combination data, obtaining the order of the multiple test boards in the test vector; Based on the timing names of the multiple test boards in the timing combination data, the board timing data is queried to obtain timing configuration information corresponding to the timing names.

3. The method according to claim 1, characterized in that The acquiring, based on the timing data, the order of the multiple test boards in the test vector and the timing configuration information corresponding to the multiple test boards comprises: Based on the timing names of the multiple test boards in the timing combination data, acquiring the types of the multiple test boards; Based on the types of the multiple test boards, a corresponding relationship between the time lengths of the test cycles of the multiple test boards is obtained.

4. The method according to any one of claims 1 to 3, characterized in that: The acquiring, based on the sorting and the pin data, the pin level information corresponding to each test vector in the test vector data comprises: Reading the board identification in the test vector data; Query the pin data based on the board identifier to obtain the pin sequences of the chip under test corresponding to the multiple test boards; Reading each test vector in the test vector data in sequence, and acquiring a level value sequence corresponding to the multiple test boards in the test vector based on the sorting; The pin sequences corresponding to the multiple test boards are correspondingly combined with the level value sequences to obtain pin level information corresponding to the test vectors.

5. The method according to claim 4, characterized in that The step of sequentially reading each test vector in the test vector data and obtaining a level value sequence corresponding to the multiple test boards in the test vector based on the sorting comprises: The level value sequence in the test vector is read row by row, each row of the level value sequence corresponds to a test board, and each row of the level value sequence is arranged according to the order.

6. The method according to any one of claims 1 to 3, characterized in that: The generating, based on the pin level information and the timing configuration information corresponding to the multiple test boards, the compiled data of the test vectors respectively corresponding to the multiple test boards comprises: Reading each test vector in the test vector data in sequence to obtain a level value sequence of a target test board corresponding to the test vector; Traversing and matching the level value sequence with the level value sequence in the test vector mapping table of the target test board; In the case that the level value sequence exists in the test vector mapping table, the number of the level value sequence in the test vector mapping table is recorded in the compiled data corresponding to the test vector instead of the level value sequence.

7. The method according to claim 6, characterized in that After traversing and matching the level value sequence with the level value sequence in the test vector mapping table of the target test board, the method further includes: In the case that the level value sequence does not exist in the test vector mapping table, recording the level value sequence in the test vector mapping table and generating a corresponding number; The number is recorded in the compiled data corresponding to the test vector data.

8. The method according to claim 6, characterized in that The generating, based on the pin level information and the timing configuration information corresponding to the multiple test boards, the compiled data of the test vectors respectively corresponding to the multiple test boards comprises: Based on the compilation data corresponding to each test vector in the test vector data, a compilation file corresponding to the test vector file is generated, and the compilation file includes the test vector compilation data corresponding to the multiple test boards and the test vector mapping table.

9. A compiling device for a test vector file, characterized in that: The device is applied to a chip testing system, wherein the chip testing system includes a plurality of testing boards connected to the chip under test, and the device includes: A reading module, used to read timing data, pin data and test vector data in a test vector file, wherein the test vector data includes a plurality of test vectors; A first acquisition module, configured to acquire, based on the timing data, the order of the multiple test boards in the test vector and the timing configuration information corresponding to the multiple test boards; A second acquisition module is used to acquire pin level information corresponding to each test vector in the test vector data based on the sorting and the pin data, wherein the pin level information includes level values ​​of each pin of each of which the chip under test is connected to the multiple test boards respectively; A generation module is used to generate compilation data of the test vectors corresponding to the multiple test boards respectively based on the pin level information and the timing configuration information corresponding to the multiple test boards.

10. A chip testing system, characterized in that: The chip testing system includes a host computer and a plurality of test boards connected to the chip under test, and the host computer is used to execute the compiling method of the test vector file according to any one of claims 1 to 8.

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