Debugging data processing method, chip and electronic equipment

Abstract

The invention relates to the technical field of data debugging, in particular to a debugging data processing method, a chip and electronic equipment, the debugging data processing method comprises the following steps: receiving debugging operation data sent by a second chip, the debugging operation data comprising first header information, debugging operation information and first verification information; performing first verification on the debugging operation data according to first header information; when the first verification is passed, performing second verification on the debugging operation data according to first verification information; when the second verification is passed, performing data debugging according to the debugging operation information; according to the mode, after the debugging operation data are received, the first verification is carried out through the first header information, and the debugging operation data are distinguished from other data; second verification is carried out through the first verification information, so that the accuracy of debugging operation data is ensured; performing data debugging according to the debugging operation information; and the data debugging accuracy and the data debugging efficiency can be improved at the same time.

Description

Technical Field

[0001] The present application relates to the field of data debugging technology, and in particular to a debugging data processing method, chip and electronic equipment. Background Art

[0002] EC (Embedded Controller) chip is a very important customized control chip in electronic devices such as laptops. After the chip is assembled into the electronic device or when problems occur during the use of the electronic device, the chip needs to be debugged.

[0003] Currently, when a chip is debugged, it is necessary to import debug data into the chip or send a debug data acquisition instruction to the chip to obtain debug data from the chip. During the process of importing debug data or sending debug data acquisition instructions, when data crosstalk or communication obstacles occur, data transmission disorder will occur, which is not conducive to improving the accuracy and efficiency of data debugging. Summary of the invention

[0004] In view of the above problems, the embodiments of the present application provide a debugging data processing method, a chip and an electronic device to solve the above technical problems that are not conducive to improving the accuracy and efficiency of data debugging.

[0005] In a first aspect, an embodiment of the present application provides a debugging data processing method, which is applied to a first chip. The debugging data processing method includes:

[0006] receiving debugging operation data sent by the second chip, wherein the debugging operation data includes first header information, debugging operation information and first verification information, and the first verification information is generated according to the first header information and the debugging operation information;

[0007] Performing a first check on the debugging operation data according to the first header information;

[0008] When the first verification passes, performing a second verification on the debugging operation data according to the first verification information;

[0009] When the second verification passes, data debugging is performed according to the debugging operation information.

[0010] In a second aspect, an embodiment of the present application provides a chip, including:

[0011] Processing module;

[0012] a storage module coupled to the processing module;

[0013] and, instructions, which are stored in the storage module and can be executed by the processing module to implement the above-mentioned debugging data processing method.

[0014] In a third aspect, an embodiment of the present application provides an electronic device, wherein the electronic device includes the above-mentioned chip.

[0015] The debugging data processing method provided in the embodiment of the present application includes: receiving debugging operation data sent by a second chip, wherein the debugging operation data includes first header information, debugging operation information and first verification information; performing a first verification on the debugging operation data according to the first header information; when the first verification passes, performing a second verification on the debugging operation data according to the first verification information; when the second verification passes, performing data debugging according to the debugging operation information; in the above manner, after receiving the debugging operation data, performing a first verification through its first header information to distinguish the debugging operation data from other data; performing a second verification through its first verification information to ensure the accuracy of the debugging operation data; and performing data debugging according to its debugging operation information; which is beneficial to simultaneously improve the accuracy and efficiency of data debugging.

[0016] These and other aspects of the present application will become more clearly understood in the description of the following embodiments. BRIEF DESCRIPTION OF THE DRAWINGS

[0017] Figure 1 An application scenario diagram of the debugging data processing method provided in an embodiment of the present application is shown.

[0018] Figure 2 A flow chart of a debugging data processing method provided in an embodiment of the present application is shown.

[0019] Figure 3 A flow chart showing a debugging data processing method provided in an embodiment of the present application is shown.

[0020] Figure 4 A schematic diagram of the structure of debugging operation data in the debugging data processing method provided in an embodiment of the present application is shown.

[0021] Figure 5 An application scenario diagram of the debugging data processing method provided in an embodiment of the present application is shown.

[0022] Figure 6 A schematic diagram of the structure of a chip provided in an embodiment of the present application is shown.

[0023] Figure 7 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application is shown. DETAILED DESCRIPTION

[0024] The embodiments of the present application are described in detail below, and examples of the embodiments are shown in the accompanying drawings, wherein the same or similar reference numerals throughout represent the same or similar elements or elements having the same or similar functions. The embodiments described below with reference to the accompanying drawings are exemplary and are only used to explain the present application, and cannot be understood as limiting the present application.

[0025] In order to enable those skilled in the art to better understand the solutions of the present application, the technical solutions in the embodiments of the present application will be clearly and completely described below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, rather than all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without making creative work are within the scope of protection of the present application.

[0026] In the embodiments of the present application, it should be noted that, in this article, relational terms such as first and second, etc. are merely used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any actual relationship or order between these entities or operations.

[0027] Moreover, the terms "comprises," "comprising," or any other variation thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus that includes a list of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of additional identical elements in the process, method, article, or apparatus that includes the element.

[0028] In the description of the embodiments of the present application, words such as "example" or "for example" are used to indicate examples, illustrations or descriptions. Any embodiment or design described as "example" or "for example" in the embodiments of the present application is not to be interpreted as being more preferred or having more advantages than another embodiment or design. The use of words such as "example" or "for example" is intended to present relative concepts in a clear manner.

[0029] In addition, the "plurality" in the embodiments of the present application refers to two or more than two. In view of this, in the embodiments of the present application, "plurality" can also be understood as "at least two". "At least one" can be understood as one or more, for example, one, two or more. For example, including at least one means including one, two or more, and there is no limit on which ones are included. For example, including at least one of A, B and C, then A, B, C, A and B, A and C, B and C, or A, B and C can be included.

[0030] It should be noted that, in the embodiments of the present application, "and / or" describes the association relationship of the associated objects, indicating that three relationships may exist. For example, A and / or B may represent: A exists alone, A and B exist at the same time, and B exists alone. In addition, the character " / ", unless otherwise specified, generally indicates that the associated objects before and after are in an "or" relationship.

[0031] It should be noted that in the embodiments of the present application, "connection" can be understood as electrical connection, and the connection between two electrical components can be a direct or indirect connection between the two electrical components. For example, the connection between A and B can be either a direct connection between A and B or an indirect connection between A and B through one or more other electrical components.

[0032] The debugging data processing method provided in the embodiment of the present application can be applied to Figure 1 In the application scenario shown, the first chip and the second chip exchange data through the bus, the second chip sends debugging operation data to the first chip through the bus, the first chip receives the debugging operation data through the bus, verifies the debugging operation data, and performs data debugging according to the debugging operation data. The first chip can also send debugging data or debugging results or feedback data when verification fails to the second chip through the bus. During the data debugging process, the first chip needs to access data in its internal storage module.

[0033] An embodiment of the present application provides a debugging data processing method applied to a first chip, see Figure 2 and Figure 3 As shown, the debugging data processing method includes steps S11 to S14:

[0034] Step S11: receiving debugging operation data sent by the second chip.

[0035] Among them, see Figure 4 As shown, the debugging operation data includes first header information, debugging operation information and first verification information, and the first verification information is generated according to the first header information and the debugging operation information.

[0036] Among them, the first header information can be used to characterize the received data related to data debugging. The first chip can verify that the currently received data is data related to data debugging through the first header information. The first header information can be used to distinguish the current debugging operation data from other data that the first chip may receive.

[0037] The debugging operation information is used to perform data debugging operations.

[0038] Step S12: performing a first check on the debugging operation data according to the first header information.

[0039] Among them, the first header information can be used to determine whether the debugging operation data is data related to data debugging that can be used by the first chip. When the debugging operation data is data related to data debugging that can be used by the first chip, the first check passes; when the debugging operation data is not debugging related data that can be used by the first chip, the first check fails. The preset data debugging check information can be used to characterize that the sending object of the data is the first chip and is of the data debugging type. The received first header information can be compared with the preset data debugging check information. If the first header information matches the preset data debugging check information, it is determined that the debugging operation data is data related to data debugging and the first check passes; if the first header information does not match the preset data debugging check information, it is determined that the debugging operation data is not data related to data debugging and the first check fails.

[0040] Step S13: When the first verification passes, a second verification is performed on the debugging operation data according to the first verification information.

[0041] Among them, the first verification information is generated by the second chip based on the first header information and the debugging operation information when assembling the debugging operation data. During the second verification process, the first chip can use the same operation method as the second chip to calculate the received first header information and debugging operation information; if the operation result is consistent with the first verification information, the second verification passes; if the operation result is inconsistent with the first verification information, the second verification fails.

[0042] Step S14: When the second verification passes, data debugging is performed according to the debugging operation information.

[0043] Among them, data debugging corresponds to data operation instructions contained in debugging operation information. The debugging operation information may include data access instructions and / or data operation instructions. The debugging operation information may also include target data, which can be used for corresponding data access or for corresponding data operation.

[0044] Exemplarily, if the debugging operation information includes a data access instruction, the data debugging includes performing data access according to the data access instruction. If the debugging operation information includes a data operation instruction and target data, the data debugging includes performing operations on the target data according to the data operation instruction. If the debugging operation information includes a data access instruction and a data operation instruction, the data debugging includes performing data access according to the data access instruction to obtain the target data, and then performing operations on the target data obtained by the data access according to the data operation instruction.

[0045] In this embodiment, after receiving the debugging operation data, a first check is performed through its first header information to distinguish the debugging operation data from other data; a second check is performed through its first check information to ensure the accuracy of the debugging operation data; and data debugging is performed according to its debugging operation information; this is beneficial to simultaneously improve the accuracy and efficiency of data debugging.

[0046] As an implementation mode, the debugging operation information includes a data access instruction and a data access address; and data debugging includes accessing data according to the data access address and the data access instruction.

[0047] In step S14, data debugging is performed according to the debugging operation information, which specifically includes the following steps:

[0048] S141, generating a data access request according to the data access instruction and the data access address;

[0049] S142: Access data according to the data access request.

[0050] The data access address is a storage address of target data to be acquired or a write address of target data to be written, and the data access address includes multiple consecutive addresses. The data access request is a data read request or a data write request, which is used to read the target data of the data access address or write the target data to the data access address.

[0051] As an implementation manner, the debugging operation information includes a data read instruction and a first access address; and first target data of a storage module in a first chip needs to be read.

[0052] In step S14, data debugging is performed according to the debugging operation information, which specifically includes the following steps:

[0053] S21, generating a first data access request for first target data according to a data read instruction and a first access address.

[0054] The first access address is a storage address of the first target data, and the first access address includes a plurality of consecutive addresses. The first data access request is a data read request, which is used to read the first target data of the first access address.

[0055] S22: Acquire first target data from a storage module according to a first data access request.

[0056] The first chip obtains the first target data according to the first data access request, and needs to feed back the first target data to the second chip.

[0057] S23, generating second verification information according to the second header information and the first target data.

[0058] Among them, the second header information can be used to characterize that the data received is related to data debugging from the first chip. The second chip can verify through the second header information that the current data debugging feedback data is data related to data debugging. The second header information can be used to distinguish the current data debugging feedback data from other data that may be received by the second chip.

[0059] S24, generating a first data packet according to the second header information, the first target data, and the second verification information, and sending the first data packet to the second chip.

[0060] Among them, after receiving the first data packet, the second chip verifies the first data packet according to the second header information; after the second header information is verified, the first data packet is verified according to the second verification information; after the second verification information is verified, the first target data is parsed. Exemplarily, the second chip can compare the received second header information with the preset data debugging verification information. If the second header information matches the preset data debugging verification information, it is determined that the first data packet is data related to data debugging and the verification passes; if the second header information does not match the preset data debugging verification information, it is determined that the first data packet is not data related to data debugging and the verification fails. In the process of verifying according to the second verification information, the second chip can use the same operation method as when the first chip generates the second verification information to operate on the received second header information and the first target data; if the operation result is consistent with the second verification information, the verification passes; if the operation result is inconsistent with the second verification information, the verification fails.

[0061] As an implementation mode, the debugging operation information includes a data writing instruction, first target data, and a second access address; and the second target data needs to be written into a storage module of the first chip.

[0062] In step S14, data debugging is performed according to the debugging operation information, which specifically includes the following steps:

[0063] S31, generating a second data access request for second target data according to the data write instruction and the second access address.

[0064] The second access address is a write address of the second target data, and the second access address includes a plurality of continuous addresses.

[0065] S32, writing the second target data into the second access address according to the second data access request.

[0066] The second data access request is a data write request, which is used to write the second target data into the second access address of the storage module.

[0067] As an implementation mode, the debugging operation information includes data reading and operation instructions and a third access address; the third target data of the storage module in the first chip needs to be read and then the third target data needs to be operated.

[0068] In step S14, data debugging is performed according to the debugging operation information, which specifically includes the following steps:

[0069] S41, generating a third data access request for third target data according to the data read sub-instruction in the data read and operation instruction and the third access address.

[0070] The third access address is a storage address of the third target data, and the third access address includes a plurality of consecutive addresses. The third data access request is a data read request, which is used to read the third target data of the third access address.

[0071] S42: Acquire third target data from the storage module according to the third data access request.

[0072] S43, according to the data operation sub-instruction in the data reading and operation instruction, the third target data is operated to obtain the fourth target data.

[0073] S44, generating third verification information according to the second header information and the fourth target data.

[0074] Among them, the second header information can be used to characterize that the data received is related to data debugging from the first chip. The second chip can verify through the second header information that the current data debugging feedback data is data related to data debugging. The second header information can be used to distinguish the current data debugging feedback data from other data that may be received by the second chip.

[0075] S45, generating a second data packet according to the second header information, the fourth target data and the third verification information, and sending the second data packet to the second chip.

[0076] Among them, after receiving the second data packet, the second chip verifies the second data packet according to the second header information; after the second header information is verified, the second data packet is verified according to the third verification information; after the third verification information is verified, the fourth target data is parsed. Exemplarily, the second chip can compare the received second header information with the preset data debugging verification information. If the second header information matches the preset data debugging verification information, it is determined that the second data packet is data related to data debugging and the verification passes; if the second header information does not match the preset data debugging verification information, it is determined that the second data packet is not data related to data debugging and the verification fails. In the process of verifying according to the third verification information, the second chip can use the same operation method as the first chip when generating the third verification information to calculate the received second header information and the fourth target data; if the operation result is consistent with the third verification information, the verification passes; if the operation result is inconsistent with the third verification information, the verification fails.

[0077] As an implementation mode, the first header information includes a first magic check value and a first data type code value, and the preset data debugging check information includes a first preset magic value and a first preset code value. The first magic check value can be used to characterize the encoding format of data debugging data or to characterize the sending object of data debugging data, and the first preset magic value can be configured for the first chip. The first preset magic value can be used to uniquely characterize the encoding format that the first chip can parse or to uniquely characterize the first chip. The first chip can determine whether the received data is data that it can parse or whether it is data sent to itself according to the first magic check value; the first data type code value can be used to characterize the data type, divide the interactive data of the first chip into different data types, and match a unique preset identification code for each data type. For example, the data type can include but is not limited to data debugging class, control signal class, first peripheral interaction class and second peripheral interaction class. Among them, the preset identification code corresponding to the data debugging class is the first preset code value.

[0078] Step S12 specifically includes the following steps:

[0079] S121, extracting a first magic number check value and a first data type code value in the first header information;

[0080] S122: If the first magic number check value is the first preset magic value and the first data type code value is the first preset code value, the first check passes.

[0081] In this embodiment, the first magic number check value can be used to verify that the receiving object of the data debugging data is the first chip, and the first data type code value can be used to verify that the data type of the data debugging data is a data debugging type, which can avoid data transmission disorder caused by the first chip receiving data sent by other electronic devices or other types of data during the upgrade process.

[0082] In some implementations, the first magic check value in the first header information may be first extracted; if the first magic check value is a first preset magic value, the first data type code value in the first header information is extracted; if the first data type code value is a first preset code value, the first verification passes. In this implementation, the first magic check value is first extracted and verified, and when the first magic check value is not the first preset magic value, the data debugging data is stopped from being received, which is conducive to improving data processing efficiency.

[0083] As an implementation manner, step S13 specifically includes the following steps:

[0084] S131, performing calculation on the first header information and the debugging operation information according to a first preset algorithm to obtain first calculation data;

[0085] S132: If the first verification information matches the first operation data, the second verification passes.

[0086] The first verification information is obtained by the second chip calculating the first header information and the debugging operation information according to the first preset algorithm. If the debugging operation data is not wrong during the packaging and / or transmission process, the first verification information is consistent with the first operation data, and the second verification passes. If the first verification information is inconsistent with the first operation data, the second verification fails.

[0087] In this implementation, a second check is performed on each debugging operation data to ensure that there is no error in the debugging operation data during transmission, which is beneficial to improving the accuracy of the data.

[0088] Exemplarily, the first preset algorithm may be a CRC algorithm (Cyclic Redundancy Check), which is a fast algorithm that generates a short fixed-bit check code based on data such as a data packet or a file, and is mainly used to detect or check errors that may occur after data transmission or storage. The CRC algorithm is used to generate the first check information and the first operation data, with only two bytes of redundant code, which improves accuracy without affecting transmission time.

[0089] In some implementations, in step S23, the second header information and the first target data are operated on according to a first preset algorithm to obtain second verification information.

[0090] In some implementations, in step S44, the second header information and the fourth target data are operated according to a first preset algorithm to obtain third verification information.

[0091] As an implementation manner, the debugging data processing method of this embodiment further includes the following steps:

[0092] S51, if the first verification or the second verification of the debugging operation data fails, corresponding data verification error information is generated.

[0093] S52, generating fourth verification information according to the second header information and the data verification error information, and sending a third data packet to the second chip, wherein the third data packet includes the second header information, the data verification error information and the fourth verification information.

[0094] The fourth verification information is generated according to the second header information and the data verification error information, the second header information, the data verification error information and the fourth verification information are assembled to form a third data packet, and the third data packet is sent to the second chip.

[0095] In this embodiment, after receiving the third data packet, the second chip regenerates and sends the current debugging operation data. For the debugging operation data, if the first check or the second check fails, the first chip re-requests the debugging operation data, which is conducive to improving the accuracy and efficiency of data debugging.

[0096] In some implementations, step S52 further includes the following steps:

[0097] S53, if the debugging operation data fails to pass the verification for a preset number of consecutive times, a prompt message is generated, and the display module is controlled to display the prompt message.

[0098] In this embodiment, if the debugging operation data is checked for errors for multiple consecutive times, a pop-up window reminder is displayed, which is beneficial to improving the accuracy and efficiency of data debugging. Exemplarily, the preset number of times may be three or five times.

[0099] As an implementation manner, the debugging data processing method of this embodiment further includes the following steps before step S11:

[0100] S61, receiving first processed data sent by the second chip, wherein the first processed data includes first header information, a model acquisition instruction and fifth verification information, and the fifth verification information is generated according to the first header information and the model acquisition instruction.

[0101] The first processed data includes a model acquisition instruction for acquiring model information of the first chip.

[0102] The second chip calculates the first header information and the model acquisition instruction according to the first preset algorithm to obtain the fifth verification information.

[0103] S62: Perform a first check on the first processed data according to the first header information.

[0104] The received first header information can be compared with the preset data debugging verification information. If the first header information matches the preset data debugging verification information, it is determined that the first processed data is data related to data debugging, and the first verification passes; if the first header information does not match the preset data debugging verification information, it is determined that the first processed data is not data related to data debugging, and the first verification fails. Further, the first header information can include a first magic number check value and a first data type code value. The verification method is described in step S121 and step S122, and will not be described one by one here.

[0105] S63: When the first verification passes, perform a second verification on the first processed data according to the fifth verification information.

[0106] Among them, the first header information and the model acquisition instruction are calculated according to the first preset algorithm to obtain the calculation data; if the fifth verification information matches the obtained calculation data, the second verification is passed.

[0107] S64, when the second verification passes, generate a fourth data packet according to the model information, and send the fourth data packet to the second chip.

[0108] The verification information may be generated according to the second header information and the model information. A fourth data packet is generated according to the second header information, the model information and the generated verification information, and the fourth data packet is sent to the second chip.

[0109] In this embodiment, before sending the debugging operation data, the second chip first obtains the model information of the first chip, and matches the obtained model information with the first chip model pre-stored in the second chip. If the two are consistent, the model is correct and the debugging operation data can continue to be sent to the first chip; if the two are inconsistent, the model is wrong, indicating that the first chip is abnormal.

[0110] In some implementations, the debugging data processing method of this embodiment further includes the following steps: if the first processing data fails the first verification or the second verification, a corresponding data verification error message is generated. Corresponding verification information is generated according to the second header information and the data verification error message, the second header information, the data verification error message and the corresponding verification information are assembled to form a first error feedback data packet, and the first error feedback data packet is sent to the second chip. For details of this implementation, please refer to the description of step S51 and step S52.

[0111] In some implementations, the debugging data processing method of this embodiment further includes the following steps: if the first processing data fails to pass the verification for a preset number of consecutive times, a prompt message is generated, and the display module is controlled to display the prompt message. For details of this implementation, please refer to the description of step S53.

[0112] As an implementation manner, the debugging data processing method of this embodiment further includes the following steps before step S11:

[0113] S71, receiving second processed data sent by the second chip, wherein the second processed data includes first header information, a status acquisition instruction and sixth verification information, and the sixth verification information is generated according to the first header information and the status acquisition instruction.

[0114] The second processing data includes a state acquisition instruction for acquiring state information of the first chip. Exemplarily, the state information may be idle or non-idle. Idle means that the first chip is not currently executing a task, and non-idle means that the first chip is currently executing a task.

[0115] The second chip calculates the first header information and the status acquisition instruction according to the first preset algorithm to obtain the sixth verification information.

[0116] S72, performing a first check on the second processed data according to the first header information.

[0117] For details of step S72, please refer to the description of step S62.

[0118] S73, when the first verification passes, performing a second verification on the second processed data according to the sixth verification information.

[0119] The first header information and the state acquisition instruction are operated according to a first preset algorithm to obtain operation data; if the sixth verification information matches the obtained operation data, the second verification is passed.

[0120] S74, when the second check passes, generate a fifth data packet according to the state information, and send the fifth data packet to the second chip.

[0121] The verification information may be generated according to the second header information and the state information. A fifth data packet is generated according to the second header information, the state information and the generated verification information, and the fifth data packet is sent to the second chip.

[0122] In this embodiment, before sending the debugging operation data, the second chip first obtains the status information of the first chip. If the status information of the first chip is idle, the second chip continues to send the debugging operation data to the first chip; if the status information of the first chip is not idle, the second processing data continues to be sent to the first chip until the status information of the first chip is idle.

[0123] In some implementations, the debugging data processing method of this embodiment further includes the following steps: if the second processing data fails the first verification or the second verification, a corresponding data verification error message is generated. Corresponding verification information is generated according to the second header information and the data verification error message, the second header information, the data verification error message and the corresponding verification information are assembled to form a second error feedback data packet, and the second error feedback data packet is sent to the second chip. For details of this implementation, please refer to the description of step S51 and step S52.

[0124] In some implementations, the debugging data processing method of this embodiment further includes the following steps: if the second processing data fails to pass the verification for a preset number of consecutive times, a prompt message is generated, and the display module is controlled to display the prompt message. For details of this implementation, please refer to the description of step S53.

[0125] As an implementation method, the first chip and the second chip communicate through a human-computer interaction protocol based on I2C communication (Human Interface Device over Inter-Integrated Circuit, HID over I2C) protocol. The human-computer interaction protocol based on I2C communication extends the HID (Human Interface Device) protocol to I2C (Inter-Integrated Circuit) and combines the I2C protocol and the HID protocol to achieve communication between the first chip and the second chip.

[0126] In this embodiment, the second chip sends the debugging operation data, the first processing data or the second processing data to the first chip through the bus according to the human-computer interaction protocol based on I2C communication, and the first chip sends the feedback data to the second chip through the bus according to the human-computer interaction protocol based on I2C communication, thereby improving the communication rate.

[0127] In some embodiments, see Figure 5 As shown, the first chip may be an EC chip, and the second chip may be a SOC (System on Chip) chip. The EC chip and the SOC chip are arranged in the same electronic device, and the SOC chip is the main control chip of the electronic device. In this embodiment, the EC chip is debugged by the SOC chip, which is conducive to improving the efficiency of data debugging.

[0128] In some implementations, the storage module of the first chip is a memory or a register.

[0129] In some embodiments, see Figure 5As shown, the first chip may be an EC chip, and the second chip may be a SOC (System on Chip) chip. The EC chip and the SOC chip are arranged in the same electronic device, the SOC chip is the main control chip of the electronic device, the storage module may be the memory or register of the first chip, and the data debugging process may involve data access to the storage module. In this embodiment, data debugging of the EC chip is performed through the SOC chip, which is conducive to improving the efficiency of data debugging. Exemplarily, the SOC chip executes the upper computer program, and the EC chip executes the lower computer program to complete data debugging.

[0130] An embodiment of the present application provides a chip 300, see Figure 6 As shown, the chip 300 is used to implement the above-mentioned debugging data processing method, and the chip 300 includes a debugging data processing program for implementing the above-mentioned debugging data processing method. A chip (Integrated Circuit, IC) is also called a chip, and the chip can be, but is not limited to, a SOC (System on Chip, chip-level system) chip, a SIP (system in package, system-level packaging) chip, or an EC chip.

[0131] The chip 300 includes a processing module 31 , a storage module 32 and instructions. The storage module 32 is coupled to the processing module 31 . The instructions are stored in the storage module 32 and can be executed by the processing module 31 to implement the above-mentioned debugging data processing method.

[0132] The processing module 31 can be a general-purpose processor, a digital signal processor (DSP), an application-specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, discrete hardware components. The general-purpose processor can be a microprocessor or the processor can also be any conventional processor, etc.

[0133] The storage module 32 may be non-volatile or volatile. The instruction may be a program instruction, and the program instruction may be stored in the storage module 32 in the form of a software product. For example, the storage module 32 may include: a read-only memory (ROM) or a random access memory (RAM) or other media that can store program codes.

[0134] After receiving the debugging operation data, the chip of this embodiment performs a first check through its first header information to distinguish the debugging operation data from other data; performs a second check through its first check information to ensure the accuracy of the debugging operation data; and performs data debugging according to its debugging operation information; which is beneficial to simultaneously improve the accuracy and efficiency of data debugging.

[0135] The present application embodiment also provides an electronic device 400, see Figure 7 As shown, the electronic device 400 includes a device body and a chip 300 as described above, which is arranged in the device body. The electronic device can be, but is not limited to, a weight scale, a body fat scale, a nutrition scale, a pulse oximeter, a human body composition analyzer, a display, a USB (Universal Serial Bus) docking station, a car, a smart wearable device, a mobile terminal, and a smart home device. Smart wearable devices include, but are not limited to, smart watches, smart bracelets, and cervical massagers. Mobile terminals include, but are not limited to, smart phones, laptops, tablet computers, and POS (point of sales terminal). Smart home devices include, but are not limited to, smart sockets, smart rice cookers, smart sweepers, and smart lights.

[0136] The electronic device of this embodiment, after receiving the debugging operation data, performs a first check through its first header information to distinguish the debugging operation data from other data; performs a second check through its first check information to ensure the accuracy of the debugging operation data; and performs data debugging according to its debugging operation information; which is beneficial to simultaneously improve the accuracy and efficiency of data debugging.

[0137] The above is only an implementation method of the present application. It should be pointed out that a person skilled in the art can make improvements without departing from the inventive concept of the present application, but these improvements are within the scope of protection of the present application.

Claims

1. A debugging data processing method, characterized in that: Applied to the first chip, the debugging data processing method includes: receiving debugging operation data sent by the second chip, wherein the debugging operation data includes first header information, debugging operation information and first verification information, and the first verification information is generated according to the first header information and the debugging operation information; Performing a first check on the debugging operation data according to the first header information; When the first verification passes, performing a second verification on the debugging operation data according to the first verification information; When the second verification passes, data debugging is performed according to the debugging operation information.

2. The debugging data processing method according to claim 1, characterized in that: The debugging operation information includes a data access instruction and a data access address; The performing data debugging according to the debugging operation information includes: Generate a data access request according to the data access instruction and the data access address; Data access is performed according to the data access request.

3. The debugging data processing method according to claim 2, characterized in that: The debugging operation information includes a data read instruction and a first access address; The performing data debugging according to the debugging operation information includes: generating a first data access request for first target data according to the data read instruction and the first access address; Acquire the first target data from a storage module according to the first data access request; generating second verification information according to the second header information and the first target data; A first data packet is generated according to the second header information, the first target data, and the second verification information, and the first data packet is sent to the second chip.

4. The debugging data processing method according to claim 2, characterized in that: The debugging operation information includes a data write instruction, second target data and a second access address; The performing data debugging according to the debugging operation information includes: generating a second data access request for the second target data according to the data write instruction and the second access address; According to the second data access request, the second target data is written into the second access address.

5. The debugging data processing method according to claim 2, characterized in that: The debugging operation information includes data reading and operation instructions and a third access address; The performing data debugging according to the debugging operation information includes: Generate a third data access request for third target data according to the data read sub-instruction in the data read and operation instruction and the third access address; Acquire the third target data from the storage module according to the third data access request; According to the data operation sub-instruction in the data reading and operation instruction, the third target data is operated to obtain fourth target data; Generate third verification information according to the second header information and the fourth target data; A second data packet is generated according to the second header information, the fourth target data, and the third verification information, and the second data packet is sent to the second chip.

6. The debugging data processing method according to claim 1, characterized in that: The first header information includes a first magic number check value and a first data type code value; The performing a first check on the debugging operation data according to the first header information includes: Extracting a first magic number check value and a first data type code value from the first header information; If the first magic check value is a first preset magic value and the first data type code value is a first preset code value, the first check passes.

7. The debugging data processing method according to claim 1, characterized in that: The performing a second verification on the debugging operation data according to the first verification information includes: Performing calculation on the first header information and the debugging operation information according to a first preset algorithm to obtain first calculation data; If the first verification information matches the first operation data, the second verification passes.

8. The debugging data processing method according to claim 1, characterized in that: The debugging data processing method also includes: If the first check or the second check of the debugging operation data fails, generating corresponding data check error information; Generate fourth verification information according to the second header information and the data verification error information, and send the third data packet to the second chip, wherein the third data packet includes the second header information, the data verification error information and the fourth verification information.

9. The debugging data processing method according to claim 8, characterized in that: The debugging data processing method also includes: If the debugging operation data fails to pass the verification for a preset number of consecutive times, a prompt message is generated and the display module is controlled to display the prompt message.

10. The debugging data processing method according to claim 1, characterized in that: Before receiving the debugging operation data sent by the second chip, the method further includes: receiving first processed data sent by the second chip, wherein the first processed data includes the first header information, a model acquisition instruction, and fifth verification information, and the fifth verification information is generated according to the first header information and the model acquisition instruction; performing a first check on the first processed data according to the first header information; When the first verification passes, performing a second verification on the first processed data according to the fifth verification information; When the second check passes, a fourth data packet is generated according to the model information, and the fourth data packet is sent to the second chip.

11. The debugging data processing method according to claim 1 or 10, characterized in that: Before receiving the debugging operation data sent by the second chip, the method further includes: receiving second processed data sent by the second chip, wherein the second processed data includes the first header information, a status acquisition instruction, and sixth verification information, and the sixth verification information is generated according to the first header information and the status acquisition instruction; performing a first check on the second processed data according to the first header information; When the first verification passes, performing a second verification on the second processed data according to the sixth verification information; When the second check passes, a fifth data packet is generated according to the state information, and the fifth data packet is sent to the second chip.

12. The debugging data processing method according to claim 1, characterized in that: The first chip is an EC chip, and the second chip is a SOC chip.

13. A chip, characterized in that: include: Processing module; a storage module coupled to the processing module; and, instructions, which are stored in the storage module and can be executed by the processing module to implement the debugging data processing method according to any one of claims 1 to 12.

14. An electronic device, characterized in that: Comprising the chip as claimed in claim 13.

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