Method and device for obtaining and processing error address information

Abstract

Embodiments of the present disclosure disclose a method and device for obtaining and processing error address information. In response to a data reading operation detected by a user interface, target test data of a target test object is read, where the target test data is error address test data corresponding to a specified address range in the error address test data of the target test object; based on the target test data, a first type of view is displayed within a view window of the user interface, and the first type of view is used to indicate test result information of different addresses within the specified address range; in response to a view switching operation detected by the user interface, based on the target test data, a second type of view is displayed within the view window of the user interface, and the second type of view is used to indicate the location distribution information of the error addresses within the specified address range on the target test object. Embodiments of the present disclosure are beneficial to improving the efficiency of obtaining and analyzing error address information of a target test object.

Description

Technical Field

[0001] The present disclosure relates to chip testing technology, and in particular to a method and device for obtaining and processing error address information. Background Art

[0002] With the development of electronic technology, the speed of replacement of electronic devices is getting faster and faster. At the same time, the demand for storage chips is also increasing, and higher requirements are put forward for the storage space of storage chips. The design complexity of chips is getting higher and higher, and the requirements for testing equipment of storage chips are also getting higher. At present, the testing of storage chips not only requires input and output testing of conventional digital chips, but also needs to test the storage addresses in the internal space of the storage chips to detect whether there are damaged error address bits in the storage space, so as to facilitate the repair of damaged storage addresses in the later stage and the analysis of the reasons for the failure of chip storage addresses. Summary of the Invention

[0003] The embodiments of the present disclosure provide a method and device for obtaining and processing error address information, which is beneficial to improving the efficiency of obtaining and analyzing error address information of a target test object.

[0004] One aspect of the embodiments of the present disclosure provides a method for obtaining and processing error address information, including:

[0005] In response to detecting a data reading operation on a user interface, reading target test data of a target test object, where the target test data is error address test data corresponding to a specified address range in the error address test data of the target test object;

[0006] Based on the target test data, displaying a first type of view in a view window of the user interface, where the first type of view is used to indicate test result information of different addresses within the specified address range;

[0007] In response to detecting a view switching operation on the user interface, based on the target test data, displaying a second type of view in the view window of the user interface, where the second type of view is used to indicate the position distribution information of error addresses within the specified address range on the target test object.

[0008] Another aspect of the embodiments of the present disclosure provides an electronic device, including:

[0009] A memory for storing a computer program;

[0010] A processor for executing the computer program stored in the memory, and when the computer program is executed, implementing the method for obtaining and processing error address information according to any one of the above embodiments of the present disclosure.

[0011] Another aspect of the embodiments of the present disclosure provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the method for obtaining and processing error address information described in any of the above embodiments of the present disclosure is implemented.

[0012] Another aspect of the embodiments of the present disclosure provides a computer program product, including a computer program. When the computer program is executed by a processor, the method for obtaining and processing error address information described in any of the above embodiments of the present disclosure is implemented.

[0013] In the embodiments of the present disclosure, in response to detecting a data reading operation on the user interface, the target test data within a specified address range corresponding to the target test object is read. Based on the target test data, a first type of view is displayed within the view window of the user interface. The user can also perform view switching through the user interface. In response to detecting a view switching operation on the user interface, the view within the view window can be switched to a second type of view. That is, the user can select different types of views within the user interface to display the error address information corresponding to the target test data, and can respectively select to view the first type of view for indicating the test results of each address within the specified address range, and the second type of view for indicating the actual position distribution of the error addresses within the specified address range on the target test object, which facilitates the user to analyze the error address information of the target test object through different types of views. By providing different types of views, the user can intuitively view various error address information, improve the information acquisition efficiency, and is conducive to the subsequent rapid positioning of the error addresses of the target test object and the rapid analysis of the error causes.

[0014] The technical solutions of the present disclosure will be further described in detail below through the accompanying drawings and embodiments. Description of the Drawings

[0015] The drawings forming a part of the specification depict embodiments of the present disclosure and, together with the description, are used to explain the principles of the present disclosure.

[0016] Referring to the accompanying drawings, the present disclosure can be more clearly understood according to the following detailed description, where:

[0017] Figure 1 is a schematic structural diagram of a test device provided for an exemplary embodiment of the present disclosure;

[0018] Figure 2 is a flowchart of a method for obtaining and processing error address information provided for an exemplary embodiment of the present disclosure;

[0019] Figure 3 is a schematic interface diagram of a first view window provided for an exemplary embodiment of the present disclosure;

[0020] Figure 4Schematic diagram of the interface of the second view window provided by an exemplary embodiment of the present disclosure;

[0021] Figure 5 Schematic diagram of the interface of the second view window provided by another exemplary embodiment of the present disclosure;

[0022] Figure 6 Flowchart showing the process of displaying a first type of view provided by an exemplary embodiment of the present disclosure;

[0023] Figure 7 Flowchart showing the process of layer superposition of a logical matrix bitmap provided by an exemplary embodiment of the present disclosure;

[0024] Figure 8 Schematic diagram of the interface of a physical matrix view provided by an exemplary embodiment of the present disclosure;

[0025] Figure 9 Flowchart showing the process of layer superposition of a physical matrix bitmap provided by an exemplary embodiment of the present disclosure;

[0026] Figure 10 Schematic diagram of the structure of an acquisition processing device for error address information provided by an exemplary embodiment of the present disclosure;

[0027] Figure 11 Schematic diagram of the structure of an electronic device provided by an exemplary embodiment of the present disclosure. Detailed implementation manners

[0028] Now, various exemplary embodiments of the present disclosure will be described in detail with reference to the accompanying drawings. It should be noted that: Unless otherwise specifically stated, the relative arrangements, numerical expressions, and numerical values of the components and steps described in these embodiments do not limit the scope of the present disclosure.

[0029] Those skilled in the art can understand that the terms "first", "second", etc. in the embodiments of the present disclosure are only used to distinguish different steps, devices, or modules, etc., and neither represent any specific technical meaning nor indicate an inevitable logical order between them.

[0030] It should also be understood that in the embodiments of the present disclosure, "a plurality" may refer to two or more, and "at least one" may refer to one, two, or more.

[0031] It should also be understood that for any component, data, or structure mentioned in the embodiments of the present disclosure, unless clearly defined or otherwise indicated by the context, it can generally be understood as one or more.

[0032] In addition, the term "and / or" in the present disclosure is merely a description of the association relationship of associated objects, indicating that three relationships may exist. For example, A and / or B may represent three situations: A exists alone, A and B exist simultaneously, and B exists alone. In addition, the character " / " in the present disclosure generally represents an "or" relationship between the associated objects before and after.

[0033] It should also be understood that the descriptions of the various embodiments in the present disclosure emphasize the differences between the various embodiments, and their similarities can be referred to each other. For the sake of brevity, they will not be elaborated one by one.

[0034] Meanwhile, it should be understood that, for the convenience of description, the dimensions of the various parts shown in the drawings are not drawn in actual proportional relationship.

[0035] The following description of at least one exemplary embodiment is actually merely illustrative and in no way a limitation on the present disclosure and its application or use.

[0036] Techniques, methods, and devices known to those of ordinary skill in the relevant art may not be discussed in detail, but where appropriate, the techniques, methods, and devices should be regarded as part of the specification.

[0037] It should be noted that like reference numerals and letters denote like items in the following figures, and thus, once an item is defined in one figure, further discussion thereof is not required in subsequent figures.

[0038] Embodiments of the present disclosure can be applied to electronic devices such as terminal devices, computer systems, servers, etc., which can operate with many other general-purpose or special-purpose computing system environments or configurations. Examples of well-known terminal devices, computing systems, environments, and / or configurations suitable for use with electronic devices such as terminal devices, computer systems, servers, etc. include, but are not limited to: personal computer systems, server computer systems, thin clients, thick clients, handheld or laptop devices, microprocessor-based systems, set-top boxes, programmable consumer electronics, network personal computers, small computer systems, large computer systems, and distributed cloud computing technology environments including any of the above systems, and so on.

[0039] Electronic devices such as terminal devices, computer systems, and servers can be described in the general context of computer system-executable instructions (such as program modules) executed by a computer system. Generally, program modules can include routines, programs, target programs, components, logics, data structures, etc., which perform specific tasks or implement specific abstract data types. The computer system / server can be implemented in a distributed cloud computing environment where tasks are executed by remote processing devices linked through a communication network. In a distributed cloud computing environment, program modules can be located on local or remote computing system storage media including storage devices.

[0040] In an embodiment of the present disclosure, a method for obtaining and processing error address information is provided, which is used to display the error address information indicated by the error address test data obtained by a test device testing the storage space of a target test object on a user interface in different types of views, so that users can quickly view and analyze the error address information of the storage space of the target test object through different types of views.

[0041] The method for obtaining and processing error address information provided in an embodiment of the present disclosure can be used for the host computer of a test device, specifically for the device for obtaining and processing error address information in the host computer. The test device can be used to perform semiconductor tests on a device under test (DUT), where the DUT can include wafers, chips, etc. In the present disclosure, the device under test is also referred to as the target test object. As Figure 1 shown, the test device includes a host computer 10 and a target slave computer 20.

[0042] An apparatus 101 for obtaining and processing error address information runs in the host computer 10. The apparatus 101 for obtaining and processing error address information is used to read the error address test data of the target test object from the target slave computer 20 and display the error address information corresponding to the obtained error address test data on the user interface in different types of views. The target slave computer 20 is used to execute the test process of the target test object, perform an error address test on the target test object, and store the obtained error address test data. When the host computer 10 issues a data reading request to the target slave computer 20, the target slave computer 20 can provide the corresponding error address test data to the host computer 10 according to the data reading request.

[0043] Figure 2 FIG. is a flowchart of a method for obtaining and processing error address information provided for an exemplary embodiment of the present disclosure. This method is used for the host computer 10 of the test device as described above, specifically for the apparatus 101 for obtaining and processing error address information of the host computer 10. As Figure 2 shown, the method of this embodiment includes:

[0044] Step 210: In response to the user interface detecting a data reading operation, read the target test data of the target test object, where the target test data is the error address test data corresponding to the specified address range in the error address test data of the target test object.

[0045] The user interface is an interface that can be interacted with by the user in the acquisition and processing device of error address information. The user interface is used to display the error address information corresponding to the read error address test data.

[0046] In a possible implementation manner, a trigger control for triggering a data reading request is provided in the user interface. The user interface determines that a data reading operation is detected in response to a trigger operation on the trigger control. When the upper computer detects a data reading operation on the user interface, it reads the target test data of the target test object.

[0047] In a possible implementation manner, the user can perform parameter configuration in the user interface to configure parameters for reading the error address test data corresponding to the specified address range. After detecting a data reading operation, a data reading request can be generated according to the configured parameters. The data reading request includes the configured specified address range. The upper computer sends the data reading request to the target lower computer, and the target lower computer provides the error address test data corresponding to the specified address range to the upper computer.

[0048] Optionally, the target lower computer can perform error address testing on multiple target test objects and stores the error address test data corresponding to the multiple target test objects. In one example, the target lower computer stores the error address test data of the specified address range corresponding to multiple target test objects. In response to the user interface detecting a data reading operation, it reads the target test data of the multiple target test objects.

[0049] Step 220: Based on the target test data, display a first type of view in the view window of the user interface. The first type of view is used to indicate the test result information of different addresses within the specified address range.

[0050] In a possible implementation manner, the first type of view is a view generated based on the error address test data corresponding to the logical address of the target test object. The indicated error address information is the error address information corresponding to the logical address of the target test object. The target lower computer stores the error address test data corresponding to the logical address of the target test object.

[0051] Optionally, the first type of view includes a view for indicating the test results corresponding to all logical addresses included in the specified address range, or a view for indicating the test results of partial logical addresses within the specified address range.

[0052] In a possible implementation, for the above-mentioned multiple target test objects, the first type of view may include a view for displaying the test results corresponding to the specified address range of the multiple target test objects.

[0053] Step 230, in response to the user interface detecting a view switching operation, based on the target test data, display a second type of view within the view window of the user interface, where the second type of view is used to indicate the location distribution information of the error addresses in the specified address range on the target test object.

[0054] The user interface also provides a view switching control for switching views. In response to detecting a triggering operation on the view switching control, the user interface determines that a view switching operation has been detected and can switch the first type of view displayed within the view window to the second type of view.

[0055] In a possible implementation, the second type of view is a view generated based on the error address data corresponding to the physical address of the target test object, and is used to indicate the actual physical location distribution of the error addresses in the specified address range of the target test object.

[0056] In a possible implementation, after the host computer obtains the target test data, it can convert the logical address corresponding to the target test data to obtain the error address data corresponding to the physical address. In another possible implementation, the slave computer can also convert the target test data, and the host computer reads the error address data corresponding to the converted physical address from the slave computer and generates the second type of view based on the error address data corresponding to the physical address.

[0057] In the embodiments of the present disclosure, in response to the user interface detecting a data reading operation, read the target test data corresponding to the specified address range of the target test object, and based on the target test data, display a first type of view within the view window of the user interface. The user can also perform view switching through the user interface. In response to the user interface detecting a view switching operation, the view within the view window can be switched to the second type of view, that is, the user can select different types of views within the user interface to display the error address information corresponding to the target test data, and can respectively select to view the first type of view for indicating the test results of different addresses within the specified address range and the second type of view for indicating the actual location distribution of each error address in the specified address range on the target test object, which is convenient for the user to analyze the error address information of the target test object through different types of views. By providing different types of views, the user can intuitively view various error address information, which is beneficial to the subsequent rapid positioning of the error addresses of the target test object and the rapid analysis of the error causes.

[0058] Optionally, the first type of view includes at least one of a test status view, a logical matrix bitmap, and an error address list.

[0059] The test status view is used to indicate the test status information of a specified address range. The test status includes a Pass / Fail status, where the Pass status indicates that the address test is passed, and the Fail status indicates that the address test is not passed and also indicates that the tested address is an error address. The test status view can represent the overall test result corresponding to the specified address range. When the target test data indicates that there is no address test result with a Fail status among all the address test results in the specified address range, the test status indicated by the test status view is the Pass status. When the target test data indicates that there is an address test result with a Fail status among all the address test results in the specified address range, the test status indicated by the test status view is the Fail status.

[0060] In a possible implementation manner, in response to a viewing request for the test status view, the test status view corresponding to the target test data is displayed in the first view window of the user interface.

[0061] A status view viewing control for viewing the test status view can be provided in the user interface. In a possible implementation manner, in response to a triggering operation on the status view viewing control, it is determined that a viewing request for the test status view is received, and the test status view corresponding to the target test data is displayed in the first view window of the user interface. Optionally, the test status view includes an object identifier characterizing the target test object, and the identifier display form can be determined according to the target test data of the target test object. When the target test data indicates that the test status of the target test object corresponding to the specified address range is the Pass status, the identifier display form of the object identifier is the first display form. When the target test data indicates that the test status of the target test object corresponding to the specified address range is the Fail status, the identifier display form of the object identifier is the second display form, and the first display form is different from the second display form, which can specifically include at least one of different identifier colors, different identifier shapes, and different identifier corresponding markings.

[0062] Optionally, the target test object includes multiple digital input / output pins (DQpins), and the target test data includes test data corresponding to the specified address ranges of each digital input / output pin. Each digital input / output pin has the same logical address range. When reading the error address test data of the specified address range corresponding to the target test object from the lower computer, the error address test data of the specified address ranges of each of the multiple digital input / output pins included in the target test object can be read. When displaying the test status view corresponding to the target test data in the first view window of the user interface, a test status view for indicating the test status of each digital input / output pin can be displayed in the first view window of the user interface. The test status of each digital input / output pin can be determined according to the test data corresponding to the specified address range of each digital input / output pin. In one example, when the test data of the specified address range corresponding to a digital input / output pin indicates that there is an address with a Fail status in the specified address range corresponding to this digital input / output pin, it is determined that the test status of this digital input / output pin is the Fail status. When the test data of the specified address range corresponding to this digital input / output pin indicates that there is no address with a Fail status (i.e., all are Pass statuses) in the specified address range corresponding to this digital input / output pin, it is determined that the test status of this digital input / output pin is the Pass status. When the test statuses of all the digital input / output pins included in a target test object are Pass statuses, the test status of the target test object is the Pass status. When there is a pin with a Fail status among the digital input / output pins of the target test object, the test status of the target test object is the Fail status. In one possible implementation manner, the pin identifier corresponding to each digital input / output pin is displayed in the test status view, and the display form of each pin identifier can be determined according to the test status of the corresponding digital input / output pin. In one example, when all the address test results of the specified address range of a digital input / output pin are in the Pass status, the display form of the pin identifier is the first display form. When all the address test results of the specified address range of a digital input / output pin are in the Fail status, the display form of the pin identifier is the second display form.

[0063] In one possible implementation manner, the object identifier for indicating the test status of the target test object and the pin identifier for indicating the test status of each digital input / output pin included in this target test object can be displayed in the test status view simultaneously.

[0064] In a possible implementation, when reading the target test data of multiple target test objects, the object identifiers corresponding to the multiple target test objects can be displayed in the test status view. In response to a selection operation on an object identifier, the multiple pin identifiers corresponding to the multiple digital input / output pins included in the target test object corresponding to the object identifier can be displayed in the test status view. Schematically, as Figure 3 shown, the object identifiers corresponding to test objects 201, 202, 203, and 204 are displayed in the test status view, which are respectively used to indicate the test status of test objects 201, 202, 203, and 204. The pin identifiers of the multiple digital input / output pins included in test object 201 (including the pin identifiers of DQL0 - DQL7 and the pin identifiers of DQU0 - DQU7) can also be selectively displayed to respectively indicate the test status of different digital input / output pins in test object 201.

[0065] The logic matrix bitmap is a two-dimensional matrix bitmap used to indicate the test results corresponding to different addresses within a specified address range. In a possible implementation, in response to a viewing request for the logic matrix bitmap, the logic matrix bitmap corresponding to the target test data is displayed in the second view window of the user interface. A matrix bitmap viewing control for viewing the logic matrix bitmap can be provided in the user interface. In a possible implementation, in response to a trigger operation on the matrix bitmap viewing control, it is determined that a viewing request for the logic matrix bitmap is received, and the logic matrix bitmap corresponding to the target test data is displayed in the second view window of the user interface.

[0066] Optionally, logic matrix bitmaps corresponding to each digital input / output pin are generated according to the test data of each digital input / output pin. The logic matrix bitmap corresponding to the target test object includes the logic matrix bitmaps corresponding to each digital input / output pin. Different matrix units in the logic matrix bitmap correspond to different logical addresses. The display state of the corresponding matrix unit can be determined according to the test result corresponding to the logical address. The display state of the matrix unit corresponding to the logical address with a test result of Pass is different from the display state of the matrix unit corresponding to the logical address with a test result of Fail. Exemplarily, different test results can be indicated by matrix units of different colors.

[0067] Optionally, the logical matrix bitmap includes at least one of a thumbnail logical matrix bitmap and a detailed logical matrix bitmap. A matrix unit in the thumbnail logical matrix bitmap corresponds to a logical address range, and a matrix unit in the detailed logical matrix bitmap corresponds to a logical address. In one possible implementation, the thumbnail logical matrix bitmap corresponding to each digital input / output pin can be displayed in the second view window, and / or, in response to a selection operation on a target pin, the detailed logical matrix bitmap corresponding to the target pin can be displayed in the second view window. That is, the thumbnail matrix bitmaps corresponding to all digital input / output pins can be displayed in the second view window to quickly view the test results of the specified address ranges of each digital input / output pin, and the detailed logical matrix bitmap of a selected digital input / output pin can also be displayed in the second view window to view the detailed test results of each logical address in the specified address range.

[0068] In one possible implementation, in response to a viewing request for the logical matrix view, first display the thumbnail logical matrix bitmap corresponding to each digital input / output pin in the second view window. In response to a selection operation on the thumbnail logical matrix bitmap corresponding to a digital input / output pin, determine the digital input / output pin corresponding to the selected thumbnail logical matrix bitmap as the target pin, that is, determine that a selection operation on the target pin has been received, and display the detailed logical matrix bitmap corresponding to the target pin in the second view window. Schematically, as Figure 4 shown, display the thumbnail logical matrix bitmaps corresponding to each digital input / output pin of the test object 201 in the second view window. When a selection operation on DQL0 among them is received, as Figure 5 shown, display the detailed logical matrix bitmap corresponding to the pin DQL0 of the test object 201 in the second view window.

[0069] In one possible implementation, the detailed logical matrix bitmap and the thumbnail logical matrix bitmap corresponding to the target pin can be displayed in the second view window simultaneously. Optionally, display the detailed logical matrix bitmap corresponding to the target pin in the first area of the second view window, and display the thumbnail logical matrix bitmap corresponding to the target pin in the second area of the second view window, where the area of the first area is larger than the area of the second area.

[0070] In one example, the detailed logical matrix bitmap in the first region corresponds to the selected matrix bitmap region of the thumbnail logical matrix bitmap in the second region. In response to an address range selection operation on the thumbnail logical matrix bitmap, the detailed logical matrix bitmap displayed in the first region is updated based on the selected address range. Optionally, the address range selection operation on the thumbnail logical matrix bitmap can be a box selection operation on the local matrix bitmap region in the thumbnail logical matrix bitmap, and the detailed logical matrix bitmap displayed in the first region is the magnified logical matrix bitmap of the box-selected local matrix bitmap region. In response to the box selection operation on the local matrix bitmap region in the thumbnail logical matrix bitmap, the corresponding selected address range is determined according to the box-selected local matrix bitmap, and the detailed logical matrix bitmap displayed in the first region is updated based on the test data corresponding to the selected address range. In one possible implementation manner, in response to a drag operation on the detailed logical matrix bitmap, the selected address range in the thumbnail matrix bitmap is updated based on the dragged address range. Optionally, the user can drag the detailed logical matrix bitmap displayed in the first region. When receiving the drag operation on the detailed logical matrix bitmap, the detailed logical matrix bitmap displayed in the first region is updated based on the drag operation, and the box-selected local matrix bitmap region in the thumbnail logical matrix bitmap in the second region is updated based on the address range corresponding to the updated detailed logical matrix bitmap.

[0071] Optionally, a horizontal drag axis and a vertical drag axis are provided in the first region. In response to a drag operation on the horizontal drag axis and / or the vertical drag axis, the detailed logical matrix bitmap displayed in the first region and the box-selected local matrix bitmap region in the thumbnail logical matrix bitmap in the second region are updated.

[0072] In one possible implementation manner, a third region is further included in the second view window for displaying detailed address information. An address information window is displayed in the third region of the second view window, and the address range information corresponding to the currently displayed detailed logical matrix bitmap in the first region is displayed in the address information window. Specifically, the address information window may display a start address item and an end address item. The start address item displays the start address of the address range corresponding to the currently displayed detailed logical matrix bitmap, and the end address item displays the end address of the address range corresponding to the currently displayed detailed logical matrix bitmap, enabling the user to view the specific address range information.

[0073] Optionally, in response to an update operation on the address range information in the address information window, the detailed logical matrix bitmap displayed in the first region is updated based on the updated address range. That is, the user can change the address range in the address information window. In response to the update operation on the address range information, the updated address range can be obtained, and the detailed logical matrix bitmap displayed in the first region is updated based on the updated address range.

[0074] Optionally, in response to a drag operation on the detailed logic matrix bitmap, update the address range information in the address information window based on the address range information after dragging. When receiving a drag operation on the detailed logic matrix bitmap, the address range information in the address information window can be updated based on the address range information after dragging, so that the user can intuitively view the updated address range.

[0075] The address range in the address information window corresponds to the address range selected in the thumbnail logic matrix bitmap in the second region, that is, it corresponds to the address range corresponding to the locally matrix bitmap region boxed in the thumbnail logic matrix bitmap. In response to an address range update operation on the thumbnail logic matrix bitmap, that is, updating the boxed locally matrix bitmap region, update the address range information in the address information window in the third region.

[0076] Schematically, as Figure 5 shown, a detailed logic matrix bitmap of the pin DQL0 of the test object 201 is displayed in the first region 501, corresponding to the thumbnail logic matrix bitmap in the second region 502. An address information window is displayed in the third region 503, which can be used to display the address range information corresponding to the logic matrix bitmap, and can also be used to configure and select the address range information to be viewed. By updating the start address and the end address, the address range to be viewed can be updated.

[0077] The error address list is used to indicate the error addresses within a specified address range. Optionally, the error address list may include detailed logic error addresses within the specified address range.

[0078] In a possible implementation manner, in response to a viewing request for the error address list, display the error address list corresponding to the target test data in the third view window of the user interface.

[0079] A list viewing control for viewing the error address list may be provided in the user interface. In a possible implementation manner, in response to a triggering operation on the list viewing control, determine that a viewing request for the error address list is received, and display the error address list corresponding to the target test data in the third view window of the user interface.

[0080] The target test data includes test data for the specified address range of each digital input / output pin. In one possible implementation, the user can select to view the incorrect addresses within the target address range of a specified address range for a digital input / output pin. That is, in response to the selection operation for the target pin and the target address range, an incorrect address list corresponding to the target address range of the target pin is displayed in the third view window. After receiving the selection operation for the target pin and the target address range, the test data corresponding to the target address range of the target pin can be obtained, and an incorrect address list is generated based on the test data of the target address range. All the logical incorrect addresses (i.e., the logical addresses with a test result of Fail) included in the target address range of the target pin are listed in this incorrect address list.

[0081] Combined with the above embodiments, in response to a viewing request for the incorrect address list, the target pin selected by the user when displaying the detailed logic matrix bitmap in the first area can be obtained, and the address range information in the address information window in the third area can be obtained. The address range in the address information window in the third area is determined as the target address range, and an incorrect address list corresponding to the target address range of the target pin is generated. That is, after displaying the detailed logic matrix bitmap and the corresponding address range information of the target pin in the second view window, the user can trigger the display of the incorrect address list of the target pin and the corresponding address range information in the third view window through a trigger operation on the list viewing space. Optionally, the target address range can also be updated by an update operation on the address in the address range window, thereby triggering an update of the incorrect address list displayed in the third view window.

[0082] In one possible implementation, the first view window, the second view window, and the third view window can be juxtaposed windows, and the user can select different view windows to view the corresponding incorrect address information.

[0083] In the embodiments of the present disclosure, according to the incorrect address test data corresponding to the obtained logical address, the corresponding test status view, logical matrix bitmap, and incorrect address list can be respectively displayed in the view window of the user interface, presenting different incorrect address information in different forms to facilitate the user to intuitively obtain different incorrect address information of the target test object.

[0084] In the embodiments of the present disclosure, the detailed logic matrix bitmap and the thumbnail logic matrix bitmap can also be displayed simultaneously, and the display contents between them correspond to each other, facilitating the user to compare and analyze the information in the detailed logic matrix bitmap and the thumbnail logic matrix bitmap, and improving the acquisition efficiency of incorrect address information.

[0085] The storage control for storing error address test data in the target slave computer includes at least one of a compressed data storage space (Compress Fail Memory, CFM) and an error address storage space (Address Fail Memory, AFM). Among them, the CFM space stores the compressed test data corresponding to the error address test data, and the AFM space stores the original error address test data.

[0086] In a possible implementation manner, the target test data obtained by the master computer from the target slave computer includes at least one of the compressed test data and the original test data corresponding to the specified address range.

[0087] Optionally, the thumbnail logic matrix bitmap is generated according to the compressed test data. In response to the target test data being the compressed test data, the thumbnail logic matrix bitmaps corresponding to each digital input / output pin are displayed in the second view window. That is, when the obtained target test data is the compressed test data, according to the test data corresponding to each digital input / output pin included in the compressed test data, the thumbnail logic matrix bitmaps corresponding to each digital input / output pin are generated. The detailed logic matrix bitmap needs to be generated according to the original test data. In response to the target test data being the original test data and the selection operation on the target pin, the detailed logic matrix bitmap corresponding to the target pin is displayed in the second view window.

[0088] Optionally, the user interface includes a parameter configuration page, and the parameter configuration page can be used to configure the access parameters for the storage space. That is, the user can configure the access parameters including the specified address range through the parameter configuration page, so that the master computer reads the corresponding target test data from the storage space according to the configured access parameters. In response to the triggering operation on the parameter configuration item in the user interface, the parameter configuration page is displayed. There is a parameter configuration item provided in the user interface, and the parameter configuration item is a trigger item for triggering the display of the parameter configuration page. The user can trigger the display of the parameter configuration page through the triggering operation on the parameter configuration item.

[0089] In response to the configuration operation and data reading operation on the parameter configuration page, the configured access parameters are obtained, and the target test data is read based on the access parameters. In a possible implementation manner, in response to the configuration operation and data reading operation on the parameter configuration page, the configured access parameters can be obtained, and the target test data is read based on the access parameters.

[0090] Optionally, the parameter configuration page includes a capture parameter configuration page and an access parameter configuration page. The capture parameters are used to indicate the test data obtained by performing an incorrect address test on the capture address range of the target test object. The access parameters are the parameters for accessing the storage space. The user can configure the capture parameters through the capture parameter configuration page. The host computer obtains the capture parameters configured by the user, sends the capture parameters to the target lower computer, and the lower computer of the test device executes a preset test vector (pattern) based on the capture parameters to obtain the test data obtained by performing an incorrect address test on the capture address range of the target test object, and stores the test data corresponding to the capture address range in the storage space. After storing the test data corresponding to the capture address range in the storage space, the test data corresponding to the capture address range stored in the storage space can be accessed (i.e., read). Among them, the test vector, which can also be called test configuration information, includes the correspondence between the input signal and the output reference signal. The test vector can include the input signal input to the object under test and its corresponding output reference signal, and the input signal can include 0 or 1. The output reference signal corresponding to the input signal can be understood as the output true value corresponding to the input signal, indicating the information that should be output by the object under test when it meets its function. In a possible implementation manner, the target lower computer stores a preset test vector, and when receiving the capture parameters sent by the host computer, it executes the preset test vector based on the capture parameters to obtain the test data corresponding to the capture address range included in the capture parameters.

[0091] Optionally, the capture parameter configuration page provides AFM space capture parameter configuration items and CFM space capture parameter configuration items. The capture parameters for the AFM space can be configured through the AFM space capture parameter configuration items, and the capture parameters for the CFM space can be configured through the CFM space capture parameter configuration items. In a possible implementation, in response to the configuration operations of the capture parameters for the AFM space capture parameter configuration items and the CFM space capture parameter configuration items, the capture parameters for the AFM space and the CFM space are respectively sent to the target lower-level machine to store the corresponding error address test data in the AFM space and the CFM space. Optionally, the capture parameters for the AFM space and the CFM space can be the same, so that the error address test data within the same address range is stored in the AFM space and the CFM space. The original error address test data for this address range is stored in the AFM space, and the compressed error address test data for this address range is stored in the CFM space. The user can configure the AFM space capture parameters and the CFM space capture parameters including the specified address range. The upper-level machine sends the AFM space capture parameters and the CFM space capture parameters including the specified address range to the target lower-level machine. The target lower-level machine respectively executes the preset test vectors based on the AFM space capture parameters and the CFM space capture parameters, stores the original test data for the specified address range in the AFM space, and stores the compressed test data for the specified address range in the CFM space.

[0092] Optionally, the access parameter configuration page provides AFM space access parameter configuration items and CFM space access parameter configuration items. The access parameters for the AFM space can be configured through the AFM space access parameter configuration items, and the access parameters for the CFM space can be configured through the CFM space access parameter configuration items. In a possible implementation, the address range included in the AFM space access parameters needs to be no larger than the address range included in the capture parameters in the AFM space, and the address range included in the CFM space access parameters needs to be no larger than the address range included in the capture parameters in the CFM space.

[0093] In a possible implementation, in response to the configuration parameters of the AFM space access parameter configuration item, the configured AFM space access parameters are obtained. Based on the specified address range included in the AFM space access parameters, the target test data for the specified address range is read from the AFM space. In response to the configuration parameters of the CFM space access parameter configuration item, the configured CFM space access parameters are obtained. Based on the specified address range included in the CFM space access parameters, the target test data for the specified address range is read from the CFM space.

[0094] Optionally, the user can configure the access parameters for the storage space by accessing the parameter configuration item. Alternatively, the corresponding access parameters can be automatically generated according to the capture parameters of the storage space configured by the user, that is, the AFM space access parameters are automatically generated according to the AFM space capture parameters, and the CFM space access parameters are automatically generated according to the CFM space capture parameters.

[0095] In a possible implementation, before configuring the capture parameters for the AFM space, it is necessary to first configure the capture rule parameters for the AFM space. The capture parameter configuration item can also be used to configure the capture rule parameters, and the capture rule parameters are used to indicate the capture rule for capturing error address test data and storing it in the storage space (including the AFM space and the CFM space).

[0096] The capture parameter configuration item includes a rule parameter configuration item for configuring the capture rule parameters. Optionally, the capture rule parameters include the storage space where the test data can be stored after capturing the test data, the maximum address range that can be captured, the minimum address range, whether the redundancy mode is enabled, the function mode used, the address arrangement rule for storing the test data corresponding to each address, the write rule for writing the test data into the storage space (e.g., the correspondence between the bits of the storage space and each digital input / output pin (DQpin), the data type that can be written into the storage space), etc. The rule parameter configuration item can include the CFM space capture rule parameter configuration item and the AFM space capture rule parameter configuration item.

[0097] Taking the configuration of the capture rule parameters for the AFM space as an example, when the host computer receives the configuration operation for the AFM space capture rule parameter configuration item, it obtains the configured capture rule parameters, and then sends the configured capture rule parameters to the target lower computer, so that the target lower computer configures the AFM space according to the capture rule parameters for the AFM space, and the AFM space captures the error address test data based on the configured capture rule parameters.

[0098] Optionally, the access parameter configuration item includes a rule parameter configuration item for configuring the access rule parameters. Optionally, the access rule parameters include the address space that can be accessed within the storage space, the maximum address range that can be accessed, the minimum address range, whether the redundancy mode is enabled, etc. The rule parameter configuration item can include the CFM space access rule parameter configuration item and the AFM space access rule parameter configuration item.

[0099] Taking the configuration of the access rule parameters for the AFM space as an example, when the host computer receives the configuration operation for the AFM space access rule parameter configuration item, it obtains the configured access rule parameters, and then sends the configured access rule parameters to the target lower computer, so that the target lower computer configures the AFM space according to the access rule parameters for the AFM space.

[0100] In a possible implementation, as Figure 6 shown, it shows a flowchart of displaying a first type of view provided by an exemplary embodiment. The display device for obtaining error address information is set to work in an online mode, and the working conditions of the AFM and / or CFM are configured (i.e., the configuration of capture rule parameters and access rule parameters), and then the process of reading data is executed. During the process of reading data, if the reconfigured capture parameters are stored, the AFM space and the CFM space need to be initialized, the test vector is executed, and the test data in the capture address range indicated by the capture parameters is stored in the AFM space and the CFM space, and then the AFM data (original test data) and / or CFM data (compressed test data) are read based on the access parameters; if there are no reconfigured capture parameters, the AFM data and / or CFM data can be directly read based on the access parameters.

[0101] After reading the CFM data, at least one of the thumbnail logic matrix bitmap and the test status view can be displayed based on the CFM data. After reading the AFM data, at least one of the detailed logic matrix bitmap and the error address list can be displayed based on the AFM data. Then, it is determined whether to reconfigure the working conditions, that is, to reconfigure the capture rule parameters and access rule parameters for the AFM space and / or CFM space. If reconfigured, the process of reading data is re-executed.

[0102] The target test object includes multiple digital input / output pins, the target test data includes the test data corresponding to the specified address range of each digital input / output pin, and different logic matrix bitmaps correspond to the test data corresponding to the specified address range of different digital input / output pins. In a possible implementation, a layer overlay operation can be performed on the logic matrix bitmaps corresponding to different pins to compare the error address test results corresponding to multiple pins. This process includes the following steps:

[0103] Step 310, in response to the layer overlay operation on at least two logic matrix bitmaps, performing a logical operation on the at least two logic matrix bitmaps to obtain a logical overlay layer.

[0104] Optionally, in the second view window for displaying the logic matrix bitmap, there is a layer overlay control for triggering the layer overlay. In the second view window, there are also pin selection items and address range configuration items. The pin selection items are used to select the digital input / output pins to be overlaid, and the address range configuration items are used to configure the specific address range to be overlaid. Optionally, the address range configuration item can be the address range window displayed in the above-mentioned third area, and the address range window can be used to select the address range.

[0105] In a possible implementation, in response to a selection operation on at least two digital input / output pins, an address range, and a logical operation mode, at least two logical matrix bitmaps corresponding to the selected address range of the at least two digital input / output pins are obtained, and based on the selected logical operation mode, a logical operation is performed on the at least two logical matrix bitmaps to obtain a logical overlay layer. The logical operation mode includes at least one of an AND operation, an OR operation, and an XOR operation.

[0106] Optionally, in response to a selection operation on a pin selection item, at least two selected digital input / output pins are obtained. In response to a selection operation on an address range and a logical operation mode, the selected address range and the selected logical operation mode are obtained.

[0107] Based on the selected address range, test data of the selected address range of the at least two selected digital input / output pins is obtained. Corresponding logical matrix bitmaps are generated based on the test data of the selected address range of the at least two digital input / output pins, and then a layer overlay operation is performed on the at least two logical matrix bitmaps based on the selected logical operation mode.

[0108] Optionally, the logical operation mode includes at least one of an AND operation, an OR operation, and an XOR operation. The AND operation means screening the Fail addresses with the same addresses within the same address range to view and analyze the distribution of the same Fail addresses within the selected address ranges of different digital input / output pins. The OR operation means screening all the Fail addresses within the same address range to view and analyze the distribution of all the Fail addresses within the selected address ranges of different digital input / output pins. The XOR operation means screening the Fail addresses with different addresses within the same address range to view and analyze the distribution of different Fail addresses within the selected address range.

[0109] Optionally, the layer overlay operation can be at least one of an overlay operation on the thumbnail logical matrix bitmaps of the at least two digital input / output pins and an overlay operation on the detailed logical matrix bitmaps of the at least two digital input / output pins.

[0110] Schematically, as Figure 5 shown, at least two digital input / output pins to be overlaid can be selected in area 504, and a logical operation mode can be selected. An address range can be selected in the third area 503.

[0111] In a possible implementation, when obtaining at least two logical matrix bitmaps corresponding to the selected address ranges of at least two digital input / output pins, it is necessary to obtain the test data corresponding to the selected address ranges of at least two digital input / output pins. Optionally, in response to the selected address range belonging to the specified address range, obtain the test data corresponding to the selected address ranges of at least two digital input / output pins from the target test data. When the selected address range belongs to the specified address range, the target test data of the specified address range is cached in the host computer, and the test data corresponding to the selected address ranges of at least two digital input / output pins can be obtained from the target test data.

[0112] In response to the selected address range not belonging to the specified address range, read the test data corresponding to the selected address range from the storage space for storing error address test data. When the selected address range does not belong to the specified address range, the test data of the selected address range is not cached in the host computer, and the capture parameters and access parameters including the selected address range can be sent to the slave computer, so as to read the test data corresponding to the selected address range from the storage space.

[0113] After obtaining the test data corresponding to the selected address range, generate the corresponding at least two logical matrix bitmaps.

[0114] In a possible implementation, a layer overlay operation can be performed on the detailed logical matrix bitmaps of at least two digital input / output pins. During the process of reading the test data corresponding to the selected address range from the storage space for storing error address test data, read the test data corresponding to the selected address range from the AFM space. Optionally, in response to the selected address range being greater than the display address range, read the compressed test data corresponding to the selected address range; in response to the selected address range not being greater than the display address range, read the original test data corresponding to the selected address range. The display address range is the address range corresponding to the number of data points that the user interface allows to display. Specifically, when displaying the superimposed logical overlay layer in the first area, the display address range is the address range corresponding to the number of data points that the first area allows to display. Among them, when reading the compressed test data corresponding to the selected address range, the host computer can determine the compression ratio parameter according to the selected address range and the display address range, and send the compression ratio parameter and the selected address range to the target slave computer. The target slave computer reads the test data of the selected address range from the AFM space, compresses the test data of the selected address range based on the compression ratio parameter, obtains the compressed test data corresponding to the selected address range, returns the compressed test data corresponding to the selected address range to the host computer, and the host computer generates the corresponding logical matrix bitmap based on the compressed test data corresponding to the selected address range of the selected digital input / output pins, and superimposes the generated logical matrix bitmap to obtain the logical overlay layer.

[0115] When reading the original test data corresponding to the selected address range, the host computer sends the selected address range to the target slave computer. The target slave computer reads the original test data of the selected address range from the AFM space, returns the original test data corresponding to the selected address range to the host computer, and the host computer generates a corresponding logical matrix bitmap based on the original test data corresponding to the selected address range of the selected digital input / output pins, and superimposes the generated logical matrix bitmap to obtain a logical superimposed layer.

[0116] Step 320, display the logical superimposed layer in the second view window of the user interface.

[0117] After superimposing the logical matrix bitmaps of at least two digital input / output pins, the superimposed logical superimposed layer can be displayed in the second view window.

[0118] Optionally, in response to the superimposition operation on the detailed logical matrix bitmaps of at least two digital input / output pins, the superimposed logical superimposed layer is displayed in the first area. In response to the superimposition operation on the thumbnail logical matrix bitmaps of at least two digital input / output pins, the superimposed logical superimposed layer is displayed in the second area.

[0119] In a possible implementation manner, the process of layer superimposition is as Figure 7 shown. The front-end user interface receives the selection operation for different digital input / output pins, receives the selection operation for the logical operation method, creates a logical operation expression, and the back-end test service unit analyzes the logical operation expression, obtains the test data according to the selected digital input / output pins and the selected address range. If the test data is not cached in the host computer, it reads the test data from the target slave computer again. During the reading process, if the selected address range is larger than the display address range, it reads the compressed test data. If the selected address range is smaller than the display address range, it reads the original test data. If the test data is already cached in the host computer, it directly reads the cached data. After reading the test data, it performs a logical operation on the test data to obtain a logical superimposed layer, and the user interface displays the logical superimposed layer.

[0120] In the embodiments of the present disclosure, the layer superimposition operation can be performed on the logical matrix bitmaps of multiple digital input / output pins of a target test object, which is beneficial to improving the analysis and processing efficiency of the wrong addresses of multiple digital input / output pins.

[0121] In a possible implementation manner, the second type of view is a physical matrix view corresponding to the physical error address data, which is used to indicate the position distribution of each error address of the target test object.

[0122] Optionally, the process of displaying the second type of view in the view window of the user interface includes the following steps:

[0123] Step 2301: Perform address conversion on the logical error address indicated by the target test data to obtain the physical error address.

[0124] In a possible implementation, the logical error address indicated in the target test data can be subjected to address conversion to obtain the physical error address. This process may include the following steps:

[0125] Step 1: In response to a configuration operation on the data source configuration item of the user interface, obtain the configured logical data file and conversion rule file.

[0126] The user interface provides a data source configuration item for configuring files related to obtaining physical error address data, including the logical data file and the conversion rule file. The logical data file stores the logical error address indicated by the target test data, and the conversion rule file stores the conversion rule for converting the logical address to the physical address.

[0127] In a possible implementation, the acquisition paths of the logical data file and the conversion rule file can be configured, and the host computer obtains the logical data file and the conversion rule file according to the acquisition paths.

[0128] Step 2: In response to an address conversion operation, read the logical error address from the logical data file and read the conversion rule from the conversion rule file, and convert the logical error address to the physical error address based on the conversion rule.

[0129] In a possible implementation, an address conversion control is set in the data source configuration item. In response to a trigger operation on the address conversion control, it is determined that an address conversion operation is received, and the logical error address indicated in the target test data is read from the logical data file and the logical error address is converted to the physical error address based on the conversion rule indicated by the conversion rule file.

[0130] Optionally, the address conversion process includes an operation of splitting the physical address of the target test object and an operation of sorting the logical error addresses. By splitting the physical address of the target test object, the physical address space can be split into different regions. After converting a logical error address to a physical address, based on the physical address space region after splitting, it is possible to determine the physical address space region to which the obtained physical error address belongs, quickly locating the physical location corresponding to the logical error address. The operation of sorting the logical error addresses can be performed based on the physical error addresses corresponding to the converted logical error addresses, which helps to quickly analyze the physical error addresses.

[0131] In a possible implementation, before address conversion, it is also necessary to configure a physical data source file, which is a file used to store physical error address data. This includes configuring the file path and file name of the physical data source file. After address conversion, the physical error addresses are stored in the configured physical data source file based on the configured file path and file name.

[0132] Step 2302: Based on the physical error addresses, display a physical matrix bitmap in the view window of the user interface. The physical matrix bitmap is used to indicate the position distribution of the error addresses of the target test object, and the physical error addresses are displayed in the physical matrix view.

[0133] In a possible implementation, the physical error addresses can be read from the physical data source file based on the configured file path and file name, a physical matrix bitmap can be generated based on the physical error addresses, and the physical matrix bitmap can be displayed in the view window of the user interface. The physical matrix bitmap corresponds to the entire target test object. The physical error addresses include the physical error addresses obtained after converting the logical error addresses of each digital input / output pin. The generated physical matrix bitmap includes the distribution of the actual physical positions of the logical error addresses of each digital input / output pin on the target test object.

[0134] Optionally, the physical matrix bitmap includes at least one of a thumbnail physical matrix bitmap and a detailed physical matrix bitmap.

[0135] Displaying the physical matrix bitmap in the view window of the user interface includes the following steps:

[0136] Step 1: Display a thumbnail physical matrix bitmap in the fourth area of the view window.

[0137] Step 2: In response to a selection operation on the address range in the thumbnail physical matrix bitmap, display a detailed physical matrix bitmap corresponding to the selected address range in the fifth area of the view window.

[0138] In a possible implementation, the thumbnail physical matrix bitmap and the detailed physical matrix bitmap corresponding to the target test object can be displayed in the view window simultaneously. Optionally, the thumbnail physical matrix bitmap corresponding to the target test object is displayed in the fourth area of the view window, and the detailed physical matrix bitmap corresponding to the target test object is displayed in the fifth area, where the area of the fifth area is larger than the area of the fourth area. Optionally, the fourth area can be the same as the above-mentioned second area, and the fifth area can be the same as the above-mentioned first area.

[0139] In a possible implementation, the selected matrix area in the thumbnail physical matrix bitmap displayed in the fourth area corresponds to the detailed physical matrix bitmap in the fifth area. In response to an address range selection operation on the thumbnail physical matrix bitmap, the detailed physical matrix bitmap displayed in the fifth area is updated based on the selected address range. Optionally, the address range selection operation on the thumbnail physical matrix bitmap can be a box selection operation on the local matrix bitmap area in the thumbnail physical matrix bitmap, and the detailed physical matrix bitmap displayed in the fifth area is the physical matrix bitmap after magnifying the box-selected local matrix bitmap area. In response to the box selection operation on the local matrix bitmap area in the thumbnail physical matrix bitmap, the corresponding selected address range is determined according to the box-selected local matrix bitmap, and the detailed physical matrix bitmap displayed in the fifth area is updated based on the physical error address corresponding to the selected address range. In a possible implementation, in response to a drag operation on the detailed physical matrix bitmap, the selected address range in the thumbnail physical matrix bitmap is updated based on the physical address range after dragging. Optionally, the user can drag the detailed physical matrix bitmap displayed in the fifth area. When a drag operation on the detailed physical matrix bitmap is received, the detailed logical matrix bitmap displayed in the fifth area is updated based on the drag operation, and the box-selected local matrix bitmap area in the thumbnail physical matrix bitmap in the fourth area is updated based on the physical address range corresponding to the updated detailed logical matrix bitmap.

[0140] Optionally, a horizontal drag axis and a vertical drag axis are set in the fifth area. In response to a drag operation on the horizontal drag axis and / or the vertical drag axis, the detailed physical matrix bitmap displayed in the fifth area and the box-selected local matrix bitmap area in the thumbnail physical matrix bitmap in the fourth area are updated.

[0141] In a possible implementation, the user can magnify the detailed physical matrix bitmap. In response to a magnification operation on the detailed physical matrix bitmap, the detailed physical matrix bitmap is magnified.

[0142] When the detailed physical matrix bitmap is magnified to the target state, in response to a viewing operation on the target physical address, the logical address corresponding to the target physical address is displayed. The target state refers to a state where each physical unit in the detailed physical matrix bitmap corresponds to a physical address.

[0143] Optionally, the target state can be the state where the detailed physical matrix is magnified to the maximum, and in this state, each physical unit in the detailed physical matrix bitmap corresponds to a physical address. In the target state, in response to a viewing operation on the target physical address, the logical address corresponding to the target physical address can be displayed. Optionally, in response to a selection operation on the target physical unit corresponding to the target physical address, it is determined that a viewing operation on the target physical address is received, and an overlay sub-window can be displayed in the view window, and the logical address information corresponding to the target physical address is displayed in the overlay sub-window.

[0144] Schematic, such as Figure 8 As shown, in response to a selection operation on the target physical unit 801, the corresponding logical address information is displayed within the overlay sub-window 802.

[0145] In one possible implementation, a layer overlay operation may be performed on the physical matrix bitmaps corresponding to multiple different target test objects to compare the distribution of physical error addresses corresponding to the multiple test objects. The steps include:

[0146] Step 410, in response to a layer overlay operation on the physical matrix bitmaps of at least two target test objects, overlay the physical matrix bitmaps of the at least two target test objects to obtain a physical overlay layer, where the at least two physical matrix bitmaps respectively correspond to the error address test data of the at least two target test objects within the same address range.

[0147] Optionally, within the view window for displaying the physical matrix bitmap, there is a layer overlay control for triggering the layer overlay, and there are also target test object selection items within the view window. The target test object selection items are used to select the target test objects to be overlaid, and the address range configuration item is used to configure the specific physical address range to be overlaid.

[0148] In one possible implementation, in response to a selection operation on at least two target test objects, an address range, and a logical operation method, obtain at least two physical matrix bitmaps corresponding to the selected address ranges of the at least two target test objects, and perform a logical operation on the at least two physical matrix bitmaps based on the selected logical operation method to obtain a physical overlay layer. The logical operation method includes at least one of AND operation, OR operation, and XOR operation.

[0149] Optionally, in response to a selection operation on the target test object selection items, obtain the at least two selected target test objects. In response to a selection operation on the address range and the logical operation method, obtain the selected physical address range and the selected logical operation method.

[0150] Based on the selected address range, obtain the physical error addresses of the selected address ranges of the at least two selected target test objects, generate the corresponding physical matrix bitmaps, and then perform a layer overlay operation on the at least two physical matrix bitmaps based on the selected logical operation method.

[0151] Optionally, the logical operation method includes at least one of AND operation, OR operation, and XOR operation. The AND operation is to filter the Fail addresses with the same address within the same address range, and is used to view and analyze the distribution of the same Fail addresses within the selected physical address range of different target test objects. The OR operation is to filter all the Fail addresses within the same address range, and is used to view and analyze the distribution of all the Fail addresses within the selected physical address range of different target test objects. The XOR operation is to filter the Fail addresses with different addresses within the same address range, and is used to view and analyze the distribution of different Fail addresses within the selected physical address range.

[0152] Optionally, the layer overlay operation may be at least one of the overlay operation on the thumbnail physical matrix bitmaps of at least two target test objects and the overlay operation on the detailed logical matrix bitmaps of at least two target test objects.

[0153] Step 420, display the physical overlay layer in the view window of the user interface.

[0154] Optionally, in response to the overlay operation on the detailed physical matrix bitmaps of at least two target test objects, display the overlaid physical overlay layer in the fifth area. In response to the overlay operation on the thumbnail logical matrix bitmaps of at least two target test objects, display the overlaid physical overlay layer in the fourth area.

[0155] In a possible implementation manner, the physical layer overlay process is as Figure 9 shown. This process includes: the front-end user interface receives the selection operation on different target test objects, receives the selection operation on the logical operation method, creates a logical operation expression. Then, the back-end test service unit analyzes the logical operation expression, obtains data from the physical data source file according to the selected target test objects and address range, performs a logical operation on the obtained data to obtain the physical overlay layer, and the user interface displays the physical overlay layer.

[0156] In the embodiments of the present disclosure, the layer overlay operation can be performed on the physical matrix bitmaps of multiple target test objects, which is beneficial to improving the analysis and processing efficiency of the position distribution of physical error addresses in multiple target test objects.

[0157] FIG. 10 is a schematic structural diagram of an error address information acquisition and processing device provided by an exemplary embodiment of the present disclosure. The device includes:

[0158] A data reading module 1001, configured to read the target test data of a target test object in response to a data reading operation detected by the user interface. The target test data is the error address test data corresponding to a specified address range in the error address test data of the target test object;

[0159] A view display module 1002, configured to display a first type of view within a view window of the user interface based on the target test data, where the first type of view is used to indicate test result information of different addresses within the specified address range;

[0160] The view display module 1002 is further configured to, in response to a view switching operation detected by the user interface, display a second type of view within the view window of the user interface based on the target test data, where the second type of view is used to indicate the location distribution information of error addresses within the specified address range on the target test object.

[0161] In an exemplary embodiment, the first type of view includes at least one of a test status view, a logic matrix bitmap, and an error address list. The test status view is used to indicate the test status information of the specified address range, the logic matrix bitmap is used to indicate the test result information corresponding to each logical address within the specified address range, and the error address list is used to indicate the error addresses within the specified address range;

[0162] The view display module 1002 is further configured to:

[0163] In response to a viewing request for the test status view, display the test status view corresponding to the target test data within a first view window of the user interface; and / or,

[0164] In response to a viewing request for the logic matrix bitmap, display the logic matrix bitmap corresponding to the target test data within a second view window of the user interface; and / or,

[0165] In response to a viewing request for the error address list, display the error address list corresponding to the target test data within a third view window of the user interface.

[0166] In an exemplary embodiment, the target test object includes multiple digital input / output pins, and the target test data includes test data corresponding to the specified address range of each of the digital input / output pins;

[0167] The view display module 1002 is further configured to:

[0168] Display a test status view within the first view window for indicating the test status of each of the digital input / output pins;

[0169] Display the thumbnail logic matrix bitmaps corresponding to each of the digital input / output pins within the second view window; and / or, in response to a selection operation on a target pin, display the detailed logic matrix bitmap corresponding to the target pin within the second view window, where the target pin is any one of the multiple digital input / output pins;

[0170] In response to a selection operation on the target pin and a target address range, display an error address list corresponding to the target address range of the target pin within the third view window, where the target address range belongs to the specified address range.

[0171] In an exemplary embodiment, the view display module 1002 is further configured to:

[0172] Display the detailed logic matrix bitmap corresponding to the target pin within the first area of the second view window;

[0173] Display the thumbnail logic matrix bitmap corresponding to the target pin within the second area of the second view window;

[0174] In response to an address range selection operation on the thumbnail logic matrix bitmap, update the detailed logic matrix bitmap displayed within the first area based on the selected address range;

[0175] In response to a drag operation on the detailed logic matrix bitmap, update the selected address range in the thumbnail logic matrix bitmap based on the dragged address range.

[0176] In an exemplary embodiment, the view display module 1002 is further configured to:

[0177] Display an address information window within the third area of the second view window, where the address range information corresponding to the detailed logic matrix bitmap currently displayed within the first area is displayed in the address information window;

[0178] In response to an update operation on the address range information within the address information window, update the detailed logic matrix bitmap displayed within the first area based on the updated address range;

[0179] In response to a drag operation on the detailed logic matrix bitmap, update the address range information within the address information window based on the dragged address range information.

[0180] In an exemplary embodiment, the target test data includes at least one of the compressed test data and the original test data corresponding to the specified address range;

[0181] The view display module 1002 is further configured to:

[0182] In response to the target test data being the compressed test data, display the thumbnail logic matrix bitmaps corresponding to each of the digital input / output pins within the second view window;

[0183] In response to the target test data being the original test data, display the detailed logic matrix bitmap corresponding to the target pin within the second view window.

[0184] In an exemplary embodiment, the compressed test data is stored in a compressed data storage space, and the original test data is stored in an error address storage space;

[0185] The apparatus further includes:

[0186] A page display module, configured to display a parameter configuration page in response to a trigger operation on a parameter configuration item in the user interface, where the parameter configuration page is used to configure access parameters for a storage space, and the storage space includes at least one of the compressed data storage space and the error address storage space;

[0187] The data reading module is further configured to:

[0188] In response to a configuration operation on the parameter configuration page and the data reading operation, obtain the configured access parameters, and read the target test data based on the access parameters, where the configured access parameters include a configured specified address range.

[0189] In an exemplary embodiment, the target test object includes a plurality of digital input / output pins, the target test data includes test data corresponding to the specified address ranges of each of the digital input / output pins, and different logic matrix bitmaps correspond to test data corresponding to the specified address ranges of different digital input / output pins;

[0190] The apparatus further includes:

[0191] A layer overlay module, configured to perform a logical operation on at least two logic matrix bitmaps in response to a layer overlay operation on the at least two logic matrix bitmaps to obtain a logical overlay layer;

[0192] A layer display module, configured to display the logical overlay layer within the second view window of the user interface.

[0193] In an exemplary embodiment, the layer overlay module is further configured to:

[0194] In response to a selection operation on at least two digital input / output pins, an address range, and a logical operation mode, obtain at least two logical matrix bitmaps corresponding to the selected address range of the at least two digital input / output pins, and perform a logical operation on the at least two logical matrix bitmaps based on the selected logical operation mode to obtain the logical overlay layer, where the logical operation mode includes at least one of an AND operation, an OR operation, and an XOR operation.

[0195] The layer overlay module is further configured to:

[0196] In response to the selected address range belonging to the specified address range, obtain test data corresponding to the selected address range of the at least two digital input / output pins from the target test data;

[0197] In response to the selected address range not belonging to the specified address range, read test data corresponding to the selected address range from the storage space for storing error address test data;

[0198] Generate the at least two logical matrix bitmaps based on the test data corresponding to the selected address range.

[0199] In an exemplary embodiment, the layer overlay module is further configured to:

[0200] In response to the selected address range being greater than the display address range, read the compressed test data corresponding to the selected address range, where the display address range is the address range allowed to be displayed by the user interface;

[0201] In response to the selected address range not being greater than the display address range, read the original test data corresponding to the selected address range.

[0202] In an exemplary embodiment, the view display module 1002 is further configured to:

[0203] Perform an address conversion on the logical error address indicated by the target test data to obtain a physical error address;

[0204] Based on the physical error address, display a physical matrix bitmap in the view window of the user interface, where the physical matrix bitmap is used to indicate the position distribution of each error address of the target test object, and the physical error address is displayed in the physical matrix view.

[0205] In an exemplary embodiment, the view display module 1002 is further configured to:

[0206] Display a thumbnail physical matrix bitmap in the fourth area of the view window;

[0207] In response to a selection operation on the address range in the thumbnail physical matrix bitmap, a detailed physical matrix bitmap corresponding to the selected address range is displayed in the fifth area of the view window.

[0208] The apparatus further includes:

[0209] A bitmap magnification module, configured to magnify the detailed physical matrix bitmap in response to a magnification operation on the detailed physical matrix bitmap;

[0210] An address information display module, configured to display a logical address corresponding to a target physical address in response to a viewing operation on the target physical address when the detailed physical matrix bitmap is magnified to a target state, where the target state refers to a state in which each physical unit in the detailed physical matrix bitmap corresponds to one physical address.

[0211] In an exemplary embodiment, the layer superposition module is further configured to:

[0212] In response to a layer superposition operation on physical matrix bitmaps of at least two target test objects, superpose the physical matrix bitmaps of the at least two target test objects to obtain a physical superposition layer, where the at least two physical matrix bitmaps respectively correspond to error address test data of the same address range of the at least two target test objects;

[0213] The layer display module is further configured to display the physical superposition layer in a view window of the user interface.

[0214] In an exemplary embodiment, the layer superposition module is further configured to:

[0215] In response to a selection operation on at least two target test objects, an address range, and a logical operation method, obtain at least two physical matrix bitmaps corresponding to the selected address range of the at least two target test objects, and perform a logical operation on the at least two physical matrix bitmaps based on the selected logical operation method to obtain the physical superposition layer, where the logical operation method includes at least one of an AND operation, an OR operation, and an XOR operation.

[0216] In an exemplary embodiment, the view display module 1002 is further configured to:

[0217] In response to a configuration operation on a data source configuration item of the user interface, obtain a configured logical data file and a conversion rule file, where the logical data file stores logical error addresses of the target test data, and the conversion rule file stores a conversion rule for converting a logical address to a physical address;

[0218] In response to an address conversion operation, read the logical error address from the logical data file and read the conversion rule from the conversion rule file, and convert the logical error address into a physical error address based on the conversion rule.

[0219] The apparatus further includes:

[0220] A file configuration module for configuring the file path and file name of the physical data source file;

[0221] A data storage module for storing the physical error address in the configured physical data source file;

[0222] The view display module is further configured to:

[0223] Read the physical error address from the physical data source file based on the configured file path and file name, and generate the physical matrix bitmap based on the physical error address;

[0224] Display the physical matrix bitmap in the view window of the user interaction interface.

[0225] In addition, an embodiment of the present disclosure further provides an electronic device, including:

[0226] A memory for storing a computer program;

[0227] A processor for executing the computer program stored in the memory, and when the computer program is executed, implementing the method for obtaining and processing error address information according to any one of the above embodiments of the present disclosure.

[0228] As Figure 11 shown, the electronic device includes one or more processors and a memory.

[0229] The processor may be a central processing unit (CPU) or other form of processing unit with data processing capabilities and / or instruction execution capabilities, and may control other components in the electronic device to perform desired functions.

[0230] The memory may store one or more computer program products. The memory may include various forms of computer-readable storage media, such as volatile memory and / or non-volatile memory. The volatile memory may, for example, include random access memory (RAM) and / or cache memory, etc. The non-volatile memory may, for example, include read-only memory (ROM), hard disk, flash memory, etc. One or more computer program products may be stored on the computer-readable storage medium, and the processor may run the computer program products to implement the method for obtaining and processing error address information according to various embodiments of the present disclosure described above and / or other desired functions.

[0231] In one example, the electronic device may further include: an input device and an output device, and these components are interconnected through a bus system and / or other forms of connection mechanisms (not shown).

[0232] In addition, the input device may further include, for example, a keyboard, a mouse, and the like.

[0233] The output device may output various information to the outside, including the determined distance information, direction information, etc. The output device may include, for example, a display, a speaker, a printer, and a communication network and its connected remote output devices, and the like.

[0234] Of course, for the sake of simplicity, Figure 11 only some of the components related to the present disclosure in the electronic device are shown, and components such as a bus, an input / output interface, and the like are omitted. In addition, according to specific application scenarios, the electronic device may further include any other appropriate components.

[0235] In addition to the above methods and devices, an embodiment of the present disclosure may also be a computer program product, which includes computer program instructions, and when the computer program instructions are run by a processor, the processor is caused to execute the steps in the method for obtaining error address information according to various embodiments of the present disclosure described in the above part of this specification.

[0236] The computer program product may be written in any combination of one or more programming languages for programming code to perform the operations of the embodiments of the present disclosure. The programming languages include object-oriented programming languages, such as Java, C++, etc., and also include conventional procedural programming languages, such as the "C" language or similar programming languages. The program code may be executed entirely on the user computing device, partially on the user device, executed as an independent software package, partially on the user computing device and partially on a remote computing device, or entirely on a remote computing device or server.

[0237] In addition, an embodiment of the present disclosure may also be a computer-readable storage medium, on which computer program instructions are stored, and when the computer program instructions are run by a processor, the processor is caused to execute the steps in the method for obtaining error address information according to various embodiments of the present disclosure described in the above part of this specification.

[0238] The computer-readable storage medium may adopt any combination of one or more readable media. The readable media may be a readable signal medium or a readable storage medium. The readable storage medium may, for example, include but is not limited to an electrical, magnetic, optical, electromagnetic, infrared, or semiconductor system, apparatus, or device, or any combination of the above. More specific examples (a non-exhaustive list) of the readable storage medium include: an electrical connection with one or more wires, a portable disk, a hard disk, a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber, a portable compact disk read-only memory (CD-ROM), an optical storage device, a magnetic storage device, or any suitable combination of the above.

[0239] The basic principles of the present disclosure have been described in conjunction with specific embodiments. However, it should be noted that the advantages, benefits, effects, etc. mentioned in the present disclosure are only examples and not limitations, and it cannot be considered that these advantages, benefits, effects, etc. are essential for each embodiment of the present disclosure. Additionally, the above-described specific details are only for illustrative and facilitating understanding purposes and are not limitations. The above details do not limit the present disclosure to necessarily adopt the above specific details for implementation.

[0240] Each embodiment in this specification is described in a progressive manner. The key point of each embodiment is to illustrate the differences from other embodiments. For the same or similar parts among the embodiments, reference may be made to each other. For system embodiments, since they basically correspond to method embodiments, the description is relatively simple, and reference may be made to the relevant parts of the method embodiments for the relevant content.

[0241] The block diagrams of the devices, apparatuses, equipment, and systems involved in the present disclosure are only illustrative examples and do not intend to require or imply that they must be connected, arranged, and configured in the manner shown in the block diagrams. As those skilled in the art will recognize, these devices, apparatuses, equipment, and systems can be connected, arranged, and configured in any manner. Words such as "comprising," "including," "having," etc. are open-ended terms, meaning "including but not limited to," and can be used interchangeably with each other. The word "or" and "and" used herein refer to the phrase "and / or" and can be used interchangeably with each other, unless the context clearly indicates otherwise. The word "such as" used herein refers to the phrase "such as but not limited to" and can be used interchangeably with each other.

[0242] The methods and apparatuses of the present disclosure can be implemented in many ways. For example, the methods and apparatuses of the present disclosure can be implemented by software, hardware, firmware, or any combination of software, hardware, and firmware. The above order of the steps for the method is for illustration only, and the steps of the method of the present disclosure are not limited to the order specifically described above, unless otherwise specifically stated. In addition, in some embodiments, the present disclosure can also be implemented as a program recorded in a recording medium, and these programs include machine-readable instructions for implementing the method according to the present disclosure. Therefore, the present disclosure also covers a recording medium storing a program for executing the method according to the present disclosure.

[0243] It should also be noted that in the apparatuses, devices, and methods of the present disclosure, each component or each step can be decomposed and / or recombined. These decompositions and / or recombinations should be regarded as equivalent solutions of the present disclosure.

[0244] The above description of the disclosed aspects is provided to enable any person skilled in the art to make or use the present disclosure. Various modifications to these aspects will be readily apparent to those skilled in the art, and the general principles defined herein can be applied to other aspects without departing from the scope of the present disclosure. Therefore, the present disclosure is not intended to be limited to the aspects shown herein, but is to be accorded the widest scope consistent with the principles and novel features disclosed herein.

[0245] The above description has been presented for purposes of illustration and description. In addition, this description is not intended to limit the embodiments of the present disclosure to the form disclosed herein. Although multiple example aspects and embodiments have been discussed above, those skilled in the art will recognize certain variations, modifications, alterations, additions, and sub-combinations thereof.

Claims

1. A method for obtaining and processing error address information, characterized in that: The method comprises: In response to a data read operation being detected by the user interaction interface, target test data of a target test object is read, wherein the target test data is error address test data corresponding to a specified address range in error address test data of the target test object; Based on the target test data, displaying a first type of view in a view window of the user interaction interface, the first type of view being used to indicate test result information of different addresses within the specified address range; In response to the user interaction interface detecting a view switching operation, displaying a second type of view in the view window of the user interaction interface based on the target test data, wherein the second type of view is used to indicate position distribution information of error addresses in the specified address range on the target test object; The displaying of the second type of view in the view window of the user interaction interface based on the target test data includes: Performing address conversion on the logical error address indicated by the target test data to obtain a physical error address; Based on the physical error address, a physical matrix bitmap is displayed in the view window of the user interaction interface, wherein the physical matrix bitmap is used to indicate the position distribution of each error address of the target test object, and the physical error address is displayed in the physical matrix bitmap.

2. The method according to claim 1, characterized in that The first type of view includes at least one of a test status view, a logic matrix bitmap, and an error address list, wherein the test status view is used to indicate test status information of the specified address range, the logic matrix bitmap is used to indicate test result information corresponding to each logical address in the specified address range, and the error address list is used to indicate error addresses within the specified address range; The displaying of the first type of view in the view window of the user interaction interface includes: In response to a request to view the test status view, displaying the test status view corresponding to the target test data in a first view window of the user interaction interface; and / or, In response to a request to view the logic matrix bitmap, displaying the logic matrix bitmap corresponding to the target test data in a second view window of the user interaction interface; and / or, In response to a request to view the error address list, the error address list corresponding to the target test data is displayed in a third viewing window of the user interaction interface.

3. The method according to claim 2, characterized in that The target test object includes a plurality of digital input and output pins, and the target test data includes test data corresponding to a specified address range of each of the digital input and output pins; The displaying of the test status view corresponding to the target test data in the first view window of the user interaction interface includes: Displaying a test status view for indicating the test status of each of the digital input and output pins in the first view window; The displaying of the logic matrix bitmap corresponding to the target test data in the second view window of the user interaction interface includes: Displaying the abbreviated logic matrix bitmap corresponding to each of the digital input and output pins in the second view window; and / or, In response to a selection operation on a target pin, displaying a detailed logic matrix bitmap corresponding to the target pin in the second view window, the target pin being any digital input / output pin among the plurality of digital input / output pins; The displaying of the error address list corresponding to the target test data in the third view window of the user interaction interface includes: In response to a selection operation on the target pin and the target address range, an error address list corresponding to the target address range of the target pin is displayed in the third view window, and the target address range belongs to the designated address range.

4. The method according to claim 3, characterized in that Displaying the detailed logic matrix bitmap corresponding to the target pin in the second view window includes: Displaying a detailed logic matrix bitmap corresponding to the target pin in the first area of the second view window; The method further comprises: Displaying the abbreviated logic matrix bitmap corresponding to the target pin in the second area of the second view window; In response to an address range selection operation on the thumbnail logic matrix bitmap, updating the detailed logic matrix bitmap displayed in the first region based on the selected address range; In response to a drag operation on the detailed logic matrix bitmap, a selected address range in the thumbnail logic matrix bitmap is updated based on the dragged address range.

5. The method according to claim 4, characterized in that The method further comprises: Displaying an address information window in the third area of the second view window, wherein the address information window displays address range information corresponding to the detailed logic matrix bitmap currently displayed in the first area; In response to an update operation on the address range information in the address information window, updating the detailed logic matrix bitmap displayed in the first area based on the updated address range; In response to a drag operation on the detailed logic matrix bitmap, the address range information in the address information window is updated based on the dragged address range information.

6. The method according to claim 3, characterized in that The target test data includes at least one of compressed test data and original test data corresponding to the specified address range; Displaying the abbreviated logic matrix bitmap corresponding to each of the digital input and output pins in the second view window includes: In response to the target test data being the compressed test data, displaying the abbreviated logic matrix bitmap corresponding to each of the digital input and output pins in the second view window; Displaying the detailed logic matrix bitmap corresponding to the target pin in the second view window includes: In response to the target test data being the original test data, a detailed logic matrix bitmap corresponding to the target pin is displayed in the second view window.

7. The method according to claim 6, characterized in that The compressed test data is stored in the compressed data storage space, and the original test data is stored in the error address storage space; Before reading the target test data of the target test object in response to the user interaction interface detecting the data reading operation, the method further includes: In response to a triggering operation on a parameter configuration item in a user interaction interface, displaying a parameter configuration page, the parameter configuration page being used to configure access parameters to a storage space, the storage space including at least one of the compressed data storage space and the error address storage space; The step of reading target test data of a target test object includes: In response to the configuration operation on the parameter configuration page and the data reading operation, configured access parameters are acquired, and the target test data is read based on the access parameters, wherein the configured access parameters include a configured designated address range.

8. The method according to any one of claims 2 to 7, characterized in that: The target test object includes a plurality of digital input and output pins, and the target test data includes test data corresponding to a specified address range of each of the digital input and output pins, and different logic matrix bitmaps correspond to test data corresponding to the specified address ranges of different digital input and output pins; The method further comprises: In response to a layer overlay operation on at least two logic matrix bitmaps, performing a logical operation on the at least two logic matrix bitmaps to obtain a logic overlay layer; The logical overlay layer is displayed in a second viewing window of the user interaction interface.

9. The method according to claim 8, characterized in that In response to the layer overlay operation on the at least two logic matrix bitmaps, performing a logical operation on the at least two logic matrix bitmaps to obtain a logic overlay layer includes: In response to a selection operation of at least two digital input / output pins, an address range, and a logic operation mode, at least two logic matrix bitmaps corresponding to the selected address range of the at least two digital input / output pins are obtained, and based on the selected logic operation mode, a logic operation is performed on the at least two logic matrix bitmaps to obtain the logic overlay layer, wherein the logic operation mode includes at least one of an AND operation, an OR operation, and an XOR operation.

10. The method according to claim 9, characterized in that The obtaining of at least two logic matrix bitmaps corresponding to the selected address ranges of the at least two digital input / output pins includes: In response to the selected address range belonging to the designated address range, acquiring test data corresponding to the selected address range of the at least two digital input and output pins from the target test data; In response to the selected address range not belonging to the designated address range, reading test data corresponding to the selected address range from a storage space for storing error address test data; The at least two logic matrix bitmaps are generated based on the test data corresponding to the selected address range.

11. The method according to claim 10, characterized in that The step of reading the test data corresponding to the selected address range from the storage space for storing error address test data includes: In response to the selected address range being larger than a display address range, reading compression test data corresponding to the selected address range, the display address range being an address range allowed to be displayed on the user interaction interface; In response to the selected address range being not larger than the display address range, original test data corresponding to the selected address range is read.

12. The method according to any one of claims 1 to 7, characterized in that: Displaying the physical matrix view in the view window of the user interaction interface includes: displaying a thumbnail physical matrix bitmap in a fourth area of the view window; In response to a selection operation on an address range in the thumbnail physical matrix bitmap, displaying a detailed physical matrix bitmap corresponding to the selected address range in a fifth area of the view window; In response to a drag operation on the detailed physical matrix bitmap, a selected address range in the thumbnail physical matrix bitmap is updated based on the dragged address range.

13. The method according to claim 12, characterized in that The method further comprises: In response to a zoom-in operation on the detailed physical matrix bitmap, zooming in on the detailed physical matrix bitmap; When the detailed physical matrix bitmap is enlarged to a target state, in response to a viewing operation on a target physical address, a logical address corresponding to the target physical address is displayed. The target state refers to a state in which one physical unit in the detailed physical matrix bitmap corresponds to one physical address.

14. The method according to any one of claims 1 to 7, characterized in that: The method further comprises: In response to a layer overlay operation on physical matrix bitmaps of at least two target test objects, the physical matrix bitmaps of the at least two target test objects are overlaid to obtain a physical overlay layer, wherein the at least two physical matrix bitmaps respectively correspond to error address test data of the same address range of the at least two target test objects; The physical overlay layer is displayed in a view window of the user interaction interface.

15. The method according to claim 14, characterized in that The method of superimposing the physical matrix bitmaps of the at least two target test objects in response to the layer superimposition operation on the physical matrix bitmaps of the at least two target test objects to obtain a physical superimposed layer includes: In response to the selection operation of at least two target test objects, address ranges and logical operation modes, at least two physical matrix bitmaps corresponding to the selected address ranges of the at least two target test objects are obtained, and based on the selected logical operation mode, a logical operation is performed on the at least two physical matrix bitmaps to obtain the physical overlay layer, wherein the logical operation mode includes at least one of an AND operation, an OR operation and an XOR operation.

16. The method according to any one of claims 1 to 7, characterized in that: The performing address conversion on the logical error address indicated by the target test data to obtain a physical error address includes: In response to a configuration operation on a data source configuration item on a user interaction interface, obtaining a configured logical data file and a conversion rule file, wherein the logical data file stores a logical error address indicated by the target test data, and the conversion rule file stores a conversion rule for converting a logical address into a physical address; In response to an address conversion operation, the logical error address is read from the logical data file and the conversion rule is read from the conversion rule file, and the logical error address is converted into a physical error address based on the conversion rule.

17. The method according to claim 16, characterized in that The method further comprises: Configure the file path and file name of the physical data source file; Storing the physical error address in a configured physical data source file; The displaying of a physical matrix bitmap in a view window of the user interaction interface based on the physical error address includes: Reading the physical error address from the physical data source file based on the configured file path and file name, and generating the physical matrix bitmap based on the physical error address; The physical matrix bitmap is displayed in a view window of the user interaction interface.

18. An electronic device, characterized in that: include: Memory for storing computer programs; A processor is used to execute the computer program stored in the memory, and when the computer program is executed, the method for obtaining and processing error address information described in any one of claims 1 to 17 is implemented.

Images