Apparatus, method and system for reducing handover jitter

Abstract

The invention relates to a device, a method and a system for reducing switching jitter. The device comprises a delay unit, and the delay unit comprises an input interface which is used for receiving at least three groups of input signals, and potential changes of the at least three groups of input signals on a transmission line correspond to different switching modes; the delay control module is used for performing logical operation and delay processing on each group of input signals according to different switching modes to obtain processed input signals; and the output interface is used for transmitting the processed input signal to a pre-stage driving and control circuit of the transmitter, so that the transmitter transmits at least three data signals to a receiver according to the processed input signal. Therefore, the switching delay of the data signal can be adjusted based on the selection of the optimal delay time, so that the switching jitter is reduced, the eye diagram window under the high-speed transmission condition is improved, and the data can be stably and reliably received and decoded.

Description

Technical Field

[0001] The present application relates to the field of power electronics technology, and in particular to a device, method and system for reducing switching jitter. Background Art

[0002] Mobile Industry Processor Interface (MIPI) is an open standard and specification initiated by the MIPI Alliance for processors used in mobile devices. C-PHY is the latest interface protocol of MIPI, which uses three wires to transmit signals. The voltages on the three wires are different, resulting in different line states, with a total of 6 states. According to the C-PHY protocol, the state of the signals A, B, and C driven on the corresponding lines (such as low, medium, and high) is used to convert to the next state to achieve encoding and decoding data.

[0003] In the conventional technology, the PU and PD signals of signals A, B and C are generated according to the signals decoded by the pre-drive and control circuit of the transmitter, namely PU_A, PU_B, PU_C, PD_A, PD_B and PD_C. Then the PU and PD signals of A, B and C are transmitted to the drive circuit of the transmitter, and the drive circuit finally outputs the three data signals A, B and C. Figure 3 As shown, the starting states of signals A, B and C are high, medium and low respectively. Figure 3 Five possible transitions to the next state are shown.

[0004] However, by Figure 3 It can be seen that there is inherent switching jitter in Mode 1 and Mode 2. If the driver of the driving signal has a slow conversion rate, the switching jitter will even be amplified, seriously affecting the eye opening for effective data transmission. Summary of the invention

[0005] Based on this, it is necessary to provide a device, method and system for reducing switching jitter that can effectively reduce the switching jitter of transmitter data signals in response to the above technical problems.

[0006] In a first aspect, the present application provides a device for reducing switching jitter, comprising:

[0007] An input interface, used to receive at least three groups of input signals, wherein potential changes of the at least three groups of input signals on the transmission lines correspond to different switching modes;

[0008] The delay control module is used to perform logic operations and delay processing on each group of input signals according to different switching modes to obtain processed input signals;

[0009] The output interface is used to transmit the processed input signal to the front-stage driving and control circuit of the transmitter, so that the transmitter sends at least three data signals to the receiver according to the processed input signal.

[0010] In one embodiment, the delay control module includes: a NOT gate, a NAND gate, a first delay controller, and a second delay controller, wherein:

[0011] The input end of the NOT gate constitutes the first input end of the delay control module, the output end of the NOT gate is respectively connected to the first input end of the NAND gate and the input end of the first delay controller, the output end of the first delay controller is connected to the second input end of the NAND gate, and the output end of the NAND gate constitutes the first output end of the delay control module;

[0012] The input end of the second delay controller constitutes the second input end of the delay control module, and the output end of the second delay controller constitutes the second output end of the delay control module.

[0013] In one embodiment, each set of input signals includes: a first input signal and a second input signal;

[0014] The first input signal is divided into two branch signals after passing through the NOT gate, the first branch signal is transmitted to the first input end of the NAND gate, the second branch signal is transmitted to the second input end of the NAND gate after passing through the first delay controller, and the output end of the NAND gate outputs the processed first input signal;

[0015] After the second input signal passes through the second delay controller, a processed second input signal is output.

[0016] In one embodiment, the processed first input signal and the processed second input signal are transmitted to the pre-stage driving and control circuit of the transmitter by the output interface, so that the pre-stage driving and control circuit of the transmitter performs logical operations on the processed first input signal and the processed second input signal and transmits them to the driving circuit of the transmitter, and the driving circuit generates a data signal.

[0017] In one of the embodiments, the delay control module is also used to: determine the delay times corresponding to the first delay controller and the second delay controller respectively according to the switching patterns of at least three groups of input signals on the transmission line, so as to adaptively eliminate the switching jitter associated with at least three data signals sent by the transmitter.

[0018] In one embodiment, each input signal of the at least three groups of input signals switches between two states of high potential and low potential, and each data signal of the at least three data signals switches between at least three logic states.

[0019] In a second aspect, the present application also provides a method for reducing switching jitter, comprising:

[0020] Receiving at least three groups of input signals, wherein potential changes of the at least three groups of input signals on the transmission lines correspond to different switching modes;

[0021] According to different switching modes, each group of input signals is subjected to logic operation and delay processing to obtain processed input signals;

[0022] The processed input signal is transmitted to the front-stage driving and control circuit of the transmitter, so that the transmitter sends at least three data signals to the receiver according to the processed input signal.

[0023] In one embodiment, performing logic operation and delay processing on each group of input signals according to different switching modes to obtain processed input signals includes:

[0024] Determine the delay times corresponding to the first delay controller and the second delay controller respectively according to the switching modes of at least three groups of input signals on the transmission line, so as to adaptively eliminate the switching jitter associated with at least three data signals sent by the transmitter;

[0025] The first input signal in each group of input signals is divided into two branch signals after passing through the NOT gate, the first branch signal is transmitted to the first input end of the NAND gate, the second branch signal is transmitted to the second input end of the NAND gate after passing through the first delay controller, and the output end of the NAND gate outputs the processed first input signal;

[0026] After the second input signal in each group of input signals passes through the second delay controller, a processed second input signal is output.

[0027] In one embodiment, the processed input signal is transmitted to a pre-stage driving and control circuit of a transmitter, so that the transmitter sends at least three data signals to a receiver according to the processed input signal, including:

[0028] The processed first input signal and the processed second input signal are transmitted to the front-stage driving and control circuit of the transmitter, so that the front-stage driving and control circuit of the transmitter performs a logic operation on the processed first input signal and the processed second input signal and transmits them to the driving circuit of the transmitter, and the driving circuit generates a data signal.

[0029] In one embodiment, according to the switching modes of at least three groups of input signals on the transmission line, respectively determining the delay times corresponding to the first delay controller and the second delay controller includes:

[0030] Setting initial values ​​of the delay times of the first delay controller and the second delay controller;

[0031] Measure the eye diagram of the transmitter’s output voltage;

[0032] The values ​​of the corresponding registers of the first delay controller and the second delay controller are adjusted respectively to change the delay time of the first delay controller and the second delay controller until the eye diagram window of the output voltage of the transmitter is maximized.

[0033] In one embodiment, each input signal of the at least three groups of input signals switches between two states of high potential and low potential, and each data signal of the at least three data signals switches between at least three logic states.

[0034] In a third aspect, the present application further provides a system for reducing switching jitter, the system comprising: a delay unit, the delay unit being coupled in a pre-stage driving and control circuit of a transmitter;

[0035] The delay unit comprises: a memory and a processor, the memory stores a computer program, and the processor implements the following steps when executing the computer program:

[0036] Receiving at least three groups of input signals, wherein potential changes of the at least three groups of input signals on the transmission lines correspond to different switching modes;

[0037] According to different switching modes, each group of input signals is subjected to logic operation and delay processing to obtain processed input signals;

[0038] The processed input signal is transmitted to the front-stage driving and control circuit of the transmitter, so that the transmitter sends at least three data signals to the receiver according to the processed input signal.

[0039] In a fourth aspect, the present application further provides a computer-readable storage medium having a computer program stored thereon, wherein when the computer program is executed by a processor, the following steps are implemented:

[0040] Receiving at least three groups of input signals, wherein potential changes of the at least three groups of input signals on the transmission lines correspond to different switching modes;

[0041] According to different switching modes, each group of input signals is subjected to logic operation and delay processing to obtain processed input signals;

[0042] The processed input signal is transmitted to the front-stage driving and control circuit of the transmitter, so that the transmitter sends at least three data signals to the receiver according to the processed input signal.

[0043] In a fifth aspect, the present application further provides a computer program product, including a computer program, which implements the following steps when executed by a processor:

[0044] Receiving at least three groups of input signals, wherein potential changes of the at least three groups of input signals on the transmission lines correspond to different switching modes;

[0045] According to different switching modes, each group of input signals is subjected to logic operation and delay processing to obtain processed input signals;

[0046] The processed input signal is transmitted to the front-stage driving and control circuit of the transmitter, so that the transmitter sends at least three data signals to the receiver according to the processed input signal.

[0047] The above-mentioned switching jitter reduction device, method, system, computer-readable storage medium and computer program product receive at least three groups of input signals, wherein the potential changes of the at least three groups of input signals on the transmission line correspond to different switching modes; thereby, the potential changes of the input signals on the respective transmission lines can be obtained. According to different switching modes, each group of input signals is subjected to logical operation and delay processing to obtain the processed input signal; thereby, the delay time of the corresponding input signal can be adaptively determined according to different switching modes, so that the input signal finally transmitted to the pre-stage drive and control circuit of the transmitter can adaptively eliminate the jitter caused by the switching of the input signal. The processed input signal is transmitted to the pre-stage drive and control circuit of the transmitter, so that the transmitter sends at least three data signals to the receiver according to the processed input signal. Thus, the switching delay of the data signal can be adjusted based on the selection of the optimal delay time, so as to reduce the switching jitter, improve the eye diagram window under high-speed transmission, and enable the data to be stably and reliably received and decoded. BRIEF DESCRIPTION OF THE DRAWINGS

[0048] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the related technologies, the drawings required for use in the embodiments of the present application or the related technical descriptions will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other related drawings can be obtained based on these drawings without paying creative work.

[0049] FIG1 is a schematic diagram of the structure of a transmission system in one embodiment;

[0050] FIG2 is a schematic diagram of the structure of a transmitter in one embodiment;

[0051] Figure 3Schematic diagram of five possible state transitions of three data signals A, B and C in one embodiment;

[0052] Figure 4 In one embodiment, when the switching state passes Figure 3 Schematic diagram of changes in signals DV and DM corresponding to signals A, B and C in modes 1, 2 and 5 shown in FIG.

[0053] Figure 5 is a schematic structural diagram of a device for reducing switching jitter in one embodiment;

[0054] Figure 6 is a schematic structural diagram of a transmitter in another embodiment;

[0055] Figure 7 is a schematic diagram of the structure of a delay unit in an embodiment;

[0056] Figure 8 For Figure 7 Schematic diagram of the delay effect of the signals DV and DM of the delay unit shown;

[0057] Fig. 9 A schematic diagram of signal changes in modes 1, 2, and 5 after applying a delay unit in one embodiment;

[0058] Fig.10 is a flow chart of a method for reducing switching jitter in an embodiment;

[0059] FIG11 is a schematic flow chart of a control method for two delay controllers in one embodiment;

[0060] FIG. 12 is a schematic diagram of the structure of a system for reducing switching jitter. DETAILED DESCRIPTION

[0061] In order to make the purpose, technical solution and advantages of the present application more clearly understood, the present application is further described in detail below in conjunction with the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application.

[0062] Exemplarily, FIG1 is a schematic diagram of the structure of a transmission system in an embodiment. As shown in FIG1 , the system includes: a transmitter TX, a receiver RX, and three transmission lines TL1, TL2, and TL3 interconnected by point-to-point lanes are provided between TX and RX. In this embodiment, TX can transmit three signals A, B, and C to RX through corresponding transmission lines TL1, TL2, and TL3. The voltages on TL1, TL2, and TL3 at the input end of RX are respectively recorded as VA, VB, and VC. In subsequent embodiments, in order to simplify the description, the voltages VA, VB, and VC may also be referred to as signals A, B, and C.

[0063] Exemplarily, FIG2 is a schematic diagram of the structure of a transmitter in an embodiment. As shown in FIG2, the pre-driver and control circuit (Pre-Drivers & Control Circuit) generates PU and PD signals (i.e., PU_A, PU_B, PU_C, PD_A, PD_B, PD_C) of signals A, B and C respectively according to the signals decoded by the pre-stage. Then, the PU and PD signals of A, B and C are transmitted to the driving circuit, and finally the driving circuit outputs three data signals A, B and C.

[0064] For example, Figure 3 Schematic diagram of five possible state transitions of three data signals A, B and C in one embodiment. According to the C-PHY protocol, data is encoded and decoded using the transition from the state (e.g., low, medium, high) of the signals A, B and C driven on the corresponding transmission lines to the next state. For example, the voltages on the signals A, B and C may be 3 / 4V, 1 / 2V and 1 / 4V, respectively, where V may represent the unit of voltage. In each unit interval (UI), the voltages of the signals A, B and C may be switched between 3 / 4V, 1 / 2V and 1 / 4V. Figure 3 As shown, the starting states of signals A, B and C are high, medium and low, respectively. Figure 3 Five possible switching modes are shown in Figure 1, where modes 1 and 2 are accompanied by inherent switching jitter, such as the misalignment of CA and BC switching in mode 1 and the misalignment of AB and CA switching in mode 2, which naturally introduce switching uncertainty. If the driver of the driving signal has a slow conversion rate, the switching jitter will even be amplified, seriously affecting the eye opening for effective data transmission.

[0065] For example, Figure 4 In one embodiment, when the switching state passes Figure 3 The schematic diagram of the changes of the signals DV and DM corresponding to the signals A, B and C in the modes 1, 2 and 5 shown in FIG. Figure 4As shown, in mode 1, signal A jumps from a high voltage to an intermediate voltage, signal B jumps from an intermediate voltage to a low voltage, and signal C jumps from a low voltage to a high voltage, so signals DV_A, DM_A, and DV_B jump from a low voltage to a high voltage, signals DM_B and DV_C jump from a high voltage to a low voltage, and signal DM_C remains at a low voltage; in mode 2, signal A jumps from an intermediate voltage to a high voltage, signal B jumps from a low voltage to an intermediate voltage, and signal C jumps from a high voltage to a low voltage, so signal DV _A, DM_A and DV_B jump from high voltage to low voltage, DM_B and DV_C jump from low voltage to high voltage, and DM_C remains at low voltage. In mode 5, A jumps from high voltage to low voltage, B maintains the intermediate voltage, and C jumps from low voltage to high voltage. Therefore, DV_A and DV_B jump from low voltage to high voltage, DV_C jumps from high voltage to low voltage, and DM_A, DM_B and DM_C remain unchanged. Figure 4 It can also be seen that there is inherent voltage switching jitter in modes 1 and 2.

[0066] For example, Figure 5 FIG. 1 is a schematic diagram of a structure of a device for reducing switching jitter in an embodiment. Figure 5 As shown, the device in this embodiment may include: a delay unit 510, the delay unit 510 includes: an input interface 511, a delay control module 512 and an output interface 513, wherein: the input interface 511 is used to receive at least three groups of input signals, wherein the potential changes of the at least three groups of input signals on the transmission line correspond to different switching modes; the delay control module 512 is used to perform logical operations and delay processing on each group of input signals according to different switching modes to obtain processed input signals; the output interface 513 is used to transmit the processed input signal to the pre-stage drive and control circuit of the transmitter, so that the transmitter sends at least three data signals to the receiver according to the processed input signal.

[0067] The delay unit included in the switching jitter reduction device in this embodiment can be coupled to the pre-driver and control circuit (Pre-Drivers) of the transmitter, thereby reducing the jitter caused by the C-PHY physical layer channel voltage switching. The delay unit adds different delay times according to the change of the signal data voltage.

[0068] For example, Figure 6 is a schematic diagram of the structure of a transmitter in another embodiment, which comprises Figure 5 The delay unit in the device shown. Figure 6As shown, the input signals DM and DV are processed by the delay unit and output two signals, which are recorded as the processed first input signal and the processed second input signal. Among them, the processed first input signal is transmitted to the second input end of the first NAND gate and the first input end of the second NAND gate respectively after passing through the first NOT gate; the processed second input signal is divided into two branches, the first branch is transmitted to the first input end of the first NAND gate, and the second branch is transmitted to the second input end of the second NAND gate after passing through the second NOT gate; the output end signal of the first NAND gate outputs the signal PU after passing through the third NOT gate, and the output signal of the second NAND gate is PV. Further, the signal PU is the control signal of the PMOS switch tube in the driving circuit, and the signal PV is the control signal of the NMOS switch tube in the driving circuit. The source of the PMOS switch tube is connected to the reference voltage terminal, the drain of the PMOS switch tube is connected to one end of the first resistor, the second end of the first resistor is connected to the first end of the second resistor, the second end of the second resistor is connected to the drain of the NMOS switch tube, and the source of the NMOS switch tube is grounded; the first end of the second resistor constitutes the output end of the driving circuit, which is used to output the data signal Vout.

[0069] Exemplarily, the delay control module 512 includes: a NOT gate, a NAND gate, a first delay controller, and a second delay controller, wherein: the input end of the NOT gate constitutes the first input end of the delay control module, the output end of the NOT gate is respectively connected to the first input end of the NAND gate and the input end of the first delay controller, the output end of the first delay controller is connected to the second input end of the NAND gate, and the output end of the NAND gate constitutes the first output end of the delay control module; the input end of the second delay controller constitutes the second input end of the delay control module, and the output end of the second delay controller constitutes the second output end of the delay control module.

[0070] In this embodiment, each group of input signals includes: a first input signal and a second input signal; the first input signal is divided into two branch signals after passing through the NOT gate, the first branch signal is transmitted to the first input end of the NAND gate, and the second branch signal is transmitted to the second input end of the NAND gate after passing through the first delay controller, and the output end of the NAND gate outputs the processed first input signal; the second input signal passes through the second delay controller and outputs the processed second input signal.

[0071] In this embodiment, the processed first input signal and the processed second input signal are transmitted to the pre-stage driving and control circuit of the transmitter by the output interface, so that the pre-stage driving and control circuit of the transmitter performs logical operations on the processed first input signal and the processed second input signal and transmits them to the driving circuit of the transmitter, and the driving circuit generates a data signal.

[0072] For example, Figure 7 FIG. 1 is a schematic diagram of the structure of a delay unit in an embodiment. Figure 7 As shown in the figure, DL_A and DL_B are two delay controllers, and different delay times can be set by modifying the registers. After some logic operations and delay controllers, the input signals DM and DV are output as DM_d and DV_d. Figure 8 As shown in , the rising edge or falling edge of the input signal DV will pass through the delay controller DL_A to obtain the delayed DV_d, the rising edge of the input signal DM will not be delayed, and the falling edge will pass through the delay controller DL_B to obtain the delayed DM_d falling edge.

[0073] In this embodiment, the delay control module 512 is also used to: determine the delay times corresponding to the first delay controller and the second delay controller respectively according to the switching patterns of at least three groups of input signals on the transmission line, so as to adaptively eliminate the switching jitter associated with at least three data signals sent by the transmitter.

[0074] Wherein, each input signal of the at least three groups of input signals switches between two states of high potential and low potential, and each data signal of the at least three data signals switches between at least three logic states.

[0075] For example, Fig. 9 FIG. 1 is a schematic diagram of signal changes in modes 1, 2, and 5 after applying a delay unit in one embodiment. Fig. 9 As shown, ta is the delay time of the delay controller DL_A, and tb is the delay time of the delay controller DL_B. Figure 8 The delay unit functions to ultimately generate delayed signals DV_A_d, DV_B_d, DV_C_d, DM_A_d, DM_B_d, and DM_C_d of signals A, B, and C.

[0076] For example, Fig. 9 As shown, in switching mode 1, the rising edge of the delay signal DV_A_d and the delay signal DV_B_d and the falling edge of the delay signal DV_C_d are delayed by ta time, the rising edge of the delay signal DM_A_d is not delayed, the falling edge of the delay signal DM_B_d is delayed by tb time, and the delay signal DM_C_d remains unchanged, so the VA voltage jump point remains unchanged, the VB voltage switching point is delayed by tb time, and the VC voltage switching point is delayed by ta time.

[0077] Exemplarily, in switching mode 2, the falling edges of the delay signal DV_A_d and the delay signal DV_B_d and the rising edge of DV_C_d are delayed by ta time, the falling edge of the delay signal DM_A_d is delayed by tb time, the rising edge of the delay signal DM_B_d is not delayed, and the delay signal DM_C_d remains unchanged. Therefore, the voltage jump point of VA is delayed by tb time, the voltage jump point of VB remains unchanged, and the voltage jump point of VC is delayed by ta time.

[0078] Exemplarily, in switching mode 3, the rising edge of the delay signal DV_A_d and the delay signal DV_B_d and the falling edge of the delay signal DV_C_d are delayed by ta time, and the delay signal DM_A_d, the delay signal DM_B_d and the delay signal DM_C_d remain unchanged, so the voltage jump point of VA is delayed by ta time, the voltage jump point of VB remains unchanged, and the voltage jump point of VC is delayed by ta time.

[0079] For example, Fig. 9 As shown in , by adjusting the delay times ta and tb, the differences between the AB, BC and CA voltage switching points in Mode 1 and Mode 2 can be eliminated, thereby eliminating the switching jitter.

[0080] The above-mentioned switching jitter reduction device receives at least three groups of input signals, wherein the potential changes of the at least three groups of input signals on the transmission line correspond to different switching modes; thereby, the potential changes of the input signals on the respective transmission lines can be obtained. According to different switching modes, each group of input signals is subjected to logical operations and delay processing to obtain processed input signals; thereby, the delay time of the corresponding input signals can be adaptively determined according to different switching modes, so that the input signals finally transmitted to the pre-stage driving and control circuits of the transmitter can adaptively eliminate the jitter caused by the switching of the input signals. The processed input signals are transmitted to the pre-stage driving and control circuits of the transmitter, so that the transmitter sends at least three data signals to the receiver according to the processed input signals. Thus, the switching delay of the data signal can be adjusted based on the selection of the optimal delay time, so as to reduce the switching jitter, improve the eye diagram window under high-speed transmission conditions, and enable the data to be stably and reliably received and decoded.

[0081] In an exemplary embodiment, Fig.10 As shown, a method for reducing switching jitter is provided, and the method is applied to Figure 5 The delay unit in FIG. 1 is taken as an example to illustrate, and the method includes the following steps 1001 to 1003. Among them:

[0082] Step 1001: Receive at least three groups of input signals.

[0083] Wherein, the potential changes of the at least three groups of input signals on the transmission line correspond to different switching modes.

[0084] In this embodiment, it can be applied to data signal transmission of the C-PHY protocol, where C-PHY is the latest interface protocol of MIPI, which uses three lines to transmit signals. The voltages on the three lines are different, resulting in different line states, with a total of 6 states. According to the C-PHY protocol, the state of signals A, B, and C driven on the corresponding lines (for example, low, medium, and high) is converted to the next state to achieve encoding and decoding of data. For example, the voltages on signals A, B, and C can be 3 / 4V, 1 / 2V, and 1 / 4V, respectively, where V can represent the unit of voltage. In each unit interval (UI), the voltages of signals A, B, and C can be switched between 3 / 4V, 1 / 2V, and 1 / 4V. For example, see Figure 3 As shown, the voltages of signals A, B and C can be switched in a variety of different ways.

[0085] Step 1002: Perform logic operation and delay processing on each group of input signals according to different switching modes to obtain processed input signals.

[0086] In this embodiment, due to the combination of the voltage switching states on the transmission line, there may be five corresponding switching modes. For different switching modes, the delay time may be set in advance.

[0087] Exemplarily, according to the switching patterns of at least three groups of input signals on the transmission line, the delay times corresponding to the first delay controller and the second delay controller are respectively determined to adaptively eliminate the switching jitter associated with at least three data signals sent by the transmitter; the first input signal in each group of input signals is divided into two branch signals after passing through the NOT gate, the first branch signal is transmitted to the first input end of the NAND gate, and the second branch signal is transmitted to the second input end of the NAND gate after passing through the first delay controller, and the output end of the NAND gate outputs the processed first input signal; the second input signal in each group of input signals passes through the second delay controller, and the processed second input signal is output.

[0088] In this embodiment, the processed first input signal and the processed second input signal are transmitted to the front-stage driving and control circuit of the transmitter, so that the front-stage driving and control circuit of the transmitter performs logical operations on the processed first input signal and the processed second input signal and transmits them to the driving circuit of the transmitter, and the driving circuit generates a data signal.

[0089] In an exemplary embodiment, as shown in FIG11 , determining the delay times corresponding to the first delay controller and the second delay controller respectively according to the switching modes of at least three groups of input signals on the transmission line may include the following steps:

[0090] Step 1101, setting the initial value of the delay time of the first delay controller and the second delay controller.

[0091] Step 1102, measuring an eye diagram of an output voltage of a transmitter;

[0092] Step 1103, respectively adjusting the values ​​of the corresponding registers of the first delay controller and the second delay controller to change the delay time of the first delay controller and the second delay controller.

[0093] Step 1104, determine whether the eye diagram window of the output voltage of the transmitter has reached the maximum, if not, return to step 1103; if yes, end the process.

[0094] In this embodiment, the initial values ​​of the delay times of the first delay controller and the second delay controller are set, and then the eye diagram of the output voltage of the transmitter is measured; the values ​​of the corresponding registers of the first delay controller and the second delay controller are adjusted respectively to change the delay times of the first delay controller and the second delay controller until the eye diagram window of the output voltage of the transmitter is maximized.

[0095] Exemplary, combined Figure 7 Taking the delay unit shown in the figure as an example, the delay time of the delay controllers DL_A and DL_B can be set to the initial value (assuming it is 0), and then the eye diagram of the output voltage is measured. Next, the register of the delay controller is adjusted to change the delay time of DL_A and DL_B, and the eye diagram of the output voltage is tested at the same time. Finally, the register value when the eye diagram window is the largest is selected as the delay time of the delay controllers DL_A and DL_B. In this case, the switching delay of the data signal can be adjusted based on the selection of the optimal delay time to reduce the switching jitter and increase the eye diagram window under high-speed transmission, so that the data can be stably and reliably received and decoded.

[0096] Step 1003: transmit the processed input signal to the front-stage driving and control circuit of the transmitter, so that the transmitter sends at least three data signals to the receiver according to the processed input signal.

[0097] In this embodiment, each input signal of the at least three groups of input signals switches between two states of high potential and low potential, and each data signal of the at least three data signals switches between at least three logic states.

[0098] It should be noted that although three data signals are used as an example in this embodiment, when more than three data signals are used as outputs, a delay unit can be added in a similar manner, that is, each group of input signals corresponds to a delay unit for delay processing, thereby obtaining a data signal with switching jitter eliminated.

[0099] In the above-mentioned method for reducing switching jitter, at least three groups of input signals are received, wherein the potential changes of the at least three groups of input signals on the transmission line correspond to different switching modes; thereby, the potential changes of the input signals on the respective transmission lines can be obtained. According to different switching modes, each group of input signals is subjected to logical operations and delay processing to obtain processed input signals; thereby, the delay time of the corresponding input signals can be adaptively determined according to different switching modes, so that the input signals finally transmitted to the pre-stage driving and control circuits of the transmitter can adaptively eliminate the jitter caused by the switching of the input signals. The processed input signals are transmitted to the pre-stage driving and control circuits of the transmitter, so that the transmitter sends at least three data signals to the receiver according to the processed input signals. Thus, the switching delay of the data signal can be adjusted based on the selection of the optimal delay time, so as to reduce the switching jitter, improve the eye diagram window under high-speed transmission conditions, and enable the data to be stably and reliably received and decoded.

[0100] It should be understood that, although the various steps in the flowcharts involved in the above-mentioned embodiments are displayed in sequence according to the indication of the arrows, these steps are not necessarily executed in sequence according to the order indicated by the arrows. Unless there is a clear explanation in this article, the execution of these steps does not have a strict order restriction, and these steps can be executed in other orders. Moreover, at least a part of the steps in the flowcharts involved in the above-mentioned embodiments can include multiple steps or multiple stages, and these steps or stages are not necessarily executed at the same time, but can be executed at different times, and the execution order of these steps or stages is not necessarily to be carried out in sequence, but can be executed in turn or alternately with other steps or at least a part of the steps or stages in other steps.

[0101] In an exemplary embodiment, as shown in FIG12 , a system for reducing switching jitter is provided, the system comprising: a delay unit 1210, the delay unit being coupled in a pre-stage driving and control circuit of a transmitter; the delay unit comprising: a memory 1211 and a processor 1212, the memory 1211 storing a computer program, and the processor 1212 implementing the steps of the method in the above embodiment when executing the computer program.

[0102] In one embodiment, a computer-readable storage medium is provided, on which a computer program is stored. When the computer program is executed by a processor, the steps in the above-mentioned method embodiments are implemented.

[0103] In one embodiment, a computer program product is provided, including a computer program, which implements the steps in the above method embodiments when executed by a processor.

[0104] It should be noted that the user information (including but not limited to user device information, user personal information, etc.) and data (including but not limited to data used for analysis, stored data, displayed data, etc.) involved in this application are all information and data authorized by the user or fully authorized by all parties, and the collection, use and processing of relevant data must comply with relevant regulations.

[0105] A person of ordinary skill in the art can understand that all or part of the processes in the above-mentioned embodiment method can be completed by instructing the relevant hardware through a computer program, and the computer program can be stored in a non-volatile computer-readable storage medium. When the computer program is executed, it can include the processes of the embodiments of the above-mentioned methods. Among them, any reference to the memory, database or other medium used in the embodiments provided in the present application can include at least one of non-volatile memory and volatile memory. Non-volatile memory can include read-only memory (ROM), magnetic tape, floppy disk, flash memory, optical memory, high-density embedded non-volatile memory, resistive random access memory (ReRAM), magnetic random access memory (MRAM), ferroelectric random access memory (FRAM), phase change memory (PCM), graphene memory, etc. Volatile memory can include random access memory (RAM) or external cache memory, etc. As an illustration and not limitation, RAM can be in various forms, such as static random access memory (SRAM) or dynamic random access memory (DRAM). The database involved in each embodiment provided in this application may include at least one of a relational database and a non-relational database. Non-relational databases may include distributed databases based on blockchains, etc., but are not limited to this. The processor involved in each embodiment provided in this application may be a general-purpose processor, a central processing unit, a graphics processor, a digital signal processor, a programmable logic device, a data processing logic device based on quantum computing, an artificial intelligence (AI) processor, etc., but are not limited to this.

[0106] The technical features of the above embodiments may be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this application.

[0107] The above-described embodiments only express several implementation methods of the present application, and the descriptions thereof are relatively specific and detailed, but they cannot be understood as limiting the scope of the present application. It should be pointed out that, for a person of ordinary skill in the art, several variations and improvements can be made without departing from the concept of the present application, and these all belong to the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the attached claims.

Claims

1. A device for reducing switching jitter, characterized in that: The device comprises: a delay unit, wherein the delay unit comprises: An input interface, used to receive at least three groups of input signals, wherein potential changes of the at least three groups of input signals on the transmission lines correspond to different switching modes; The delay control module is used to perform logic operations and delay processing on each group of input signals according to different switching modes to obtain processed input signals; The output interface is used to transmit the processed input signal to the front-stage driving and control circuit of the transmitter, so that the transmitter sends at least three data signals to the receiver according to the processed input signal.

2. The device according to claim 1, characterized in that The delay control module includes: a NOT gate, a NAND gate, a first delay controller, and a second delay controller, wherein: The input end of the NOT gate constitutes the first input end of the delay control module, the output end of the NOT gate is respectively connected to the first input end of the NAND gate and the input end of the first delay controller, the output end of the first delay controller is connected to the second input end of the NAND gate, and the output end of the NAND gate constitutes the first output end of the delay control module; The input end of the second delay controller constitutes the second input end of the delay control module, and the output end of the second delay controller constitutes the second output end of the delay control module.

3. The device according to claim 2, characterized in that Each group of input signals includes: a first input signal and a second input signal; The first input signal is divided into two branch signals after passing through the NOT gate, the first branch signal is transmitted to the first input end of the NAND gate, the second branch signal is transmitted to the second input end of the NAND gate after passing through the first delay controller, and the output end of the NAND gate outputs the processed first input signal; After the second input signal passes through the second delay controller, a processed second input signal is output.

4. The device according to claim 3, characterized in that The processed first input signal and the processed second input signal are transmitted to the pre-stage driving and control circuit of the transmitter by the output interface, so that the pre-stage driving and control circuit of the transmitter performs logical operations on the processed first input signal and the processed second input signal and transmits them to the driving circuit of the transmitter, and the driving circuit generates a data signal.

5. The device according to any one of claims 2 to 4, characterized in that: The delay control module is also used to: determine the delay times corresponding to the first delay controller and the second delay controller respectively according to the switching modes of at least three groups of input signals on the transmission line, so as to adaptively eliminate the switching jitter associated with at least three data signals sent by the transmitter.

6. The device according to any one of claims 1 to 4, characterized in that: Each input signal of the at least three groups of input signals switches between two states of high potential and low potential, and each data signal of the at least three data signals switches between at least three logic states.

7. A method for reducing switching jitter, characterized in that: The method comprises: Receiving at least three groups of input signals, wherein potential changes of the at least three groups of input signals on the transmission lines correspond to different switching modes; According to different switching modes, each group of input signals is subjected to logic operation and delay processing to obtain processed input signals; The processed input signal is transmitted to the front-stage driving and control circuit of the transmitter, so that the transmitter sends at least three data signals to the receiver according to the processed input signal.

8. The method according to claim 7, characterized in that According to different switching modes, each group of input signals is subjected to logic operation and delay processing to obtain processed input signals, including: Determine the delay times corresponding to the first delay controller and the second delay controller respectively according to the switching modes of at least three groups of input signals on the transmission line, so as to adaptively eliminate the switching jitter associated with at least three data signals sent by the transmitter; The first input signal in each group of input signals is divided into two branch signals after passing through the NOT gate, the first branch signal is transmitted to the first input end of the NAND gate, the second branch signal is transmitted to the second input end of the NAND gate after passing through the first delay controller, and the output end of the NAND gate outputs the processed first input signal; After the second input signal in each group of input signals passes through the second delay controller, a processed second input signal is output.

9. The method according to claim 8, characterized in that The processed input signal is transmitted to a front-stage driving and control circuit of the transmitter, so that the transmitter sends at least three data signals to the receiver according to the processed input signal, including: The processed first input signal and the processed second input signal are transmitted to the front-stage driving and control circuit of the transmitter, so that the front-stage driving and control circuit of the transmitter performs a logic operation on the processed first input signal and the processed second input signal and transmits them to the driving circuit of the transmitter, and the driving circuit generates a data signal.

10. The method according to claim 8, characterized in that Determining the delay times corresponding to the first delay controller and the second delay controller respectively according to the switching modes of at least three groups of input signals on the transmission line, including: Setting initial values ​​of the delay times of the first delay controller and the second delay controller; Measure the eye diagram of the transmitter’s output voltage; The values ​​of the corresponding registers of the first delay controller and the second delay controller are adjusted respectively to change the delay time of the first delay controller and the second delay controller until the eye diagram window of the output voltage of the transmitter is maximized.

11. The method according to any one of claims 7 to 10, characterized in that: Each input signal of the at least three groups of input signals switches between two states of high potential and low potential, and each data signal of the at least three data signals switches between at least three logic states.

12. A system for reducing switching jitter, characterized in that: The system includes: a delay unit coupled in a pre-stage drive and control circuit of a transmitter; The delay unit comprises: a memory and a processor, wherein the memory stores a computer program, and the processor implements the steps of the method according to any one of claims 7 to 11 when executing the computer program.

13. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 7 to 11 are implemented.

14. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 7 to 11 are implemented.

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