DMA device, data processing system and DMA device execution state detection method

Abstract

The embodiment of the invention discloses a DMA device, a data processing system and a DMA device execution state detection method, relates to the technical field of data processing, and is convenient for saving the resource overhead of a processor. The DMA device comprises a byte counter which is configured to track and control the data transmission length during data carrying and transmission; and the fault detection module is connected with the byte counter and is at least configured to detect whether the execution state of the data carrying transmission task is normal or not according to the data transmission length. By adding the fault detection module in the DMA device, the DMA device can be independent of the processor to perform exception monitoring of the execution state, so that the resource overhead of the processor is saved. The method and the device are suitable for DMA fault detection and data processing scenes.

Description

Technical Field

[0001] The present application relates to the field of data processing technology, and in particular to a DMA device, a data processing system and a DMA device execution status detection method. Background Art

[0002] As the scale of large AI models continues to expand, the demand for computing resources has also increased dramatically. A single graphics processing unit (GPU) can no longer meet the training needs of large training models, and multi-card interconnection technology has emerged and gradually become mainstream. However, as the bandwidth of multi-card interconnection continues to increase, the capacity of a single direct memory access (DMA) device in a traditional chip has gradually become a bottleneck. Some chip manufacturers have begun to integrate multiple DMA devices (generally referred to as DMA in the industry) to improve data transmission efficiency. Due to the influence of factors such as high-pressure environment and long-term use of chips, DMA devices may age or other failures.

[0003] In some related technologies, the processor detects DMA device failures when starting the DMA device to perform data transfer. However, when there are many DMA devices and the DMA devices perform a large amount of tasks, the processor needs to create a detection thread for each task, which consumes more processor resources. Summary of the invention

[0004] In view of this, the embodiments of the present application provide a DMA device, a data processing system and a DMA device execution status detection method, so as to save processor resource overhead.

[0005] In order to achieve the above application purpose, the following technical solutions are adopted: The embodiment of the present application provides a DMA device, comprising: a byte counter configured to track and control the data transmission length during data handling transmission; The fault detection module is connected to the byte counter and is at least configured to detect whether the execution status of the data handling transmission task is normal according to the data transmission length.

[0006] According to a specific implementation of the embodiment of the present application, the fault detection module includes: a counting detection module connected to the byte counter and configured to periodically read the data transmission length from the byte counter; Whether the execution status of the data handling and transmission task is normal is determined based on the consistency comparison result of the data transmission lengths of two adjacent cycles.

[0007] According to a specific implementation of the embodiment of the present application, the fault detection module includes: a counting detection module connected to the byte counter and configured to periodically read the data transmission length from the byte counter; Performing consistency comparison according to the data transmission lengths of two adjacent cycles; If they are consistent, it is determined that the execution state of the data handling and transmission task is abnormal, and the detection is suspended; If they are inconsistent, it is determined that the execution status of the data handling and transmission task is normal and the detection continues.

[0008] According to a specific implementation method of the embodiment of the present application, the counting detection module is also configured to generate and report a first fault interrupt signal at the same time or after the pause detection; the first fault interrupt signal is used to notify the processor that the execution status of the DMA device is abnormal.

[0009] According to a specific implementation of the embodiment of the present application, the counting detection module is further configured to resume detecting the execution status of the current data handling and transmission task after generating and reporting the first fault interrupt signal; If it is detected that the execution status of the current data handling and transmission task is abnormal again, a second fault interrupt signal is generated and reported.

[0010] According to a specific implementation of the embodiment of the present application, the DMA device further includes: a status register configured to record the execution status during data handling and transmission; The status register is connected to the fault detection module, and the fault detection module is further configured to read the execution status during the data handling and transmission from the status register and determine whether the execution status is normal.

[0011] In a second aspect, the present application also provides a data processing system, including: a DMA device, the DMA device including: a fault detection module, connected to the processor, at least configured to detect whether the execution state of the data handling transmission task is normal according to the data transmission length, and send a fault interrupt signal to the processor when the execution state is detected to be abnormal; The processor is at least configured to determine whether a fault occurs in the DMA device according to the fault interrupt signal.

[0012] According to a specific implementation method of an embodiment of the present application, the DMA device includes multiple devices, and the fault interrupt signal includes: a first fault interrupt signal, and the processor is further configured to retain the data transfer task executed by the current DMA device and unload the data transfer tasks executed by the remaining DMA devices according to the first fault interrupt signal.

[0013] According to a specific implementation method of an embodiment of the present application, the processor is also configured to send a recovery fault detection control signal to the current DMA device after receiving the first fault interrupt signal, so that the DMA device can restore the detection of the execution status of the current data handling and transmission task according to the recovery fault detection control signal; if the second fault interrupt signal reported by the fault detection module is received again, it is determined that the DMA device has a fault.

[0014] According to a specific implementation method of an embodiment of the present application, the processor is also configured to migrate the data transfer task performed by the failed DMA device to at least one of the remaining DMA devices for processing after determining that the DMA device has failed, and record the failed DMA device in a non-volatile memory.

[0015] In a third aspect, the present application also provides a DMA device execution state detection method according to an embodiment, including: Periodically read the data transfer length during the data handling transfer of the DMA device; According to the consistency comparison result of the data transmission lengths of two adjacent cycles, it is judged whether the execution status of the data handling and transmission task of the DMA device is normal.

[0016] According to a specific implementation of the embodiment of the present application, judging whether the execution state of the data handling and transmission task of the DMA device is normal according to the consistency comparison result of the data transmission lengths of two adjacent cycles includes: performing consistency comparison according to the data transmission lengths of two adjacent cycles; if they are consistent, judging that the execution state of the data handling and transmission task of the DMA device is abnormal; If they are inconsistent, it is determined that the execution status of the data handling and transmission task of the DMA device is normal.

[0017] According to a specific implementation of the embodiment of the present application, after determining whether the execution state of the data handling and transmission task of the DMA device is normal, the method further includes: if it is determined that the execution state of the data handling and transmission task of the DMA device is abnormal, suspending detection, generating a first fault interrupt signal and reporting it; the first fault interrupt signal is used to indicate that the execution state of the DMA device is abnormal; If it is determined that the execution status of the data handling and transmission task of the DMA device is normal, continue to detect.

[0018] According to a specific implementation of the embodiment of the present application, after the first fault interrupt signal is generated and reported, the method further includes: recovering and detecting the execution status of the current data handling and transmission task; If it is detected that the execution state of the current data handling and transmission task is abnormal again, a second fault interrupt signal is generated.

[0019] According to a specific implementation method of an embodiment of the present application, before restoring the execution status of the current data handling and transmission task, the method also includes: according to the first fault interrupt signal, retaining the data handling task executed by the current DMA device, and unloading the data handling tasks executed by the remaining DMA devices.

[0020] According to a specific implementation method of an embodiment of the present application, after generating a second fault interrupt signal, the method also includes: determining that the DMA device has a fault based on the second fault interrupt signal, migrating the data transfer task performed by the faulty DMA device to at least one of the remaining DMA devices for processing, and recording the faulty DMA device in a non-volatile memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying creative work.

[0022] Figure 1 This is a schematic diagram of a typical DMA transmission scenario; Figure 2 It is a typical structural diagram of a DMA device according to an embodiment; Figure 3 This is a schematic block diagram of the DMA device structure according to an embodiment of the present application; Figure 4 This is a schematic diagram of a DMA device execution state abnormality detection process according to an embodiment of the present application; Figure 5 This is a schematic block diagram of the structure of a data processing system composed of a DMA device and a processor according to another embodiment of the present application; Figure 6 This is a schematic diagram of a DMA device execution state abnormality detection process according to another embodiment of the present application; Figure 7 This is a schematic block diagram of the structure of a DMA device according to another embodiment of the present application; Figure 8 This is a schematic block diagram of the structure of a data processing system according to an embodiment of the present application; Fig. 9 A schematic diagram of a data processing flow chart of a data processing system according to an embodiment of the present application; Fig.10 This is a flow chart of a DMA device execution status detection method according to an embodiment of the present application. DETAILED DESCRIPTION

[0023] The embodiments of the present application are described in detail below with reference to the accompanying drawings.

[0024] It should be clear that the described embodiments are only part of the embodiments of the present application, rather than all the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in the field without creative work are within the scope of protection of the present application.

[0025] As the core of electronic devices with data processing functions, the processor has the functions of transferring data, calculating, and controlling program transfer. When the electronic device is in operation, the processor needs to handle a large number of transactions. In order to save the processor's resource overhead, for the processing of some tasks, such as data transmission, DMA devices can be used to provide high-speed data transmission between peripherals and memory or between memory and memory, such as Figure 1 In this way, without the intervention of the processor, the data can be quickly transferred by directly accessing the data through the DMA device, thereby saving the processor's resource overhead.

[0026] DMA devices may experience aging and other faults under high-pressure environments or after long-term use, resulting in abnormal task execution status. In some related technical solutions, the existing fault detection solution is mainly handled by the processor. When starting DMA to execute data transfer, a timeout threshold is set for each data transfer command. The processor periodically detects whether each data transfer command is completed within the preset time. If not, it is determined that the DMA has a fault. However, by detecting the time of each data transfer to determine whether there is a fault, when the number of DMA devices is large and the amount of transfer tasks to be executed is large, the CPU resources will be consumed sharply because the processor driver will create a detection thread for each task.

[0027] like Figure 2As shown in the figure, the internal structure of a typical DMA device mainly includes registers and counters, namely, control register, address register, status register and byte counter. The control register is used to select the operation type, working mode and transmission direction of the DMA device, so as to flexibly configure the working mode of the DMA device according to different application requirements. The address register includes the source address register and the destination address register, which are used to store the starting address and the destination address of the data transmission respectively, so as to ensure that the data can be accurately transferred from the source location to the destination location. The status register is used to record the status information of the DMA transmission process, including whether the current transmission is in progress, whether it is completed, and whether an error occurs. This information is crucial for subsequent data processing and system monitoring. The byte counter is used to track and control the length of the transmission data block, so as to ensure that the amount of data transferred each time can be accurately managed during the data handling process. When the peripheral needs to transfer data between the memory and the memory, the DMA device first makes a bus request to the processor. After obtaining the processor authorization, the DMA device starts the data transmission process and coordinates the data flow by controlling each register. This process enables the DMA device to achieve efficient data handling and transmission without the intervention of the processor, thereby significantly saving processor resources.

[0028] Figure 3 The schematic diagram of the structure of the improved DMA device of an embodiment of the present application is shown. Compared with the typical DMA structure, the DMA device provided in the embodiment of the present application has an internal fault detection module, which enables the DMA to not only perform high-speed data transmission, but also monitor its own execution status in real time to see if it is abnormal, and promptly discover and handle potential faults, saving the processor's resource overhead of creating a detection process for each DMA device, and improving the performance of the overall system.

[0029] See also Figure 3 and Figure 4 Specifically, the DMA device provided in the embodiment of the present application includes: a byte counter and a fault detection module. The byte counter is configured to track and control the data transmission length during the data handling transmission. Specifically, the byte counter can automatically update its count value after each data transmission is completed to record the number of data bytes that have been successfully transmitted.

[0030] The fault detection module is connected to the byte counter and is at least configured to detect whether the execution status of the data handling task is normal according to the data transmission length recorded by the byte counter. The fault detection module determines whether the current data handling task is performed as expected by regularly reading the data transmission length in the byte counter to determine whether the execution status of the DMA device is normal.

[0031] In this embodiment, by adding a fault detection module inside the DMA device, the DMA device can perform abnormality monitoring of the execution state independently of the processor, thereby saving the resource overhead of the processor to create a detection process.

[0032] It should be noted that, in this embodiment, the DMA device can perform abnormal monitoring of the execution state independently of the processor, and does not exclude the cooperation of the two to achieve abnormal monitoring. When necessary, the DMA device can also cooperate with the processor to perform fault detection of the DMA device.

[0033] In a specific implementation, a detection cycle can be configured for the fault detection module, for example, the value of the byte counter is read every 100 milliseconds. During the reading process, if it is found that the data transmission length in the current cycle has not changed compared with the previous cycle, it can be inferred that there may be a problem, such as data failure to be successfully transmitted or a system failure, which enables the DMA device to detect potential problems in time and take corresponding measures.

[0034] For example, when the fault detection module detects that the data transmission length has not changed, it will generate a fault interrupt signal and report the signal to the processor. After receiving the signal, the processor can start the corresponding fault handling program to quickly locate and solve the problem, ensuring that the system can respond quickly when an abnormality occurs, thereby improving the reliability of data transmission.

[0035] Specifically, the fault detection module can be implemented by a program or by a circuit. For example, when the fault detection module is implemented by a circuit, the fault detection module can be implemented by a comparator or a subtractor.

[0036] The DMA device provided in the embodiment of the present application improves its own internal structure and adds a fault detection module internally to monitor the data transfer status of the DMA device. Compared with some technical solutions in which the processor creates a detection process to implement fault detection of the DMA device, it is convenient to save processor resource overhead, thereby improving the performance of the overall system.

[0037] In some technical solutions for performing DMA device fault detection by a processor, the fault detection of the DMA device usually relies on setting a preset time threshold and comparing the byte counter value of each cycle with the preset time threshold. However, this method of setting a fixed threshold lacks dynamic adaptability and may have the problem of difficulty in capturing short-term execution state anomalies.

[0038] In some embodiments, the fault detection module includes a counting detection module, which is connected to the byte counter and configured to periodically read the data transmission length from the byte counter; based on the consistency comparison result of the data transmission length of two adjacent cycles, it is judged whether the execution status of the data handling and transmission task is normal.

[0039] The counting detection module is driven by a clock signal to obtain the current value of the byte counter at a fixed time interval (detection cycle) so as to perform a subsequent consistency comparison based on the data transmission length of two adjacent cycles, and then determine whether the execution status of the data handling and transmission task is normal. In this way, by comparing the consistency of the data transmission length of two adjacent cycles, even short-term anomalies can be captured.

[0040] See also Figure 5 and Figure 6 In some other embodiments, the fault detection module includes: a counting detection module, connected to the byte counter, and configured to periodically read the data transmission length from the byte counter; perform consistency comparison based on the data transmission lengths of two adjacent cycles; if they are consistent, it is determined that the execution status of the data handling and transmission task is abnormal and the detection is suspended; if they are inconsistent, it is determined that the execution status of the data handling and transmission task is normal and the detection is continued.

[0041] Specifically, the specific implementation method of suspending detection is: updating the value in the detection period register to infinity, thereby temporarily suspending detection.

[0042] In this embodiment, at the end of each cycle, the counting detection module compares the data transmission length read in the current cycle with the data transmission length of the previous cycle for consistency. Specifically, the counting detection module can use a digital comparator circuit to compare the byte count values ​​of the current cycle and the previous cycle. If the two are equal, it means that no data transmission occurs during the time period, which may indicate that there is a fault. If they are consistent, the counting detection module will determine that the execution state of the data handling transmission task is abnormal and suspend subsequent fault detection. Specifically, it can be achieved by setting a status flag bit, which indicates that it is currently in an "abnormal state". In this state, the fault detection module will temporarily stop detecting the next cycle to avoid frequently triggering interrupt signals, thereby reducing the system burden. If they are inconsistent, the counting detection module will determine that the execution state of the data handling transmission task is normal, and continue to perform subsequent fault detection. In this case, the counting detection module will update the status flag bit to "normal" and prepare to continue reading the data transmission length of the byte counter in the next cycle.

[0043] In addition, in the solution of executing DMA device detection through the processor, if data congestion occurs on the link, it is also possible that the data transfer task cannot be completed within the preset time threshold, and a false alarm of DMA device failure may occur.

[0044] In order to further improve the reliability of fault detection, the counting detection module is also configured to generate and report a first fault interrupt signal while or after suspending detection; the first fault interrupt signal is used to notify the processor that the execution state of the DMA device is abnormal.

[0045] Specifically, when the counting detection module finds that the data transmission lengths of two adjacent cycles are consistent and have not changed, it will trigger a status flag to indicate that it is currently in an "abnormal state". At this time, the counting detection module will immediately generate a first fault interrupt signal and report the signal to the processor through the interrupt controller to notify its DMA device of a possible execution state abnormality. After receiving the first fault interrupt signal, the processor can perform corresponding processing according to the specific situation, such as recording logs, adjusting data transmission strategies, or performing other fault recovery operations.

[0046] Specifically, after receiving the first fault interrupt signal, the processor unloads the tasks executed by other DMA devices, retains only the tasks executed by the current DMA device, and restarts the fault detection function of the current DMA device to continue detection, thereby avoiding false alarm problems caused by data congestion on the link.

[0047] Specifically, the counting detection module is also configured to resume detecting the execution status of the current data handling and transmission task after generating and reporting the first fault interrupt signal; if it is detected that the execution status of the current data handling and transmission task is abnormal again, generate and report a second fault interrupt signal.

[0048] In this embodiment, the counting detection module will restart reading the value of the byte counter after a certain time interval and continue to compare adjacent cycles. If the execution state of the data handling and transmission task is found to be abnormal again after the recovery detection, for example, the data transmission length of adjacent cycles is still the same, the counting detection module will generate a second fault interrupt signal and report it to the processor again. By monitoring potential problems multiple times in a short period of time, the accuracy of fault detection is improved and false alarms are avoided.

[0049] It is understandable that the status register can reflect the key indicators of the DMA device in the data transmission process in real time, such as whether the data transmission is successful, whether an error occurs, the current transmission progress, etc. Figure 7In some embodiments, the DMA device further includes: a status register configured to record an execution status during data handling and transmission; the status register is connected to the fault detection module, and the fault detection module is further configured to read the execution status during data handling and transmission from the status register and determine whether the execution status is normal.

[0050] The fault detection module periodically accesses the status register to obtain the current data transfer execution status and compares it with the preset normal state, thereby simply and quickly determining the execution status of the DMA device.

[0051] In addition, this fault detection module realizes the detection of abnormal execution status of DMA device, and can also verify or combine with the detection result obtained according to the value of byte counter, so as to improve the accuracy of DMA device fault detection.

[0052] If the fault detection module finds that the execution status read from the status register does not meet the normal standard, for example, an error flag appears or data transmission is not completed, the fault handling mechanism will be triggered immediately. At this time, the fault detection module will generate a first fault interrupt signal and report it to the processor to notify its DMA device of an abnormal execution status.

[0053] Similarly, in order to ensure that the system can respond in time and resume normal operation, the fault detection module will suspend subsequent detection of the current data handling and transmission task after generating the first fault interrupt signal, and re-read the status register information after a certain period of time. If the execution status is abnormal again after the resumption of detection, a second fault interrupt signal will be generated and reported to the processor again, indicating that the current DMA device has a fault.

[0054] In addition, the efficiency and reliability of data processing depend on the cooperation between various components. Figure 8 , the present application also provides a data processing system in an embodiment, including: a DMA device, the DMA device including: a fault detection module, connected to the processor, configured at least to detect whether the execution state of the data handling transmission task is normal according to the data transmission length, and send a fault interrupt signal to the processor when the execution state is detected to be abnormal; The processor is at least configured to determine whether a fault occurs in the DMA device according to the fault interrupt signal.

[0055] The data processing system provided in the embodiment of the present application adds a fault detection module in the DMA device to monitor the abnormal data transfer execution status of the device itself. The processor only needs to determine whether the DMA device has a fault based on the abnormal execution status result reported by the DMA device, thereby saving the processor's resource overhead.

[0056] In addition, if the processor confirms that the DMA device has failed, it can take a series of measures to restore the normal operation of the system. For example, the processor can suspend the current data transfer task, reinitialize the DMA device, or adjust the data transfer strategy to avoid similar problems from happening again. In addition, the processor can also record the fault information for subsequent analysis and optimization.

[0057] Therefore, by collaboratively determining the fault of the DMA device through the fault detection module and the processor of the DMA device and making a timely dynamic response, not only the accuracy of fault detection during data transmission is improved, but also the system's response capability to abnormal situations is enhanced, thereby improving the stability and reliability of the entire data processing system in performing data processing in complex environments.

[0058] As mentioned earlier, when there are multiple DMA devices executing tasks, false alarms may occur if data congestion occurs on the link. Fig. 9 In some embodiments, the DMA device includes multiple devices, and the fault interrupt signal includes: a first fault interrupt signal, and the processor is further configured to retain the data transfer task performed by the current DMA device and unload the data transfer tasks performed by the remaining DMA devices according to the first fault interrupt signal.

[0059] In this embodiment, after receiving the first fault interrupt signal, the processor does not immediately determine that a DMA device has failed, but instead unloads the data transfer tasks performed by the remaining DMA devices, retains the data transfer tasks performed by the current DMA device, and continues to restore the execution status detection of the current DNA device to eliminate the false alarm problem caused by data congestion in the link, thereby improving the accuracy of fault detection, and further achieving effective response and ensuring the stability of data processing.

[0060] Specifically, the processor is further configured to send a recovery fault detection control signal to the current DMA device after receiving the first fault interrupt signal; the DMA device is further configured to recover and detect the execution status of the current data handling and transmission task according to the recovery fault detection control signal; the processor is further configured to determine that the DMA device has a fault if the second fault interrupt signal reported by the fault detection module is received again.

[0061] In this embodiment, by eliminating the false alarm problem caused by data congestion on the link based on the first fault interrupt signal, and then determining that the DMA device has failed based on the second fault interrupt signal reported by only the task currently executed by the DMA device, it is beneficial to improve the accuracy of detection.

[0062] The processor is further configured to, after determining that the DMA device fails, migrate the data transfer task performed by the failed DMA device to at least one of the remaining DMA devices for processing, and record the failed DMA device in a non-volatile memory.

[0063] If it is confirmed that the DMA device has failed, the processor will take a series of measures to ensure the normal operation of the system. Specifically, the processor is also configured to migrate the data handling tasks performed by the failed DMA device to at least one of the remaining DMA devices for processing after determining that the DMA device has failed. This can be achieved through a dynamic load balancing algorithm to ensure that data transmission tasks can be quickly and effectively transferred to other available DMA devices.

[0064] In addition, the processor will also record the faulty DMA device in the non-volatile memory to completely isolate the faulty DMA device. The recorded information includes the identification information of the DMA device, the fault type, the occurrence time and other key information for subsequent analysis and maintenance.

[0065] In this embodiment, by recording the failed DMA device in the non-volatile memory, the DMA device can be automatically shielded in subsequent operations to prevent it from participating in the data transfer task again, thereby improving the overall stability and reliability of the system.

[0066] In addition, see Fig.10 The present application also provides a DMA device execution status detection method in an embodiment, which is not limited to running on a certain physical hardware device to realize the detection of the DMA device execution status and data processing. It should be noted that the method can be solidified in a certain manufactured physical product in the form of software, and when the product is used, the method flow steps of the present application can be reproduced. The method includes: S310, periodically reading the data transmission length during the data handling and transmission of the DMA device; S320: judging whether the execution status of the data handling and transmission task of the DMA device is normal according to the consistency comparison result of the data transmission lengths of two adjacent cycles.

[0067] As mentioned above, in some technical solutions where the processor performs DMA device fault detection, the fault detection of the DMA device usually relies on setting a preset duration threshold and comparing the byte counter value of each cycle with the preset duration threshold. However, since the system load and data transmission volume during the DMA transmission process will change dynamically, the preset fixed duration threshold cannot adapt to such fluctuations. Therefore, when the system load is light, the threshold may be too high, causing minor anomalies to be ignored; and when the system load is heavy, the threshold may be too low, causing normal fluctuations to be misjudged as abnormalities.

[0068] In the embodiment of the present application, the data transmission length of the current cycle is compared with that of the previous cycle by comparing the consistency of the data transmission length of adjacent cycles to dynamically capture changes. Under normal circumstances, the transmission length of adjacent cycles should remain relatively consistent, while abnormal conditions will cause sudden changes or slight deviations in data length. Since it is based on the relative consistency of data between cycles rather than absolute values, to a certain extent, the overall fluctuations caused by the load can be ignored, and subtle, short-term anomalies can be keenly perceived, thereby improving the accuracy of fault detection to a certain extent.

[0069] According to some embodiments of the present application, judging whether the execution status of the data handling and transmission task of the DMA device is normal based on the consistency comparison result of the data transmission lengths of two adjacent cycles includes: performing a consistency comparison based on the data transmission lengths of two adjacent cycles; if they are consistent, judging that the execution status of the data handling and transmission task of the DMA device is abnormal; if they are inconsistent, judging that the execution status of the data handling and transmission task of the DMA device is normal.

[0070] According to some embodiments of the present application, after determining whether the execution status of the data handling and transmission task of the DMA device is normal, the method further includes: if it is determined that the execution status of the data handling and transmission task of the DMA device is abnormal, suspending detection, generating a first fault interrupt signal and reporting it; the first fault interrupt signal is used to indicate that the execution status of the DMA device is abnormal; if it is determined that the execution status of the data handling and transmission task of the DMA device is normal, continuing detection.

[0071] According to some embodiments of the present application, after generating and reporting a first fault interrupt signal, the method further includes: resuming detection of the execution status of the current data handling and transmission task; if it is detected that the execution status of the current data handling and transmission task is abnormal again, generating a second fault interrupt signal.

[0072] According to some embodiments of the present application, before resuming detection of the execution status of the current data handling and transmission task, the method further includes: retaining the data handling task executed by the current DMA device and unloading the data handling tasks executed by the remaining DMA devices according to the first fault interrupt signal.

[0073] According to some embodiments of the present application, after generating a second fault interrupt signal, the method further includes: determining that the DMA device has failed based on the second fault interrupt signal, migrating the data transfer task performed by the failed DMA device to at least one of the remaining DMA devices for processing, and recording the failed DMA device in a non-volatile memory.

[0074] The DMA device execution status detection method provided in the embodiment of the present application can be applied to but not limited to the hardware devices provided in the aforementioned embodiments. Its specific implementation and technical effects can be found in the relevant descriptions in the aforementioned embodiments. For the sake of clarity and brevity, they will not be elaborated here.

[0075] In summary, the DMA device, data processing system and DMA device execution status detection method provided in the embodiments of the present application monitor the data transfer status of the DMA device by adding a new fault detection module internally, which is convenient for saving processor resource overhead, thereby improving the performance of the overall system.

[0076] In addition, the fault detection module and processor of the DMA device collaborate to determine the fault of the DMA device and respond dynamically in a timely manner, which not only improves the accuracy of fault detection during data transmission, but also enhances the system's response capability to abnormal situations, thereby improving the stability and reliability of the entire data processing system in performing data processing in complex environments.

[0077] It should be noted that, in this article, the emphasis of the scheme described between the various embodiments is different, but the various embodiments have a certain interrelated relationship. When understanding the scheme of the present application, the various embodiments can refer to each other; in addition, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or measurement control unit including a series of elements includes not only those elements, but also other elements that are not explicitly listed, or also includes elements inherent to such process, method, article or measurement control unit. In the absence of more restrictions, the elements defined by the sentence "including one..." do not exclude the existence of other identical elements in the process, method, article or measurement control unit including the elements.

[0078] The above is only a specific implementation of the present application, but the protection scope of the present application is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed in the present application should be included in the protection scope of the present application. Therefore, the protection scope of the present application shall be based on the protection scope of the claims.

Claims

1. A DMA device, characterized in that: include: a byte counter configured to track a length of data transferred during a control data handling transmission; The fault detection module is connected to the byte counter and is at least configured to detect whether the execution status of the data handling transmission task is normal according to the data transmission length.

2. The DMA device according to claim 1, wherein: The fault detection module includes: a counting detection module, which is connected to the byte counter and configured to periodically read the data transmission length from the byte counter; and judge whether the execution status of the data handling and transmission task is normal based on the consistency comparison result of the data transmission length of two adjacent cycles.

3. The DMA device according to claim 1, wherein: The fault detection module includes: a counting detection module, which is connected to the byte counter and configured to periodically read the data transmission length from the byte counter; perform consistency comparison based on the data transmission lengths of two adjacent cycles; if they are consistent, it is determined that the execution status of the data handling and transmission task is abnormal and the detection is suspended; if they are inconsistent, it is determined that the execution status of the data handling and transmission task is normal and the detection is continued.

4. The DMA device according to claim 3, characterized in that: The counting detection module is further configured to generate and report a first fault interrupt signal simultaneously with or after the pause detection; the first fault interrupt signal is used to notify the processor that an execution state abnormality occurs in the DMA device.

5. The DMA device according to claim 4, characterized in that The counting detection module is further configured to resume detecting the execution status of the current data handling and transmission task after generating and reporting the first fault interruption signal; If it is detected that the execution status of the current data handling and transmission task is abnormal again, a second fault interrupt signal is generated and reported.

6. The DMA device according to claim 1, wherein: The DMA device further comprises: a status register configured to record the execution status during the data handling transmission; The status register is connected to the fault detection module; The fault detection module is further configured to read the execution status during the data handling and transmission from the status register, and determine whether the execution status is normal.

7. A data processing system, characterized in that: include: DMA devices and processors; The DMA device comprises: a fault detection module, the fault detection module is connected to the processor, and is at least configured to detect whether the execution state of the data handling transmission task is normal according to the data transmission length, and send a fault interrupt signal to the processor when the execution state is detected to be abnormal; The processor is at least configured to determine whether a fault occurs in the DMA device according to the fault interrupt signal.

8. The data processing system according to claim 7, characterized in that The DMA device includes a plurality of; The fault interrupt signal includes: a first fault interrupt signal; The processor is further configured to retain the data handling task executed by the current DMA device and unload the data handling tasks executed by other DMA devices according to the first fault interrupt signal.

9. The data processing system according to claim 8, characterized in that The processor is further configured to send a recovery fault detection control signal to the current DMA device after receiving the first fault interrupt signal, so that the DMA device recovers and detects the execution state of the current data handling and transmission task according to the recovery fault detection control signal; If the second fault interrupt signal reported by the fault detection module is received again, it is determined that the DMA device fails.

10. The data processing system according to claim 9, characterized in that The processor is further configured to, after determining that the DMA device fails, migrate the data transfer task performed by the failed DMA device to at least one of the remaining DMA devices for processing, and record the failed DMA device in a non-volatile memory.

11. A DMA device execution status detection method, characterized in that: include: Periodically read the data transfer length during the data handling transfer of the DMA device; According to the consistency comparison result of the data transmission lengths of two adjacent cycles, it is judged whether the execution status of the data handling and transmission task of the DMA device is normal.

12. The DMA device execution status detection method according to claim 11, characterized in that: The step of judging whether the execution state of the data handling and transmission task of the DMA device is normal according to the consistency comparison result of the data transmission lengths of two adjacent cycles comprises: performing consistency comparison according to the data transmission lengths of two adjacent cycles; if they are consistent, judging that the execution state of the data handling and transmission task of the DMA device is abnormal; If they are inconsistent, it is determined that the execution status of the data handling and transmission task of the DMA device is normal.

13. The DMA execution status detection method according to claim 11, characterized in that: After determining whether the execution state of the data handling and transmission task of the DMA device is normal, the method further comprises: if it is determined that the execution state of the data handling and transmission task of the DMA device is abnormal, suspending detection, generating and reporting a first fault interrupt signal; the first fault interrupt signal is used to indicate that the execution state of the DMA device is abnormal; If it is determined that the execution status of the data handling and transmission task of the DMA device is normal, continue to detect.

14. The DMA execution status detection method according to claim 13, characterized in that: After the first fault interrupt signal is generated and reported, the method further includes: resuming detection of the execution state of the current data handling and transmission task; If it is detected that the execution state of the current data handling and transmission task is abnormal again, a second fault interrupt signal is generated.

15. The DMA execution status detection method according to claim 14, wherein: Before resuming detection of the execution status of the current data handling and transmission task, the method further includes: according to the first fault interrupt signal, retaining the data handling task executed by the current DMA device and unloading the data handling tasks executed by the remaining DMA devices.

16. The DMA execution status detection method according to claim 15, wherein: After generating the second fault interrupt signal, the method further includes: determining that the DMA device has failed based on the second fault interrupt signal, migrating the data transfer task performed by the failed DMA device to at least one of the remaining DMA devices for processing, and recording the failed DMA device in a non-volatile memory.

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