Model training method and device, chip design method and device and electronic equipment

Abstract

The invention discloses a model training method and device, a chip design method and device and electronic equipment. The method comprises the steps of obtaining a sample data set of chip design; obtaining a chip design tool and a chip test design case set; based on the chip design tool, the chip test design case set and the sample data set, multiple times of training operation are carried out on the initial prediction model until the training ending condition is met, a trained prediction model is obtained, and for each set of sample data, the training is carried out; under the condition that sample tool parameters output by the trained prediction model serve as setting parameters of a chip design tool, a chip design result generated based on each chip test design case conforms to sample optimization target information. The trained prediction model has the capability of predicting setting parameters of the chip design tool, and the predicted tool parameters enable a chip design result generated by the prediction chip design tool to meet optimization target information.

Description

Technical Field

[0001] The present application belongs to the field of artificial intelligence technology, and in particular relates to a model training method, a chip design method, a device and an electronic device. Background Art

[0002] With the increasing complexity of integrated circuit design and the scale of transistors, the number of setting parameters involved in chip design tools even exceeds hundreds. These setting parameters influence and depend on each other. The combination and value of setting parameters are extremely important for obtaining the best chip design results.

[0003] When automatically generating chip designs, it is usually necessary to optimize multiple objectives at the same time, such as area, power consumption, performance, etc. Currently, the setting parameters of chip design tools are adjusted manually, and the chip design results are difficult to meet the optimization goals of the chip design. Summary of the invention

[0004] The embodiments of the present application provide a model training method, a chip design method, a device and an electronic device, which can make the chip design results more in line with the optimization goals at least to a certain extent.

[0005] Other features and advantages of the present application will become apparent from the following detailed description, or may be learned in part by the practice of the present application.

[0006] According to a first aspect of an embodiment of the present application, a model training method is provided, comprising: Acquire a sample data set for chip design, wherein the sample data set includes multiple groups of sample data, each group of sample data includes sample process parameters and sample optimization target information for chip design, and the sample optimization target information includes at least one sample optimization strategy for chip design; Acquire a chip design tool and a chip test design case set, wherein the chip test design case set includes a plurality of chip test design cases; Based on the chip design tool, the chip test design case set and the sample data set, the initial prediction model is trained multiple times until the training end conditions are met, so as to obtain the trained prediction model and the sample tool parameters corresponding to each sample data output by the trained prediction model, wherein for each set of sample data, when the sample tool parameters output by the trained prediction model are used as the setting parameters of the chip design tool, the chip design results generated based on each of the chip test design cases meet the sample optimization target information.

[0007] In some possible implementations, each training operation includes: For each set of sample data, the sample data is input into an initial prediction model to obtain sample tool parameters; Using the sample tool parameters as setting parameters corresponding to the current training operation of the chip design tool, and running each of the chip test design cases based on the chip design tool to obtain each sample chip design result corresponding to the current training operation; Based on the sample chip design results corresponding to the executed training operations, the parameters of the initial prediction model are adjusted, and the initial prediction model after the adjustment of the parameters is used as the initial prediction model corresponding to the next training operation.

[0008] In some possible implementations, adjusting the parameters of the initial prediction model based on the sample chip design results corresponding to the executed training operations respectively includes: For each chip test design case of each set of sample data, based on the sample chip design results corresponding to the executed training operations, determine the change information of each sample chip design result corresponding to the chip test design case; Determine the parameter iteration strategy corresponding to the current training operation based on the change information corresponding to each chip test design case of each set of sample data and the parameter iteration strategy corresponding to the previous training operation; Based on the parameter iteration strategy corresponding to the current training operation, the parameters of the initial prediction model are adjusted.

[0009] In some possible implementations, the change information includes single change information and global change information, and for each chip test design case of each set of sample data, based on the sample chip design results corresponding to the executed training operations, the change information of the sample chip design result is determined, including: For each chip test design case of each set of sample data, based on the sample chip design results corresponding to the executed training operations, the distribution information of each sample chip design result is determined, and the global change information is determined based on the distribution information of each sample chip design result; For each chip test design case of each set of sample data, the single change information is determined based on the sample chip design result corresponding to the last training operation and the sample chip design result corresponding to the current training operation.

[0010] In some possible implementations, the determining the parameter iteration strategy corresponding to the current training operation based on the change information corresponding to each chip test design case of each set of sample data and the parameter iteration strategy corresponding to the previous training operation includes: For each chip test design case of each set of sample data, if the change information corresponding to the chip test design case meets the optimization target information, the parameter iteration strategy corresponding to the previous training operation is used as the parameter iteration strategy corresponding to the current training operation; If the change information corresponding to at least a preset number of chip test design cases does not conform to the optimization target information, the parameter iteration strategy corresponding to the previous training operation is adjusted to obtain the parameter iteration strategy corresponding to the current training operation.

[0011] In some possible implementations, the training end condition includes at least one of the following: For each chip test design case of each set of sample data, the sample chip design result corresponding to the current training operation conforms to the corresponding sample target optimization information or conforms to the corresponding reference chip design result; The number of training operations reaches a preset number.

[0012] In some possible implementations, the sample process parameters are obtained in the following manner: Acquire initial sample process parameters, wherein the initial sample process parameters include parameters of multiple processes of chip design; Based on the influencing factors of each initial sample process parameter, the initial sample process parameters are screened to obtain sample process parameters, wherein the influencing factors are used to characterize the degree of correlation between the initial sample process parameters and the corresponding sample chip design results.

[0013] According to a second aspect of an embodiment of the present application, a chip design method is provided, including: Acquiring target data for chip design, wherein the target data includes process parameters and optimization target information for chip design; Inputting the target data into a trained prediction model to obtain target tool parameters, wherein the prediction model is trained based on the above-mentioned model training method; The target tool parameters are used as setting parameters of a chip design tool, and the target chip design use case is run based on the chip design tool to obtain a target chip design result.

[0014] According to a third aspect of an embodiment of the present application, a model training device is provided, comprising: A sample data acquisition module, used to acquire a sample data set for chip design, wherein the sample data set includes multiple groups of sample data, each group of sample data includes sample process parameters and sample optimization target information for chip design, and the sample optimization target information includes at least one sample optimization strategy for chip design; A tool acquisition module, used to acquire a chip design tool and a chip test design case set, wherein the chip test design case set includes a plurality of chip test design cases; A training module is used to perform multiple training operations on the initial prediction model based on the chip design tool, the chip test design case set and the sample data set until the training end conditions are met, thereby obtaining a trained prediction model and sample tool parameters corresponding to each sample data output by the trained prediction model, wherein for each set of sample data, when the sample tool parameters output by the trained prediction model are used as setting parameters of the chip design tool, the chip design results generated based on each of the chip test design cases meet the sample optimization target information.

[0015] In some possible implementations, when the training module performs each training operation, it is specifically used to: For each set of sample data, the sample data is input into an initial prediction model to obtain sample tool parameters; Using the sample tool parameters as setting parameters corresponding to the current training operation of the chip design tool, and running each of the chip test design cases based on the chip design tool to obtain each sample chip design result corresponding to the current training operation; Based on the sample chip design results corresponding to the executed training operations, the parameters of the initial prediction model are adjusted, and the initial prediction model after the adjustment of the parameters is used as the initial prediction model corresponding to the next training operation.

[0016] In some possible implementations, when the training module adjusts the parameters of the initial prediction model based on the sample chip design results corresponding to the executed training operations, the training module is specifically used to: For each chip test design case of each set of sample data, based on the sample chip design results corresponding to the executed training operations, determine the change information of each sample chip design result corresponding to the chip test design case; Determine the parameter iteration strategy corresponding to the current training operation based on the change information corresponding to each chip test design case of each set of sample data and the parameter iteration strategy corresponding to the previous training operation; Based on the parameter iteration strategy corresponding to the current training operation, the parameters of the initial prediction model are adjusted.

[0017] In some possible implementations, the change information includes single change information and global change information. When the training module determines the change information of the sample chip design result based on the sample chip design results corresponding to the executed training operations for each chip test design case of each set of sample data, it is specifically used to: For each chip test design case of each set of sample data, based on the sample chip design results corresponding to the executed training operations, the distribution information of each sample chip design result is determined, and the global change information is determined based on the distribution information of each sample chip design result; For each chip test design case of each set of sample data, the single change information is determined based on the sample chip design result corresponding to the last training operation and the sample chip design result corresponding to the current training operation.

[0018] In some possible implementations, the training module is specifically used to determine the parameter iteration strategy corresponding to the current training operation based on the change information corresponding to each chip test design case of each set of sample data and the parameter iteration strategy corresponding to the previous training operation: For each chip test design case of each set of sample data, if the change information corresponding to the chip test design case meets the optimization target information, the parameter iteration strategy corresponding to the previous training operation is used as the parameter iteration strategy corresponding to the current training operation; If the change information corresponding to at least a preset number of chip test design cases does not conform to the optimization target information, the parameter iteration strategy corresponding to the previous training operation is adjusted to obtain the parameter iteration strategy corresponding to the current training operation.

[0019] In some possible implementations, the training end condition includes at least one of the following: For each chip test design case of each set of sample data, the sample chip design result corresponding to the current training operation conforms to the corresponding sample target optimization information or conforms to the corresponding reference chip design result; The number of training operations reaches a preset number.

[0020] In some possible implementations, the sample process parameters are obtained in the following manner: Acquire initial sample process parameters, wherein the initial sample process parameters include parameters of multiple processes of chip design; Based on the influencing factors of each initial sample process parameter, the initial sample process parameters are screened to obtain sample process parameters, wherein the influencing factors are used to characterize the degree of correlation between the initial sample process parameters and the corresponding sample chip design results.

[0021] According to a fourth aspect of an embodiment of the present application, a chip design device is provided, including: A target data acquisition module, used to acquire target data of chip design, wherein the target data includes process parameters and optimization target information of chip design; A parameter acquisition module, used for inputting the target data into a trained prediction model to obtain target tool parameters, wherein the prediction model is trained by the above-mentioned model training method; The chip design module is used to use the target tool parameters as setting parameters of the chip design tool, run the target chip design use case based on the chip design tool, and obtain the target chip design result.

[0022] According to a fifth aspect of an embodiment of the present application, an electronic device is provided, including a memory, a processor, and a computer program stored in the memory, wherein the processor executes the computer program to implement the steps of the method of the above embodiment.

[0023] According to a sixth aspect of an embodiment of the present application, a computer-readable storage medium is provided, on which a computer program is stored, characterized in that when the computer program is executed by a processor, the steps of the method of the above embodiment are implemented.

[0024] It should be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present application.

[0025] The beneficial effects of the technical solution provided by the embodiment of the present application are: The initial prediction model is trained using sample process parameters and sample optimization target information of chip design, and the sample tool parameters output by the initial prediction model are verified to see if they meet the training requirements through chip design tools and chip test design case sets, so that after the prediction model is trained, for each set of sample data, when the sample tool parameters output by the trained prediction model are used as the setting parameters of the chip design tool, the chip design results generated based on each of the chip test design cases meet the sample optimization target information, that is, the prediction model has the ability to predict the setting parameters of the chip design tool, and the predicted setting parameters enable the chip design results generated by the predicted chip design tool to meet the optimization target information. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The drawings herein are incorporated into the specification and constitute a part of the specification, showing embodiments consistent with the present application, and together with the specification, are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work. In the drawings: Figure 1 A flowchart of a model training method provided in an embodiment of the present application; Figure 2 A schematic diagram of a model training scheme provided for an example of the present application; Figure 3 A schematic diagram of a chip design method provided in an embodiment of the present application; Figure 4 A schematic diagram of the structure of a model training device provided in an embodiment of the present application; Figure 5 A schematic diagram of the structure of a chip design device provided in an embodiment of the present application; Figure 6 A schematic diagram of the structure of an electronic device for model training or chip design provided in an embodiment of the present application. DETAILED DESCRIPTION

[0027] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field without creative work are within the scope of protection of this application.

[0028] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided to provide a full understanding of the embodiments of the present application. However, those skilled in the art will appreciate that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps, etc. can be adopted. In other cases, known methods, devices, realizations or operations are not shown or described in detail to avoid blurring the various aspects of the application.

[0029] The block diagrams shown in the accompanying drawings are merely functional entities and do not necessarily correspond to physically independent entities. That is, these functional entities may be implemented in software form, or in one or more hardware modules or integrated circuits, or in different networks and / or processor devices and / or microcontroller devices.

[0030] The flowcharts shown in the accompanying drawings are only exemplary and do not necessarily include all the contents and operations / steps, nor must they be executed in the order described. For example, some operations / steps can be decomposed, and some operations / steps can be combined or partially combined, so the actual execution order may change according to actual conditions.

[0031] It should also be noted that the terms "first", "second", etc. in the specification and claims of the present application and the above-mentioned drawings are used to distinguish similar objects, and are not necessarily used to describe a specific order or sequence. It should be understood that the objects used in this way can be interchanged where appropriate, so that the embodiments of the present application described herein can be implemented in an order other than those shown or described.

[0032] The following describes several exemplary embodiments to illustrate the technical solutions of the embodiments of the present application and the technical effects produced by the technical solutions of the present application. It should be noted that the following embodiments can refer to, draw on or combine with each other, and the same terms, similar features and similar implementation steps in different embodiments will not be described repeatedly.

[0033] The model training method of the present application can be executed by any electronic device, and the electronic device may include a server or a terminal.

[0034] It can be understood by technicians in this technical field that the server can be an independent physical server, or a server cluster or distributed system composed of multiple physical servers, or a cloud server or server cluster that provides basic cloud computing services such as cloud services, cloud databases, cloud computing, cloud functions, cloud storage, network services, cloud communications, middleware services, domain name services, security services, CDN (Content Delivery Network), and big data and artificial intelligence platforms. The terminal can be a smart phone (such as Android phones, iOS phones, etc.), a tablet computer, a laptop computer, a digital broadcast receiver, a MID (Mobile Internet Devices), a PDA (personal digital assistant), a desktop computer, a smart home appliance, a vehicle-mounted terminal (such as a vehicle-mounted navigation terminal, a vehicle-mounted computer, etc.), a smart speaker, a smart watch, etc. The terminal and the server can be directly or indirectly connected by wired or wireless communication, but are not limited to this. The embodiments of the present invention can be applied to various scenarios, including but not limited to cloud technology, artificial intelligence, smart transportation, assisted driving, etc. The specific can also be determined based on the actual application scenario requirements, and is not limited here. The terminal (also referred to as a user terminal or user device) can be a smart phone, a tablet computer, a laptop computer, a desktop computer, an intelligent voice interaction device (such as a smart speaker), a wearable electronic device (such as a smart watch), a vehicle terminal, a smart home appliance (such as a smart TV), an AR / VR device, an aircraft, etc., but is not limited to these.

[0035] like Figure 1 As shown, in some possible implementations, the present application embodiment provides a model training method, taking the execution subject as a server as an example, the method may include the following steps: Step S101, obtaining a sample data set for chip design.

[0036] The sample data set includes multiple groups of sample data, each group of sample data includes sample process parameters and sample optimization target information of chip design, and the sample optimization target information includes at least one sample optimization strategy for chip design.

[0037] The sample process parameters include relevant parameters of each process of chip design, such as logic synthesis, DFT (Design for Testability), layout, static timing analysis, clock tree synthesis, routing, GDS (a file format for circuit layout) layout or FPGA (Field-Programmable Gate Array) bit stream.

[0038] Specifically, the sample process parameters can also be obtained in the following ways: Acquire initial sample process parameters, wherein the initial sample process parameters include parameters of multiple processes of chip design; Based on the influencing factors of each initial sample process parameter, the initial sample process parameters are screened to obtain sample process parameters, wherein the influencing factors are used to characterize the degree of correlation between the initial sample process parameters and the corresponding sample chip design results.

[0039] That is to say, sample process parameters that have a greater impact on chip design results can be screened out from multiple initial sample process parameters, reducing the impact of irrelevant initial sample process parameters and reducing the amount of data processing.

[0040] Among them, the sample optimization strategy may include the constraints and optimization strategies of chip design. The constraints may include meeting the requirements of all timing constraints WNS (Worst Negative Slack) and TNS (Total Negative Slack), meeting the manufacturability requirements, including DRC (Design Rule Check) violation clearing, LVS (Linux Virtual Server, load balancing solution service) violation clearing, and the optimization strategy package includes but is not limited to: minimizing chip area A, minimizing power consumption Pow, maximum frequency Per, and shortest running time T. This is the most basic chip performance-related design goal in addition to the chip functional design goal. Usually, the direction of a chip design exploration includes: when the power consumption and frequency meet the requirements, the chip area is minimized; when the chip area cannot be reduced and the main frequency cannot be further optimized, the power consumption is required to be the lowest; when the above performance design goals are met, the overall running time of the EDA software is required to be the shortest.

[0041] Step S102, obtaining chip design tools and a chip test design case set.

[0042] Among them, chip design tools may include EDA (Electronic Design Automation) tools, simulation tools, layout tools, and the like.

[0043] Among them, the chip test design case set includes multiple chip test design cases.

[0044] Specifically, the chip design tool is used to run each chip test design case in the chip test design case set after adjusting the setting parameters to obtain the corresponding chip design result.

[0045] Step S103, based on the chip design tool, the chip test design case set and the sample data set, the initial prediction model is trained multiple times until the training end conditions are met, and the trained prediction model and the sample tool parameters corresponding to each sample data output by the trained prediction model are obtained.

[0046] Among them, for each set of sample data, when the sample tool parameters output by the trained prediction model are used as the setting parameters of the chip design tool, the chip design results generated based on each chip test design case meet the sample optimization target information.

[0047] It can be understood that the prediction model obtained after training actually constructs a correspondence between the sample data set and the corresponding sample tool parameters, that is, it constructs a mapping relationship between the sample process parameters of chip design, sample optimization target information and sample tool parameters. The mapping relationship can be stored in the form of a weight matrix.

[0048] Specifically, during each training operation, the sample tool parameters output by the initial prediction model can be used as the setting parameters of the chip design tool, and then the chip design tool is used to run multiple chip test design cases in the chip test design case set respectively to obtain the corresponding sample chip design results, and then determine whether the sample chip design results meet the sample optimization target information, so as to determine whether the training operation needs to be continued. The training process of the initial prediction model will be further elaborated below.

[0049] In some possible implementations, the training end condition includes at least one of the following: For each chip test design case of each set of sample data, the sample chip design result corresponding to the current training operation conforms to the corresponding sample target optimization information or conforms to the corresponding reference chip design result; The number of training operations reaches the preset number.

[0050] Specifically, the number of iterations of the training operation can be set, or the same sample tool parameters can be input into the reference design tool to obtain a benchmark result as a reference chip design result.

[0051] For example, when the chip design tool is an EDA tool, the reference tool may be Golden EDA (benchmark EDA tool).

[0052] In this embodiment, the initial prediction model is trained through sample process parameters and sample optimization target information of chip design, and the sample tool parameters output by the initial prediction model are verified whether they meet the training requirements through chip design tools and chip test design case sets, so that after the prediction model is trained, for each set of sample data, when the sample tool parameters output by the trained prediction model are used as the setting parameters of the chip design tool, the chip design results generated based on each chip test design case meet the sample optimization target information, that is, the prediction model has the ability to predict the setting parameters of the chip design tool, and the predicted setting parameters enable the chip design results generated by the predicted chip design tool to meet the optimization target information.

[0053] The training process of the initial prediction model will be further described below in conjunction with the embodiments.

[0054] In some possible implementations, each training operation includes: (1) For each set of sample data, the sample data is input into the initial prediction model to obtain the sample tool parameters; (2) Using the sample tool parameters as setting parameters corresponding to the current training operation of the chip design tool, running each chip test design case based on the chip design tool, and obtaining each sample chip design result corresponding to the current training operation; (3) Based on the sample chip design results corresponding to the executed training operations, the parameters of the initial prediction model are adjusted, and the initial prediction model after the adjusted parameters is used as the initial prediction model corresponding to the next training operation.

[0055] Specifically, that is to say, in each training operation, the sample tool parameters corresponding to the sample data are first predicted through the initial prediction model, and then the sample tool parameters are used as the setting parameters of the chip design tool. The corresponding chip test design case is run based on the chip design tool to obtain the corresponding sample chip design result, and then the parameters of the initial prediction model are adjusted according to the sample chip design result, and the next training operation is repeated.

[0056] Specifically, for each set of sample data, the sample data is input into an initial prediction model, and the initial prediction model iteratively generates sample tool parameters according to an optimization algorithm, including simulated annealing, linear programming, genetic algorithm, artificial intelligence algorithm, quantum annealing, etc.

[0057] Among them, the initial prediction model may include BP (back propagation, feedforward neural network), RBF (RadialBasis Function, radial basis function) neural network, Hopfield (feedback neural network) network, etc., which is not limited in this application.

[0058] In a specific implementation process, adjusting the parameters of the initial prediction model based on the sample chip design results corresponding to the executed training operations may include: ① For each chip test design case of each set of sample data, based on the sample chip design results corresponding to the executed training operations, determine the change information of each sample chip design result corresponding to the chip test design case.

[0059] The change information includes single change information and global change information.

[0060] In a specific implementation process, for each chip test design case of each set of sample data, based on the sample chip design results corresponding to the executed training operations, determining the change information of the sample chip design results may include: For each chip test design case of each set of sample data, based on the sample chip design results corresponding to the executed training operations, the distribution information of each sample chip design result is determined, and the global change information is determined based on the distribution information of each sample chip design result; For each chip test design case of each set of sample data, single change information is determined based on the sample chip design result corresponding to the previous training operation and the sample chip design result corresponding to the current training operation.

[0061] For example, the training operation has been executed 100 times. For a chip test design case of a set of sample data, the sample chip design results corresponding to the 100 training operations have been obtained. Then, the single change information can be determined based on the sample chip design results obtained by the 100th training operation and the sample chip design results obtained by the 99th training operation. The global change information can also be determined based on the sample chip design results corresponding to these 100 training operations.

[0062] In the specific implementation process, the global change information can be obtained through statistical analysis, including linear regression, confidence interval, probability distribution, etc.

[0063] ② Based on the change information corresponding to each chip test design case of each set of sample data, and the parameter iteration strategy corresponding to the previous training operation, determine the parameter iteration strategy corresponding to the current training operation.

[0064] In some possible implementations, based on the change information corresponding to each chip test design case of each set of sample data and the parameter iteration strategy corresponding to the previous training operation, determining the parameter iteration strategy corresponding to the current training operation includes: For each chip test design case of each set of sample data, if the change information corresponding to the chip test design case meets the optimization target information, the parameter iteration strategy corresponding to the previous training operation is used as the parameter iteration strategy corresponding to the current training operation; If the change information corresponding to at least a preset number of chip test design cases does not meet the optimization target information, the parameter iteration strategy corresponding to the previous training operation is adjusted to obtain the parameter iteration strategy corresponding to the current training operation.

[0065] Specifically, the change information may be change information for chip area, power consumption, frequency, running time, etc. For example, for single change information, the sample optimization target information includes minimum chip area and minimum power. Then, it can be determined whether the area and power of the sample chip design results obtained by the current training operation are showing a shrinking trend by comparing the area and power of the sample chip design results obtained by the previous training operation.

[0066] ③ Based on the parameter iteration strategy corresponding to the current training operation, adjust the parameters of the initial prediction model.

[0067] Specifically, if the sample chip design result obtained by the current training operation does not reach the reference chip design result corresponding to the training end condition, the parameters of the initial prediction model can be adjusted based on the parameter iteration strategy corresponding to the current training operation, and the training operation can be repeated until the training end condition is met.

[0068] In order to more clearly illustrate the above model training method, it will be further explained with examples below.

[0069] like Figure 2 As shown, in one example, taking the chip design tool as an EDA tool as an example, the model training method of the present application may include the following steps: Obtain a sample data set of chip design, including sample process parameters and sample optimization target information of chip design. The sample process parameters may include parameters corresponding to logic synthesis, DFT, layout, static timing analysis, clock tree synthesis, routing, GDS layout or FPGA bitstream respectively; the sample optimization target information may include minimizing chip area A, minimizing power consumption Pow, maximum frequency Per, shortest running time T, etc.; Perform multiple training operations on the initial prediction model based on the sample data set, wherein each training operation includes: inputting the sample data set into the initial prediction model, and the model iteratively generates sample tool parameters according to the optimization algorithm, including simulated annealing, linear programming, genetic algorithm, AGI, quantum annealing, etc.; the EDA tool runs the chip test design case according to the sample tool parameters to obtain the sample chip design result, and stores the sample chip design result in the database; Perform statistical analysis on the design results of each sample chip in the database, including linear regression, confidence interval, probability distribution, etc., and calculate the change information of the sample chip design results, including global change information and single iteration change information, to determine whether to stop training. If the sample optimization target information is not reached, determine whether the change information Δ meets the expected strategy requirements. If it meets the strategy requirements, continue to the next iteration. If it does not meet the strategy requirements, correct the iteration strategy, including adjusting the sampling interval of the sample process parameters, which can be adjusted according to the probability distribution, and then continue the next training operation until the training end conditions are met; After the training is completed, the mapping relationship between the sample process parameters, the sample optimization target information and the sample tool parameters is obtained, and the mapping relationship is stored in a multi-dimensional matrix data structure.

[0070] The above-mentioned model training method trains the initial prediction model through the sample process parameters and sample optimization target information of the chip design, and verifies whether the sample tool parameters output by the initial prediction model meet the training requirements through the chip design tool and the chip test design case set, so that after the prediction model is trained, for each set of sample data, when the sample tool parameters output by the trained prediction model are used as the setting parameters of the chip design tool, the chip design results generated based on each chip test design case meet the sample optimization target information, that is, the prediction model has the ability to predict the setting parameters of the chip design tool, and the predicted setting parameters enable the chip design results generated by the predicted chip design tool to meet the optimization target information.

[0071] In some possible implementations, such as Figure 3 As shown, a chip design method is provided, comprising: Step S301, obtaining target data for chip design.

[0072] Among them, the target data includes process parameters and optimization target information of chip design.

[0073] Step S302, input the target data into the trained prediction model to obtain the target tool parameters.

[0074] Among them, the prediction model is trained based on the above-mentioned model training method.

[0075] Specifically, the prediction model has constructed a mapping relationship between sample process parameters, sample optimization target information and corresponding sample tool parameters through training, and the corresponding target tool parameters can be obtained through the process parameters and optimization target information.

[0076] Step S303: Use the target tool parameters as setting parameters of the chip design tool, run the target chip design use case based on the chip design tool, and obtain the target chip design result.

[0077] Specifically, in the process of training the initial prediction model, multiple chip test design cases are combined for verification. That is to say, for the target tool parameters predicted by the trained prediction model, the chip design tool, when using the target tool parameters, can run various different chip test cases to obtain the target chip design results that are relatively most consistent with the optimization target information.

[0078] The above-mentioned chip design method obtains the target tool parameters based on the target data of the chip design through the trained prediction model. The prediction model has constructed the mapping relationship between the sample process parameters, the sample optimization target information and the corresponding sample tool parameters through training, and the initial prediction model is trained in combination with multiple chip test design use cases. When the chip design tool adopts the target tool parameters, it can obtain the target chip design results that are relatively most consistent with the optimization target information, and can also effectively improve the chip design efficiency.

[0079] In some possible implementations, such as Figure 4 As shown, a model training device 40 is provided, comprising: The sample data acquisition module 401 is used to acquire a sample data set for chip design, wherein the sample data set includes multiple groups of sample data, each group of sample data includes sample process parameters and sample optimization target information for chip design, and the sample optimization target information includes at least one sample optimization strategy for chip design; A tool acquisition module 402 is used to acquire a chip design tool and a chip test design case set, wherein the chip test design case set includes a plurality of chip test design cases; The training module 403 is used to perform multiple training operations on the initial prediction model based on the chip design tool, the chip test design case set and the sample data set until the training end conditions are met, thereby obtaining the trained prediction model and the sample tool parameters corresponding to each sample data output by the trained prediction model. For each set of sample data, when the sample tool parameters output by the trained prediction model are used as the setting parameters of the chip design tool, the chip design results generated based on each chip test design case meet the sample optimization target information.

[0080] In some possible implementations, the training module 403 is specifically configured to: For each set of sample data, the sample data is input into the initial prediction model to obtain sample tool parameters; The sample tool parameters are used as setting parameters corresponding to the current training operation of the chip design tool, and each chip test design case is run based on the chip design tool to obtain each sample chip design result corresponding to the current training operation; Based on the sample chip design results corresponding to the executed training operations, the parameters of the initial prediction model are adjusted, and the initial prediction model after the adjustment of the parameters is used as the initial prediction model corresponding to the next training operation.

[0081] In some possible implementations, when the training module 403 adjusts the parameters of the initial prediction model based on the sample chip design results corresponding to the executed training operations, it is specifically used to: For each chip test design case of each set of sample data, based on the sample chip design results corresponding to the executed training operations, determine the change information of each sample chip design result corresponding to the chip test design case; Determine the parameter iteration strategy corresponding to the current training operation based on the change information corresponding to each chip test design case of each set of sample data and the parameter iteration strategy corresponding to the previous training operation; Based on the parameter iteration strategy corresponding to the current training operation, adjust the parameters of the initial prediction model.

[0082] In some possible implementations, the change information includes single change information and global change information. When the training module 403 determines the change information of the sample chip design result based on the sample chip design results corresponding to the executed training operations for each chip test design case of each set of sample data, it is specifically used to: For each chip test design case of each set of sample data, based on the sample chip design results corresponding to the executed training operations, the distribution information of each sample chip design result is determined, and the global change information is determined based on the distribution information of each sample chip design result; For each chip test design case of each set of sample data, single change information is determined based on the sample chip design result corresponding to the previous training operation and the sample chip design result corresponding to the current training operation.

[0083] In some possible implementations, the training module 403 determines the parameter iteration strategy corresponding to the current training operation based on the change information corresponding to each chip test design case of each set of sample data and the parameter iteration strategy corresponding to the previous training operation, specifically for: For each chip test design case of each set of sample data, if the change information corresponding to the chip test design case meets the optimization target information, the parameter iteration strategy corresponding to the previous training operation is used as the parameter iteration strategy corresponding to the current training operation; If the change information corresponding to at least a preset number of chip test design cases does not meet the optimization target information, the parameter iteration strategy corresponding to the previous training operation is adjusted to obtain the parameter iteration strategy corresponding to the current training operation.

[0084] In some possible implementations, the training end condition includes at least one of the following: For each chip test design case of each set of sample data, the sample chip design result corresponding to the current training operation meets the corresponding sample optimization target information or meets the corresponding reference chip design result; The number of training operations reaches the preset number.

[0085] In some possible implementations, the sample process parameters are obtained in the following manner: Acquire initial sample process parameters, wherein the initial sample process parameters include parameters of multiple processes of chip design; Based on the influencing factors of each initial sample process parameter, the initial sample process parameters are screened to obtain sample process parameters, wherein the influencing factors are used to characterize the degree of correlation between the initial sample process parameters and the corresponding sample chip design results.

[0086] The above-mentioned model training device trains the initial prediction model through the sample process parameters and sample optimization target information of the chip design, and verifies whether the sample tool parameters output by the initial prediction model meet the training requirements through the chip design tool and the chip test design case set, so that after the prediction model is trained, for each set of sample data, when the sample tool parameters output by the trained prediction model are used as the setting parameters of the chip design tool, the chip design results generated based on each chip test design case meet the sample optimization target information, that is, the prediction model has the ability to predict the setting parameters of the chip design tool, and the predicted setting parameters enable the chip design results generated by the predicted chip design tool to meet the optimization target information.

[0087] Among some possible factual approaches, such as Figure 5 As shown, a chip design device 50 is provided, comprising: The target data acquisition module 501 is used to acquire the target data of the chip design, wherein the target data includes the process parameters and optimization target information of the chip design; The parameter acquisition module 502 is used to input the target data into the trained prediction model to obtain the target tool parameters, wherein the prediction model is trained based on the above-mentioned model training method; The chip design module 503 is used to use the target tool parameters as setting parameters of the chip design tool, run the target chip design use case based on the chip design tool, and obtain the target chip design result.

[0088] The above-mentioned chip design device obtains target tool parameters based on the target data of chip design through the trained prediction model. The prediction model has constructed a mapping relationship between sample process parameters, sample optimization target information and corresponding sample tool parameters through training, and in the process of training the initial prediction model, it is verified by combining multiple chip test design use cases. When the chip design tool adopts the target tool parameters, it can obtain the target chip design results that are relatively most consistent with the optimization target information, and can also effectively improve the chip design efficiency.

[0089] In an alternative embodiment, an electronic device is provided, such as Figure 6 As shown, Figure 6The electronic device 4000 shown includes: a processor 4001 and a memory 4003. The processor 4001 and the memory 4003 are connected, such as through a bus 4002. Optionally, the electronic device 4000 may also include a transceiver 4004, which may be used for data interaction between the electronic device and other electronic devices, such as data transmission and / or data reception. It should be noted that in actual applications, the transceiver 4004 is not limited to one, and the structure of the electronic device 4000 does not constitute a limitation on the embodiments of the present application.

[0090] Processor 4001 may be a CPU (Central Processing Unit), a general-purpose processor, a DSP (Digital Signal Processor), an ASIC (Application Specific Integrated Circuit), an FPGA (Field Programmable Gate Array) or other programmable logic devices, transistor logic devices, hardware components or any combination thereof. It may implement or execute various exemplary logic blocks, modules and circuits described in conjunction with the disclosure of this application. Processor 4001 may also be a combination that implements computing functions, such as a combination of one or more microprocessors, a combination of a DSP and a microprocessor, etc.

[0091] The bus 4002 may include a path to transmit information between the above components. The bus 4002 may be a PCI (Peripheral Component Interconnect) bus or an EISA (Extended Industry Standard Architecture) bus. The bus 4002 may be divided into an address bus, a data bus, a control bus, etc. For ease of representation, Figure 6 Only one thick line is used in the diagram, but this does not mean that there is only one bus or only one type of bus.

[0092] The memory 4003 may be a ROM (Read Only Memory) or other types of static storage devices that can store static information and instructions, a RAM (Random Access Memory) or other types of dynamic storage devices that can store information and instructions, or an EEPROM (Electrically Erasable Programmable Read Only Memory), a CD-ROM (Compact Disc Read Only Memory) or other optical disk storage, optical disk storage (including compressed optical disk, laser disk, optical disk, digital versatile disk, Blu-ray disk, etc.), magnetic disk storage media, other magnetic storage devices, or any other medium that can be used to carry or store computer programs and can be read by a computer, without limitation herein.

[0093] The memory 4003 is used to store the computer program for executing the embodiment of the present application, and the execution is controlled by the processor 4001. The processor 4001 is used to execute the computer program stored in the memory 4003 to implement the steps shown in the above method embodiment.

[0094] An embodiment of the present application provides a computer-readable storage medium, on which a computer program is stored. When the computer program is executed by a processor, the steps and corresponding contents of the aforementioned method embodiment can be implemented.

[0095] The embodiment of the present application also provides a computer program product, including a computer program, which can implement the steps and corresponding contents of the aforementioned method embodiment when executed by a processor.

[0096] It should be understood that, although each operation step is indicated by arrows in the flowchart of the embodiment of the present application, the implementation order of these steps is not limited to the order indicated by the arrows. Unless clearly stated herein, in some implementation scenarios of the embodiment of the present application, the implementation steps in each flowchart can be performed in other orders according to demand. In addition, some or all of the steps in each flowchart may include multiple sub-steps or multiple stages based on actual implementation scenarios. Some or all of these sub-steps or stages may be executed at the same time, and each sub-step or stage in these sub-steps or stages may also be executed at different times respectively. In different scenarios of execution time, the execution order of these sub-steps or stages may be flexibly configured according to demand, and the embodiment of the present application does not limit this.

[0097] The above are only optional implementation methods for some implementation scenarios of the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the technical concept of the scheme of the present application, other similar implementation methods based on the technical ideas of the present application are also within the protection scope of the embodiments of the present application.

Claims

1. A model training method, characterized in that: include: Acquire a sample data set for chip design, wherein the sample data set includes multiple groups of sample data, each group of sample data includes sample process parameters and sample optimization target information for chip design, and the sample optimization target information includes at least one sample optimization strategy for chip design; Acquire a chip design tool and a chip test design case set, wherein the chip test design case set includes a plurality of chip test design cases; Based on the chip design tool, the chip test design case set and the sample data set, the initial prediction model is trained multiple times until the training end conditions are met, so as to obtain the trained prediction model and the sample tool parameters corresponding to each sample data output by the trained prediction model, wherein for each set of sample data, when the sample tool parameters output by the trained prediction model are used as the setting parameters of the chip design tool, the chip design results generated based on each of the chip test design cases meet the sample optimization target information.

2. The method according to claim 1, characterized in that Each training operation includes: For each set of sample data, the sample data is input into an initial prediction model to obtain sample tool parameters; Using the sample tool parameters as setting parameters corresponding to the current training operation of the chip design tool, and running each of the chip test design cases based on the chip design tool to obtain each sample chip design result corresponding to the current training operation; Based on the sample chip design results corresponding to the executed training operations, the parameters of the initial prediction model are adjusted, and the initial prediction model after the adjustment of the parameters is used as the initial prediction model corresponding to the next training operation.

3. The method according to claim 2, characterized in that The adjusting the parameters of the initial prediction model based on the sample chip design results respectively corresponding to the executed training operations includes: For each chip test design case of each set of sample data, based on the sample chip design results corresponding to the executed training operations, determine the change information of each sample chip design result corresponding to the chip test design case; Determine the parameter iteration strategy corresponding to the current training operation based on the change information corresponding to each chip test design case of each set of sample data and the parameter iteration strategy corresponding to the previous training operation; Based on the parameter iteration strategy corresponding to the current training operation, the parameters of the initial prediction model are adjusted.

4. The method according to claim 3, characterized in that The change information includes single change information and global change information. For each chip test design case of each set of sample data, based on the sample chip design results corresponding to the executed training operations, the change information of the sample chip design result is determined, including: For each chip test design case of each set of sample data, based on the sample chip design results corresponding to the executed training operations, the distribution information of each sample chip design result is determined, and the global change information is determined based on the distribution information of each sample chip design result; For each chip test design case of each set of sample data, the single change information is determined based on the sample chip design result corresponding to the last training operation and the sample chip design result corresponding to the current training operation.

5. The method according to claim 3, characterized in that: The step of determining the parameter iteration strategy corresponding to the current training operation based on the change information corresponding to each chip test design case of each set of sample data and the parameter iteration strategy corresponding to the previous training operation includes: For each chip test design case of each set of sample data, if the change information corresponding to the chip test design case meets the optimization target information, the parameter iteration strategy corresponding to the previous training operation is used as the parameter iteration strategy corresponding to the current training operation; If the change information corresponding to at least a preset number of chip test design cases does not conform to the optimization target information, the parameter iteration strategy corresponding to the previous training operation is adjusted to obtain the parameter iteration strategy corresponding to the current training operation.

6. The method according to claim 2, characterized in that The training end condition includes at least one of the following: For each chip test design case of each set of sample data, the sample chip design result corresponding to the current training operation conforms to the corresponding sample target optimization information or conforms to the corresponding reference chip design result; The number of training operations reaches a preset number.

7. The method according to claim 1, characterized in that The sample process parameters are obtained in the following manner: Acquire initial sample process parameters, wherein the initial sample process parameters include parameters of multiple processes of chip design; Based on the influencing factors of each initial sample process parameter, the initial sample process parameters are screened to obtain sample process parameters, wherein the influencing factors are used to characterize the degree of correlation between the initial sample process parameters and the corresponding sample chip design results.

8. A chip design method, characterized in that: include: Acquiring target data for chip design, wherein the target data includes process parameters and optimization target information for chip design; Inputting the target data into a trained prediction model to obtain target tool parameters, wherein the prediction model is trained based on the model training method according to any one of claims 1 to 7; The target tool parameters are used as setting parameters of a chip design tool, and the target chip design use case is run based on the chip design tool to obtain a target chip design result.

9. A model training device, characterized in that: include: A sample data acquisition module, used to acquire a sample data set for chip design, wherein the sample data set includes multiple groups of sample data, each group of sample data includes sample process parameters and sample optimization target information for chip design, and the sample optimization target information includes at least one sample optimization strategy for chip design; A tool acquisition module, used to acquire a chip design tool and a chip test design case set, wherein the chip test design case set includes a plurality of chip test design cases; A training module is used to perform multiple training operations on the initial prediction model based on the chip design tool, the chip test design case set and the sample data set until the training end conditions are met, thereby obtaining a trained prediction model and sample tool parameters corresponding to each sample data output by the trained prediction model, wherein for each set of sample data, when the sample tool parameters output by the trained prediction model are used as setting parameters of the chip design tool, the chip design results generated based on each of the chip test design cases meet the sample optimization target information.

10. A chip design device, characterized in that: include: A target data acquisition module, used to acquire target data of chip design, wherein the target data includes process parameters and optimization target information of chip design; A parameter acquisition module, used for inputting the target data into a trained prediction model to obtain target tool parameters, wherein the prediction model is trained based on the model training method according to any one of claims 1 to 7; The chip design module is used to use the target tool parameters as setting parameters of the chip design tool, run the target chip design use case based on the chip design tool, and obtain the target chip design result.

11. An electronic device comprising a memory, a processor and a computer program stored in the memory, characterized in that: The processor executes the computer program to implement the steps of the method according to any one of claims 1 to 7 or claim 8.

12. A computer-readable storage medium having a computer program stored thereon, characterized in that: When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 or claim 8 are implemented.

13. A computer program product, comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method according to any one of claims 1 to 7 or claim 8 are implemented.

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