Driving module and display device

Abstract

The present application belongs to the field of display, and specifically relates to a driving module and a display device. The driving module includes multiple source driving chips, a polarity partition control module, a picture detection module and an inversion mode control module. Each source driving chip is connected to multiple columns of data lines of a display panel. The source driving chips of odd columns are connected to a pull-down power supply. The source driving chips of even columns are connected to a pull-up power supply and a pull-down power supply through a polarity partition control module. The picture detection module is connected to the display panel and is used to control the polarity partition control module to work according to the detected crosstalk degree of the display picture to form a conventional polarity mode and a polarity symmetry mode. In the polarity symmetry mode, the polarity partition control module turns on the pull-up power supply and the source driving chips of the even columns, so that the second display area controlled by the source driving chips of the even columns is polarity symmetric with the first display area, so as to offset the coupling, improve or eliminate the lateral crosstalk, and improve the display effect of the display panel.

Description

Technical Field

[0001] The present application belongs to the field of display, and specifically relates to a driving module and a display device. Background Art

[0002] Thin Film Transistor Liquid Crystal Display (TFT-LCD) includes an array substrate, a color filter substrate, and a liquid crystal layer disposed between the array substrate and the color filter substrate. When the liquid crystal display is displayed, the pixel electrode on one side of the array substrate and the common electrode on one side of the color filter substrate form a liquid crystal capacitor (Clc) to drive the deflection of the liquid crystal molecules and control the brightness of each sub-pixel to realize the picture display. The pixel electrode and the common electrode on one side of the array substrate form a storage capacitor (Cst) to maintain the voltage of the liquid crystal capacitor.

[0003] If a single-direction electric field is applied to the liquid crystal molecules for a long time, the liquid crystal molecules may be polarized, resulting in a decrease in display quality or even damage to the liquid crystal material. By reversing the polarity and alternating the direction of the electric field, the polarization of the liquid crystal molecules can be effectively avoided. Polarity reversal methods include frame reversal, row reversal, column reversal, and dot reversal.

[0004] When the liquid crystal display is displaying, the data line provides pixel voltage to the pixel electrode. The polarity reversal makes the pixel voltage greater than or less than the voltage of the common electrode. The coupling capacitance (Cdc) formed between the data line and the pixel electrode will cause the pixel voltage to shift, resulting in lateral crosstalk (H-Crosstalk), which affects the display effect of the liquid crystal display. Summary of the invention

[0005] The purpose of the present application is to provide a driving module and a display device to improve or eliminate lateral crosstalk and improve the display effect of a liquid crystal display.

[0006] In order to achieve the above object, the present application provides a driving module, including a plurality of source driving chips, each of which is connected to a plurality of columns of data lines of a display panel, and the driving module further includes:

[0007] A polarity partition control module, wherein the source driver chips of the odd columns are connected to a pull-down power supply, and the source driver chips of the even columns are connected to a pull-up power supply and the pull-down power supply through the polarity partition control module, and the pull-down power supply includes a ground terminal;

[0008] An image detection module, connected to the display panel and the polarity partition control module, for controlling the polarity partition control module to work according to the detected crosstalk degree of the display image, so as to form a conventional polarity mode and a polarity symmetric mode;

[0009] An inversion mode control module connected to all the source driving chips and one of the picture detection module and the polarity partition control module;

[0010] Among them, in the normal polarity mode, the pull-down power supply is connected to the source driver chip of the even-numbered columns, and the source driver chip controls the display panel to be reversed in a single column in the row direction; in the polarity symmetry mode, the pull-up power supply is connected to the source driver chip of the even-numbered columns, and the reversal mode control module outputs a polarity reversal control signal to the source driver chip, so that the source driver chip controls the display panel to be reversed in a double column in the row direction.

[0011] Optionally, the polarity partition control module includes a first transistor and a second transistor, the first transistor is an N-type field effect transistor, the second transistor is a P-type field effect transistor, the control end of the first transistor and the control end of the second transistor are both connected to the screen detection module, the first end of the first transistor is connected to the pull-up power supply, the second end of the first transistor is connected to the source driver chip of the even column through the first node, the first end of the second transistor is connected to the pull-down power supply, and the second end of the second transistor is connected to the first node.

[0012] Optionally, the polarity partition control module includes a first transistor and a first resistor, the first transistor is an N-type field effect transistor, the first end of the first transistor is connected to the pull-up power supply, the second end of the first transistor is connected to the source driver chip of the even column through a first node, the control end of the first transistor is connected to the screen detection module through a second node, and the first resistor is connected to the pull-down power supply and the first node.

[0013] Optionally, the polarity partition control module also includes a third transistor, which is a triode, a control end of the third transistor is connected to the picture detection module, a first end of the third transistor is connected to the pull-up power supply, and a second end of the third transistor is connected to the second node.

[0014] Optionally, the inversion mode control module is connected to the polarity partition control module through the first node.

[0015] Optionally, the inversion mode control module includes a fourth transistor, which is a triode, wherein the control end of the fourth transistor is connected to the first node, the first end of the fourth transistor is connected to the pull-up power supply, and the second end of the fourth transistor is connected to all the source driver chips.

[0016] Optionally, the inversion mode control module also includes a fifth transistor and a fourth resistor, the fifth transistor is an N-type field effect transistor, the control end of the fifth transistor is connected to the second end of the fourth transistor, the first end of the fifth transistor is connected to the pull-up power supply, the second end of the fifth transistor is connected to all the source driver chips through a third node, and the fourth resistor is connected to the pull-down power supply and the third node.

[0017] Optionally, the inversion mode control module includes a fifth transistor and a fourth resistor, the fifth transistor is an N-type field effect transistor, the control end of the fifth transistor is connected to the first node, the first end of the fifth transistor is connected to the pull-up power supply, the second end of the fifth transistor is connected to all the source driver chips through a third node, and the fourth resistor is connected to the pull-down power supply and the third node.

[0018] Optionally, the picture detection module includes a timing controller, the timing controller includes a waveform recognition unit, the waveform recognition unit is connected to the common electrode of the display panel and the polarity partition control module, and the waveform recognition unit is used to control the polarity partition control module to turn on the source driver chip and the pull-up power supply of the even column when the common electrode voltage exceeds a preset interval.

[0019] The present application also provides a display device, comprising:

[0020] Display panel;

[0021] The driving module is connected to the display panel.

[0022] The driving module and display device disclosed in this application have the following beneficial effects:

[0023] In the present application, the driving module includes multiple source driver chips, a polarity partition control module, a picture detection module and an inversion mode control module. Each source driver chip is connected to multiple columns of data lines of the display panel. The source driver chips of the odd columns are connected to the pull-down power supply. The source driver chips of the even columns are connected to the pull-up power supply and the pull-down power supply through the polarity partition control module. The picture detection module is connected to the display panel and the polarity partition control module, and is used to control the operation of the polarity partition control module according to the detected crosstalk degree of the display picture to form a conventional polarity mode and a polarity symmetry mode. In the polarity symmetry mode, the polarity partition control module turns on the pull-up power supply and the source driver chips of the even columns, so that the second display area controlled by the source driver chips of the even columns is polarity symmetrical with the first display area. The inversion mode control module outputs a polarity inversion control signal to the source driver chip, and the polarity of the display panel in the row direction is double-column inversion. In the polarity symmetry mode, the pixel voltage coupling directions of the display areas controlled by adjacent source driver chips are opposite, which can offset the coupling and improve or eliminate lateral crosstalk. At the same time, the inversion mode control module controls the polarity of the display panel to be double-column inversion in the row direction, eliminating the difference in pixel polarity at the boundary position of the display area and other positions, thereby improving the display effect of the display panel.

[0024] Other features and advantages of the present application will become apparent from the following detailed description, or may be learned in part by the practice of the present application.

[0025] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the present disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] The drawings herein are incorporated into the specification and constitute a part of the specification, illustrate embodiments consistent with the present application, and together with the specification are used to explain the principles of the present application. Obviously, the drawings described below are only some embodiments of the present application, and for ordinary technicians in this field, other drawings can be obtained based on these drawings without creative work.

[0027] Figure 1 It is a structural schematic diagram of the driving module in Example 1 of the present application.

[0028] Figure 2 It is a schematic diagram of a conventional polarity mode when the display area is an even number of columns in the first embodiment of the present application.

[0029] Figure 3 It is a schematic diagram of the polarity symmetry of the display area in the first embodiment of the present application.

[0030] Figure 4 It is a schematic diagram of the polarity symmetry mode when the display area is an even number of columns in the first embodiment of the present application.

[0031] Figure 5 It is a schematic diagram of the polarity symmetry mode when the display area is an odd number of columns in the first embodiment of the present application.

[0032] Figure 6 It is a structural diagram of the second reversing mode control module in the first embodiment of the present application.

[0033] Figure 7 It is a structural diagram of the third reversal mode control module in the first embodiment of the present application.

[0034] Figure 8 Schematic diagram of the common electrode voltage waveform in Example 1 of the present application.

[0035] Fig. 9 It is a structural diagram of the driving module in the second embodiment of the present application.

[0036] Fig.10 It is a schematic diagram of a polarity partition control module with a triode in the second embodiment of the present application.

[0037] Fig.11 It is a schematic diagram of a polarity partition control module with a triode in the second embodiment of the present application.

[0038] Description of reference numerals:

[0039] 10. Drive module;

[0040] 100. Source driver chip;

[0041] 200, polarity partition control module; 210, first transistor; 220, second transistor; 230, first resistor; 240, second resistor; 250, capacitor; 260, third transistor;

[0042] 300, picture detection module; 310, waveform recognition unit;

[0043] 400, inversion mode control module; 410, fourth transistor; 420, third resistor; 430, fifth transistor; 440, fourth resistor; 450, fifth resistor;

[0044] 501, pull-down power supply; 502, pull-up power supply;

[0045] 20. Display panel; 21. First display area; 22. Second display area. DETAILED DESCRIPTION

[0046] Example embodiments will now be described more fully with reference to the accompanying drawings. However, example embodiments can be implemented in a variety of forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided so that this application will be more comprehensive and complete and fully convey the concept of the example embodiments to those skilled in the art.

[0047] In addition, described feature, structure or characteristic can be combined in one or more embodiments in any suitable manner. In the following description, many specific details are provided so as to provide a full understanding of the embodiments of the present application. However, it will be appreciated by those skilled in the art that the technical scheme of the present application can be put into practice without one or more of the specific details, or other methods, components, devices, steps, etc. can be adopted. In other cases, known methods, devices, realizations or operations are not shown or described in detail to avoid blurring the various aspects of the present application.

[0048] The present application is further described in detail below in conjunction with the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments of the present application described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and are intended to be used to explain the present application, and should not be understood as limiting the present application.

[0049] Embodiment 1

[0050] See also Figure 1 As shown, in this embodiment, the driving module 10 is used to drive the display panel 20 to display a picture, and the driving module 10 includes a source driving chip 100, a polarity partitioning control module 200, a picture detection module 300 and an inversion mode control module 400. The display panel 20 includes multiple rows of scan lines and multiple columns of data lines, and the driving module 10 includes multiple source driving chips 100, each source driving chip 100 is connected to multiple columns of data lines of the display panel 20, that is, multiple source driving chips 100 form multiple columns.

[0051] The source driver chips 100 of the odd columns are connected to the pull-down power supply 501, and the source driver chips 100 of the even columns are connected to the pull-up power supply 502 and the pull-down power supply 501 through the polarity partition control module 200, and the pull-down power supply 501 includes a ground terminal (GND). The voltage VDD of the pull-up power supply 502 is greater than the voltage of the pull-down power supply 501, and the voltage VDD of the pull-up power supply 502 is 1V~5V, and the pull-up power supply 502 includes a power management chip (PMIC). The total number of source driver chips 100 can be an odd number or an even number.

[0052] The image detection module 300 is connected to the display panel 20 and the polarity partition control module 200, and is used to control the polarity partition control module 200 to work according to the detected crosstalk degree of the display image, so as to form a normal polarity mode and a polarity symmetric mode.

[0053] In the normal polarity mode, the pull-down power supply 501 outputs a low-level signal to the source driver chip 100 of the odd-numbered columns, and the polarity of the first display area 21 controlled by the source driver chip 100 of the odd-numbered columns is "+-+-" in both the row direction and the column direction; the polarity partitioning control module 200 connects the pull-down power supply 501 to the source driver chip 100 of the even-numbered columns, and the pull-down power supply 501 outputs a low-level signal to the source driver chip 100 of the even-numbered columns, and the polarity of the second display area 22 controlled by the source driver chip 100 of the even-numbered columns is "+-+-" in the row direction, such as Figure 2 shown.

[0054] In the polarity symmetry mode, the pull-down power supply 501 outputs a low-level signal to the source driver chip 100 of the odd-numbered columns, so that the polarity of the first display area 21 controlled by the source driver chip 100 of the odd-numbered columns is "+-+-" in the row direction; the polarity partition control module 200 turns on the pull-up power supply 502 and the source driver chip 100 of the even-numbered columns, and the pull-up power supply 502 outputs a high-level signal to the source driver chip 100 of the even-numbered columns, so that the second display area 22 controlled by the source driver chip 100 of the even-numbered columns is polarity symmetrical with the first display area 21, that is, the polarity of the second display area 22 controlled by the source driver chip 100 of the even-numbered columns in the row direction is "-+-+", such as Figure 3 shown.

[0055] In the polarity symmetry mode, the pixel voltage and common voltage coupling directions of the adjacent first display area 21 and the second display area 22 are opposite, which can offset the coupling and improve or eliminate lateral crosstalk. However, the sub-pixels of the adjacent first display area 21 and the second display area 22 always have the "++" or "--" polarity and will not change. Under the effect of long-term lighting and aging, it may have a certain impact on this part of the liquid crystal. In addition, at the boundary position of the adjacent first display area 21 and the second display area 22, the polarity of the adjacent sub-pixels in the row direction is always the same, while the polarity of the sub-pixels in the same row in other areas is alternating "+-+-", causing the sub-pixels at the boundary position to become brighter or darker than the surrounding sub-pixels, that is, forming bright lines or dark lines, affecting the display effect of the display panel 20.

[0056] In order to improve or eliminate the display unevenness caused by the bright and dark lines, the driving module 10 in this embodiment further includes an inversion mode control module 400. The inversion mode control module 400 is connected to all the source driving chips 100 and one of the image detection module 300 and the polarity partition control module 200.

[0057] In the polarity symmetry mode, the inversion mode control module 400 outputs a polarity inversion control signal to the source driver chips 100 of the odd columns, so that the polarity of the first display area 21 controlled by the source driver chips 100 of the odd columns in the row direction is "++--", that is, the row direction is a double-column inversion mode; the inversion mode control module 400 outputs a polarity inversion control signal to the source driver chips 100 of the even columns, so that the polarity of the second display area 22 controlled by the source driver chips 100 of the even columns in the row direction is "--++", that is, the row direction is a double-column inversion mode. In other words, the inversion mode control module 400 outputs a polarity inversion control signal to all source driver chips 100, so that the source driver chips 100 control the display panel 20 in the row direction from single-column inversion to double-column inversion. In the normal polarity mode, the polarity of the first display area 21 and the second display area 22 in the column direction remains unchanged, and is still a single-column inversion mode of "+-+-".

[0058] When the sub-pixels of the adjacent first display area 21 and the second display area 22 always have "++" or "--" polarity, the polarity of the sub-pixels in the row direction is always the same, while the polarity of the sub-pixels in the same row in other areas is "+-+-" alternating, and there is a difference in the polarity of the pixels at the boundary position and other positions, resulting in the formation of bright and dark lines at the boundary position. In the polarity symmetry mode, when the inversion mode control module 400 outputs the polarity inversion control signal to the source driver chip 100, the row direction is a double-column inversion mode, and the difference in the polarity of the pixels at the boundary position and other positions of the entire display panel 20 is eliminated, thereby avoiding the formation of bright and dark lines at the boundary position.

[0059] In this embodiment, the driving module 10 includes a plurality of source driver chips 100, a polarity partition control module 200, a picture detection module 300 and an inversion mode control module 400, each source driver chip 100 is connected to a plurality of columns of data lines of the display panel 20, the source driver chips 100 of the odd columns are connected to the pull-down power supply 501, and the source driver chips 100 of the even columns are connected to the pull-up power supply 502 and the pull-down power supply 501 through the polarity partition control module 200, and the picture detection module 300 is connected to the display panel 20 and the polarity partition control module 200, and is used to control the polarity according to the crosstalk degree of the detected display picture. The partition control module 200 works to form a normal polarity mode and a polarity symmetry mode. In the normal polarity mode, the polarity partition control module 200 turns on the pull-down power supply 501 and the source driver chip 100 of the even-numbered columns. In the polarity symmetry mode, the polarity partition control module 200 turns on the pull-up power supply 502 and the source driver chip 100 of the even-numbered columns, so that the second display area 22 controlled by the source driver chip 100 of the even-numbered columns is polarity symmetric with the first display area 21. The inversion mode control module 400 outputs a polarity inversion control signal to the source driver chip 100, and the polarity of the display panel 20 in the row direction is double-column inversion. In the polarity symmetry mode, the pixel voltage coupling directions of the display areas controlled by adjacent source driver chips 100 are opposite, which can offset the coupling and improve or eliminate lateral crosstalk. At the same time, the inversion mode control module 400 controls the polarity of the display panel 20 to be double-column inversion in the row direction, eliminating the difference in pixel polarity at the boundary position and other positions of the display area, thereby improving or eliminating lateral crosstalk and avoiding the formation of bright and dark lines at the boundary position, thereby improving the display effect of the display panel 20.

[0060] It should be noted that the inversion mode control module 400 controls the polarity of the display panel 20 to be double-column inversion in the row direction. When the display area controlled by the source driver chip 100 is an even-numbered column, the polarities of the sub-pixels in adjacent columns of adjacent display areas are the same. For the entire display panel 20: the polarity of the sub-pixels in the first column is different from the polarity of the sub-pixels in the second column, the polarity of the sub-pixels in the penultimate column is different from the polarity of the sub-pixels in the penultimate column, and the polarity of the sub-pixels in the first column is the same as the polarity of the sub-pixels in the penultimate column. Figure 4 As shown; when the display area controlled by the source driver chip 100 is an odd number of columns, the polarities of the sub-pixels in adjacent columns of the adjacent display areas are the same. For the entire display panel 20: the polarity of the sub-pixels in the first column is the same as the polarity of the sub-pixels in the second column, the polarity of the sub-pixels in the penultimate column is the same as the polarity of the sub-pixels in the second-to-last column, and the polarity of the sub-pixels in the first column is the same as or different from the polarity of the sub-pixels in the penultimate column, as shown in FIG. Figure 5 shown.

[0061] See also Figure 1As shown, the polarity partition control module 200 includes a first transistor 210 and a second transistor 220, the first transistor 210 is an N-type metal oxide field effect transistor (NMOS), and the second transistor 220 is a P-type metal oxide field effect transistor (PMOS). The control end of the first transistor 210 and the control end of the second transistor 220 are both connected to the picture detection module 300, the first end of the first transistor 210 is connected to the pull-up power supply 502, the second end of the first transistor 210 is connected to the source driver chip 100 of the even column through the first node A, the first end of the second transistor 220 is connected to the pull-down power supply 501, and the second end of the second transistor 220 is connected to the first node A.

[0062] When the display screen detected by the picture detection module 300 has no crosstalk or the degree of crosstalk does not affect the display, and polarity partitioning is not required, a low-level signal is output to the polarity partitioning control module 200, the second transistor 220 of the polarity partitioning control module 200 is turned on and the first transistor 210 is turned off, and the pull-down power supply 501 outputs a low-level signal to the source driver chip 100 of the even column through the second transistor 220, forming a conventional polarity mode; when the display screen detected by the picture detection module 300 has serious crosstalk and polarity partitioning is required, a high-level signal is output to the polarity partitioning control module 200, the first transistor 210 of the polarity partitioning control module 200 is turned on and the second transistor 220 is turned off, and the pull-up power supply 502 outputs a high-level signal to the source driver chip 100 of the even column through the first transistor 210, forming a polarity symmetric mode.

[0063] It should be noted that the first transistor 210 is an N-type metal oxide field effect transistor, and the second transistor 220 is a P-type metal oxide field effect transistor, but it is not limited to this. By modifying the high and low levels of the control signal output by the picture detection module 300, the first transistor 210 can also be a P-type metal oxide field effect transistor, and the second transistor 220 can also be an N-type metal oxide field effect transistor, depending on the specific situation.

[0064] See also Figure 1 As shown, the inversion mode control module 400 is connected to the polarity partition control module 200 via the first node A.

[0065] The inversion mode control module 400 is controlled by the voltage of the first node A, that is, when the polarity partition control module 200 switches to the polarity symmetry mode, the inversion mode control module 400 is controlled to output a polarity inversion control signal to the source driver chip 100, and the polarity inversion mode of the display panel 20 in the row direction is changed from single-column inversion to double-column inversion, without affecting the conventional polarity mode.

[0066] See also Figure 1As shown, the inversion mode control module 400 includes a fourth transistor 410 and a third resistor 420, the fourth transistor 410 is a triode, the control end of the fourth transistor 410 is connected to the first node A through the third resistor 420, the first end of the fourth transistor 410 is connected to the pull-up power supply 502, and the second end of the fourth transistor 410 is connected to all source driver chips 100.

[0067] The first node A controls the fourth transistor 410 to be turned on or off. The fourth transistor 410 is a triode capable of amplifying current. This design can avoid attenuation of the control signal and affect the switching polarity reversal mode of the source driver chip 100.

[0068] In some embodiments, the inversion mode control module 400 includes a fifth transistor 430 and a fourth resistor 440, the fifth transistor 430 is an N-type metal oxide field effect transistor, the control end of the fifth transistor 430 is connected to the first node A, the first end of the fifth transistor 430 is connected to the pull-up power supply 502, the second end of the fifth transistor 430 is connected to all source driver chips 100 through the third node C, and the fourth resistor 440 is connected to the pull-down power supply 501 and the third node C. Figure 6 shown.

[0069] In the normal polarity mode, the first node A is at a low level, the fifth transistor 430 is turned off, and the pull-down power supply 501 outputs a low level signal to all source driver chips 100, maintaining the polarity reversal mode of the display panel 20 as a single column reversal in both the row direction and the column direction; in the polarity symmetry mode, the first node A is at a high level, the fifth transistor 430 is turned on, and the pull-up power supply 502 outputs a high level signal to all source driver chips 100, modifying the polarity reversal mode of the display panel 20 to a double column reversal in the row direction.

[0070] In some embodiments, the inversion mode control module 400 includes a fourth transistor 410, a third resistor 420, a fifth transistor 430, a fourth resistor 440, and a fifth resistor 450. The fourth transistor 410 is a triode, the control end of the fourth transistor 410 is connected to the first node A through the third resistor 420, the first end of the fourth transistor 410 is connected to the pull-up power supply 502, and the second end of the fourth transistor 410 is indirectly connected to all source driver chips 100, such as Figure 7 shown.

[0071] The fifth transistor 430 is an N-type metal oxide field effect transistor. The control end of the fifth transistor 430 is connected to the second end of the fourth transistor 410 through the fifth resistor 450. The first end of the fifth transistor 430 is connected to the pull-up power supply 502. The second end of the fifth transistor 430 is connected to all source driver chips 100 through the third node C. The fourth resistor 440 is connected to the pull-down power supply 501 and the third node C.

[0072] In the normal polarity mode, the first node A is at a low level, the fourth transistor 410 is turned off and the fifth transistor 430 is turned off, the pull-down power supply 501 outputs a low level signal to all source driver chips 100, and the polarity reversal mode of the display panel 20 is maintained as a single column reversal in both the row direction and the column direction; in the polarity symmetry mode, the first node A is at a high level, the fourth transistor 410 is turned off, the pull-up power supply 502 outputs a high level signal to the control end of the fifth transistor 430, the fifth transistor 430 is turned on, and the pull-up power supply 502 outputs a high level signal to all source driver chips 100 through the fifth transistor 430, and the polarity reversal mode of the display panel 20 is modified to a double column reversal in the row direction.

[0073] In some embodiments, the picture detection module 300 is a timing controller (TCON), which includes a waveform recognition unit 310, which is connected to the common electrode of the display panel 20 and the polarity partition control module 200. The waveform recognition unit 310 is used to control the polarity partition control module 200 to conduct the source driver chip 100 of the even column and the pull-up power supply 502 when the common electrode voltage Vcom exceeds the preset interval. It should be noted that the picture detection module 300 can be a timing controller, but is not limited thereto. The picture detection module 300 can also be an additional detection module, which can be determined according to the specific situation.

[0074] When the pixel voltage is offset during lateral crosstalk, it will cause coupling fluctuation of the common electrode voltage Vcom. In the waveform recognition unit 310, an interval value is set according to the common electrode voltage Vcom, that is, a positive and negative trigger value m1 and m2 are set, such as Figure 8 As shown, when it is recognized that the common electrode voltage Vcom exceeds the preset interval (greater than m1 and maintained for t1 time or less than m2 and maintained for t2 time, indicating that the lateral crosstalk is serious and the picture effect is poor), a high-level signal is output to the source driver chip 100 of the even-numbered columns, and the display panel 20 switches to the polarity symmetric mode. The pixel voltage and common voltage coupling directions of the adjacent first display area 21 and second display area 22 are opposite, so that the coupling can be offset and the lateral crosstalk can be improved or eliminated. On the contrary, when the common electrode voltage Vcom does not exceed the preset interval, the display panel 20 is in the normal polarity mode.

[0075] In some embodiments, the timing controller can detect the display screen and control the display panel 20 to a conventional polarity mode or a polarity symmetric mode according to the display screen. When using the timing controller to detect the display screen, some complex screens may not be detected, and the detection must be performed based on the pixel arrangement structure and number. The existing known lateral crosstalk screens may not be complete. If a new screen has lateral crosstalk later, then the pixel structure of this screen is different from the existing one, and the timing controller cannot detect it either. In addition, the lateral crosstalk phenomenon of different liquid crystals is inconsistent, and the unified setting cannot be fully compatible, which requires more debugging time.

[0076] In this embodiment, the waveform recognition unit 310 is connected to the common electrode of the display panel 20 and the polarity partition control module 200. The waveform recognition unit 310 switches the display panel 20 to a conventional polarity mode or a polarity symmetric mode according to the common electrode voltage Vcom. Compared with the solution of using a timing controller to detect the display screen, it can be generally used to detect different lateral crosstalk phenomena.

[0077] Embodiment 2

[0078] The main difference between the second embodiment and the first embodiment is that the structure of the polarity partition control module 200 is different.

[0079] See also Fig. 9 As shown, the polarity partition control module 200 includes a first transistor 210 and a first resistor 230. The first transistor 210 is an N-type metal oxide field effect transistor. The first end of the first transistor 210 is connected to the pull-up power supply 502. The second end of the first transistor 210 is connected to the source driver chip 100 of the even column through the first node A. The control end of the first transistor 210 is connected to the picture detection module 300 through the second node B. The first resistor 230 is connected to the pull-down power supply 501 and the first node A.

[0080] When the display screen detected by the picture detection module 300 has no crosstalk or the degree of crosstalk does not affect the display, and polarity partitioning is not required, a low-level signal is output to the polarity partitioning control module 200, the first transistor 210 of the polarity partitioning control module 200 is turned off, and the pull-down power supply 501 outputs a low-level signal to the source driver chip 100 of the even-numbered columns through the first resistor 230, forming a conventional polarity mode; when the display screen detected by the picture detection module 300 has serious crosstalk and polarity partitioning is required, a high-level signal is output to the polarity partitioning control module 200, the first transistor 210 of the polarity partitioning control module 200 is turned on, and the pull-up power supply 502 outputs a high-level signal to the source driver chip 100 of the even-numbered columns through the first transistor 210, forming a polarity symmetric mode.

[0081] In some embodiments, the polarity partition control module 200 further includes a second resistor 240 and a capacitor 250 , and the second resistor 240 and the capacitor 250 are both connected to the first node A and the second node B.

[0082] The second resistor 240 and the capacitor 250 can maintain the gate voltage of the first transistor 210 when the first transistor 210 is turned on, thereby improving circuit stability.

[0083] In some embodiments, the polarity partition control module 200 further includes a third transistor 260, the third transistor 260 is a triode, the control end of the third transistor 260 is connected to the picture detection module 300, the first end of the third transistor 260 is connected to the pull-up power supply 502, and the second end of the third transistor 260 is connected to the second node B. Fig.10 shown.

[0084] The picture detection module 300 controls the third transistor 260 to turn on or off, and the pull-up power supply 502 controls the first transistor 210 to turn on or off through the third transistor 260. The third transistor 260 is a triode that can amplify current. This design can avoid the control signal of the picture detection module 300 from attenuating, causing the control signal voltage to fluctuate, thereby affecting the mode switching of the polarity partition control module 200.

[0085] Embodiment 3

[0086] See also Fig.11 As shown, the display device in this embodiment includes the driving module 10 and the display panel 20 disclosed in the first and second embodiments, and the display panel 20 is connected to the source driving chip 100 of the driving module 10 .

[0087] In this embodiment, the display device includes a driving module 10, the driving module 10 includes a plurality of source driving chips 100, a polarity partition control module 200, a picture detection module 300 and an inversion mode control module 400, each source driving chip 100 is connected to a plurality of columns of data lines of the display panel 20, the source driving chips 100 of the odd columns are connected to the pull-down power supply 501, the source driving chips 100 of the even columns are connected to the pull-up power supply 502 and the pull-down power supply 501 through the polarity partition control module 200, the picture detection module 300 is connected to the display panel 20 and the polarity partition control module 200, and is used to detect the crosstalk of the display picture according to the detected The degree of control of the polarity partition control module 200 is to form a normal polarity mode and a polarity symmetry mode. In the normal polarity mode, the polarity partition control module 200 turns on the pull-down power supply 501 and the source driver chip 100 of the even-numbered columns. In the polarity symmetry mode, the polarity partition control module 200 turns on the pull-up power supply 502 and the source driver chip 100 of the even-numbered columns, so that the second display area 22 controlled by the source driver chip 100 of the even-numbered columns is polarity symmetrical with the first display area 21. The inversion mode control module 400 outputs a polarity inversion control signal to the source driver chip 100, and the polarity of the display panel 20 in the row direction is double-column inversion. In the polarity symmetry mode, the pixel voltage coupling directions of the display areas controlled by adjacent source driver chips 100 are opposite, which can offset the coupling and improve or eliminate lateral crosstalk. At the same time, the inversion mode control module 400 controls the polarity of the display panel 20 to be double-column inversion in the row direction, eliminating the difference in pixel polarity at the boundary position and other positions of the display area, thereby improving or eliminating lateral crosstalk and avoiding the formation of bright and dark lines at the boundary position, thereby improving the display effect of the display panel 20.

[0088] The terms "first", "second", etc. are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the indicated technical features. Thus, a feature defined as "first", "second", etc. may explicitly or implicitly include one or more of the feature. In the description of this application, the meaning of "plurality" is two or more, unless otherwise clearly and specifically defined.

[0089] In this application, unless otherwise clearly specified and limited, the terms "assembly", "connection" and the like should be understood in a broad sense, for example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be a direct connection or an indirect connection through an intermediate medium, it can be the internal connection of two elements or the interaction relationship between two elements. For ordinary technicians in this field, the specific meanings of the above terms in this application can be understood according to specific circumstances.

[0090] In the description of this specification, the description with reference to the terms "some embodiments", "exemplarily", etc. means that the specific features, structures, materials or characteristics described in conjunction with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner. In addition, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of the different embodiments or examples, without contradiction.

[0091] Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and cannot be understood as limitations on the present application. Ordinary technicians in this field can change, modify, replace and modify the above embodiments within the scope of the present application. Therefore, any changes or modifications made in accordance with the claims and description of the present application should fall within the scope of the patent of this application.

Claims

1. A driving module, comprising a plurality of source driving chips, each of which is connected to a plurality of columns of data lines of a display panel, characterized in that: The driving module also includes: A polarity partition control module, wherein the source driver chips of the odd columns are connected to a pull-down power supply, and the source driver chips of the even columns are connected to a pull-up power supply and the pull-down power supply through the polarity partition control module, and the pull-down power supply includes a ground terminal; An image detection module, connected to the display panel and the polarity partition control module, for controlling the polarity partition control module to work according to the detected crosstalk degree of the display image, so as to form a conventional polarity mode and a polarity symmetric mode; An inversion mode control module connected to all the source driving chips and one of the picture detection module and the polarity partition control module; Among them, in the normal polarity mode, the pull-down power supply is connected to the source driver chip of the even-numbered columns, and the source driver chip controls the display panel to be reversed in a single column in the row direction; in the polarity symmetry mode, the pull-up power supply is connected to the source driver chip of the even-numbered columns, and the reversal mode control module outputs a polarity reversal control signal to the source driver chip, so that the source driver chip controls the display panel to be reversed in a double column in the row direction.

2. The driving module according to claim 1, characterized in that: The polarity partition control module includes a first transistor and a second transistor, the first transistor is an N-type field effect transistor, the second transistor is a P-type field effect transistor, the control end of the first transistor and the control end of the second transistor are both connected to the picture detection module, the first end of the first transistor is connected to the pull-up power supply, the second end of the first transistor is connected to the source driver chip of the even column through a first node, the first end of the second transistor is connected to the pull-down power supply, and the second end of the second transistor is connected to the first node.

3. The driving module according to claim 1, characterized in that: The polarity partition control module includes a first transistor and a first resistor, the first transistor is an N-type field effect transistor, the first end of the first transistor is connected to the pull-up power supply, the second end of the first transistor is connected to the source driver chip of the even column through a first node, the control end of the first transistor is connected to the picture detection module through a second node, and the first resistor is connected to the pull-down power supply and the first node.

4. The driving module according to claim 3, characterized in that: The polarity partition control module also includes a third transistor, which is a triode. The control end of the third transistor is connected to the picture detection module, the first end of the third transistor is connected to the pull-up power supply, and the second end of the third transistor is connected to the second node.

5. The driving module according to any one of claims 2 to 4, characterized in that: The inversion mode control module is connected to the polarity partition control module through the first node.

6. The driving module according to claim 5, characterized in that: The inversion mode control module includes a fourth transistor, which is a triode. The control end of the fourth transistor is connected to the first node, the first end of the fourth transistor is connected to the pull-up power supply, and the second end of the fourth transistor is connected to all the source driver chips.

7. The driving module according to claim 6, characterized in that: The inversion mode control module also includes a fifth transistor and a fourth resistor, the fifth transistor is an N-type field effect transistor, the control end of the fifth transistor is connected to the second end of the fourth transistor, the first end of the fifth transistor is connected to the pull-up power supply, the second end of the fifth transistor is connected to all the source driver chips through a third node, and the fourth resistor is connected to the pull-down power supply and the third node.

8. The driving module according to claim 5, characterized in that: The inversion mode control module includes a fifth transistor and a fourth resistor, the fifth transistor is an N-type field effect transistor, the control end of the fifth transistor is connected to the first node, the first end of the fifth transistor is connected to the pull-up power supply, the second end of the fifth transistor is connected to all the source driver chips through a third node, and the fourth resistor is connected to the pull-down power supply and the third node.

9. The driving module according to claim 1, characterized in that: The picture detection module includes a timing controller, which includes a waveform recognition unit. The waveform recognition unit is connected to the common electrode of the display panel and the polarity partition control module. The waveform recognition unit is used to control the polarity partition control module to turn on the source driver chip and the pull-up power supply of the even column when the voltage of the common electrode exceeds a preset interval.

10. A display device, characterized in that: include: Display panel; The driving module as described in any one of claims 1 to 9, connected to the display panel.

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