Biasing circuit for reducing read string crosstalk

Abstract

The application provides a bias circuit for reducing read string interference. In a read operation on a selected memory cell, a control device is used to control the control gate voltage and the word line voltage of unselected memory cells according to a read enable signal. When the read enable signal is high, the control gate voltage of the unselected memory cells is set to a first high voltage and the word line voltage is set to a second high voltage in a first time period during which the read enable signal is high. The first high voltage ensures that the channel region controlled by the first gate structure of the unselected memory cells is turned on, and the second high voltage ensures that the channel region controlled by the second gate structure is turned on. When the read enable signal is low, the first and second high voltages are adjusted to a medium voltage in a second time period during which the read enable signal is low. The medium voltage is within the range of the first and second high voltages, and is used to prevent read interference in the second time period. The application can reduce read string interference while reducing the impact on speed and power consumption.

Description

TECHNICAL FIELD

[0001] The present application relates to the field of semiconductor technology, and in particular to a bias circuit for reducing read disturb. BACKGROUND

[0002] As shown in FIG. 1 is a circuit structure schematic diagram of a storage unit 101 of a prior art flash memory; as shown in FIG. 2 is a cross-sectional structure schematic diagram of the storage unit 101 of the prior art flash memory; each of the storage units 101 adopts a split-gate floating-gate device. Figure 1 Figure 2 As shown in FIG. 1 is a circuit structure schematic diagram of a storage unit 101 of a prior art flash memory; as shown in FIG. 2 is a cross-sectional structure schematic diagram of the storage unit 101 of the prior art flash memory; each of the storage units 101 adopts a split-gate floating-gate device.

[0003] As shown in FIG. 1 is a circuit structure schematic diagram of a storage unit 101 of a prior art flash memory; as shown in FIG. 2 is a cross-sectional structure schematic diagram of the storage unit 101 of the prior art flash memory; each of the storage units 101 adopts a split-gate floating-gate device. Figure 2 As shown in FIG. 1 is a circuit structure schematic diagram of a storage unit 101 of a prior art flash memory; as shown in FIG. 2 is a cross-sectional structure schematic diagram of the storage unit 101 of the prior art flash memory; each of the storage units 101 adopts a split-gate floating-gate device.

[0004] The split-gate floating-gate device is a double split-gate floating-gate device, and the number of the first gate structures is two, which are respectively indicated by marks 102a and 102b.

[0005] The split-gate floating-gate device is an N-type device, and the first source-drain region 205 and the second source-drain region 206 are both composed of N+ regions.

[0006] A P-type doped channel region is located between the first source-drain region 205 and the second source-drain region 206 and is covered by each of the first gate structures and the second gate structure 103. The first source-drain region 205 and the second source-drain region 206 are both formed in a P-type semiconductor substrate 201 and are self-aligned with the outer sides of the corresponding two first gate structures, and the channel region is composed of the P-type semiconductor substrate 201 between the first source-drain region 205 and the second source-drain region 206 or is further formed by doping on the P-type semiconductor substrate 201.

[0007] The second source-drain region 206 of the storage unit 101 is connected to a bit line BL1.

[0008] The first source-drain region 205 of the storage unit 101 is connected to a bit line BL0.

[0009] Each of the first gate structures is composed of a tunneling dielectric layer 202, the floating gate 104, a control gate dielectric layer 203 and the control gate 105.

[0010] Each of the second gate structures 103 is composed of a word line gate dielectric layer 204 and a word line gate 106. ​

[0011] Figure 2 In the embodiment, two control gates 105 can be controlled separately and connected to control gate lines CG0 and CG1 respectively, and the word line gate 106 is connected to a word line WL.

[0012] When reading the memory cell 101, taking the reading operation of the memory bit 'a' close to the first source-drain region 205 as an example, the control gate line CG0 is connected to 0V;

[0013] The word line WL is connected to 3.5V;

[0014] The control gate line CG1 is connected to 5.4V;

[0015] The word line WL is connected to 3.5V;

[0016] As shown in FIG. 1, it is a read voltage curve of a read circuit of a memory cell of a prior art flash memory during a read operation; Figure 3 Figure 3 In the embodiment, the read voltage includes the control gate voltage of an unselected memory bit and the word line voltage, which is also denoted as WL, and the control gate voltage of an unselected memory bit is denoted as CG, Figure 3 In the embodiment, only the high and low levels of WL or CG are represented in the read voltage curve, and the actual voltage is not represented, so the voltage change of WL or CG adopts the same curve, and the corresponding curve is the WL / CG curve.

[0017] As can be seen, in the WL / CG curve, the read voltage will switch between the high voltage, i.e. the high level 'H', and the low voltage, i.e. the low level 'L'. When the WL / CG is the high level 'H', the read disturb will be generated if the read enable signal SEB is the low level.

[0018] To solve the above problems, a new bias circuit for reducing read disturb needs to be proposed. SUMMARY

[0019] In view of the above-mentioned disadvantages of the prior art, the purpose of the present application is to provide a bias circuit for reducing read disturb, which is used to solve the problem of read disturb in the prior art flash memory.

[0020] To achieve the above-mentioned purpose and other related purposes, the present application provides a bias circuit for reducing read disturb, which comprises:

[0021] The flash memory comprises a plurality of memory cells, each of which adopts a split gate floating gate device.

[0022] ​The isolated gate floating gate device comprises: a first source-drain region and a second source-drain region, a plurality of isolated first gate structures with floating gates between the first source-drain region and the second source-drain region, a second gate structure between the first gate structures; the first gate structure has a control gate on top of the floating gate;

[0023] A channel region is between the first source-drain region and the second source-drain region and is covered by each of the first gate structures and the second gate structure, each of the first gate structures and the second gate structure controls a region segment of the channel region;

[0024] The floating gate of each of the first gate structures serves as a storage bit;

[0025] The control gate of each of the first gate structures is connected to a corresponding control gate line;

[0026] Each of the second gate structures is connected to a corresponding word line;

[0027] A read circuit is configured to provide a control gate voltage for each of the control gate lines and a word line voltage for the word line during a read operation;

[0028] In a read operation of a selected storage cell, a control device is configured to control the control gate voltage and the word line voltage of unselected storage bits according to a read enable signal, comprising:

[0029] When the read enable signal is high, the control gate voltage of the unselected storage bits is set to a first high voltage and the word line voltage is set to a second high voltage during the first time period of the high level, the first high voltage ensures that the region segment of the channel region controlled by the first gate structure of the unselected storage bits is turned on, and the second high voltage ensures that the region segment of the channel region controlled by the second gate structure is turned on;

[0030] When the read enable signal is low, the first and second high voltages are adjusted to a medium voltage during the second time period of the low level, the medium voltage is in the range between the first and second high voltages, to prevent read disturbance in the second time period.

[0031] Preferably, the read enable signal is a pulse signal.

[0032] Preferably, the control device further comprises a chip enable signal, which sets a chip enable time period of the flash memory.

[0033] Preferably, in the chip enable time period, a cycle unit is composed of the first time period and the second time period and is cycled more than once; at the end of the chip enable time period, the control gate voltage of the unselected memory bit and the word line voltage are set to the low voltage.

[0034] Preferably, the low voltage is a ground voltage.

[0035] Preferably, the control device comprises a pre-decoder for converting binary codes with specific meanings into corresponding output signals, a first and a second level converter and a first and a second driving circuit; the first high voltage is connected to the control gate line through the first level converter and the first driving circuit, and the first medium voltage is connected to the control gate line through the driving circuit; the second high voltage is connected to the control gate line through the second level converter and the second driving circuit, and the second medium voltage is connected to the control gate line through the driving circuit.

[0036] Preferably, the control device further comprises a plurality of charge pumps, and the first and second high voltages and the medium voltage are respectively output by corresponding charge pumps.

[0037] Preferably, the control device comprises two charge pumps; the first charge pump comprises a plurality of output terminals for respectively outputting the second high voltage and the medium voltage; and the second charge pump comprises a plurality of output terminals for respectively outputting the first high voltage and the medium voltage.

[0038] Preferably, the control device further comprises a first to third switch circuit; the output terminals of the first charge pump are connected to the first switch circuit, the output terminals of the second charge pump are connected to the second switch circuit, and the selection terminal of the third switch circuit is connected to a read enable signal; the third switch is respectively connected to the first and second switch circuits; when the read enable signal is at a low level, the third switch circuit is opened, the first and second switch circuits are closed, and the control gate voltage and the word line voltage are the medium voltage; when the read enable signal is at a high level, the third switch circuit is closed, the first and second switch circuits are opened, the control gate voltage is the first high voltage, and the word line voltage is the second high voltage.

[0039] Preferably, the third switch circuit comprises a first PMOS transistor and a second PMOS transistor, the gate of the first PMOS transistor and the gate of the second PMOS transistor are connected together and serve as a selection terminal, and the drain of the first PMOS transistor and the drain of the second PMOS transistor are connected together.

[0040] As described above, the bias circuit for reducing read crosstalk of the application has the following beneficial effects:

[0041] The present application can reduce read disturb while reducing the impact on speed and power consumption by balancing the CG / WL voltage during non-sensing time. BRIEF DESCRIPTION OF DRAWINGS

[0042] Figure 1 A circuit structure schematic diagram of a memory cell of a flash memory as prior art;

[0043] Figure 2 A schematic diagram of a split-gate floating gate device as prior art;

[0044] Figure 3 A read voltage curve schematic diagram of a read circuit of a memory cell of a flash memory as prior art during a read operation;

[0045] Figure 4 A bias circuit schematic diagram for reducing read disturb as the present application;

[0046] Figure 5 A circuit schematic diagram for generating a middle voltage as the present application;

[0047] Figure 6 A read voltage curve schematic diagram of a read circuit of a memory cell of a flash memory as the present application during a read operation. DETAILED DESCRIPTION

[0048] The present application is described in detail below with specific reference being made to certain specific examples. Those skilled in the art will readily understand other advantages and benefits of the present application from the following description, taken in connection with the accompanying drawings. The present application can be embodied in other different forms without departing from the spirit of the present application, and the details of the present application can be modified in various ways based on different viewpoints and applications without departing from the spirit of the present application.

[0049] Reference will now be made to Figure 4 The present application provides a bias circuit for reducing read disturb, comprising:

[0050] A flash memory comprising a plurality of memory cells, each memory cell employing a split-gate floating gate device;

[0051] The split-gate floating gate device comprises: a first source-drain region and a second source-drain region, a plurality of split first gate structures with floating gates located between the first source-drain region and the second source-drain region, and a second gate structure located between the first gate structures; the first gate structures each have a control gate located on top of the floating gate;

[0052] A channel region is located between the first source-drain region and the second source-drain region and is covered by each first gate structure and the second gate structure, and each first gate structure and the second gate structure controls a region segment of the channel region;

[0053] The floating gate of each first gate structure serves as a storage bit;

[0054] the control gate of each first gate structure is connected to a corresponding control gate line;

[0055] each second gate structure is connected to a corresponding word line;

[0056] the read circuit is configured to provide a control gate voltage for each control gate line and a word line voltage for each word line during a read operation;

[0057] Referring to Figure 6 In a read operation of a selected memory cell, the control device is configured to control the control gate voltage and the word line voltage of unselected memory cells according to a read enable signal SEN, including:

[0058] when the read enable signal SEN is high, the control gate voltage of the unselected memory cells is set to a first high voltage ZVDD_CG for a first time period during which the high level is maintained, and the word line voltage is set to a second high voltage ZVDD_WL, the first high voltage ZVDD_CG ensures that the region of the channel region controlled by the first gate structure of the unselected memory cell is turned on, and the second high voltage ZVDD_WL ensures that the region of the channel region controlled by the second gate structure is turned on;

[0059] when the read enable signal SEN is low, the first and second high voltages are adjusted to a medium voltage (ZVDDL_WL, ZVDDL_CG) for a second time period during which the low level is maintained, the medium voltage (ZVDDL_WL, ZVDDL_CG) is within the range of the first and second high voltages, and is used to prevent read interference during the second time period.

[0060] By balancing the CG / WL voltage during the non-induction time, the read crosstalk can be reduced while reducing the impact on speed and power consumption.

[0061] In some embodiments, the read enable signal SEN is a pulse signal.

[0062] In some embodiments, the control device further includes a chip enable signal that sets a chip enable time period of the flash memory.

[0063] In some embodiments, in the chip enable time period, a cycle unit composed of the first time period and the second time period is repeated more than once; at the end of the chip enable time period, the control gate voltage and the word line voltage of the unselected memory cells are set to a low voltage.

[0064] In some embodiments, the low voltage is a ground voltage.

[0065] In some embodiments, the control device comprises: a pre-decoder for converting binary codes with specific meanings into corresponding output signals; first and second level converters and first and second driving circuits; a first high voltage ZVDD_CG connected to the control gate line through the first level converter and the first driving circuit, a first middle voltage (ZVDDL_WL, ZVDDL_CG) connected to the control gate line through the driving circuit; a second high voltage ZVDD_WL connected to the control gate line through the second level converter and the second driving circuit, and a second middle voltage (ZVDDL_WL, ZVDDL_CG) connected to the control gate line through the driving circuit.

[0066] In some embodiments, the control device further comprises a plurality of charge pumps, and the first and second high voltages and the middle voltages (ZVDDL_WL, ZVDDL_CG) are respectively output by corresponding charge pumps.

[0067] In some embodiments, referring to Figure 5 , the control device comprises two charge pumps; the first charge pump comprises a plurality of output terminals for respectively outputting the second high voltage ZVDD_WL and the middle voltages (ZVDDL_WL, ZVDDL_CG); and the second charge pump comprises a plurality of output terminals for respectively outputting the first high voltage ZVDD_CG and the middle voltages (ZVDDL_WL, ZVDDL_CG).

[0068] In some embodiments, the control device further comprises first to third switch circuits; the output terminals of the first charge pump are connected to the first switch circuit, the output terminals of the second charge pump are connected to the second switch circuit, the selection terminal of the third switch circuit is connected to the read enable signal SEN, and the third switch is respectively connected to the first and second switch circuits; when the read enable signal SEN is at a low level, the third switch circuit is opened, the first and second switch circuits are closed, and the control gate voltage and the word line voltage are the middle voltages (ZVDDL_WL, ZVDDL_CG); when the read enable signal SEN is at a high level, the third switch circuit is closed, the first and second switch circuits are opened, the control gate voltage is the first high voltage ZVDD_CG, and the word line voltage is the second high voltage ZVDD_WL.

[0069] In some embodiments, the third switch circuit comprises: a first PMOS transistor and a second PMOS transistor, the gate of the first PMOS transistor and the gate of the second PMOS transistor are connected together and serve as the selection terminal; and the drain of the first PMOS transistor and the drain of the second PMOS transistor are connected together.

[0070] It is to be noted that the drawings provided in the embodiments only schematically illustrate the basic concept of the present application, and only the components related to the present application are shown in the drawings, not the number, shape and size of the components when actually implemented. The shape, number and ratio of the components when actually implemented can be arbitrarily changed, and the layout of the components can be more complex.

[0071] In summary, the present application can reduce the read string interference while reducing the impact on speed and power consumption by balancing the CG / WL voltage during non-induction time. Therefore, the present application effectively overcomes the various shortcomings in the prior art and has a high industrial utilization value.

[0072] The above embodiments only exemplarily illustrate the principles and effects of the present application, and are not used to limit the present application. Any person skilled in the art can modify or change the above embodiments without departing from the spirit and scope of the present application. Therefore, all equivalent modifications or changes made by those skilled in the art without departing from the spirit and technical ideas disclosed by the present application should be covered by the claims of the present application.

Claims

1. A bias circuit for reducing read crosstalk, characterized in that, include; Flash memory consists of multiple storage cells, each of which uses a discrete-gate floating-gate device; The split-gate floating gate device includes: a first source-drain region and a second source-drain region, a plurality of split first gate structures with floating gates located between the first source-drain region and the second source-drain region, and a second gate structure located between the first gate structures; the first gate structure has a control gate located on top of the floating gate. The channel region is located between the first source / drain region and the second source / drain region and is covered by each of the first gate structure and the second gate structure, each of the first gate structure and the second gate structure controlling a segment of the channel region; Each of the floating gates of the first gate structure serves as a storage bit; The control gate of each of the first gate structures is connected to a corresponding control gate line; Each of the second gate structures is connected to the corresponding word line; The read circuitry provides control gate voltages to each of the control gate lines and word line voltages to the word lines during a read operation. In a read operation on a selected memory cell, the control device controls the control gate voltages and word line voltages for unselected memory bits based on a read enable signal, including: When the read enable signal is high, the duration for which the read enable signal remains high is defined as a first time period. During the first time period, the control gate voltage of the unselected memory bit is set to a first high voltage and the word line voltage is set to a second high voltage. The first high voltage ensures that the channel region controlled by the first gate structure of the unselected memory bit is turned on and the second high voltage ensures that the channel region controlled by the second gate structure is turned on. When the read enable signal is low, the duration for which the read enable signal remains low is defined as a second time period. During the second time period, the first and second high voltages are adjusted to medium voltages. The range of the medium voltages is between the first and second high voltages, in order to prevent read interference during the second time period. The control device includes: a pre-decoder for converting an input binary code into a corresponding output signal; a first and second level converter and a first and second driving circuit; a first high voltage connected to the control gate line through the first level converter and the first driving circuit, and a middle voltage connected to the control gate line through the first driving circuit; a second high voltage connected to the word line through the second level converter and the second driving circuit, and a middle voltage connected to the word line through the second driving circuit.

2. The bias circuit for reducing read crosstalk according to claim 1, characterized in that: The read enable signal is a pulse signal.

3. The bias circuit for reducing read crosstalk according to claim 1, characterized in that: The control device further includes setting a chip enable signal, which sets the chip enable time period of the flash memory.

4. The bias circuit for reducing read crosstalk according to claim 3, characterized in that: During the chip enable time period, the first time period and the second time period form a loop unit and cycle more than once; at the end of the chip enable time period, the control gate voltage and the word line voltage of the unselected memory bit are both set to the low level.

5. The bias circuit for reducing read crosstalk according to claim 4, characterized in that: The low level is the ground voltage.

6. The bias circuit for reducing read crosstalk according to claim 1, characterized in that: The control device also includes multiple charge pumps, and the first and second high voltages and the medium voltage are output by the corresponding charge pumps.

7. The bias circuit for reducing read crosstalk according to claim 6, characterized in that: The control device includes two charge pumps; the first charge pump includes multiple output terminals, which output the second high voltage and the medium voltage respectively; the second charge pump includes multiple output terminals, which output the first high voltage and the medium voltage respectively.

8. The bias circuit for reducing read crosstalk according to claim 7, characterized in that: The control device further includes a first to a third switching circuit; the output terminal of the first charge pump is connected to the first switching circuit, the output terminal of the second charge pump is connected to the second switching circuit, the selection terminal of the third switching circuit receives a read enable signal, and the third switching circuit is also connected to the first and second switching circuits respectively; when the read enable signal is low, the third switching circuit is open, the first and second switching circuits are closed, and the control gate voltage and the word line voltage are the medium voltage; when the read enable signal is high, the third switching circuit is closed, the first and second switching circuits are open, the control gate voltage is the first high voltage, and the word line voltage is the second high voltage.

9. The bias circuit for reducing read crosstalk according to claim 8, characterized in that: The third switching circuit includes: a first PMOS transistor and a second PMOS transistor, wherein the gates of the first PMOS transistor and the second PMOS transistor are connected together and serve as selection terminals; and the drains of the first PMOS transistor and the second PMOS transistor are connected together.

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