A control circuit

Abstract

The embodiment of the application discloses a control circuit, which comprises a period control module, a conduction time control module and a driving module. The period control module is used for outputting a first control signal. The driving module is used for controlling a first switch tube in a step-down power factor correction (PFC) circuit to be turned on in the case that the first control signal changes from a low level to a high level. The conduction time control module is used for outputting a second control signal. The second control signal changes from a low level to a high level when the first product of a first average current value and a current conduction time of the first switch tube reaches a second preset threshold. The first average current value is an average current value of a first current signal in one switching cycle of the first switch tube. The driving module is used for controlling the first switch tube to be turned off in the case that the second control signal changes from a low level to a high level. The embodiment of the application can save the control cost of the step-down PFC circuit.

Description

TECHNICAL FIELD

[0001] The present application relates to the drive technology field, and particularly relates to a control circuit. BACKGROUND

[0002] With the rapid development of fast charging technology, the power supply of consumer electronic devices such as mobile phones, tablets, computers, notebooks and televisions is increasing, so it is necessary to equip the power factor correction (PFC) circuit in the power adapter to meet the requirements of GB17625.1 standard and IEC61000-3-2 standard for input current harmonics. For adapter power supply, when the power is more than 100W, an active PFC circuit is usually used. The active PFC circuit is to control the DC / DC conversion circuit composed of power electronic switching devices to make the average input current value of the PFC circuit follow the input voltage value, so as to realize power factor correction. In order to be suitable for high-power scenarios, the working mode of the conversion circuit in the active PFC circuit is usually continuous current mode (CCM), and in the CCM mode, the control principle of the traditional PFC circuit is to sample the input voltage and multiply it with the output voltage value of the voltage outer loop circuit as the reference value of the current inner loop circuit control, and then control the average input current to follow the sinusoidal input voltage to realize power factor correction. The above control method is complex and high in cost.

[0003] For the active PFC circuit with DC / DC conversion circuit as a boost circuit (i.e. Boost PFC), the prior art adopts a peak current single cycle control method, which can realize the effect of average current following input voltage without sampling input voltage, simplifying the PFC circuit control in CCM mode. However, the scenario that needs to be stepped down usually uses a step-down PFC circuit (such as Buck PFC), because the circuit structures of the step-down PFC circuit and the Boost PFC circuit are different, the input current of the step-down PFC circuit is discontinuous, and the peak input current and the average input current of the step-down PFC circuit do not have a linear relationship, so the above peak current single cycle control method is no longer applicable. Therefore, how to save the control cost of the step-down PFC circuit is a technical problem to be solved by those skilled in the art. SUMMARY

[0004] The embodiment of the present application discloses a control circuit for saving the control cost of the step-down PFC circuit.

[0005] In a first aspect, an embodiment of the present application provides a control circuit, the control circuit comprising a period control module 11, a conduction time control module 12 and a driving module 13, wherein: the period control module 11 is configured to output a first control signal V_ON, a period of the first control signal V_ON being a first preset threshold; the driving module 13 is configured to control a first switch Q1 in a buck power factor correction (PFC) circuit 2 to turn on in a case where the first control signal V_ON changes from a low level to a high level, a working mode of the buck PFC circuit 2 being a continuous current mode (CCM), an input current value of the buck PFC circuit 2 being equal to a current value of a first current signal I_Q1 flowing through the first switch Q1; the conduction time control module 12 is configured to output a second control signal V_OFF, the second control signal V_OFF changing from the low level to the high level in a case where a first product of a first average current value and a current conduction time of the first switch Q1 reaches a second preset threshold, the first average current value being an average current value of the first current signal I_Q1 in one switching period of the first switch Q1; and the driving module 13 is configured to control the first switch Q1 to turn off in a case where the second control signal V_OFF changes from the low level to the high level.

[0006] The control circuit can control a maximum value of the first product (i.e., a product of an average input current value of the buck PFC circuit 2 and a total conduction time of the first switch Q1) to be a constant value (i.e., equal to the second preset threshold) in one switching period of the first switch Q1 in the buck PFC circuit 2, so as to control the average input current value of the buck PFC circuit 2 to follow a change in an input voltage value, thereby controlling the buck PFC circuit 2 to achieve power factor correction without sampling the input voltage, and further reducing a control cost of the buck PFC circuit 2.

[0007] In combination with the first aspect, in a possible implementation manner, the conduction time control module 12 comprises a current sampling module 121 and an operation module 122, wherein: the current sampling module 121 is configured to convert the first current signal I_Q1 into a first voltage signal V_CS, a current value of the first current signal I_Q1 being proportional to a voltage value of the first voltage signal V_CS; the operation module 122 is configured to, in a case where the first switch Q1 is turned on, perform an operation on the first voltage signal V_CS to generate a second voltage signal V_INT2, a voltage value of the second voltage signal V_INT2 being proportional to the first product; and the operation module 122 is further configured to output the second control signal V_OFF, the second control signal V_OFF changing from the low level to the high level in a case where the voltage value of the second voltage signal V_INT2 reaches a third preset threshold.

[0008] The control circuit can sample the first current signal I_Q1 flowing through the first switch tube Q1, and operate the first voltage signal V_CS obtained after sampling when the first switch tube Q1 is turned on, so that the voltage value of the second voltage signal V_INT2 obtained during the conduction of the first switch tube Q1 is proportional to the first product, and the maximum value of the voltage value of the second voltage signal V_INT2 is a constant value (i.e. equal to the third preset threshold), thereby indirectly making the maximum value of the first product in a single switching cycle of the first switch tube Q1 constant, and further controlling the average input current value of the Buck PFC circuit 21 to follow the input voltage value.

[0009] With reference to the first aspect, or any possible implementation manner of the first aspect, in another possible implementation manner, the operation module 122 comprises a voltage amplification circuit GAIN, a voltage sampling and holding circuit S / H, a plus-minus operation circuit SUM, and an integration circuit 1221; the positive input end of the plus-minus operation circuit SUM is connected to the output end of the voltage amplification circuit GAIN, the negative input end of the plus-minus operation circuit SUM is connected to the output end of the voltage sampling and holding circuit S / H, and the output end of the plus-minus operation circuit SUM is connected to the input end of the integration circuit 1221, wherein: the voltage amplification circuit GAIN is configured to amplify the first voltage signal V_CS to output a third voltage signal V_GAIN, and the voltage value of the third voltage signal V_GAIN is proportional to the voltage value of the first voltage signal V_CS; the voltage sampling and holding circuit S / H is configured to output a fourth voltage signal V_SH, and the voltage value of the fourth voltage signal V_SH is equal to the initial voltage value of the first voltage signal V_CS when the first switch tube Q1 starts to conduct; the plus-minus operation circuit SUM is configured to output a fifth voltage signal V_SUM, and the voltage value of the fifth voltage signal V_SUM is equal to the difference between the voltage value of the third voltage signal V_GAIN and the voltage value of the fourth voltage signal V_SH; and the integration circuit 1221 is configured to, in the case that the first switch tube Q1 is turned on, perform two-stage integration on the fifth voltage signal V_SUM with respect to time to generate the second voltage signal V_INT2.

[0010] With reference to the first aspect, or any possible implementation manner of the first aspect, in a possible implementation manner, the operation module 122 further comprises a comparator CMP and a voltage loop module 1222, a positive input terminal of the comparator CMP is connected to an output terminal of the integral circuit 1221, and a negative input terminal of the comparator CMP is connected to an output terminal of the voltage loop module 1222, wherein: the voltage loop module 1222 is configured to output a sixth voltage signal V_C according to a voltage difference between the reference voltage signal and an output voltage signal V_OUT of the buck PFC circuit 2, and a voltage value of the sixth voltage signal V_C is equal to a third preset threshold value; and the comparator CMP is configured to compare the sixth voltage signal V_C and the second voltage signal V_INT2, and output a second control signal V_OFF.

[0011] With reference to the first aspect, or any possible implementation manner of the first aspect, in a possible implementation manner, a first input terminal of the integral circuit 1221 is connected to an output terminal of the adder-subtract circuit SUM, a first output terminal of the drive module 13 is connected to a gate of the first switch Q1, a second output terminal of the drive module 13 is connected to a second input terminal of the integral circuit 1221, a first input terminal of the drive module 13 is connected to an output terminal of the period control module 11, and a second input terminal of the drive module 13 is connected to an output terminal of the comparator CMP, wherein: the drive module 13 is further configured to control the integral circuit 1221 to output the second voltage signal V_INT2 in a case where the first control signal V_ON changes from a low level to a high level; and the drive module 13 is further configured to control a voltage value of the second voltage signal V_INT2 to be zero in a case where the second control signal V_OFF changes from a low level to a high level.

[0012] With reference to the first aspect or any possible implementation of the first aspect, in a possible implementation, the integration circuit 1221 comprises a first integration circuit 1221 and a second integration circuit 1221, a first input terminal of the integration circuit 1221 is connected to a first input terminal of the first integration circuit 1221, an output terminal of the first integration circuit 1221 is connected to a first input terminal of the second integration circuit 1221, an output terminal of the second integration circuit 1221 is connected to an output terminal of the integration circuit 1221, a second input terminal of the integration circuit 1221 is connected to a second input terminal of the first integration circuit 1221 and a second input terminal of the second integration circuit 1221, wherein: the driving module 13 is configured to output, through the second output terminal of the driving module 13, a third control signal V_RST, the third control signal V_RST is changed from high level to low level when the first control signal V_ON is changed from low level to high level, the third control signal V_RST is changed from low level to high level when the second control signal V_OFF is changed from low level to high level; the first integration circuit 1221 is configured to, in a case that the third control signal V_RST is low level, perform first-order integration on the fifth voltage signal V_SUM with respect to time to generate a seventh voltage signal; and the second integration circuit 1221 is configured to, in a case that the third control signal V_RST is low level, perform first-order integration on the seventh voltage signal with respect to time to generate the second voltage signal V_INT2.

[0013] With reference to the first aspect or any possible implementation of the first aspect, in a possible implementation, the driving module 13 comprises a flip-flop SR and a driving circuit DRV, the first input terminal of the driving module 13 is connected to a set terminal of the flip-flop SR, the second input terminal of the driving module 13 is connected to a reset terminal of the flip-flop SR, a first output terminal of the flip-flop SR is connected to an input terminal of the driving circuit DRV, an output terminal of the driving circuit DRV is connected to the first output terminal of the driving module 13, and a second output terminal of the flip-flop SR is connected to the second output terminal of the driving module 13.

[0014] With reference to the first aspect or any possible implementation of the first aspect, in a possible implementation, the voltage value V cs_int2 satisfies the following formula:

[0015] V cs_int2 = β0 * ∫0 t (∫0 t V cs_s dt)dt

[0016] V cs_s = V cs_g -V cs0 = 3V cs -V cs 0

[0017] wherein, β0 is a preset second integral coefficient, V cs_s is a voltage value of the fifth voltage signal V_SUM, V cs_g is a voltage value of the third voltage signal V_GAIN, V cs0 is a voltage value of the fourth voltage signal V_SH, V cs is a voltage value of the first voltage signal V_CS.

[0018] With reference to the first aspect, or any possible implementation manner of the first aspect, in a further possible implementation manner, the buck PFC circuit 2 comprises a buck PFC circuit 21, a forward topology PFC circuit 71, or a push-pull topology PFC circuit 72.

[0019] In a second aspect, an embodiment of the present application provides a control device, which comprises the control circuit described in the first aspect or any possible implementation manner of the first aspect.

[0020] In a third aspect, an embodiment of the present application provides a PFC device, which comprises the control circuit described in the first aspect or any possible implementation manner of the first aspect and the buck PFC circuit.

[0021] The related devices provided in the second and third aspects of the present application have the beneficial effects of the first aspect, which will not be repeated here. SUMMARY

[0022] The drawings used in the description of the embodiments of the present application will be briefly introduced as follows.

[0023] Figure 1 is a structural schematic diagram of a control circuit provided by an embodiment of the present application;

[0024] Figure 2 is a structural schematic diagram of another control circuit provided by an embodiment of the present application;

[0025] Figure 3 is a structural schematic diagram of a voltage loop module provided by an embodiment of the present application;

[0026] Figure 4 is a structural schematic diagram of a driving module provided by an embodiment of the present application;

[0027] Figure 5 is a signal waveform diagram provided by an embodiment of the present application;

[0028] Figure 6 is another signal waveform diagram provided by an embodiment of the present application;

[0029] Figure 7ais a structural schematic diagram of a Buck PFC circuit provided by an embodiment of the present application.

[0030] Figure 7b is a structural schematic diagram of a forward topology PFC circuit provided by an embodiment of the present application.

[0031] Figure 7c is a structural schematic diagram of a push-pull topology PFC circuit provided by an embodiment of the present application. DETAILED DESCRIPTION

[0032] The embodiments of the present application will be described in detail below with reference to the accompanying drawings.

[0033] Please refer to Figure 1 , Figure 1 is a structural schematic diagram of a control circuit provided by an embodiment of the present application. The control circuit 1 comprises a period control module 11, a conduction time control module 12 and a driving module 13. The output end a of the period control module 11 is connected to the first input end b1 of the driving module, and the output end c of the conduction time control module 12 is connected to the second input end b2 of the driving module. The control circuit 1 can control the average input current value I avg of the Buck PFC circuit 2 to follow the input voltage value V in , so as to realize power factor correction.

[0034] The Buck PFC circuit 2 comprises a first switch Q1, and the input current value I in of the Buck PFC circuit 2 is equal to the current value I1 of a first current signal I_Q1 flowing through the first switch Q1, and the working mode of the Buck PFC circuit 2 is continuous current mode CCM. It can be understood that the first switch Q1 can be regarded as a main switch in the Buck PFC circuit 2. The embodiments of the present application do not make strict limitation to the specific circuit structure of the Buck PFC circuit 2. For example, the Buck PFC circuit 2 can be a Buck PFC circuit, a forward topology PFC circuit or a push-pull topology PFC circuit. In addition, in actual application, the direct current at the input end of the Buck PFC circuit 2 is usually obtained by AC / DC conversion of the alternating current of an alternating current power supply. For example, as shown in FIG. 2, the Buck PFC circuit 2 comprises a rectifier circuit 21 and a Buck PFC circuit 22. The rectifier circuit 21 is connected to the alternating current power supply, and the Buck PFC circuit 22 is connected to the rectifier circuit 21. Figure 1As shown, the input terminal of the buck PFC circuit 2 is connected to the AC / DC converter circuit 3. The AC / DC converter circuit 3 includes an AC power supply S, an electromagnetic interference (EMI) filter circuit 31, and a rectifier bridge DBI. The output terminal of the AC power supply S is connected to the rectifier bridge DBI through the EMI filter circuit 31, and the output terminal of the rectifier bridge DBI is connected to the input terminal of the buck PFC circuit 2. The EMI filter circuit 31 is used to filter out circuit interference, and the rectifier bridge DBI is used to convert the sinusoidal AC voltage signal V_AC output from the AC power supply S into a DC voltage signal with a wavy shape (i.e., the input voltage signal V_IN of the buck PFC circuit 2) for output.

[0035] From the output side perspective, the input voltage value V of the buck PFC circuit 2 is... in Average input current value I avg and equivalent impedance R e Satisfies formula (1-1):

[0036] v in =I avg *R e (1-1)

[0037] According to the second-volt balance principle, under continuous current mode (CCM), the output voltage V of buck PFC circuit 2 is... out and input voltage value V in The ratio of the first switch Q1 to the duty cycle D on Proportional. Assuming the proportionality constant is k1, then the output voltage value V out Input voltage value V in and duty cycle D on Satisfies formula (1-2):

[0038]

[0039] Formula (1-3) is derived from formulas (1-1) and (1-2):

[0040]

[0041] Among them, T on For the first switching transistor Q1 in a single switching cycle T s The total dry-through time within the period (hereinafter referred to as the total dry-through time T) on ).

[0042] In the control circuit 1, the period control module 11 is configured to output a first control signal V_ON, and a period of the first control signal is a first preset threshold. The drive module 13 is configured to control the first switch Q1 in the buck PFC circuit 2 to be turned on when the first control signal changes from low level to high level. It can be understood that the first control signal V_ON is a voltage signal with continuity and periodicity formed by high and low level combination, and the first control signal V_ON can be a pulse signal with fixed frequency.

[0043] The on-time control module 12 is configured to output a second control signal V_OFF, and the second control signal V_OFF changes from low level to high level when a first product of the first average current value and the current on-time t on of the first switch Q1 reaches a second preset threshold, the first average current value is an average current value of the first current signal I_Q1 in a single switching period T s of the first switch Q1. The drive module 13 is configured to control the first switch Q1 to be turned off when the second control signal changes from low level to high level. It can be understood that the total on-time T on of the first switch Q1 is the time when the first product reaches the second preset threshold, and the switching period T s of the first switch Q1 is a constant value, which is equal to the period of the first control signal V_ON, i.e. equal to the first preset threshold. Then, in the single switching period T s of the first switch Q1, the maximum value of the first product is equal to the product of the first average current value and the total on-time T on , i.e. always equal to the second preset threshold. Since the input current value I in of the buck PFC circuit 2 is equal to the current value I1 of the first current signal I_Q1 flowing through the first switch Q1, the first average current value is equal to the average input current value I avg of the buck PFC circuit 2, and the maximum value of the first product is equal to the product of the average input current value I avg of the buck PFC circuit 2 and the total on-time T on of the first switch Q1.

[0044] It can be known from the formula (1-3) that the left side of the formula (1-3) is the maximum value of the first product, and the right side of the formula is the second preset threshold. Since the switching period T s of the first switch Q1 is a constant value, and the output voltage V out of the buck PFC circuit 2 when the buck PFC circuit 2 works stably can be regarded as a constant value, therefore, the control circuit 1 can realize that the equivalent impedance R e of the buck PFC circuit 2 is a constant value, and then it can be known from the formula (1-1) that the average input current value I avgFollow the input voltage value V in change.

[0045] Therefore, it can be seen that the control circuit 1 in this embodiment can control the average input current value I of the buck PFC circuit 2 within a single switching cycle of the first switching transistor Q1 in the buck PFC circuit 2. avg The total on-time T of the first switch Q1 on The product of these values ​​is a constant (i.e., equal to the second preset threshold) to control the average input current value I of the buck PFC circuit 2. avg Follow the input voltage value V in The change allows the buck PFC circuit 2 to achieve power factor correction without sampling the input voltage, thus saving the control cost of the buck PFC circuit.

[0046] The following text combines Figures 2 to 7c right Figure 1 The working principle of the control circuit 1 shown will be further explained.

[0047] In one alternative implementation, Figure 1 The step-down PFC circuit 2 shown is a Buck PFC circuit. The first control signal V_ON is a pulse signal with a fixed frequency, and the on-time control module 12 includes a current sampling module and a calculation module. Please refer to [link to relevant documentation]. Figure 2 , Figure 2 This is a schematic diagram of another control circuit provided in the embodiments of this application.

[0048] like Figure 2 As shown, the Buck PFC circuit 21 includes a first capacitor C1, a second capacitor C2, a first diode D1, a first switching transistor Q1, and a first inductor L1. The positive input terminal i1 of the Buck PFC circuit 21 is connected to one end of the first capacitor C1, the negative terminal of the first diode D1, one end of the second capacitor C2, and the positive output terminal o1 of the Buck PFC circuit 21. The positive terminal of the first diode D1 is connected to one end of the first inductor L1 and the drain of the first switching transistor Q1. The other end of the second capacitor C2 is connected to the other end of the first inductor L1 and the negative output terminal o2 of the Buck PFC circuit 21. The negative input terminal i2 of the Buck PFC circuit 21 is connected to the other end of the first capacitor C1, the source of the first switching transistor Q1, and reference ground.

[0049] The first input end e1 of the conduction time control module 12 in the control circuit 1 is connected with the source of the first switch tube Q1, the second input end e2 of the conduction time control module 12 is connected with the output end of the Buck PFC circuit 21, the first output end d1 of the drive module 13 is connected with the gate of the first switch tube Q1, and the second output end d2 of the drive module 13 is connected with the third input end e3 of the conduction time control module 12. The output end a of the period control module 11 is connected with the first input end b1 of the drive module and the fourth input end e4 of the conduction time control module 12, and the output end c of the conduction time control module 12 is connected with the second input end b2 of the drive module.

[0050] The conduction time control module 12 comprises a current sampling module 121 and an operation module 122. The input end f of the current sampling module 121 is connected with the first input end e1 of the conduction time control module 12, the output end g of the current sampling module 121 is connected with the first input end h1 of the operation module 122, the second input end h2 of the operation module 122 is connected with the second input end e2 of the conduction time control module 12, the third input end h3 of the operation module 122 is connected with the third input end e3 of the conduction time control module 12, the fourth input end h4 of the operation module 122 is connected with the fourth input end e4 of the conduction time control module 12, and the output end j of the operation module 122 is connected with the output end c of the conduction time control module 12.

[0051] The current sampling module 121 is used for converting the first current signal I_Q1 into the first voltage signal V_CS, and the current value I1 of the first current signal I_Q1 is proportional to the voltage value V cs The period control module 11 is used for outputting the first control signal V_ON to the drive module 13, and the first control signal V_ON is a pulse signal with a fixed frequency, and the period of the pulse signal is a first preset threshold. The drive module 13 is used for outputting the fourth control signal V_GATE to the first switch tube Q1, and when the first control signal V_ON is suddenly changed from low level to high level, the fourth control signal V_GATE is suddenly changed from low level to high level, so as to control the first switch tube Q1 to be turned on. Optionally, since the current signal flowing through the first inductor L1 is equivalent to the first current signal I_Q1 flowing through the first switch tube Q1 when the first switch tube Q1 is turned on, the input end f of the current sampling module 121 can also be connected with one end of the first inductor L1 in the Buck PFC circuit 21, so as to sample the first current signal I_Q1.

[0052] The operation module 122 in the conduction time control module 12 is used for, in the case that the first switch tube Q1 is turned on, operating the first voltage signal V_CS to generate the second voltage signal V_INT2, and the voltage value V cs_int2The first product (i.e., equivalent to the average input current value Iavg of Buck PFC circuit 21 and the current on-time t of the first switch Q1) is multiplied by the first product. on The product of the two is proportional. The arithmetic module 122 is also used to output a second control signal V_OFF to the drive module 13 when the voltage value V of the second voltage signal V_INT2 is... cs_int2 When the third preset threshold is reached, the second control signal V_OFF changes from low to high. When the second control signal V_OFF changes from low to high, the fourth control signal V_GATE output by the drive module 13 changes from high to low, thereby controlling the first switch Q1 to turn off.

[0053] Understandable Figure 2 The control circuit 1 shown can sample the first current signal I_Q1 flowing through the first switch Q1, and calculate the first voltage signal V_CS obtained after sampling when the first switch Q1 is turned on, so that the voltage value V of the second voltage signal V_INT2 obtained during the period when the first switch Q1 is turned on is V_CS. cs_int2 Proportional to the first product, and causing the voltage value V of the second voltage signal V_INT2 to be... cs_int2 The maximum value is a constant value (i.e., equal to the third preset threshold), thereby indirectly ensuring that the maximum value of the first product within a single switching cycle of the first switching transistor Q1 (i.e., the average input current value I of the buck PFC circuit 2) is the maximum value. avg The total on-time T of the first switch Q1 on The product of these two factors is kept constant, thereby controlling the average input current value I of the Buck PFC circuit 21. avg Follow the input voltage value V in change.

[0054] For example, such as Figure 2 As shown, the arithmetic module 122 in the conduction time control module 12 includes a voltage amplifier circuit GAIN, a voltage sample and hold circuit S / H, an addition and subtraction operation circuit SUM, an integrator circuit 1221, a comparator CMP, and a voltage loop module 1222.

[0055] The first input end h1 of the operation module 122 is connected with the input end of the voltage amplification circuit GAIN and the first input end k1 of the voltage sampling and holding circuit S / H, the second input end k2 of the circuit S / H is connected with the fourth input end h4 of the operation module 122, the output end of the voltage amplification circuit GAIN is connected with the positive input end of the addition and subtraction operation circuit SUM, the output end of the voltage sampling and holding circuit S / H is connected with the negative input end of the addition and subtraction operation circuit, the output end of the addition and subtraction operation circuit SUM is connected with the first input end m1 of the integration circuit 1221, the second output end m2 of the integration circuit 1221 is connected with the third input end h3 of the operation module 122, the output end of the integration circuit 1221 is connected with the positive input end of the comparator CMP, the negative input end of the comparator CMP is connected with the output end p of the voltage loop module 1222, the input end n of the voltage loop module 1222 is connected with the second input end h2 of the operation module 122, and the output end of the comparator CMP is connected with the output end j of the operation module 122.

[0056] The voltage amplification circuit GAIN is used for amplifying the first voltage signal V_CS output by the current sampling module 121 to output a third voltage signal V_GAIN, and the voltage value V_GAIN of the third voltage signal V_GAIN is proportional to the voltage value V_CS of the first voltage signal V_CS. cs_g The voltage value V_GAIN of the third voltage signal V_GAIN is proportional to the voltage value V_CS of the first voltage signal V_CS. cs The voltage sampling and holding circuit S / H is used for starting to sample the current voltage value of the first voltage signal V_CS when the first control signal V_ON is changed from low level to high level (i.e. at the moment when the first switch tube Q1 is turned on), and holding the sampled current voltage value and outputting a fourth voltage signal V_SH when the voltage sampling and holding circuit S / H is changed from high level to low level. It can be understood that the voltage sampling of the voltage sampling and holding circuit S / H needs a certain time, and the sampling time is equal to the time when the first control signal V_ON is at high level. It is mentioned above that the first control signal V_ON is a pulse signal with a fixed frequency, and in actual application, the time (i.e. pulse width) when the first control signal V_ON is at high level can be set according to the required time of sampling and holding, which does not affect the control effect of the switching period of the first switch tube Q1, and the time is usually short. That is to say, the voltage value V_SH of the fourth voltage signal V_SH can be regarded as equal to the initial voltage value V_CS of the first voltage signal V_CS when the first switch tube Q1 starts to be turned on. cs_h cs0 The addition and subtraction operation circuit SUM is used for outputting a fifth voltage signal V_SUM, and the voltage value V_SUM of the fifth voltage signal V_SUM is equal to the voltage value V_GAIN of the third voltage signal V_GAIN. cs_s cs_g The voltage value V_SUM of the fifth voltage signal V_SUM is equal to the voltage value V_SH of the fourth voltage signal V_SH. cs_h That is, the initial voltage value V_CS of the first voltage signal V_CS when the first switch tube Q1 starts to be turned on. cs0 ​​The difference between ).

[0057] The driving module 13 is also used to output a third control signal V_RST to the integrator circuit 1221 through the second output terminal d2. When the first control signal V_ON changes from low level to high level, the third control signal V_RST changes from high level to low level. When the second control signal V_OFF changes from low level to high level, the third control signal V_RST changes from low level to high level. The integrator circuit 1221 is used to start performing a second-order integration of the fifth voltage signal V_SUM with respect to time when the third control signal V_RST changes from high level to low level, generating a second voltage signal V_INT2. It is also used to control the voltage of the second voltage signal V_INT2 to zero when the third control signal V_RST changes from low level to high level (i.e., the integrator circuit 1221 is reset, and the voltage at the positive input terminal of the comparator CMP is zero at this time), until the third control signal V_RST changes from high level to low level again, at which point the fifth voltage signal V_SUM is again integrated with respect to time to generate the second voltage signal V_INT2. In other words, the integrator circuit 1221 can perform a second-order time integration of the fifth voltage signal V_SUM with respect to time when the first switch Q1 is turned on, generating a second voltage signal V_INT2. The voltage loop module 1222 is used to output a sixth voltage signal V_C based on the voltage difference between the reference voltage signal and the output voltage signal VOUT of the Buck_PFC circuit 21. The voltage value of the sixth voltage signal V_C is V... c It equals the third preset threshold. It can be understood that the output voltage Vout of the Buck PFC circuit 21 when it is operating stably can be considered a constant value, then the voltage value V of the sixth voltage signal V_C is... c It can be considered a constant value.

[0058] The comparator CMP compares the sixth voltage signal V_C and the second voltage signal V_INT2, and outputs the second control signal V_OFF. It can be understood that after the first switch Q1 is turned on, the second voltage signal V_INT2 gradually increases. When the voltage value of the second voltage signal V_INT2 V_OFF... cs_int2 The voltage value V equal to the sixth voltage signal V_C c When the second control signal V_OFF abruptly changes from low to high, the first switch Q1 is turned off, and the integrating circuit 1221 stops its integration operation. The voltage value V of the second voltage signal V_INT2... cs_int2 It becomes zero. Therefore, during a single switching cycle of the first switch Q1, the voltage value V of the second voltage signal V_INT2 becomes zero. cs_int2 The maximum value is a constant, which is equal to the voltage value V of the sixth voltage signal V_C. c .

[0059] Further, during the conduction period of the first switch Q1, the voltage value V cs_int2 is proportional to the first product. For example, the amplification of the voltage amplification circuit GAIN is 3, and the second-order integration coefficient of the integration circuit 1221 is β0, then the voltage value V cs_int2 The formula (1-4) and the formula (1-5) can be satisfied:

[0060]

[0061] V cs_s = V cs_g -V cs0 = 3V cs -V cs0 (1-5)

[0062] Wherein, the formula (1-4) is the integration formula when the integration circuit 1221 works, T s is a single switching period of the first switch Q1, V cs_s is the voltage value of the fifth voltage signal V_SUM, V cs_g is the voltage value of the third voltage signal V_GAIN, V cs0 is the initial voltage value of the first voltage signal V_CS, V cs is the voltage value of the first voltage signal V_CS.

[0063] Based on the working principle of the Buck PFC circuit 21, during a single switching period of the first switch Q1, the voltage value V cs satisfies the formula (1-6):

[0064]

[0065] Wherein, k2 is the rising slope of the first voltage signal V_CS.

[0066] According to the formula (1-4) to the formula (1-6), during the conduction period of the first switch Q1, the voltage value V cs_int2 satisfies the formula (1-7):

[0067]

[0068]

[0069] According to the formula (1-6), during a single switching period of the first switch Q1, the average voltage value V cs_avg satisfies the formula (1-8):

[0070]

[0071] Since the current value I1 of the first current signal I_Q1 (i.e. equivalent to the input current value I in of the Buck PFC circuit 21) is proportional to the voltage value V cs of the first voltage signal V_CS, the average input current value I avg of the Buck PFC circuit 21 is proportional to the average voltage value V cs_avg of the first voltage signal V_CS, and assuming the sampling proportional coefficient is k3, the average input current value I avg is proportional to the average voltage value V cs_avg , the formula (1-9) is satisfied:

[0072] V cs_avg = k3*I avg (1-9)

[0073] Therefore, in combination with the formula (1-7) to the formula (1-9), the first product (i.e. the product of the average input current value Iavg of the Buck PFC circuit 21 and the current on-time t on of the first switch Q1) satisfies the formula (1-10):

[0074]

[0075] As can be seen, when the amplification factor of the voltage amplification circuit GAIN is 3, the second-order integration coefficient of the integration circuit 1221 is β0, and the integration formula of the integration circuit 1221 when working satisfies the formula (1-4), the voltage value V cs_int2 of the second voltage signal V_INT2 is proportional to the first product during the on-time of the first switch Q1.

[0076] Further, according to the formula (1-7), the maximum voltage value V cs_int2(max) of the second voltage signal V_INT2 satisfies the formula (1-11) during the on-time of the first switch Q1:

[0077]

[0078] According to the formula (1-10), the maximum value of the first product (i.e. the product of the average input current value I avg of the Buck PFC circuit 21 and the total on-time T on of the first switch Q1) satisfies the formula (1-12):

[0079]

[0080] Optionally, since the switching period T sIt can be considered a constant value, and the second-order integration coefficient β0 of the integrator circuit 1221 can be...

[0081] Therefore, Figure 2 The control circuit 1 shown can control the maximum value of the first product to be constant within a single switching cycle of the first switching transistor Q1. Based on formula (1-3), when the maximum value of the first product is constant, the average input current value I of the Buck PFC circuit 21 is... avg Follow the input voltage value V in change.

[0082] The following is about Figure 2 The specific circuit structures of the integrator circuit 1221, voltage loop module 1222, and drive module 13 are illustrated by way of example.

[0083] Optional, such as Figure 2 As shown, the integrator circuit 1221 may include a first integrator circuit INT1 and a second integrator circuit INT2. The first input terminal m1 of the integrator circuit 1221 is connected to the first input terminal of the first integrator circuit INT1, the output terminal of the first integrator circuit INT1 is connected to the first input terminal of the second integrator circuit INT2, the first input terminal m2 of the integrator circuit 1221 is connected to the second input terminal of the first integrator circuit INT1 and the second input terminal of the second integrator circuit INT2, and the output terminal of the second integrator circuit INT2 is connected to the output terminal of the integrator circuit 1221.

[0084] Specifically, the first integrating circuit INT1 is used to integrate the fifth voltage signal V_SUM over time in the case that the third control signal V_RST is low, generating the seventh voltage signal V_INT1. The second integrating circuit INT2 is used to integrate the seventh voltage signal V_INT1 over time in the case that the third control signal V_RST is low, generating the second voltage signal V_INT2.

[0085] The voltage value V of the seventh voltage signal V_INT1 cs_int1 It can satisfy formula (1-13):

[0086]

[0087] Then, the voltage value V of the second voltage signal V_INT2 cs_int2 It can satisfy formula (1-14):

[0088]

[0089] Wherein, the formula (1-13) and the formula (1-14) are integral formulas when the first integral circuit INT1 and the second integral circuit INT2 work respectively, β1 is a first integral coefficient of the first integral circuit INT1, and β2 is a first integral coefficient of the second integral circuit INT2.

[0090] It can be seen from the formula (1-14) that when the product of the first integral coefficient β1 of the first integral circuit INT1 and the first integral coefficient β2 of the second integral circuit INT2 is β0, the formula (1-14) is the same as the formula (1-4). It should be noted that the present application does not strictly limit the values of β1 and β2 respectively, for example, β1 and β2 can be equal to

[0091] In addition, in actual application, when the third control signal V_RST changes from high level to low level, the first integral circuit INT1 and the second integral circuit INT2 usually do not immediately integrate the voltage signal, but wait for a period of time before integrating the voltage signal, that is, the first integral circuit INT1 and the second integral circuit INT2 can be provided with a buffer time T banking to filter out current ringing and noise at the moment when the first switch tube Q1 is turned on. The setting of the buffer time T banking can be realized by the internal circuit of the first integral circuit INT1 and the second integral circuit INT2, or by the first control signal V_ON. Taking the first integral circuit INT1 as an example, the first integral circuit INT1 includes a third input end, the third input end of the first integral circuit INT1 is connected to the fourth input end h4 of the operation module 122 (that is, the first integral circuit INT1 can receive the first control signal V_ON), and the first integral circuit INT1 starts to integrate only when the third control signal V_RST is low and the first control signal V_ON changes from high level to low level. That is, the buffer time T banking may be equal to the time when the first control signal V_ON is at high level.

[0092] Optionally, please refer to Figure 3 , Figure 3 is a structural schematic diagram of a voltage loop module provided by an embodiment of the present application. As shown in Figure 3 , the input end n of the voltage loop module 1222 includes a first sub-input end n 11 and a second sub-input end n 12 , and the voltage loop module 1222 includes a voltage detection module VSENCE and a loop compensation module LOOP. The positive output end o1 of the Buck PFC circuit 21 is connected to the first sub-input end n 11The negative output end o2 of the Buck PFC circuit 21 is connected to the second sub-input end n of the voltage loop module 1222 12 The first sub-input end n of the voltage loop module 1222 is connected to the first input end of the voltage detection module VSENCE 11 The second sub-input end n of the voltage loop module 1222 is connected to the second input end of the voltage detection module VSENCE 12 The output end of the voltage detection module VSENCE is connected to the first input end of the loop compensation module LOOP, and the output end of the loop compensation module LOOP is connected to the output end p of the voltage loop module 1222.

[0093] Specifically, the voltage detection module VSENCE is configured to output an eighth voltage signal V_FB, and the voltage value of the eighth voltage signal V_FB is equal to the output voltage value V out The loop compensation module LOOP is configured to output a sixth voltage signal V_C according to the voltage difference between the reference voltage signal V_REF and the eighth voltage signal V_FB. In actual applications, the loop compensation module LOOP can include a PI compensation circuit or a type II compensation circuit, etc.

[0094] Optionally, referring to Figure 4 , Figure 4 is a structural schematic diagram of a driving module provided by the embodiment of the present application. As shown in Figure 4 , the driving module 13 includes a flip-flop SR and a driving circuit DRV, the first input end b1 of the driving module 13 is connected to the set end S of the flip-flop SR, the second input end b2 of the driving module 13 is connected to the reset end R of the flip-flop SR, the first output end Q of the flip-flop SR is connected to the input end of the driving circuit DRV, the output end of the driving circuit DRV is connected to the first output end d1 of the driving module 13, and the second output end of the flip-flop SR is connected to the second output end d2 of the driving module 13.

[0095] Specifically, the driving circuit DRV is configured to amplify the fifth control signal V_SR output by the first output end of the flip-flop SR to generate the fourth control signal V_GATE. The fourth control signal V_GATE has the same change trend as the fifth control signal V_SR.

[0096] Understandably, when the first control signal V_ON received by the reset terminal R of the flip-flop SR changes from low to high, the second control signal V_OFF received by the set terminal S of the flip-flop SR is low. Then, the fourth control signal V_GATE changes from low to high and remains high until the second control signal V_OFF changes from low to high again, and the first switch Q1 is turned on. Simultaneously, the third control signal V_RST output by the second output terminal of the flip-flop SR changes from high to low and remains low until the second control signal V_OFF changes from low to high. Therefore, the integrator circuit 1221 can operate when the first switch Q1 is turned on.

[0097] After the first switch Q1 is turned on, the voltage value V of the second voltage signal V_INT2 generated by the integrating circuit 1221 is... cs_int2 It gradually increases and reaches the voltage value V of the sixth voltage signal V_C. c When the second control signal V_OFF received by the reset terminal R of the flip-flop SR changes from low to high, the fourth control signal V_GATE changes from high to low and remains low until the first control signal V_ON changes from low to high. The first switch Q1 then switches to the off state. Simultaneously, the third control signal V_RST output from the second output terminal of the flip-flop SR changes from low to high and remains high until the first control signal V_ON changes from low to high. The integrator circuit 1221 can then be in the reset state when the first switch Q1 is turned off.

[0098] Therefore, Figure 2 The control circuit 1 shown controls the average input current value I of the Buck PFC circuit 21. avg Follow the input voltage value V in During changes, the interaction of multiple signals is involved. To better understand the working principle of control circuit 1, the following explanation is based on signal waveform diagrams. Please refer to... Figure 5 , Figure 5 This is a signal waveform diagram provided in an embodiment of this application.

[0099] The waveforms 501-510 are waveforms of the first control signal V_ON, the first current signal I_Q1 (equivalent to the input current signal I_IN of the Buck PFC circuit 21), the first voltage signal V_CS, the third voltage signal V_GAIN, the fifth voltage signal V_SUM, the third control signal V_RST, the seventh voltage signal V_INT1, the second voltage signal V_INT2, the second control signal V_OFF and the fourth control signal V_GATE, respectively. Based on the waveform 501 of the first current signal I_Q1, it can be understood that, in the single switching period T s The input current of the Buck PFC circuit 21 is discontinuous, and the peak input current and the average input current thereof do not have a linear relationship.

[0100] In combination Figures 2 to 5 , it can be understood that, when the first control signal V_ON output by the period control module 11 in the control circuit 1 is suddenly changed from low level to high level, the fourth control signal V_GATE output by the driving circuit DRV in the driving module 13 is suddenly changed from low level to high level, and is maintained in the high level state. The first switch Q1 in the Buck PFC circuit 21 starts to conduct (i.e. current flows through the first switch Q1), and the voltage sampling holding circuit S / H starts to collect the initial voltage value V cs0 of the first voltage signal V_CS. At the same time, the third control signal V_RST output by the flip-flop SR in the driving module 13 is suddenly changed from high level to low level, and is maintained in the low level state. The first integral circuit INT1 and the second integral circuit INT1 in the integral circuit 1221 start to perform one-stage integral operation, respectively. Specifically, in the conduction time T cs0 of the first switch Q1, the voltage value of the first voltage signal V_CS output by the current sampling module 121 follows the rising trend of the current value of the first current signal I_Q1. The voltage amplification circuit GAIN in the conduction time control module 12 amplifies the first voltage signal V_CS to output the third voltage signal V_GAIN. The add-subtract operation circuit SUM performs operation on the voltage value V on of the third voltage signal V_GAIN and the initial voltage value V cs_g of the first voltage signal V_CS to output the fifth voltage signal V_SUM. The first integral circuit INT1 performs one-stage integral operation on the fifth voltage signal V_SUM to output the seventh voltage signal V_INT1. The second integral circuit INT2 performs one-stage integral operation on the seventh voltage signal V_INT1 to output the second voltage signal V_INT2, and the voltage value V cs0 of the second voltage signal V_INT2 iscs_int2 is in a gradually rising trend.

[0101] When the voltage value V cs_int2 of the second voltage signal V_INT2 reaches the voltage value V c of the sixth voltage signal V_C output by the voltage loop module 1222, the second control signal V_OFF output by the comparator CMP jumps from low level to high level, the flip-flop SR is reset and the fourth control signal V_GATE output by the driving circuit DRV jumps from high level to low level and is maintained in low level state. The first switch Q1 in the Buck PFC circuit 21 starts to be turned off (i.e. no current flows through the first switch Q1), and the voltage sampling holding circuit S / H still outputs the fourth voltage signal until the initial voltage value of the first voltage signal V_CS is re-collected when the first control signal V_ON output by the period control module 11 jumps from low level to high level. At the same time, the third control signal V_RST output by the flip-flop SR in the driving module 13 jumps from low level to high level and is maintained in high level state, and the first integral circuit INT1 and the second integral circuit INT1 in the integral circuit 1221 stop the first-order integral operation (i.e. are reset). Specifically, during the off time T off of the first switch Q1, the seventh voltage signal V_INT1 and the second voltage signal V_INT2 are both zero. Until the first control signal V_ON output by the period control module 11 jumps from low level to high level, the first switch Q1 is turned on again.

[0102] As can be known from the working principle of the control circuit 1 detailed above, Figure 2 the control circuit 1 shown can control the average input current value I avg of the Buck PFC circuit 21 to follow the input voltage value V in in a single period of the first switch Q1. Therefore, from the perspective of the AC power supply S, in a single power frequency period of the AC power supply S, the average input current value I avg of the Buck PFC circuit 21 follows the input voltage value V in . For easy understanding, please refer to Figure 6 , Figure 6 which is another signal waveform diagram provided by the embodiment of the present application.

[0103] The waveform diagram 601-waveform diagram 604 are respectively the sinusoidal AC voltage signal V_AC output by the AC power supply S, the AC current signal I_AC output by the AC power supply S, the input voltage signal V_IN of the Buck PFC circuit 21 and the input current signal I_IN of the Buck PFC circuit 21.

[0104] As Figure 6As shown, since the Buck PFC circuit 21 is a step-down circuit, during a single power frequency cycle T of the AC power supply S... ac Inside, only the voltage value V_IN of the input voltage signal of the Buck PFC circuit 21 is displayed. in The output voltage V of Buck PFC circuit 21 is greater than out Only when the current values ​​of the AC current signal I_AC and the input current signal I_IN are not zero.

[0105] Furthermore, due to Figure 2 The control circuit 1 shown in the Buck PFC circuit 21 has a single switching cycle T of the first switching transistor Q1. s The current signal flowing through the first switching transistor Q1 is sampled in real time, thereby enabling the measurement of the current signal within a single switching cycle T. s Track and control the target. Therefore... Figure 2 The control circuit 1 shown has a fast response speed and can quickly converge to circuit disturbances, thereby reducing current oscillations generated in the Buck PFC circuit 21 during the control process. Figure 6 As can be seen from markings 611 and 612, the Buck PFC circuit 21 basically does not generate current oscillations.

[0106] It should be noted that, Figure 2 The Buck PFC circuit 21 shown is a low-side driven Buck PFC circuit (i.e., the source voltage of the main switch in the Buck PFC circuit is zero). This application does not strictly limit the circuit structure of the Buck PFC circuit 21. Figure 2 The structure of the Buck PFC circuit 21 shown is for illustrative purposes only.

[0107] Optional, Figure 2 The Buck PFC circuit 21 shown can also be a high-side drive Buck PFC circuit (i.e., the source voltage of the main switch in the Buck PFC circuit is not zero). Please refer to [link to relevant documentation]. Figure 7a , Figure 7a This is a schematic diagram of a Buck PFC circuit provided in an embodiment of this application. Compared to Figure 2 The Buck PFC circuit 21 shown is... Figure 7aThe electrical elements in the Buck PFC circuit 21 shown are the same, and the connection modes between the electrical elements are different. Specifically, the positive input end i1 of the Buck PFC circuit 21 is connected to one end of the first capacitor C1 and the drain of the first switch tube Q1, the source of the first switch tube Q1 is connected to the negative electrode of the first diode D1 and one end of the first inductor L1, the other end of the first inductor L1 is connected to one end of the second capacitor C2 and the positive output end o1 of the Buck PFC circuit 21, and the negative input end i2 of the Buck PFC circuit 21, the other end of the first capacitor C1, the positive electrode of the first diode D1, the other end of the second capacitor C2 and the negative output end o2 of the Buck PFC circuit 21 are all connected to the reference ground.

[0108] It can be understood that, for Figure 2 the Buck PFC circuit 21 shown and Figure 7a the Buck PFC circuit 21 shown, the proportional coefficient k1 in the formula (1-2) is all 1. Therefore, referring to the working principle of the control circuit 1 detailed above, Figure 2 it can be understood that, Figure 2 when the Buck PFC circuit 21 shown is replaced by Figure 7a the Buck PFC circuit 21 shown, the control circuit 1 can still control Figure 7a the average input current value of the Buck PFC circuit 21 shown to follow the change of the input voltage value, so as to realize power factor correction.

[0109] Optionally, Figure 2 the Buck PFC circuit 21 shown can also be a forward topology PFC circuit. For example, referring to Figure 7b , Figure 7b is a structural schematic diagram of a forward topology PFC circuit provided by an embodiment of the present application. As Figure 7b shown, the forward topology PFC circuit 71 includes a third capacitor C3, a fourth capacitor C4, a second switch tube Q2, a second diode D2, a third diode D3, a second inductor L2, a first main side winding N p1 , a first auxiliary side winding N s1 , and a first core F1.

[0110] Specifically, the positive input end i3 of the forward topology PFC circuit 71 is connected to one end of the third capacitor C3 and one end of the first main side winding N p1 , the other end of the first main side winding N p1 is connected to the drain of the second switch tube Q2, and the negative input end i4 of the forward topology PFC circuit 71, the other end of the third capacitor C3 and the source of the second switch tube Q2 are all connected to the reference ground. The first main side winding N p1 and the first auxiliary side winding N s1Winded on the first iron core F1, the first secondary winding N s1 One end of the circuit is connected to the positive terminal of the second diode D2. The negative terminal of the second diode D2 is connected to the negative terminal of the third diode D3 and one end of the second inductor L2. The other end of the second inductor L2 is connected to one end of the fourth capacitor C4 and the positive output terminal o3 of the forward topology PFC circuit 71. The negative output terminal o4 of the forward topology PFC circuit 71 is connected to the first secondary winding N. s1 The other end, the positive terminal of the third diode D3, and the other end of the fourth capacitor C4.

[0111] Understandable Figure 7b The second switch Q2 in the forward topology PFC circuit 71 shown can be considered equivalent to Figure 2 The first switch Q1 in the Buck PFC circuit 21 shown. For Figure 2 The Buck PFC circuit 21 shown has a proportional coefficient k1 of 1 in formula (1-2). For Figure 7b The forward topology PFC circuit 71 shown has a proportional coefficient k1 in formula (1-2) that is the first secondary winding N. s1 The number of turns and the first main winding N p1 The ratio between the number of turns, i.e., the proportionality constant k1, remains a constant. Therefore, see the detailed explanation above. Figure 2 The working principle of the control circuit 1 shown can be understood as follows: Figure 2 The Buck PFC circuit 21 shown is Figure 7b When the forward topology PFC circuit 71 shown is replaced, the control circuit 1 can still control the average input current value of the forward topology PFC circuit 71 to follow the change of the input voltage value, thereby realizing power factor correction.

[0112] Optional, Figure 2 The Buck PFC circuit 21 shown can also be a push-pull topology PFC circuit. For an example, please refer to [link to example]. Figure 7c , Figure 7c This is a schematic diagram of a push-pull topology PFC circuit provided in an embodiment of this application. Figure 7c As shown, the push-pull topology PFC circuit 72 includes a fourth capacitor C4, a fifth capacitor C5, a third switch Q3, a fourth switch Q4, a fourth diode D4, a fifth diode D5, a third inductor L3, and a second main winding N. p2 The third main winding N p3 The second secondary winding N s2 and the third secondary winding N s3 .

[0113] Specifically, the positive input terminal i5 of the push-pull topology PFC circuit 72 is connected to one end of the fourth capacitor C4 and the third main winding N. p3one end of the second main edge winding N p2 and the third main edge winding N p3 are connected in series to form a main edge series winding, one end of the second main edge winding N p2 is connected to the drain of the third switch tube Q3, the other end of the third main edge winding N p3 is connected to the drain of the fourth switch tube Q4, the negative input end i6 of the push-pull topology PFC circuit 72, the other end of the fourth capacitor C4, the source of the third switch tube Q3, and the source of the fourth switch tube Q4 are all connected to the reference ground. The second auxiliary edge winding N s2 and the third auxiliary edge winding N s3 are connected in series to form an auxiliary edge series winding, the main edge series winding and the auxiliary edge series winding are wound on the second core F2, one end of the second auxiliary edge winding N s2 is connected to the anode of the fourth diode D4, the cathode of the fourth diode D4 is connected to one end of the third inductor L3 and the cathode of the fifth diode D5, the anode of the fifth diode D5 is connected to the other end of the third auxiliary edge winding N s3 , the other end of the third inductor L3 is connected to one end of the fifth capacitor C5 and the positive output end o5 of the push-pull topology PFC circuit 72, and the other end of the fifth capacitor C5 is connected to one end of the third auxiliary edge winding N s3 and the negative output end o6 of the push-pull topology PFC circuit 72.

[0114] It can be understood that, Figure 7c the third switch tube Q3 and the fourth switch tube Q4 in the push-pull topology PFC circuit 72 shown in FIG. 8 are alternately switched to output the voltage.

[0115] For the Buck PFC circuit 21 shown in FIG. 6, the proportional coefficient k1 in formula (1-2) is 1. For the push-pull topology PFC circuit 72 shown in FIG. 8, the proportional coefficient k1 in formula (1-2) is twice the ratio between the number of turns of the main edge series winding and the number of turns of the auxiliary edge series winding, that is, the proportional coefficient k1 is still a constant value. Therefore, referring to the working principle of the control circuit 1 detailed above, when the Buck PFC circuit 21 shown in FIG. 6 is replaced by the push-pull topology PFC circuit 72 shown in FIG. 8, the control circuit 1 can adopt the same control mode for the third switch tube Q3 as for the first switch tube Q1 in the Buck PFC circuit 21 shown in FIG. 6, so that the average input current value of the push-pull topology PFC circuit 72 follows the change of the input voltage value, and then the power factor correction is realized. Figure 2 Figure 7b Figure 2 Figure 2 Figure 7c Figure 2

[0116] ​​​​​​In summary, the control circuit in the embodiments of the present application can sample the current signal flowing through the main switch tube in real time within a single switching cycle of the main switch tube in the step-down PFC circuit, so as to control the average input current value of the step-down PFC circuit to follow the change of the input voltage value. The step-down PFC circuit can not only realize power factor correction without sampling the input voltage, but also save the control cost of the step-down PFC circuit. In addition, the control circuit can realize fast convergence in response to circuit disturbance, reduce current oscillation generated in the control process of the step-down PFC circuit, and enhance the stability of the step-down PFC circuit. Furthermore, the control circuit in the embodiments of the present application can be applied to various step-down PFC circuits, and has wide application range and high flexibility.

[0117] In the embodiments of the present application, "a plurality of" refers to two or more than two. In addition, unless otherwise stated, "first" mentioned in the embodiments of the present application is only used to identify the name, and is not used to limit the order, timing, priority or importance of multiple objects, such as the first control signal, the first switch tube, etc. The same rule applies to "second", "third" and "fourth".

[0118] The above is only a specific embodiment of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art can easily think of various equivalent modifications or replacements within the technical range disclosed in the present application, and these modifications or replacements should be covered within the protection scope of the present application. Therefore, the protection scope of the present application should be subject to the protection scope of the claims.

Claims

1. A control circuit, characterized by The control circuit comprises a period control module (11), a conduction time control module (12) and a driving module (13), wherein: The period control module (11) is configured to output a first control signal (V_ON), and a period of the first control signal (V_ON) is a first preset threshold; The driving module (13) is configured to control a first switch tube (Q1) in a step-down power factor correction (PFC) circuit (2) to be turned on when the first control signal (V_ON) changes from a low level to a high level, the step-down PFC circuit (2) operates in a continuous current mode (CCM), and an input current value of the step-down PFC circuit (2) is equal to a current value of a first current signal (I_Q1) flowing through the first switch tube (Q1); The conduction time control module (12) is configured to output a second control signal (V_OFF), and the second control signal (V_OFF) changes from a low level to a high level when a first product of a first average current value and a current conduction time of the first switch tube (Q1) reaches a second preset threshold, and the first average current value is an average current value of the first current signal (I_Q1) in one switching period of the first switch tube (Q1); The driving module (13) is configured to control the first switch tube (Q1) to be turned off when the second control signal (V_OFF) changes from the low level to the high level.

2. The control circuit of claim 1, wherein, The conduction time control module (12) comprises a current sampling module (121) and an operation module (122), wherein: The current sampling module (121) is configured to convert the first current signal (I_Q1) into a first voltage signal (V_CS), and a current value of the first current signal (I_Q1) is proportional to a voltage value of the first voltage signal (V_CS); The operation module (122) is configured to generate a second voltage signal (V_INT2) by operating the first voltage signal (V_CS) when the first switch tube (Q1) is turned on, and a voltage value of the second voltage signal (V_INT2) is proportional to the first product; The operation module (122) is further configured to output the second control signal (V_OFF), and the second control signal (V_OFF) changes from the low level to the high level when the voltage value of the second voltage signal (V_INT2) reaches a third preset threshold.

3. The control circuit of claim 2, wherein, The operation module (122) comprises a voltage amplification circuit (GAIN), a voltage sampling and holding circuit (S / H), a plus-minus operation circuit (SUM) and an integration circuit (1221), a positive input end of the plus-minus operation circuit (SUM) is connected to an output end of the voltage amplification circuit (GAIN), a negative input end of the plus-minus operation circuit (SUM) is connected to an output end of the voltage sampling and holding circuit (S / H), and an output end of the plus-minus operation circuit (SUM) is connected to an input end of the integration circuit (1221), wherein: The voltage amplification circuit (GAIN) is configured to amplify the first voltage signal (V_CS) to output a third voltage signal (V_GAIN), a voltage value of the third voltage signal (V_GAIN) being proportional to a voltage value of the first voltage signal (V_CS); The voltage sampling and holding circuit (S / H) is configured to output a fourth voltage signal (V_SH), a voltage value of the fourth voltage signal (V_SH) being equal to an initial voltage value of the first voltage signal (V_CS) when the first switch tube (Q1) starts to conduct; The addition and subtraction operation circuit (SUM) is configured to output a fifth voltage signal (V_SUM), a voltage value of the fifth voltage signal (V_SUM) being equal to a difference between the voltage value of the third voltage signal (V_GAIN) and the voltage value of the fourth voltage signal (V_SH); The integral circuit (1221) is configured to, in a case where the first switch tube (Q1) conducts, perform two-stage integration on the fifth voltage signal (V_SUM) with respect to time to generate the second voltage signal (V_INT2).

4. The control circuit of claim 3, wherein, The operation module (122) further comprises a comparator (CMP) and a voltage loop module (1222), a positive input end of the comparator (CMP) being connected to an output end of the integral circuit (1221), and a negative input end of the comparator (CMP) being connected to an output end of the voltage loop module (1222), wherein: The voltage loop module (1222) is configured to output a sixth voltage signal (V_C) according to a voltage difference between a reference voltage signal and an output voltage signal (V_OUT) of the buck PFC circuit (2), a voltage value of the sixth voltage signal (V_C) being equal to the third preset threshold value; The comparator (CMP) is configured to compare the sixth voltage signal (V_C) and the second voltage signal (V_INT2) to output the second control signal (V_OFF).

5. The control circuit of claim 4, wherein, A first input end of the integral circuit (1221) is connected to an output end of the addition and subtraction operation circuit (SUM), a first output end of the drive module (13) is connected to a gate of the first switch tube (Q1), a second output end of the drive module (13) is connected to a second input end of the integral circuit (1221), a first input end of the drive module (13) is connected to an output end of the period control module (11), and a second input end of the drive module (13) is connected to an output end of the comparator (CMP), wherein: The drive module (13) is further configured to, in a case where the first control signal (V_ON) changes from a low level to a high level, control the integral circuit (1221) to output the second voltage signal (V_INT2); The drive module (13) is further configured to, in a case where the second control signal (V_OFF) changes from a low level to a high level, control the voltage value of the second voltage signal (V_INT2) to be zero.

6. The control circuit of claim 5, wherein, The integral circuit (1221) comprises a first integral circuit (INT1) and a second integral circuit (INT2), a first input end of the integral circuit (1221) is connected to a first input end of the first integral circuit (INT1), an output end of the first integral circuit (INT1) is connected to a first input end of the second integral circuit (INT2), an output end of the second integral circuit (INT2) is connected to an output end of the integral circuit (1221), and a second input end of the integral circuit (1221) is connected to a second input end of the first integral circuit (INT1) and a second input end of the second integral circuit (INT2), wherein: The driving module (13) is configured to output a third control signal (V_RST) through a second output end of the driving module (13), the third control signal (V_RST) changes from high level to low level when the first control signal (V_ON) changes from low level to high level, and the third control signal (V_RST) changes from low level to high level when the second control signal (V_OFF) changes from low level to high level; The first integral circuit (INT1) is configured to generate a seventh voltage signal by integrating the fifth voltage signal (V_SUM) with respect to time when the third control signal (V_RST) is low level. The second integral circuit (INT2) is configured to generate the second voltage signal (V_INT2) by integrating the seventh voltage signal with respect to time when the third control signal (V_RST) is low level.

7. The control circuit of claim 6, wherein, The driving module (13) comprises a flip-flop (SR) and a driving circuit (DRV), a first input end of the driving module (13) is connected to a set end of the flip-flop (SR), a second input end of the driving module (13) is connected to a reset end of the flip-flop (SR), a first output end of the flip-flop (SR) is connected to an input end of the driving circuit (DRV), an output end of the driving circuit (DRV) is connected to a first output end of the driving module (13), and a second output end of the flip-flop (SR) is connected to a second output end of the driving module (13).

8. The control circuit according to any one of claims 3-7, characterized in that, a voltage value V of the second voltage signal (V INT2) cs_int2 satisfies the following equation: V cs_int2 = β0*∫0 t (∫0 t V cs_s dt)dt V cs_s = V cs_g - V cs0 = 3V cs - V cs0 wherein the β0 is a preset second integral coefficient, the V cs_s is a voltage value of the fifth voltage signal (V_SUM), the V cs_g is a voltage value of the third voltage signal (V_GAIN), the V cs0 is a voltage value of the fourth voltage signal (V_SH), the V cs is a voltage value of the first voltage signal (V_CS).

9. The control circuit of claim 8, wherein, The step-down PFC circuit (2) comprises a step-down Buck PFC circuit (21), a forward topology PFC circuit (71), or a push-pull topology PFC circuit (72).

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