A high-resolution and high-precision multi-slope integral analog-to-digital converter and analog-to-digital conversion method

Abstract

The present invention belongs to the field of measurement technology, specifically a high-resolution, high-precision multi-slope integral analog-to-digital converter and an analog-to-digital conversion method, including a four-way parallel high-precision constant current source circuit, an integrator, an integral output ratio amplification module, a comparator, an integrator zero reset circuit and an FPGA; the charge injection combination of the traditional voltage source / resistor is replaced by a four-way high-precision constant current source circuit to achieve a higher precision quantization of the charge and discharge amount of the integrator, while making the integrator appear two zero crossing points, reducing the influence of the comparator judgment hysteresis phenomenon on the accuracy. By operating the integrator charge and discharge control, data calculation and filtering, and data transmission and display and other events in parallel in the FPGA, the problem that the switch control integrator in the traditional dual-slope integral analog-to-digital converter needs to obtain the calculation processing result and filter the calculation result before starting the next analog-to-digital conversion after charging and discharging is solved. In summary, the present invention has higher resolution, accuracy and conversion speed.

Description

Technical Field

[0001] The invention belongs to the field of measurement technology, and in particular relates to a high-resolution and high-precision multi-slope integral analog-to-digital converter and an analog-to-digital conversion method. Background Art

[0002] The traditional dual slope integrating analog-to-digital converter (block diagram see Figure 1 ) The working process is as follows: first open the switch of the unknown measured voltage, and use the high-precision resistor to perform forward integration on the integrator (rising stage), fix the integration time, then disconnect the switch of the unknown measured voltage, open the switch of the known reference voltage, and use the high-precision resistor to reversely integrate the integrator (descending stage), and continue until the integrator output voltage is 0, the comparator outputs the over-0 judgment result, and the reverse integration time period is obtained through the timer. Finally, the measured voltage is calculated using the known reference voltage and integration time.

[0003] The dual-slope integral ADC has high precision, but with the development of technology, the performance of the dual-slope integral ADC can no longer meet the demand, and its limitations begin to be exposed, as follows:

[0004] 1: The output voltage of the integrator is limited by the rail voltage of the op amp device. To prevent the integrator from entering the saturation working state, the integration time of the measured voltage is limited, which restricts the resolution of the analog-to-digital conversion.

[0005] 2: Use switching devices to control the on and off of the measured voltage and voltage source, and then use resistors to integrate and charge the integrator. Due to the limitations of resistor accuracy, parasitic capacitance of switching devices, and temperature drift of components, the actual integrated current deviates greatly from the ideal current Vref / R. This control method cannot accurately control the amount of charge charged and discharged by the integrator, which restricts the accuracy of analog-to-digital conversion.

[0006] 3: There is a hysteresis in the comparator's judgment of the integrator's zero point, and the greater the slope of the integrator's falling phase, the greater the judgment error of the comparator due to the hysteresis phenomenon, which will affect the accuracy of the analog-to-digital conversion.

[0007] 4: Traditional single-chip microcomputers and other MCU computing units have a slow processing speed and are unable to perform fast calculations and filtering of long-bit-width data, which not only affects the speed of analog-to-digital conversion, but also the existence of truncation errors affects the accuracy of the final result.

[0008] Therefore, considering the limited accuracy and resolution of traditional dual-slope integral analog-to-digital conversion circuits, how to improve the resolution, accuracy and conversion speed of integral analog-to-digital conversion has become a technical problem that needs to be solved urgently. Summary of the invention

[0009] In view of this, the present invention provides a high-precision, high-resolution and high-speed integrating analog-to-digital converter and conversion method, which breaks through the limitations of traditional dual-slope integrating analog-to-digital converters and has higher resolution, accuracy and conversion speed.

[0010] The technical solution adopted by the present invention is:

[0011] A high-precision and high-resolution multi-slope integral analog-to-digital converter, comprising: a four-way parallel high-precision constant current source circuit, an integrator, an integral output proportional amplification module, a comparator, an integrator zero reset circuit, and an FPGA;

[0012] The four-way parallel high-precision constant current source circuit comprises: four current sources and four switches, the four current sources are respectively a first current source, a second current source, a third current source and a fourth current source, the four switches are respectively a first switch, a second switch, a third switch and a fourth switch, and the four current sources are connected to the four switches in a one-to-one correspondence;

[0013] The output end of the integrator is connected to the same-direction input end of the comparator via an integral output proportional amplification module;

[0014] The inverting input terminal of the comparator is connected to the reference voltage, and the output terminal is connected to the input terminal of the FPGA;

[0015] The input end of the integrator zero reset circuit is connected to the first output end of the FPGA, and the output end is connected to the integrator, and is used to reset the integrator according to the output result of the first output end of the FPGA;

[0016] The FPGA has a first output end connected to the first switch, the second switch, the third switch, the fourth switch and the integrator zero reset circuit respectively, and a second output end connected to the digital tube peripheral.

[0017] Furthermore, the integrator zero reset circuit includes an integrator discharge module and a fifth switch matched therewith, the input end of the integrator discharge module is connected to the first output end of the FPGA through the fifth switch, and the output end is connected to the integrator.

[0018] Furthermore, the first current source and the third current source are both positive voltage to negative reference constant current source modules; the second current source and the fourth current source are both positive voltage to positive reference constant current source modules.

[0019] Furthermore, the circuit structure of the third current source has the same circuit structure as the first current source; the circuit structure of the third current source includes two operational amplifiers: operational amplifier U12 and operational amplifier U13; nine resistors: resistor R12, resistor R13, resistor R14, resistor R15, resistor R16, resistor R63, resistor R72, resistor R64, resistor R73; five capacitors: capacitor C23, capacitor C32, capacitor C33, capacitor C24, capacitor C4; 1 2.5V high-precision voltage regulator;

[0020] The inverting input terminal of the operational amplifier U12 is connected to one end of the resistor R13 and one end of the resistor R12, the non-inverting input terminal is connected to one end of the resistor R15 and one end of the resistor R16, and the output terminal is connected to the other end of the resistor R12 and one end of the resistor R14; the non-inverting input terminal of the operational amplifier U13 is connected to the other end of the resistor R14 and the input of the third switch circuit matched therewith, and the output terminal and the inverting input terminal are connected to the other end of the resistor R16; the other end of the resistor R13 is connected to the first end of the 2.5V high-precision voltage stabilizing chip; the other end of the resistor R15 is grounded; one end of the resistor R63 is connected to the operational amplifier The reverse input terminal of the amplifier U12 and the other end are grounded via capacitor C23; one end of the resistor R72 is connected to the positive input terminal of the operational amplifier U12, and the other end is grounded via capacitor C32; one end of the resistor R64 is connected to the reverse input terminal of the operational amplifier U13, and the other end is grounded via capacitor C24; one end of the resistor R73 is connected to the positive input terminal of the operational amplifier U13, and the other end is grounded via capacitor C33; one end of the capacitor C4 is connected to the power supply VCC and the second end of the 2.5V high-precision voltage regulator chip, and the other end is grounded; the third end of the 2.5V high-precision voltage regulator chip is grounded.

[0021] Furthermore, the circuit structure of the fourth current source has the same circuit structure as the second current source; the fourth current source includes another operational amplifier: operational amplifier U9, operational amplifier U10; nine resistors: resistor R1, resistor R5, resistor R7, resistor R8, resistor R62, resistor R70, resistor R9, resistor R65, resistor R71; five capacitors: capacitor C3, capacitor C31, capacitor C25, capacitor C30, capacitor C22; 1 1.25V high-precision voltage source;

[0022] The inverting input terminal of the operational amplifier U9 is connected to one end of the resistor R1 and one end of the resistor R5, the non-inverting input terminal is connected to one end of the resistor R7 and one end of the resistor R8, and the output terminal is connected to the other end of the resistor R1 and one end of the resistor R9; the non-inverting input terminal of the operational amplifier U10 is connected to the other end of the resistor R9 and the input of the fourth switch circuit of the subsequent stage matched therewith, and the output terminal and the inverting input terminal are connected to the other end of the resistor R7; the other end of the resistor R8 is connected to the first end of the 1.25V high-precision voltage stabilizing chip, and the other end of the resistor R5 is grounded; one end of the resistor R62 is connected to the operational amplifier The reverse input terminal of U9, and the other end is grounded via capacitor C22; one end of resistor R70 is connected to the positive input terminal of operational amplifier U9, and the other end is grounded via capacitor C30; one end of resistor R65 is connected to the reverse input terminal of operational amplifier U10, and the other end is grounded via capacitor C25; one end of resistor R71 is connected to the positive input terminal of operational amplifier U10, and the other end is grounded via capacitor C31; one end of capacitor C3 is connected to the power supply VCC and the second end of the 1.25V high-precision voltage regulator chip, and the other end is grounded; the third end of the 1.25V high-precision voltage regulator chip is grounded.

[0023] Furthermore, the FPGA includes: an integrator zero-crossing comparison result input pin, a mean filter module, an analog-to-digital conversion result display drive module, a multi-slope integral control state machine, a counter data calculation processing module and a switch control output pin; the integrator zero-crossing comparison result input pin is the input end of the FPGA, the switch control output pin is the first output end of the FPGA, and the analog-to-digital conversion result display drive module is the second output end of the FPGA; the integrator zero-crossing comparison result input pin is connected to the counter data calculation processing module, the mean filter module, and the analog-to-digital conversion result display drive module in sequence through the multi-slope integral control state machine on the one hand, and is connected to the switch control output pin through the multi-slope integral control state machine on the other hand.

[0024] A method for analog-to-digital conversion of a high-precision and high-resolution multi-slope integral analog-to-digital device, comprising:

[0025] S1, initialize the integrator, that is, clear the integrator and make all switches in the off state;

[0026] S2, by controlling the first switch to be turned on, the tested voltage is positively integrated for a fixed time, and after the fixed time, the first switch is turned off to stop the positive integration of the tested voltage;

[0027] S3, by controlling the second switch and the first switch to be turned on and off alternately, until the negative direction of the integrator returns to zero, and then setting both the first switch and the second switch to the off state;

[0028] S4, controlling the third switch to turn on, performing a forward integration of the third current source for a fixed time, and after the fixed time, turning off the third switch to stop the forward integration of the third current source;

[0029] S5, by controlling the fourth switch to turn on, the fourth current source is negatively integrated until the negative integral is zero, and the integration is stopped, and at the same time the comparator is flipped and a 0 signal is output;

[0030] S6. Use the counter of the FPGA to count the conduction time of the first switch, the second switch, the third switch and the fourth switch during the integration process, respectively, to obtain the total integration time of each switch being turned on; use the calculation processing module of the FPGA to perform addition, subtraction, multiplication and division operations to obtain the final analog-to-digital conversion result.

[0031] Furthermore, (6) is converted using the following analog-to-digital conversion relationship:

[0032] ;

[0033] ;

[0034] ;

[0035] ;

[0036] ;

[0037] ;

[0038] In the formula, A represents the measured voltage, i.e., the total integrated charge of the first current source; B represents the total integrated charge of the third current source and the total integrated charge brought by the switch device when the integrator is positively integrated; C represents the total integrated charge of the second current source and the total integrated charge of the fourth current source; D represents the total integrated charge brought by the switch device when the integrator is negatively integrated; R represents resistance; V represents voltage; Indicates the voltage input value being tested, b represents the base current, t 1 represents the total integration time of the first switch being on, t 2 represents the total integration time of the second switch being turned on, t 3 represents the total integration time of the third switch being turned on, t 4 represents the total integration time during which the fourth switch is turned on.

[0039] The present invention provides a high-resolution, high-precision multi-slope integral analog-to-digital converter and an analog-to-digital conversion method. By replacing the charge injection combination of the traditional voltage source / resistor with a four-way high-precision constant current source circuit, a higher-precision quantization of the charge and discharge amount of the integrator is achieved, and two zero crossing points appear in the integrator, which reduces the influence of the comparator judgment hysteresis phenomenon on the accuracy. By controlling the charging and discharging of the integrator, data calculation and filtering, data transmission and display, and other events in parallel in the FPGA, that is, a three-stage pipeline design is made, the analog-to-digital conversion is split into three operations: switch control of the integrator charging and discharging operation, data calculation and filtering operation, and analog-to-digital conversion result transmission and display operation, which greatly improves the speed of analog-to-digital conversion and solves the problem that in the traditional dual-slope integral analog-to-digital converter, after using the switch to control the charging and discharging of the integrator, it is necessary to stop first for calculation and filtering, and then send the result after obtaining the result before starting the next analog-to-digital conversion. In addition, all switches are designed as high-speed analog switch circuits to speed up the current source switching speed, and on the original basis, the conversion speed is better improved. Compared with the prior art, the present invention breaks through the limitations of the traditional dual-slope integral analog-to-digital converter and has higher resolution, accuracy and conversion speed. BRIEF DESCRIPTION OF THE DRAWINGS

[0040] Figure 1 It is the principle block diagram of the traditional dual slope integrating analog-to-digital converter;

[0041] Figure 2 The schematic diagram of the high-resolution and high-precision multi-slope integral analog-to-digital converter of the present invention is shown in FIG.

[0042] Figure 3 A schematic diagram of the internal structure of an FPGA in a high-resolution, high-precision, multi-slope integrating analog-to-digital converter of an embodiment;

[0043] Figure 4 4 is a circuit structure diagram of a third current source in a high-resolution and high-precision multi-slope integrating analog-to-digital converter of an embodiment;

[0044] Figure 5 4 is a circuit structure diagram of a fourth current source in a high-resolution and high-precision multi-slope integrating analog-to-digital converter of an embodiment;

[0045] Figure 6 4 is a circuit structure diagram of a third switch in a high-resolution and high-precision multi-slope integrating analog-to-digital converter of an embodiment;

[0046] Figure 7 4 is a circuit structure diagram of a fourth switch in a high-resolution and high-precision multi-slope integrating analog-to-digital converter of an embodiment;

[0047] Figure 8 1 is a circuit structure diagram of an integration unit in a high-resolution and high-precision multi-slope integrating analog-to-digital converter of an embodiment;

[0048] Fig. 9 A circuit structure diagram of a comparator in a high-resolution and high-precision multi-slope integrating analog-to-digital converter of an embodiment;

[0049] Fig.10 An integrator output waveform for an integration period of the embodiment integrator;

[0050] Fig.11 It is a state transfer flow chart of a multi-slope integral control state machine in an FPGA in an embodiment;

[0051] Fig.12 It is a simplified calculation flow chart of the counter data calculation module and the filter module in the FPGA of the embodiment. DETAILED DESCRIPTION

[0052] The technical solution of the present invention is described in detail below in conjunction with the accompanying drawings and embodiments.

[0053] like Figure 2 As shown, a high-resolution, high-precision multi-slope integral analog-to-digital converter provided in this embodiment includes a four-way parallel high-precision constant current source circuit, an integrator, a comparator, an integrator zero reset circuit, an FPGA, and a digital tube digital tube peripheral. The connection relationship between the modules and the functions of each module are set according to the above content, which will not be repeated here. The present invention is to replace the charge injection combination of the traditional voltage source / resistor by designing a four-way high-precision constant current source circuit to achieve a higher precision quantization of the charge and discharge amount of the integrator, while enabling the integrator to have two zero crossing points, thereby reducing the influence of the comparator judgment hysteresis phenomenon on the accuracy. In the present invention, the four-way parallel high-precision constant current source circuit includes four current sources: a first current source, a second current source, a third current source, and a fourth current source; four switches: a first switch, a second switch, a third switch, and a fourth switch; four current sources are connected to the four switches one by one.

[0054] In the four-way parallel high-precision constant current source circuit in this embodiment, the first current source and the third current source have the same structure, and both are positive voltage to negative reference constant current source modules. The second power source and the fourth current source have the same structure, and both are positive voltage to positive reference constant current source modules. The second current source and the fourth current source have the same structure. All four switches use a combination of MOS tubes and BJT tubes to realize high-speed switching of the current source. The circuit structure of the first switch and the third switch is the same, and the circuit structure of the second switch and the fourth switch is the same. For the four-way parallel high-precision constant current source circuit, this embodiment details the specific structure of the third current source, the fourth current source, the third switch and the fourth switch, to illustrate the advantages of the four-way parallel high-precision constant current source circuit.

[0055] like Figure 4As shown, the third current source is a high-precision constant current source circuit, including an operational amplifier U12, an operational amplifier U13, a resistor R12, a resistor R13, a resistor R14, a resistor R15, a resistor R16, a resistor R63, a resistor R72, a resistor R64, a resistor R73, a capacitor C23, a capacitor C32, a capacitor C33, a capacitor C24, and a capacitor C4. The inverting input terminal of the operational amplifier U12 is connected to one end of the resistor R13 and one end of the resistor R12, the in-phase input terminal is connected to one end of the resistor R15 and one end of the resistor R16, and the output terminal is connected to the other end of the resistor R12 and one end of the resistor R14. The in-phase input terminal of the operational amplifier U13 is connected to the other end of the resistor R14 and the input of the third switch circuit matched therewith, and the output terminal and the inverting input terminal are connected to the other end of the resistor R16. The other end of the resistor R13 is connected to the first end of the 2.5V high-precision voltage stabilizing chip. The other end of the resistor R15 is grounded. One end of the resistor R63 is connected to the reverse input terminal of the operational amplifier U12, and the other end is grounded via the capacitor C23. One end of the resistor R72 is connected to the positive input terminal of the operational amplifier U12, and the other end is grounded via the capacitor C32. One end of the resistor R64 is connected to the reverse input terminal of the operational amplifier U13, and the other end is grounded via the capacitor C24. One end of the resistor R73 is connected to the positive input terminal of the operational amplifier U13, and the other end is grounded via the capacitor C33. One end of the capacitor C4 is connected to the power supply VCC and the second end of the 2.5V high-precision voltage stabilizing chip, and the other end is grounded. The third end of the 2.5V high-precision voltage stabilizing chip is grounded.

[0056] The third current source is a high-precision constant current source circuit. The 2.5V voltage source chip provides high-precision voltage. It is separated to keep it away from the core heating area of ​​the circuit in the PCB layout design, thereby improving the output quality of the constant current source. Resistors R13, R12 and R14 serve as the constant current source current path, while resistors R15 and R16 clamp the voltage. Operational amplifier U13 is used for voltage collection and moves with the circuit disturbance δ. Finally, the current entering the third switch through resistor R14 is ((-2.5V+δ)-δ) / R14=-0.25mA, achieving an anti-interference and high-precision constant current effect.

[0057] like Figure 5 As shown, the fourth current source includes an operational amplifier U9, an operational amplifier U10, a resistor R1, a resistor R5, a resistor R7, a resistor R8, a resistor R62, a resistor R70, a resistor R9, a resistor R65, a resistor R71, a capacitor C3, a capacitor C31, a capacitor C25, a capacitor C30, and a capacitor C22. The inverting input terminal of the operational amplifier U9 is connected to one end of the resistor R1 and one end of the resistor R5, the non-inverting input terminal is connected to one end of the resistor R7 and one end of the resistor R8, and the output terminal is connected to the other end of the resistor R1 and one end of the resistor R9.

[0058] The in-phase input terminal of the operational amplifier U10 is connected to the other end of the resistor R9 and the input of the fourth switch circuit of the subsequent stage matched therewith, and the output terminal and the inverting input terminal are connected to the other end of the resistor R7. The other end of the resistor R8 is connected to the first end of the 1.5V high-precision voltage stabilizing chip; the other end of the resistor R5 is grounded. One end of the resistor R62 is connected to the reverse input terminal of the operational amplifier U9, and the other end is grounded through the capacitor C22. One end of the resistor R70 is connected to the positive input terminal of the operational amplifier U9, and the other end is grounded through the capacitor C30. One end of the resistor R65 is connected to the reverse input terminal of the operational amplifier U10, and the other end is grounded through the capacitor C25. One end of the resistor R71 is connected to the positive input terminal of the operational amplifier U10, and the other end is grounded through the capacitor C31. One end of the capacitor C3 is connected to the power supply VCC and the second end of the 1.5V high-precision voltage stabilizing chip, and the other end is grounded. The third end of the 1.5V high-precision voltage stabilizing chip is grounded.

[0059] The fourth current source is a high-precision constant current source circuit, and its principle is the same as that of the third current source, which will not be described in detail here.

[0060] like Figure 6 As shown, the third switch circuit includes nmos tube Q4, pnp transistor Q5, resistor R25, resistor R27, resistor R29, resistor R31, and resistor R52. The gate of nmos tube Q4 is connected to the control signal provided by the output IO port of FPGA through resistor R52, the source is grounded, and the drain is connected to 3.3vref through resistor R29. One end of resistor R31 is connected to the gate of nmos tube Q4, and the other end is connected to the source of nmos tube Q4. One end of resistor R25 is connected to the drain of nmos tube Q4, and the other end is connected to the base of pnp transistor Q5. One end of resistor R27 is connected to the base of pnp transistor Q5, and the other end is connected to -3.3vref. The emitter of pnp transistor Q5 is connected to the input of the post-stage integrator, and the collector of pnp transistor Q5 is connected to the output of the third current source. Explanation of the design of the third switch circuit: Resistor R31 acts as a voltage clamp to avoid high-resistance state, while accelerating the discharge of parasitic capacitance between the gate and source of nmos tube Q4 and thus accelerating the shutdown speed. Resistor R52 eliminates gate ringing. 3.3vref and -3.3vref quantify the base current of pnp transistor Q5. When FPGA outputs a low level through the IO port connected to R52, nmos tube Q4 is turned off and pnp transistor Q5 is turned off. When FPGA outputs a high level, nmos tube Q4 is turned on and pnp transistor Q5 is turned on. The third current source 3 enters the integrator through the pnp transistor Q5.

[0061] like Figure 7As shown, the fourth switch circuit includes nmos tube Q7, npn-type triode Q8, resistor R53, resistor R48, resistor R21, resistor R28, and resistor R38. The gate of nmos tube Q7 is connected to the control signal provided by the FPGA IO port through resistor R53, the source is grounded, and the drain is connected to 3.3vref through resistor R21. Resistor R48 connects the gate and source of nmos tube Q7, one end of resistor R28 is connected to the drain of nmos tube Q7, and the other end is connected to the base of npn-type triode Q8. One end of resistor R38 is connected to the base of npn-type triode Q8, and the other end is grounded. The emitter of npn-type triode Q8 is connected to the input of the post-stage integrator, and the collector of npn-type triode Q8 is connected to the output of the fourth current source at the front end. Explanation of the fourth switch circuit design: 3.3vref quantifies the base current of the npn transistor Q8. When the FPGA outputs a high level through the resistor R53 connected to the IO port, the nmos tube Q7 is turned on and the npn transistor Q8 is turned off. When the FPGA outputs a low level, the nmos tube Q7 is turned off and the npn transistor Q8 is turned on. The current source 4 enters the integrator through the npn transistor Q8.

[0062] In this embodiment, the integrator, the integral input proportional amplification module and the integrator zero reset circuit together constitute an integration unit. The circuit structure of the integration unit is as follows: Figure 8 As shown, it includes: npn transistor Q9, npn transistor Q10, operational amplifier U1, operational amplifier U16, resistor R42, resistor R24, resistor R35, resistor R46, resistor R43, resistor R50, resistor R67, resistor R75, resistor R51, resistor R68, resistor R58, resistor R76, adjustable resistor R32, capacitor C14, capacitor C27, capacitor C35, capacitor C36, and capacitor C28.

[0063] The base of npn transistor Q9 is connected to the control signal provided by the IO output port of FPGA through resistor R4, the emitter is connected to one end of resistor R24, the collector is connected to the collector of npn transistor Q10 and then connected to the common point of the output end of operational amplifier U1 and the in-phase input end of operational amplifier U16. The base of npn transistor Q10 is connected to the output IO port of FPGA through resistor R46, and the emitter is grounded through resistor R50. The in-phase input end of operational amplifier U1 is connected to the first end of adjustable resistor R32, the inverting input end is connected to one end of capacitor C14 and then connected to the output ends of four switch circuits respectively, and the output end is connected to the other end of capacitor C14 and the common point of the in-phase input end of operational amplifier U16. The inverting input end of operational amplifier U16 is connected to one end of resistor R58 and one end of resistor R51, and the output end is connected to the other end of resistor R51 and then connected to the comparator. The other end of resistor R24 ​​is grounded. One end of the resistor R35 is connected to the common point of the resistor R42 and the base of the npn transistor Q9, and the other end is grounded. One end of the resistor R43 is connected to the common point of the resistor R46 and the base of the npn transistor Q10, and the other end is connected to -3.3VREF. One end of the resistor R67 is connected to the reverse input terminal of the operational amplifier U1, and the other end is grounded through the capacitor C27. One end of the resistor R75 is connected to the in-phase input terminal of the operational amplifier U1, and the other end is grounded through the capacitor C35, and the common point of the resistor R75 and the capacitor C35 is connected to a -15V voltage. The other end of the resistor R58 is grounded. One end of the resistor R68 is connected to the reverse input terminal of the operational amplifier U16, and the other end is grounded through the capacitor C28. One end of the resistor R76 is connected to the in-phase input terminal of the operational amplifier U16, and the other end is grounded through the capacitor C36, and the common point of the resistor R76 and the capacitor C36 is connected to a -15V voltage. A first terminal of the adjustable resistor R32 is connected to 3.3 VREF, and the other terminal is connected to -3.3 VREF.

[0064] The circuit design is explained as follows: adjustable resistor R32 adjusts the voltage at the non-inverting input of operational amplifier U1 to offset the offset voltage of the operational amplifier device. As a calibration knob, the output of the integrator of the amplifier circuit passes through zero, thereby improving the flipping accuracy of the subsequent comparator.

[0065] like Fig. 9 As shown, the circuit structure of the comparator includes an operational amplifier U3, an adjustable resistor R60, a resistor R77, a resistor R69, a resistor R39, a resistor R41, a resistor 40, a capacitor C37, a capacitor C29, and a MOS tube Q11.

[0066] The in-phase input terminal of the operational amplifier U3 is connected to the first end of the adjustable resistor R60, and the inverting input terminal is connected to the output terminal of the operational amplifier U16. The output terminal of the operational amplifier U16 is connected to one end of the resistor R40. The second end of the adjustable resistor R60 is connected to 3.3VREF, and the third end is connected to -3.3VREF. One end of the resistor R69 is connected to the reverse input terminal of the operational amplifier U3, and the other end is grounded through the capacitor C29. The common point of the resistor R69 and the capacitor C29 is connected to a +15V voltage. The other end of the resistor R40 is connected to the gate of Q11 after being connected to one end of the resistor R39. One end of the resistor R77 is connected to the positive input terminal of the operational amplifier U3, and the other end is grounded through the capacitor C37; the common point of the resistor R77 and the capacitor C37 is connected to a -15V voltage. The other end of the resistor R39 is connected to the source of Q11 and then grounded. One end of the resistor R41 is connected to the drain of Q11 and then connected to the input IO port of the FPGA as the output of the comparator, and the other end is connected to 3.33.3vref.

[0067] Explain the circuit design: when the integrator passes through zero, the comparator flips, and when the comparator outputs +Uom, Q11 turns on, and the FPGA's IO port input is low level 0; when the comparator outputs -Uom, Q11 turns off, and the FPGA's IO port input is pulled up to high level 1.

[0068] In this embodiment, the FPGA is responsible for data processing and controlling the switch on and off and output acquisition through the IO port. The present invention parallelizes the switch control integrator charging and discharging events, data calculation and filtering events, and data transmission and display events in the FPGA, that is, a three-stage pipeline design is made, and the analog-to-digital conversion is divided into three operations: switch control integrator charging and discharging operation, data calculation and filtering operation, and analog-to-digital conversion result transmission and display operation.

[0069] The following is a specific design of a three-stage pipeline: Figure 3 As shown, the FPGA includes: an integrator zero-crossing comparison result input IO, a mean filter module, an analog-to-digital conversion result display driving module, a multi-slope integral control state machine, a counter data calculation processing module and a switch control output IO; the integrator zero-crossing comparison result input IO is the input end of the FPGA, the switch control output IO is the first output end of the FPGA, and the analog-to-digital conversion result display driving module is the second output end of the FPGA; the integrator zero-crossing comparison result input IO is connected to the counter data calculation processing module, the mean filter module, and the analog-to-digital conversion result display driving module in sequence through the multi-slope integral control state machine on the one hand, and is connected to the switch control output IO through the multi-slope integral control state machine on the other hand.

[0070] In this embodiment, the multi-slope integral control state machine is designed for the charging and discharging process of the first-stage integrator of the pipeline in the FPGA. The state transfer process of the multi-slope integral control state machine is as follows: Fig.11As shown, its input and output signals are as follows:

[0071] The input signals of this state machine module include 100M clock signal clk, 10M clock signal clk_10m, reset signal reset and comparator output signal out_sta. The output signals include negative switch control signal neg_dis and positive switch control signal pos_dis of switch 5 of the integral discharge control module, first switch 1 control signal vin_cntr, second switch 2 control signal v10_cntr, third switch 3 control signal v25_cntr, fourth switch 4 control signal v125_cntr, and 20-bit analog-to-digital conversion data [19:0]data.

[0072] The working process of the state machine in this embodiment is as follows: when the reset signal is valid, the FPGA performs a reset operation on the integration circuit. When the reset stops, the FPGA issues a command to start analog-to-digital conversion. First, the state machine enters the initia state for initializing all switches. At this time, all switches will be disconnected. Then the state machine enters the discharge state, pos_dis and neg_dis are opened in a cycle to reset the integrator output voltage to zero. Then the state machine enters the vin_charge state, and the first current source 1 is integrated for a timed period of 5ms. Then the state machine enters the v10_charge state, first turning on the second current source 2, and fixing the integration time to 1ms; after the fixed time period of 1ms ends, the 10V second current source 2 is disconnected. At this time, the integrator integration voltage input will only have the first current source 1, and the period is fixed to 0.4ms. After 0.4ms ends, the second current source 2 is turned on for a fixed time of 1ms, and the two integration charge and discharge states are cycled until the integrator output voltage becomes slightly less than 0 The comparator flips, turns off the second current source 2 and the first current source 1, and the counter obtains the integration time of the two voltages. The state machine jumps to the v25_charge state, the third current source 3 is turned on, and the timed integration is 1ms. Then the state machine jumps to the v125_charge state and the third current source 3 is turned on. In the v125_charge state, the third current source 4 is turned on until the integrator output crosses zero. Then the state machine jumps to the num state, and the first current source 1 integration time counter cnt_t1 in the v10_charge state, the second current source 2 integration time counter cnt_t2, the third current source 3 integration time counter cnt_t3 in the v25_charge state, and the 1.25V reference constant current source integration time counter cnt_t4 in the v125_charge state are assigned to t1, t2, t3, and t4 respectively. At the same time, all four counters are cleared to complete a multi-slope integration process. Then the state machine will jump back to the initia state to start the next multi-slope integration. At the same time, t1, t2, t3, and t4 are It will be input to the post-stage jisuan module for addition, subtraction, multiplication, division, filtering and calculation to obtain the final analog-to-digital conversion result [19:0]data. In this embodiment, the output waveform of the integrator during an integration period is shown in Figure 1. Fig.10 .

[0073] Fig.12 1 is a simplified flow chart of the calculation of the counter data calculation module and the filter module in the FPGA of the embodiment; Fig.12As shown, the counter data calculation module is used to perform addition, subtraction, multiplication and division, and simplify the analog-to-digital conversion equation as necessary. For decimal multiplication, the current source voltage regulation value of 0.25ma, 0.125ma, etc., is converted into integer 5 multiplication, and then the final result is shifted for fast calculation; and for the final data processing result, the filter module is used to perform mean smoothing filtering on it, and the data is added and averaged by fast shift division. There are four counters in total, t1 is the charging time of Vin / 10K first current source 1 in v10_charge state, t2 is the charging time of 10V / 10K second current source 2 in v10_charge state, t3 is the charging time of 2.5V / 10K third current source 3 in v25_charge state, t4 is the charging time of 1.25V / 10K fourth current source 4 in v125_charge state, analog-to-digital conversion measured voltage Vin is regularly integrated for 5ms in vin_charge state, and 5ms is converted into a counter value of 50000 under 100M clock. Considering the constant current Ib of the transistor base, the analog-to-digital conversion relationship is obtained as formula (1), and the simplified result formula (2) is:

[0074] Vin / R×500000+Vin / R×(t1+t2)+2.5V / R×t3+Ib×(500000+t1+t2+t3)=

[0075] 10V / R×t1+1.25V / R×t4+Ib×(t1+t4) (1)

[0076] Vin×(500000+t1+t2)+2.5×t3=

[0077] 10×t1+1.25×t4-Ib×10000×(500000+t1+t2-t4) (2)

[0078] For the decimal multiplication in the formula, the method of first expanding it to an integer and then shifting it for division is adopted. For example, 1.25V multiplied by t4, t4 is multiplied by 5 and the result is shifted right by two bits to get the result of 1.25V multiplied by t4; for Ib=10.5uA, after multiplying by 100000, it is 0.105. Considering that multiplying by 128 is equal to 13.44, the counter value is multiplied by 13 and the result is shifted right by 7 bits to get the final result. For each addition, subtraction and division module instantiated in the calculation module, the pipeline delay setting is different to ensure that the data after inputting t1, t2, t3, and t4 arrives at the same time after processing. Fig.12In the addition and subtraction IP module, avoid the erroneous dividend or metastable data with a small time interval due to the misalignment of the dividend. After obtaining the dividend and divisor, input them into the division IP core, and store the quotient and decimal part in the data output respectively, data[19:17] is the integer part, and data[16:0] is the decimal part. The data is non-blockingly assigned to 4 registers for storage, and after addition, it is right-shifted by 2 bits for mean filtering, and then the new data is sent to the third stage of the pipeline. The third stage of the pipeline uses the right shift minus 3 algorithm to convert the binary code into BCD code and display it on the digital tube.

[0079] A PCB circuit board is designed by using the high-resolution and high-precision multi-slope integrating analog-to-digital converter of this embodiment. The usage of the PCB circuit board is briefly described as follows: an adjustable resistor R32 is used to calibrate the integrator, and an adjustable resistor R60 is used to calibrate the comparator. The left Vin pin is connected to the input converted signal, the -15V, +15V, and +5V pins are power supply signals, the right out-sta pin is the logic signal of the comparator output that meets the IO level standard after level conversion by Q14, neg-dis and pos-dis are signals for the FPGA to control the reset of the integrator to zero, the vincntr pin is used by the FPGA to control the on and off of the first stream source 1, the 10vcntr pin is used by the FPGA to control the on and off of the second stream source 2, the 1.25vcntr pin is used by the FPGA to control the on and off of the fourth stream source 4, and the 2.5vcntr pin is used by the FPGA to control the on and off of the third stream source 3.

[0080] The present embodiment provides a high-resolution, high-precision multi-slope integral analog-to-digital converter and an analog-to-digital conversion method. By designing a four-way high-precision constant current source circuit to replace the charge injection combination of the traditional voltage source / resistor, a higher-precision quantization of the charge and discharge amount of the integrator can be achieved. At the same time, two zero crossing points can be made in the integrator, reducing the influence of the comparator judgment hysteresis phenomenon on the accuracy. By operating the switch-controlled integrator charge and discharge events, data calculation and filtering events, and data transmission and display events in parallel in the FPGA, that is, a three-stage pipeline design is made, the analog-to-digital conversion is split into three operations: switch-controlled integrator charge and discharge operation, data calculation and filtering operation, and analog-to-digital conversion result transmission and display operation, which greatly improves the speed of analog-to-digital conversion and solves the problem that the traditional processor MCU needs to stop to calculate and filter and send the result after the switch-controlled integrator is charged and discharged in analog-to-digital conversion before starting the next analog-to-digital conversion. In addition, the four switches are all high-speed switching circuits, which can speed up the current source switching speed and further improve the conversion speed. The present invention breaks through the limitations of the traditional dual-slope integral analog-to-digital converter and has higher resolution, accuracy and conversion speed.

[0081] The above description is only a specific implementation mode of the present invention. Any feature disclosed in this specification, unless otherwise stated, can be replaced by other alternative features that are equivalent or have similar purposes; all the disclosed features, or all the steps in the methods or processes, except for mutually exclusive features and / or steps, can be combined in any way.

[0082] It is to be understood that the present invention is described by some embodiments, and it is known to those skilled in the art that various changes or equivalent substitutions may be made to these features and embodiments without departing from the spirit and scope of the present invention. In addition, under the teachings of the present invention, these features and embodiments may be modified to adapt to specific circumstances and materials without departing from the spirit and scope of the present invention. Therefore, the present invention is not limited by the specific embodiments disclosed herein, and all embodiments falling within the scope of the claims of this application are within the scope of protection of the present invention.

Claims

1. A high-precision and high-resolution multi-slope integrating analog-to-digital converter, characterized in that: include: Four parallel high-precision constant current source circuits, integrators, integral output proportional amplifier modules, comparators, integrator zero reset circuits, and FPGAs; The four-way parallel high-precision constant current source circuit comprises: four current sources and four switches, the four current sources are respectively a first current source, a second current source, a third current source and a fourth current source, the four switches are respectively a first switch, a second switch, a third switch and a fourth switch, and the four current sources are connected to the four switches in a one-to-one correspondence; The output end of the integrator is connected to the same-direction input end of the comparator via an integral output proportional amplification module; The inverting input terminal of the comparator is connected to the reference voltage, and the output terminal is connected to the input terminal of the FPGA; The input end of the integrator zero reset circuit is connected to the first output end of the FPGA, and the output end is connected to the integrator, and is used to reset the integrator according to the output result of the first output end of the FPGA; The FPGA has a first output end connected to the first switch, the second switch, the third switch, the fourth switch and the integrator zero reset circuit respectively, and a second output end connected to a digital tube peripheral.

2. The high-precision and high-resolution multi-slope integrating analog-to-digital converter according to claim 1, characterized in that: The integrator zero reset circuit includes an integrator discharge module and a fifth switch matched therewith. The input end of the integrator discharge module is connected to the first output end of the FPGA through the fifth switch, and the output end is connected to the integrator.

3. The high-precision and high-resolution multi-slope integrating analog-to-digital converter according to claim 1, characterized in that: The first current source and the third current source are both positive voltage to negative reference constant current source modules; the second current source and the fourth current source are both positive voltage to positive reference constant current source modules.

4. The high-precision and high-resolution multi-slope integral analog-to-digital converter according to claim 3, characterized in that: The circuit structure of the third current source has the same circuit structure as the first current source; the circuit structure of the third current source includes two operational amplifiers: operational amplifier U12 and operational amplifier U13; nine resistors: resistor R12, resistor R13, resistor R14, resistor R15, resistor R16, resistor R63, resistor R72, resistor R64, resistor R73; five capacitors: capacitor C23, capacitor C32, capacitor C33, capacitor C24, capacitor C4; 1 2.5V high-precision voltage regulator; The inverting input terminal of the operational amplifier U12 is connected to one end of the resistor R13 and one end of the resistor R12, the non-inverting input terminal is connected to one end of the resistor R15 and one end of the resistor R16, and the output terminal is connected to the other end of the resistor R12 and one end of the resistor R14; the non-inverting input terminal of the operational amplifier U13 is connected to the other end of the resistor R14 and the input of the third switch circuit matched therewith, and the output terminal and the inverting input terminal are connected to the other end of the resistor R16; the other end of the resistor R13 is connected to the first end of the 2.5V high-precision voltage stabilizing chip; the other end of the resistor R15 is grounded; one end of the resistor R63 is connected to the operational amplifier The reverse input terminal of the amplifier U12 and the other end are grounded via capacitor C23; one end of the resistor R72 is connected to the positive input terminal of the operational amplifier U12, and the other end is grounded via capacitor C32; one end of the resistor R64 is connected to the reverse input terminal of the operational amplifier U13, and the other end is grounded via capacitor C24; one end of the resistor R73 is connected to the positive input terminal of the operational amplifier U13, and the other end is grounded via capacitor C33; one end of the capacitor C4 is connected to the power supply VCC and the second end of the 2.5V high-precision voltage regulator chip, and the other end is grounded; the third end of the 2.5V high-precision voltage regulator chip is grounded.

5. The high-precision and high-resolution multi-slope integral analog-to-digital converter according to claim 3, characterized in that: The circuit structure of the fourth current source is the same as that of the second current source; the fourth current source includes another operational amplifier: operational amplifier U9, operational amplifier U10; nine resistors: resistor R1, resistor R5, resistor R7, resistor R8, resistor R62, resistor R70, resistor R9, resistor R65, resistor R71; five capacitors: capacitor C3, capacitor C31, capacitor C25, capacitor C30, capacitor C22; 1 1.25V high-precision voltage source; The inverting input terminal of the operational amplifier U9 is connected to one end of the resistor R1 and one end of the resistor R5, the non-inverting input terminal is connected to one end of the resistor R7 and one end of the resistor R8, and the output terminal is connected to the other end of the resistor R1 and one end of the resistor R9; the non-inverting input terminal of the operational amplifier U10 is connected to the other end of the resistor R9 and the input of the fourth switch circuit of the subsequent stage matched therewith, and the output terminal and the inverting input terminal are connected to the other end of the resistor R7; the other end of the resistor R8 is connected to the first end of the 1.25V high-precision voltage stabilizing chip, and the other end of the resistor R5 is grounded; one end of the resistor R62 is connected to the operational amplifier The reverse input terminal of U9, and the other end is grounded via capacitor C22; one end of resistor R70 is connected to the positive input terminal of operational amplifier U9, and the other end is grounded via capacitor C30; one end of resistor R65 is connected to the reverse input terminal of operational amplifier U10, and the other end is grounded via capacitor C25; one end of resistor R71 is connected to the positive input terminal of operational amplifier U10, and the other end is grounded via capacitor C31; one end of capacitor C3 is connected to the power supply VCC and the second end of the 1.25V high-precision voltage regulator chip, and the other end is grounded; the third end of the 1.25V high-precision voltage regulator chip is grounded.

6. The high-precision and high-resolution multi-slope integral analog-to-digital converter according to claim 2, characterized in that: The FPGA comprises: an integrator zero-crossing comparison result input pin, a mean filter module, an analog-to-digital conversion result display driving module, a multi-slope integral control state machine, a counter data calculation processing module and a switch control output pin; the integrator zero-crossing comparison result input pin is the input end of the FPGA, the switch control output pin is the first output end of the FPGA, and the analog-to-digital conversion result display driving module is the second output end of the FPGA; the integrator zero-crossing comparison result input pin is connected to the counter data calculation processing module, the mean filter module, and the analog-to-digital conversion result display driving module in sequence through the multi-slope integral control state machine on the one hand, and is connected to the switch control output pin through the multi-slope integral control state machine on the other hand.

7. A method for analog-to-digital conversion of a high-precision and high-resolution multi-slope integral analog-to-digital device, characterized in that: The method is implemented using a high-precision and high-resolution multi-slope integral modulus device as described in any one of claims 1 to 6, comprising the following steps: S1, initialize the integrator, that is, clear the integrator and make all switches in the off state; S2, by controlling the first switch to be turned on, the tested voltage is positively integrated for a fixed time, and after the fixed time, the first switch is turned off to stop the positive integration of the tested voltage; S3, by controlling the second switch and the first switch to be turned on and off alternately, until the negative direction of the integrator returns to zero, and then setting both the first switch and the second switch to the off state; S4, controlling the third switch to turn on, performing a forward integration of the third current source for a fixed time, and after the fixed time, turning off the third switch to stop the forward integration of the third current source; S5, by controlling the fourth switch to turn on, negatively integrating the fourth current source until the negative integral is zero, stopping the integration, and at the same time, the comparator flips and outputs a 0 signal; S6. Use the counter of the FPGA to count the conduction time of the first switch, the second switch, the third switch and the fourth switch during the integration process, respectively, to obtain the total integration time of each switch being turned on; use the calculation processing module of the FPGA to perform addition, subtraction, multiplication and division operations to obtain the final analog-to-digital conversion result.

8. The analog-to-digital conversion method of a high-precision and high-resolution multi-slope integral analog-to-digital device according to claim 7, characterized in that: The step S6 uses the following analog-to-digital conversion relationship for conversion: Vin×(500000+t1+t2)+2.5×t3=CD C=10×t1+1.25×t4 D=Ib×10000×(500000+t1+t2-t4); In the formula, A represents the measured voltage, that is, the total integrated charge of the first current source, B represents the total integrated charge of the third current source and the total integrated charge brought by the switching device when the integrator is positively integrated, C represents the total integrated charge of the second current source and the total integrated charge of the fourth current source, D represents the total integrated charge brought by the switching device when the integrator is negatively integrated, R represents resistance, V represents voltage, Vin represents the input value of the tested voltage, Ib represents the base current, t1 represents the total integrated time length of the first switch being turned on, t2 represents the total integrated time length of the second switch being turned on, t3 represents the total integrated time length of the third switch being turned on, and t4 represents the total integrated time length of the fourth switch being turned on.

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