Dynamic cell-matched enhanced current steering digital-to-analog converter based on pseudo-random sequence generation

Abstract

The application discloses a dynamic cell matching enhanced current steering digital-to-analog converter structure based on pseudo-random sequence generation. The application is composed of a high-speed parallel serial interface, a decoder, a shifter, a sampling driving circuit, a clock divider, a band gap reference circuit and a switching current cell. The digital-to-analog converter controls the shifter to randomly shift through random numbers generated by a pseudo-random sequence generator, and increases the randomness of input data by alternately selecting traditional sequential shift and cross shift. The application selects MOS tube types with small mismatch degree and four-quadrant random walk layout mode, buffers the clock of the sampling driving circuit through a six-level binary tree, and alternately selects traditional sequential shift and cross shift, thereby reducing the mismatch degree caused by process manufacturing and real working environment and the timing deviation on the clock link, improving the randomization degree of data, enhancing the dynamic cell matching degree, and being applicable to various communication and measurement devices.

Description

Technical Field

[0001] This invention relates to the field of integrated circuit design, and more specifically to a dynamic cell matching enhanced current-steering digital-to-analog converter based on pseudo-random sequence generation. Background Technology

[0002] A digital-to-analog converter (DAC) is a medium that converts digital signals into analog signals. Digital signals are stable and easy to process, making them the primary signals processed by modern computers. However, human interaction and communication with equipment often rely more conveniently and intuitively on analog signals. Therefore, DACs are needed to convert digitally processed signals back into analog signals. The metrics for evaluating DACs include accuracy, speed, and power consumption. High-speed, high-precision DACs are widely used in communications, as they can directly synthesize the required signals without an up-conversion process, significantly improving system reliability.

[0003] Current-controlled digital-to-analog converters (DACs) are characterized by high speed and strong driving capability, and are a primary implementation method for high-speed, high-precision DACs. They mainly consist of a decoding circuit, a driving circuit, and an array of switching current units. The binary digital code is decoded by the decoding circuit to generate a thermometer code, reducing glitches caused by high-order bits. The driving circuit uses the decoding result to generate a high-quality differential switching signal, controlling the corresponding switching current unit to direct either the positive or negative output terminal. The output signal is obtained by the voltage difference across the output terminal resistor.

[0004] However, the following problems typically exist in the traditional current-driven digital-to-analog converter structure:

[0005] 1. Manufacturing processes and real-world working environments can lead to varying degrees of mismatch between internal chip components;

[0006] 2. Timing deviations with gradient characteristics may occur on the internal clock link of the chip;

[0007] 3. Traditional dynamic unit matching based on sequential shifting has limited randomization capabilities.

[0008] Therefore, current-controlled digital-to-analog converters need to be improved accordingly to solve the above problems. Summary of the Invention

[0009] This invention aims to address the problems of device mismatch, timing error, and limited randomness of dynamic element matching in traditional current-controlled digital-to-analog converters by proposing a current-controlled digital-to-analog converter with enhanced dynamic element matching.

[0010] The present invention includes a high-speed parallel-to-serial interface, a decoder, a shifter and a delayer, a sampling drive circuit, a clock divider, a bandgap reference circuit and a switching current unit.

[0011] The high-speed parallel-to-serial interface is used to convert multiple low-speed data streams into a single high-speed data stream and then provide the single high-speed data stream to the decoder.

[0012] The decoder is used to translate the high-order bits of the single-channel high-speed data into thermometer code and the low-order bits into binary code, and output the data to the shifter and the delayer.

[0013] The shifter and delayer are used to randomly shift the thermometer code, delay and match the binary code, and output to the sampling drive circuit, respectively.

[0014] The sampling drive is used to resample, adjust the crossover point, isolate the power domain, and enhance the driving force of the digital signals sent from the shifter and the delayer, respectively, and then output them to the switching current unit.

[0015] The switching current unit is used to control the current flow of the signal output by the sampling drive circuit to the positive or negative terminal, and convert it into a voltage signal output through the load resistor.

[0016] The clock divider is used to provide different clock rates required by the high-speed parallel-to-serial interface, decoder, shifter, and sampling drive circuit.

[0017] The bandgap reference circuit is used to provide the required voltage bias for the current source MOS transistor, Cascode transistor, and Switch transistor of the switching current unit.

[0018] The beneficial effects of this invention are as follows:

[0019] This invention reduces the degree of mismatch caused by manufacturing process and actual working environment by selecting MOS transistor types with low mismatch and four-quadrant random walk layout; reduces timing deviation on clock link by using binary tree buffer for the sampling drive circuit clock; and improves the randomization of data by alternately selecting traditional sequential shift and cross shift, thereby enhancing the dynamic cell matching degree. Attached Figure Description

[0020] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments recorded in the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.

[0021] Figure 1 This is a block diagram of a dynamic unit matching enhanced current steering type digital-to-analog converter based on pseudo-random sequence generation.

[0022] Figure 2 It is a segmented decoding flowchart and its corresponding timing diagram.

[0023] Figure 3 This is a schematic diagram of a pseudo-random sequence generation circuit.

[0024] Figure 4 This is a schematic diagram of a traditional sequential shifter circuit.

[0025] Figure 5 This is a schematic diagram of a cross shifter circuit.

[0026] Figure 6 This is a schematic diagram of a sampling drive circuit. Detailed Implementation

[0027] The present invention will be described in detail below with reference to the accompanying drawings and preferred embodiments. The purpose and effects of the present invention will become clearer. It should be understood that the specific examples described herein are merely for explaining the present invention and are not intended to limit the present invention.

[0028] It should also be noted that, in order to avoid obscuring the invention with unnecessary details, only the structures and / or processing steps closely related to the solution according to the invention are shown in the accompanying drawings, while other details that are not closely related to the invention are omitted.

[0029] In the description of this invention, the terms "upper," "lower," "side," etc., indicating orientation or positional relationships based on the orientation or positional relationships shown in the accompanying drawings, are used only for the convenience of describing the invention and for simplifying the description, and do not indicate or imply that the device or element referred to must have a specific orientation, or be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the invention. Furthermore, the terms "highest," "first," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance.

[0030] The current-controlled digital-to-analog converter proposed in this invention consists of a high-speed parallel-to-serial interface, a decoder, a shifter, a sampling drive circuit, a clock divider, a bandgap reference circuit, and a switching current unit.

[0031] The shifter randomly shifts the thermometer code to achieve dynamic unit matching. This shifter mainly consists of a traditional sequential shifter, a cross shifter, and a shift mode selector. The traditional sequential shifter moves the data entirely to the left, the cross shifter shuffles and crosses the data, and the shift mode selector alternates between the two shift modes to further enhance the randomness of the shift.

[0032] The sampling drive circuit consists of a sampling stage, a latching stage, and a driving stage. It resamples the input data, improves the driving capability, and adjusts the crossover point.

[0033] The switching current unit consists of a current source and a differential switch, and has a small current source to reduce the parasitic capacitance of the switching circuit.

[0034] Furthermore, the dynamic unit matching enhancement technology described in this invention is mainly implemented by a thermometer decoder, a binary decoder, a pseudo-random sequence generator, a cross shifter, and a shift mode selector. When the enable signal for the dynamic unit matching technology is low, only the conventional sequential shifter is connected to the output, achieving only the effect of sequential shifting. When the enable signal for the dynamic unit matching technology is high, the results of the conventional sequential shifter and the cross shifter are connected to the output through the selector. The clock on the selector alternately controls the output of the conventional sequential shifter and the cross shifter, achieving the purpose of dynamic unit matching enhancement.

[0035] Furthermore, this invention employs a 6-6-4 segmented current steering structure, with the high 6 bits and middle 6 bits using thermometer decoding, and the low 4 bits using binary decoding. In the field of high-speed, high-precision digital-to-analog converters, purely using binary decoding would cause very serious current mismatch and conversion glitches. Using purely thermometer decoding, however, would increase the layout area exponentially with each additional bit, posing significant obstacles to power supply, clock, and signal routing, and also increasing the cost of chip fabrication. Generally, purely thermometer decoding is not used in digital-to-analog converters with a conversion accuracy exceeding 10 bits.

[0036] The segmented current-controlled structure employs thermometer decoding for the high-order bits and binary decoding for the low-order bits. Compared to pure binary decoding, this significantly reduces current mismatch and layout area, as well as routing complexity. Therefore, the segmented current-controlled structure offers the advantages of both high matching accuracy and moderate complexity. This invention uses a three-segment current-controlled structure, further reducing the number of binary decoding bits at the cost of lower circuit design complexity, thus increasing matching accuracy while minimizing complexity.

[0037] Furthermore, to reduce timing skew, this invention employs a binary tree routing for the clock signal when designing the actual layout of the sampling drive circuit. Generally, clock routing in sampling drive circuits typically uses either a daisy-chain routing starting from the edge or a daisy-chain routing starting from the center. While these two routing methods are very simple and convenient, they inevitably introduce timing skew with gradient characteristics, which will significantly impair the dynamic performance of the current-controlled digital-to-analog converter.

[0038] Furthermore, the binary tree-like routing method employed in this invention not only routes the clock signals according to the binary tree but also uses inverters at each branch level to improve drive capability, avoiding insufficient drive force caused by excessive fan-out. Therefore, the length and load of all clock paths remain consistent, minimizing clock delay differences between channels and reducing timing deviations on the clock link.

[0039] Furthermore, in the switching current unit designed in this invention, the type and area of ​​the MOSFETs corresponding to the current source array are carefully selected, and a four-quadrant random walk layout is adopted. Under 28nm process technology, the mismatch between 1.8V and 0.9V MOSFETs differs significantly. Even among 0.9V MOSFETs, the mismatch varies between low-threshold and high-threshold voltage MOSFETs. To reduce mismatch caused by manufacturing processes, this invention selects MOSFETs with low mismatch characteristics (nch_mac). However, the MOSFET area also significantly affects the degree of mismatch. Generally, a larger area results in less mismatch due to manufacturing processes, but this increases system mismatch caused by ambient temperature. Therefore, this invention employs a four-quadrant random walk layout to compensate for mismatch caused by manufacturing processes and ambient temperature to the greatest extent possible.

[0040] Furthermore, in the switching current unit designed in this invention, the input drive signals of the switching transistors are cross-wired. Traditional vertical wiring methods result in a large coupling capacitance between the input drive signal and the output current signal. Even with ground plane isolation of these two critical signals, the inevitable capacitance coupled to the ground plane means that the equivalent capacitance of these two capacitors connected in series is still sufficient to affect performance. The cross-wired method used in this invention ensures that the coupling capacitance generated by the differential input drive signal on the output signal is the same. Since the input drive signals are exactly inversely phased, their effects on the output signal cancel each other out. This improves the linearity of the digital-to-analog converter output signal.

[0041] The present invention will be further described below with reference to the accompanying drawings and embodiments.

[0042] Figure 1 This is a structural block diagram of a current-controlled digital-to-analog converter with dynamic unit matching enhancement according to an embodiment of this application. Figure 1 As shown, this embodiment mainly consists of a high-speed parallel-to-serial interface 100, a decoder 200, a shifter and delayer 300, a sampling drive circuit 400, a bandgap reference circuit 500, a clock divider 600, and a switching current unit 700.

[0043] The sampling clock, after frequency division, becomes four low-speed clocks CLK_1 / 2 / 3 / 4, which serve as the clock input for the high-speed parallel-to-serial interface, controlling the acceleration of multiple low-speed data streams into a single high-speed data stream. This high-speed data stream then enters the decoder, which translates the high-order bits into thermometer code and the low-order bits into binary code. Next, it passes through a shifter with dynamic unit matching enhancement to improve the randomness of the digital data. Then, it enters the sampling drive circuit, which increases the drive capability while adjusting the crossover point of SW_P and SW_N. Finally, it enters the switching current unit, controlling the current flow of the current source to either the positive or negative output terminal.

[0044] Figure 2 This is a key component of the dynamic unit matching enhancement technology for current-controlled digital-to-analog converters—the segmented decoding flowchart and corresponding timing diagram. This part mainly includes the thermometer decoding circuit, the binary decoding circuit, and the synchronization circuit. The thermometer decoding circuit translates the binary code Binary<15:4> into the thermometer codes Thermometer_MSB<63:0> and Thermometer_ULSB<63:0>. Figure 2 The correspondence between the data before and after decoding is marked. The binary decoding circuit consists of buffers, the purpose of which is to match the delay of the thermometer decoding circuit. After being aligned by the synchronization circuit, the decoded data is output as MSB<63:0>, ULSB<63:0>, and LSB<3:0>.

[0045] Figure 3 This is the schematic diagram of a pseudo-random sequence generation circuit, a key component of the dynamic unit matching enhancement technology for current-driven digital-to-analog converters. This circuit consists of a shift register formed by connecting registers end-to-end. Data is sequentially passed forward when the rising edge of the clock signal CLK arrives. To prevent the data stream from simultaneously outputting a "0" level and becoming unable to exit, a state avoidance circuit is designed to promptly exit the state when all output levels are "0". Finally, Q is selected. <1> Q <3> Q <9> Q <19> Q <25> Q <31> The shifter is controlled by random numbers to perform dynamic cell matching.

[0046] Figure 4 and Figure 5 The schematic diagram of a traditional sequential shifter and cross shifter circuit is a key component of the dynamic unit matching enhancement technology for current-steering digital-to-analog converters. Figure 4Traditional sequential shifters consist of multiple stages of selectors, each with 63 selectors. Clearly, each stage of selectors can either shift left or not shift. Whether to shift is determined by a 6-bit data Q generated by a pseudo-random sequence circuit. <1> Q <3> Q <9> Q <19> Q <25> Q <31> This control allows the input data MSB<63:0> to be randomly shifted to the left within the range of 0 to 63. While this sequential shifting method achieves the purpose of dynamic unit matching to some extent, it is limited by the degree of randomness of the shift and can only shift within the range of 0 to 63. The dynamic unit enhancement technology proposed in this application adds an extra cross shifter, which... Figure 5 As can be seen, the shifting method is no longer the traditional sequential shift, but instead involves varying degrees of cross-shifting. Using this shifting method, the data MSB<63:0> is no longer moved sequentially as a whole; instead, MSB<63:0> is shuffled and shifted. Combining the traditional sequential shifting method with the cross-shifting method further increases the degree of randomness and enhances the matching accuracy of dynamic units.

[0047] Figure 6 This is a schematic diagram of the sampling drive circuit for a current-driven digital-to-analog converter. Data MSB<63:0>, ULSB<63:0>, and LSB<3:0> each have their own channels. To ensure that all data reaches the switching current unit simultaneously after passing through the drive circuit, the sampling clock of the drive circuit corresponding to each channel should have the smallest possible timing error. Therefore, in this embodiment, the clock CLK is buffered through a multi-level binary tree to obtain 132 clock channels CLK_Drive<131:0>, which ensures sufficient driving capability while minimizing timing errors.

[0048] In addition to introducing a binary tree clock into the sampling drive circuit, this embodiment also uses a new set of power grounds VDDC10 and VSSC to avoid introducing signal-related fluctuations into the drive signal. In the sampling drive circuit, whether it's the sampling stage, latch stage, or drive stage, the high and low levels and transition processes of their respective outputs are directly affected by their corresponding power and ground. Essentially, the sampling stage composed of M0, M1, M2, M3, M4, and M5, the latch stage composed of INV0 and INV1, and the drive stage composed of INV2 and INV3 are all push-pull structures. Therefore, the transition process is completed by the power ground, and their respective high and low levels completely reflect the fluctuations of the power ground. These fluctuations will enter the switching current unit along with the drive signal. If the sampling drive circuit uses the same power grounds VDDD10 and VSSD as the digital circuit, then the signal-related fluctuations they carry will directly enter the switching current unit, and then greatly reduce the linearity of the output signal by coupling to the crossover point. Therefore, this application embodiment uses a new set of power grounds VDDC10 and VSSC to avoid the influence of the original power grounds VDDD10 and VSSD, which have signal-related fluctuations, on the drive signal, thereby improving the linearity of the output signal.

[0049] The current-controlled digital-to-analog converter with enhanced dynamic unit matching proposed in this application, compared with the traditional current-controlled digital-to-analog converter, reduces device mismatch caused by process manufacturing and actual working environment by using shifters with enhanced randomization, tree-shaped sampling drive circuit, MOS transistor area selection with low mismatch characteristics, and switching transistors with dual cross-drive signals. It minimizes the clock error with gradient characteristics between each bit channel, enhances the dynamic unit matching degree, and is applicable to various communication and measurement equipment.

[0050] It will be understood by those skilled in the art that the above descriptions are merely preferred examples of the invention and are not intended to limit the invention. Although the invention has been described in detail with reference to the foregoing examples, those skilled in the art can still modify the technical solutions described in the foregoing examples or make equivalent substitutions for some of the technical features. All modifications and equivalent substitutions made within the spirit and principles of the invention should be included within the scope of protection of the invention.

Claims

1. A dynamic unit-matched enhanced current-controlled digital-to-analog converter based on pseudo-random sequence generation, comprising a high-speed parallel-to-serial interface, a decoder, a shifter and a delayer, a sampling drive circuit, a clock divider, a bandgap reference circuit, and a switching current unit; characterized in that: The high-speed parallel-to-serial interface is used to convert multiple low-speed data streams into a single high-speed data stream and then provide the single high-speed data stream to the decoder. The decoder is used to translate the high-order bits of the single-channel high-speed data into thermometer code and the low-order bits into binary code, and output the data to the shifter and the delayer. The shifter and delayer are used to randomly shift the thermometer code, delay and match the binary code, and output to the sampling drive circuit, respectively. The sampling drive is used to resample, adjust the crossover point, isolate the power domain, and enhance the driving force of the digital signals sent from the shifter and the delayer, respectively, and then output them to the switching current unit. The switching current unit is used to control the current flow of the signal output by the sampling drive circuit to the positive or negative terminal, and convert it into a voltage signal output through the load resistor. The clock divider is used to provide different clock rates required by the high-speed parallel-to-serial interface, decoder, shifter, and sampling drive circuit. The bandgap reference circuit is used to provide the required voltage bias for the current source MOS transistor, Cascode transistor, and Switch transistor of the switching current unit.

2. The dynamic unit-matched enhanced current-steering digital-to-analog converter based on pseudo-random sequence generation according to claim 1, characterized in that: For 16-bit precision, the decoder performs thermometer decoding on the high 6 bits, resulting in a 63-bit thermometer code. It then performs thermometer decoding on 6 of these bits, again resulting in a 63-bit thermometer code. Finally, it performs binary decoding on the low 4 bits, resulting in a 4-bit binary code.

3. The dynamic unit-matched enhanced current-steering digital-to-analog converter based on pseudo-random sequence generation according to claim 1 or 2, characterized in that: The shifter includes a conventional sequential shifter, a cross shifter, a pseudo-random sequence generator, and a shift mode selector.

4. The dynamic unit-matched enhanced current-steering digital-to-analog converter based on pseudo-random sequence generation according to claim 3, characterized in that: The cross shifter is a shifting method that uses multiple selectors to shuffle and shift a set of data.

5. The dynamic unit-matched enhanced current-steering digital-to-analog converter based on pseudo-random sequence generation according to claim 3, characterized in that: The pseudo-random sequence generator consists of multiple registers connected end to end, and has a zero-state avoidance circuit that feeds back to the first register.

6. The dynamic unit-matched enhanced current-steering digital-to-analog converter based on pseudo-random sequence generation according to claim 3, characterized in that: The shift mode selector connects the outputs of traditional sequential shift and cross shift to the selector, and the two shift modes are alternately selected by the clock.

7. The dynamic unit-matched enhanced current-steering digital-to-analog converter based on pseudo-random sequence generation according to claim 1 or 2, characterized in that: The clock of the sampling drive circuit adopts a binary tree wiring method, and each level of the binary tree has an inverter as a buffer unit.

8. The dynamic unit-matched enhanced current-steering digital-to-analog converter based on pseudo-random sequence generation according to claim 7, characterized in that: The sampling stage of the sampling drive circuit is based on a push-pull structure to complete data sampling, and the drive stage is based on a push-pull structure to complete the drive capability enhancement and cross-point adjustment, and uses a power supply and ground that are different from other circuits on the chip.

9. The dynamic unit-matched enhanced current-steering digital-to-analog converter based on pseudo-random sequence generation according to claim 1 or 2, characterized in that: The current source array of the switching current unit adopts a four-quadrant random walk layout.

10. The dynamic unit-matched enhanced current-steering digital-to-analog converter based on pseudo-random sequence generation according to claim 9, characterized in that: The switching transistor input drive signal of the switching current unit adopts a cross-wiring method.

Images