Chip verification device and method, electronic equipment and storage medium

Abstract

The embodiment of the invention provides a chip verification device and method, electronic equipment and a storage medium, and relates to the technical field of chips, the device comprises an input component, an output component and a comparison component; the input component is used for acquiring a plurality of test messages and inputting the plurality of test messages into a circuit to be tested; the output component is used for generating feedback signals corresponding to the plurality of test messages according to a preset post-processing logic, inputting the feedback signals to the to-be-tested circuit, so that the to-be-tested circuit forwards the plurality of test messages according to the feedback signals, and inputting actual messages obtained after processing into the output component; the comparison component is used for collecting data information of messages to be discarded in the plurality of test messages in the process of processing the test messages by the circuit to be tested; eliminating messages to be discarded in the plurality of test messages by using the data information to obtain residual messages; and comparing the residual message with the actual message to obtain a first chip verification result. According to the scheme, chip verification in a packet loss scene can be realized.

Description

Technical Field

[0001] The present application relates to the field of chip technology, and in particular to a chip verification device, method, electronic device and storage medium. Background Art

[0002] In communication chips such as network processing chips and switch chips, there are a lot of data path processing logic, such as multicast paths. The multicast path performs multicast replication on messages. After multicast replication, the message expansion will cause back pressure packet loss.

[0003] In chip verification, data path verification not only needs to focus on normal paths to ensure normal flow, but also needs to focus on various packet loss scenarios caused by back pressure, complex scheduling congestion, system abnormalities, etc. However, the current verification environment cannot perform accurate packet loss operations, so there is a certain lack of chip verification with similar packet loss scenarios. Summary of the invention

[0004] The purpose of the embodiments of the present application is to provide a chip verification device, method, electronic device and storage medium to implement chip verification in a packet loss scenario. The specific technical solution is as follows:

[0005] In a first aspect, an embodiment of the present application provides a chip verification device, the device comprising: an input component, an output component and a comparison component;

[0006] The input component is used to obtain multiple test messages and input the multiple test messages into the circuit to be tested;

[0007] The output component is used to generate feedback signals corresponding to the multiple test messages according to the preset post-processing logic, and input the feedback signals to the circuit under test, so that the circuit under test forwards the multiple test messages according to the feedback signals, and inputs the actual messages obtained after processing into the output component;

[0008] The comparison component is used to collect data information of the to-be-discarded messages among the multiple test messages during the process of the circuit under test processing the test message; use the data information to eliminate the to-be-discarded messages among the multiple test messages to obtain remaining messages; and compare the remaining messages with the actual messages to obtain the first chip verification result.

[0009] In some embodiments, the circuit under test includes a first subcircuit; the first subcircuit is used to perform pre-packet loss processing and perform packet loss processing using the feedback signal; the comparison component also includes an intermediate subcomponent;

[0010] The intermediate subcomponent is used to collect data information of the to-be-discarded messages determined after the first subcircuit processes the multiple test messages.

[0011] In some embodiments, the apparatus further comprises a first reference model, and the comparison component further comprises a first scoreboard;

[0012] The input component is further used to input the multiple test messages into the first reference model;

[0013] The first reference model is used to simulate the function of the circuit under test to process the multiple test messages to obtain a first expected message, and input the first expected message into the first scoreboard;

[0014] The intermediate subcomponent is further used to input the data information into the first scoreboard;

[0015] The first scoring board is used to use the data information to eliminate the to-be-discarded messages in the first expected messages to obtain remaining messages; and compare the remaining messages with the actual messages to obtain a first chip verification result.

[0016] In some embodiments, the circuit under test further includes a second subcircuit, the second subcircuit being used to perform post-packet loss processing; the comparison component further includes an intermediate model and a first scoreboard;

[0017] The intermediate subcomponent is further used to collect all messages before discarding the message to be discarded during the process of the circuit to be tested processing the test message; use the data information to eliminate the message to be discarded from all the messages; and input the message after eliminating the message to be discarded into the intermediate model;

[0018] The intermediate model is used to simulate the function of the second sub-circuit to process the input message to obtain the remaining message;

[0019] The first scoring board is used to compare the remaining message with the actual message to obtain a first chip verification result.

[0020] In some embodiments, the apparatus further comprises a second reference model, and the comparison component further comprises a second scoreboard;

[0021] The input component is further used to input the multiple test messages into the second reference model;

[0022] The second reference model is used to simulate the function of the first sub-circuit to process the multiple test messages to obtain a second expected message, and input the second expected message into the second scoreboard;

[0023] The intermediate subcomponent is further used to input all the messages into the second scoreboard;

[0024] The second scoreboard is used to compare the second expected message with all the messages to obtain a second chip verification result.

[0025] In some embodiments, the contrast component includes an intermediate subcomponent;

[0026] The intermediate subcomponent is used to detect the data information using a preset packet loss rule to obtain a detection result of the message to be discarded; when the detection result indicates that the behavior of discarding the message to be discarded is wrong, output a prompt message.

[0027] In some embodiments, the comparison component is further used for:

[0028] The number of the multiple test messages and the number of messages output by the circuit to be tested are counted, and the number of lost packets and the number of non-discarded messages are counted using the data information.

[0029] In some embodiments, the comparison component is specifically used for:

[0030] Perform at least one of the following comparison processes on the remaining message and the actual message to obtain a first chip verification result:

[0031] Comparison of message sequence;

[0032] Comparison and processing of message contents;

[0033] Compare the number of messages.

[0034] In a second aspect, an embodiment of the present application provides a chip verification method, the method comprising:

[0035] Acquire multiple test messages, and input the multiple test messages into the circuit to be tested;

[0036] Generate feedback signals corresponding to the multiple test messages according to a preset post-processing logic, and input the feedback signals to the circuit under test, so that the circuit under test forwards the multiple test messages according to the feedback signals and outputs actual messages;

[0037] In the process of the circuit under test processing the test message, collecting data information of the message to be discarded among the multiple test messages;

[0038] Using the data information, removing the to-be-discarded messages from the multiple test messages to obtain remaining messages;

[0039] The remaining message is compared with the actual message to obtain a first chip verification result.

[0040] In some embodiments, the circuit under test includes a first subcircuit; the first subcircuit is used to perform pre-packet loss processing and perform packet loss processing using the feedback signal;

[0041] The step of collecting data information of the to-be-discarded messages among the multiple test messages during the process of the circuit under test processing the test message comprises:

[0042] Collect data information of the to-be-discarded messages determined after the first sub-circuit processes the multiple test messages.

[0043] In some embodiments, the method further comprises:

[0044] Inputting the multiple test messages into a first reference model, so that the first reference model simulates the function of the circuit under test to process the multiple test messages to obtain a first expected message;

[0045] The step of using the data information to remove the to-be-discarded messages from the multiple test messages to obtain the remaining messages includes:

[0046] The data information is used to remove the to-be-discarded messages from the first expected messages to obtain remaining messages.

[0047] In some embodiments, the circuit under test further includes a second subcircuit, and the second subcircuit is used to perform post-packet loss processing; the method further includes:

[0048] In the process of the circuit under test processing the test message, collecting all messages before discarding the message to be discarded;

[0049] The step of using the data information to remove the to-be-discarded messages from the multiple test messages to obtain the remaining messages includes:

[0050] Using the data information, eliminating the to-be-discarded messages from all the messages;

[0051] The messages after the to-be-discarded messages are removed are input into the intermediate model, so that the intermediate model simulates the function of the second sub-circuit to process the messages and obtain remaining messages.

[0052] In some embodiments, the method further comprises:

[0053] Inputting the multiple test messages into a second reference model, so that the second reference model simulates the function of the first sub-circuit to process the multiple test messages to obtain a second expected message;

[0054] The second expected message is compared with all the messages to obtain a second chip verification result.

[0055] In some embodiments, the method further comprises:

[0056] The data information is detected using a preset packet loss rule to obtain a detection result of the message to be discarded;

[0057] When the detection result indicates that the behavior of discarding the to-be-discarded message is wrong, a prompt message is output.

[0058] In some embodiments, the method further comprises:

[0059] The number of the multiple test messages and the number of messages output by the circuit to be tested are counted, and the number of lost packets and the number of non-discarded messages are counted using the data information.

[0060] In some embodiments, the step of comparing the remaining message with the actual message to obtain a first chip verification result includes:

[0061] Perform at least one of the following comparison processes on the remaining message and the actual message to obtain a first chip verification result:

[0062] Comparison of message sequence;

[0063] Comparison and processing of message contents;

[0064] Compare the number of messages.

[0065] In a third aspect, an embodiment of the present application provides an electronic device, including a processor, a communication interface, a memory, and a communication bus, wherein the processor, the communication interface, and the memory communicate with each other through the communication bus;

[0066] Memory, used to store computer programs;

[0067] The processor is used to implement any of the above-mentioned chip verification methods when executing the program stored in the memory.

[0068] In a fourth aspect, an embodiment of the present application provides a computer-readable storage medium, wherein the computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the chip verification method described above is implemented.

[0069] In a fifth aspect, an embodiment of the present application further provides a computer program product comprising instructions, which, when executed on a computer, enables the computer to execute any of the chip verification methods described above.

[0070] Beneficial effects of the embodiments of the present application:

[0071] In the technical solution provided by the embodiment of the present application, the input component inputs the test message into the circuit to be tested for processing, and the output component generates a feedback signal according to the preset post-stage processing logic, and inputs it to the circuit to be tested. The circuit to be tested forwards and processes multiple test messages according to the feedback signal, such as forwarding after packet loss or caching for a period of time, and inputs the actual message obtained after processing into the output component. By inputting a feedback signal to the circuit to be tested by the output component, various packet loss scenarios caused by front-stage packet loss due to back pressure, complex scheduling congestion, system abnormality, etc. can be simulated. The comparison component collects data information of the message to be discarded in the process of the circuit to be tested processing the test message, eliminates the message to be discarded in multiple test messages based on the data information, and compares the remaining messages with the actual messages output by the circuit to be tested, so that the message comparison can be accurately realized, and then the chip verification under the packet loss scenario can be accurately realized.

[0072] Of course, implementing any product or method of the present application does not necessarily require achieving all of the advantages described above at the same time. BRIEF DESCRIPTION OF THE DRAWINGS

[0073] In order to more clearly illustrate the embodiments of the present application or the technical solutions in the prior art, the drawings required for use in the embodiments or the description of the prior art will be briefly introduced below. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other embodiments can also be obtained based on these drawings.

[0074] Figure 1 A schematic diagram of the first structure of a chip verification device provided in an embodiment of the present application;

[0075] Figure 2 A second structural diagram of a chip verification device provided in an embodiment of the present application;

[0076] Figure 3a A first structural schematic diagram of a circuit to be tested provided in an embodiment of the present application;

[0077] Figure 3b A second structural schematic diagram of the circuit to be tested provided in an embodiment of the present application;

[0078] Figure 4 A third structural schematic diagram of a chip verification device provided in an embodiment of the present application;

[0079] Figure 5 A fourth structural schematic diagram of a chip verification device provided in an embodiment of the present application;

[0080] Figure 6 A fifth structural diagram of a chip verification device provided in an embodiment of the present application;

[0081] Figure 7A schematic diagram of a process flow of a chip verification method provided in an embodiment of the present application;

[0082] Figure 8 A schematic diagram of the structure of an electronic device provided in an embodiment of the present application. DETAILED DESCRIPTION

[0083] The following will be combined with the drawings in the embodiments of the present application to clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only part of the embodiments of the present application, not all of the embodiments. Based on the embodiments in the present application, all other embodiments obtained by ordinary technicians in this field based on the present application belong to the scope of protection of the present application.

[0084] As for chip verification, the current verification environment cannot perform accurate packet loss operations. Therefore, there are certain deficiencies in chip verification with similar packet loss scenarios.

[0085] To solve the above problems, the present application provides a chip verification device, such as Figure 1 As shown, the device includes: an input component 101, an output component 102 and a comparison component 103;

[0086] The input component 101 is used to obtain multiple test messages, input the multiple test messages into the circuit under test, so that the circuit under test performs data path processing on the multiple test messages, and input the processed multiple test messages into the output component 102;

[0087] The output component 102 is used to generate feedback signals corresponding to multiple test messages according to the preset post-processing logic, and input the feedback signals to the circuit under test, so that the circuit under test forwards the multiple test messages according to the feedback signals, and inputs the actual messages obtained after processing into the output component 102;

[0088] The comparison component 103 is used to collect data information of messages to be discarded from multiple test messages during the process of the circuit under test processing the test message; use the data information to eliminate the messages to be discarded from the multiple test messages to obtain remaining messages; compare the remaining messages with the actual messages to obtain the first chip verification result.

[0089] In the technical solution provided by the embodiment of the present application, the input component inputs the test message into the circuit to be tested for processing, and the output component generates a feedback signal according to the preset post-stage processing logic, and inputs it to the circuit to be tested. The circuit to be tested forwards and processes multiple test messages according to the feedback signal, such as forwarding after packet loss or caching for a period of time, and inputs the actual message obtained after processing into the output component. By inputting a feedback signal to the circuit to be tested by the output component, various packet loss scenarios caused by front-stage packet loss due to back pressure, complex scheduling congestion, system abnormality, etc. can be simulated. The comparison component collects data information of the message to be discarded in the process of the circuit to be tested processing the test message, eliminates the message to be discarded in multiple test messages based on the data information, and compares the remaining messages with the actual messages output by the circuit to be tested, so that the message comparison can be accurately realized, and then the chip verification under the packet loss scenario can be accurately realized.

[0090] In addition, in the embodiments of the present application, accurate message comparison is achieved by utilizing the internal information of the circuit to be tested, especially the comparison in the packet loss scenario, without modifying the test message, such as without inserting a specific mark in the message. In this way, a message with a smaller packet length or a message with a larger amount of simulation data can be used for chip verification, thus solving the problem of limited test message selection.

[0091] In the embodiment of the present application, the test message is a message used to test the circuit under test. The circuit under test is a design under test (DUT) that executes the processing logic of the data path, such as the processing logic of the multicast path.

[0092] The output port (vif) of the input component 101 is connected to the input port of the circuit to be tested, the output port of the circuit to be tested is connected to the input port (vif) of the output component 102, and the output port of the circuit to be tested is connected to the input port (vif) of the comparison component. The output port of the output component 102 is connected to the input port (vif) of the comparison component. For specific connection relationships, see Figure 1 shown.

[0093] During the chip verification process, the sequencer is started, and the sequencer in the input component 101 is called through the virtual sequencer to distribute transaction data. The format of the transaction data can be defined as in_trans.

[0094] A driver may be set in the input component 101. The driver is responsible for receiving transaction data (ie, test messages), simulating the stimulus timing, and sending corresponding interface signals (such as valid & data) to the circuit under test through the output port (vif) in the input component 101. The input component 101 may be represented as IN_UVC.

[0095] The output component 102 can be used to simulate the processing logic of the subsequent circuit, such as the preset subsequent processing logic. Based on the preset subsequent processing logic, a feedback signal is generated, and the feedback signal is input to the circuit under test. The feedback signal can be a back pressure signal, a congestion control signal, a signal indicating system abnormality, etc. The feedback signal may cause the circuit under test to perform packet loss processing in an uncertain manner. The output component 102 can be represented as OUT_UVC.

[0096] The circuit under test receives the test message input by the input component 101 and the feedback signal input by the output component 102, and performs forwarding processing (such as multicast processing) on ​​the test message using the feedback signal. Packets may or may not be lost during the forwarding processing. The number of actual messages obtained after processing may be the same as the number of test messages; it may also be less than the number of test messages, such as when packet loss processing is performed; it may also be more than the number of test messages, such as when multicast replication processing is performed. The circuit under test inputs the actual message obtained after processing into the output component 102.

[0097] The comparison component 103 collects data information (out_d_trans) of the message to be discarded from the circuit to be tested. The data information may include but is not limited to quintuple information, message length, message type and other information. The comparison component 103 compares the test message received from the input component 101 with the data information collected from the circuit to be tested, deletes the test message corresponding to the data information (i.e., the message to be discarded), and then compares the message remaining after deletion (i.e., the remaining message) with the actual message (act_data) received from the output component 102 to obtain the chip verification result, i.e., the first chip verification result. Here, the message remaining after deletion is the data remaining after the expected discard, and the actual message is the data remaining after the actual discard. The first chip verification result can be used to indicate whether the circuit to be tested has passed the verification.

[0098] In the embodiment of the present application, the comparison component 103 can be specifically used to perform at least one of the following comparison processes on the remaining message and the actual message to obtain the first chip verification result:

[0099] Comparison of message sequence;

[0100] Comparison and processing of message contents;

[0101] Compare the number of messages.

[0102] In special scenarios such as multicast, data information cannot completely distinguish different messages. In the embodiment of the present application, the problem that data information cannot distinguish different messages can be solved by comparing the message sequence and message content, thereby further improving the accuracy of chip verification.

[0103] In some embodiments, the circuit to be tested may include a first subcircuit; the first subcircuit is used to perform pre-packet loss processing and perform packet loss processing using a feedback signal; the comparison component 103 may also include an intermediate subcomponent 113; the input port (vif) of the intermediate subcomponent 113 is connected to the output port of the first subcircuit, such as Figure 2 In this case, the intermediate subcomponent 113 can be used to collect data information of the message to be discarded determined after the first subcircuit processes the multiple test messages.

[0104] In the embodiment of the present application, the intermediate subcomponent 113 can sample data information of the message that currently needs to be discarded (i.e., the message to be discarded) from the first subcircuit, and construct a discard signal (such as a drop_en signal) corresponding to the message to be discarded based on the data information. The comparison component 103 uses the discard signal to delete the message to be discarded.

[0105] For example Figure 3a As shown, the circuit to be tested includes a preprocessing module A, a copying module B, and a cache processing module C, and the cache processing module C includes a packet loss processing submodule C1 and an output processing submodule C2. Among them, the packet loss processing submodule C1 is used to perform packet loss processing using a feedback signal, that is, the preprocessing module A, the copying module B and the packet loss processing submodule C1 constitute a first subcircuit. The intermediate subcomponent 113 is connected to the output port of the packet loss processing submodule C1 to accurately collect data information of the message to be discarded and realize the deletion of the message to be discarded.

[0106] Another example Figure 3b As shown, the circuit to be tested includes a preprocessing module A, a replication module B, and a cache processing module C, and the replication module B includes a packet loss processing submodule B1 and an output processing submodule B2. Among them, the packet loss processing submodule B1 is used to perform packet loss processing using a feedback signal, that is, the preprocessing module A and the packet loss processing submodule B1 constitute a first subcircuit. The intermediate subcomponent 113 is connected to the output port of the packet loss processing submodule B1 to accurately collect data information of the message to be discarded and realize the deletion of the message to be discarded.

[0107] In some embodiments, in order to more accurately verify packet loss, such as Figure 4As shown, the chip verification device may further include a first reference model 104, and the comparison component 103 may further include a first scoreboard (SCB) 123. A monitor may be provided in the input component 101, and the monitor in the input component 101 is connected to the input port of the first reference model 104 as an output port, and the output port of the first reference model 104 is connected to the input port of the first scoreboard 123; the input port (vif) of the intermediate subcomponent 113 is connected to the output port of the first subcircuit; a monitor may be provided in the intermediate subcomponent 113, and the monitor in the intermediate subcomponent 113 is connected to the input port of the first scoreboard 123 as an output port; a monitor may be provided in the output component 102, and the monitor in the output component 102 is connected to the input port of the first scoreboard 123 as an output port.

[0108] In this case, the input component 101 may also be used to input a plurality of test messages into the first reference model 104;

[0109] The first reference model 104 is used to simulate the function of the circuit under test to process multiple test messages to obtain a first expected message, and input the first expected message into the first scoreboard 123;

[0110] The intermediate subcomponent 113 may also be used to input data information into the first scoreboard 123;

[0111] The first scoring board 123 is used to use the data information to remove the to-be-discarded messages in the first expected messages to obtain the remaining messages; and compare the remaining messages with the actual messages to obtain the first chip verification result.

[0112] In the embodiment of the present application, the input component 101 can collect data on the output port (vif) through a monitor, convert the data into an in_trans format (i.e., transaction data) and send it to the first reference model 104. The first reference model 104 simulates the function of the circuit to be tested and processes the transaction data (i.e., test message) sent by the input component 101.

[0113] Taking the circuit under test as a multicast circuit as an example, the first reference model 104 performs table lookup and replication test messages according to the multicast index table and the multicast replication table. The first reference model 104 can be represented as REF_MDL. After the verification environment generates different table entries according to the table entry generation principle, one copy is configured to the circuit under test through the register, and the other copy is transmitted to the first reference model 104. The circuit under test and the first reference model 104 perform replication functions respectively. The first reference model 104 does not consider the discard function related to the timing, and sends the first expected message to the first scoreboard 123 in a specified format (such as out_trans format).

[0114] The intermediate subcomponent 113 samples data information of the message that needs to be discarded (i.e., the message to be discarded) from the first subcircuit, and constructs a discard signal (such as a drop_en signal) corresponding to the message to be discarded according to the data information, and encapsulates the discard signal into a specific format data (such as out_d_trans format data) through the monitor and sends it to the first scoring board 123. The generated drop_en signal trusts the discard behavior in the circuit to be tested, so that the first scoring board 123 can accurately compare the non-discarded message.

[0115] The first scoring board 123 compares the first expected message (exp_data) received from the first reference model 104 with the data information (such as out_d_trans format data) received from the intermediate subcomponent 113, and deletes the message marked with the drop_en signal from the first expected message. The first scoring board 123 compares the processed first expected message (i.e., the remaining message) with the actual message received from the output component 102, such as comparing the message sequence and the message content according to the order preservation principle, to obtain the first chip verification result. If the remaining message is consistent with the actual message, it means that the circuit to be tested has passed the verification. If the remaining message is inconsistent with the actual message, it means that the circuit to be tested has failed the verification.

[0116] In the embodiment of the present application, the first reference model 104 is set to simulate the behavior of the circuit under test, and a first expected message is obtained, which is then compared with the message actually output by the circuit under test, thereby improving the accuracy of chip verification.

[0117] In some embodiments, the circuit under test may further include a second subcircuit, the second subcircuit being used to perform post-packet loss processing, such as Figure 3a The output processing submodule C2 in Figure 3b The output processing submodule B2 and the cache processing module C in the example. Figure 5 As shown, the comparison component 103 may also include an intermediate model 133 and a first scoreboard 123. The input port (vif) of the intermediate subcomponent 113 is connected to the output port of the first subcircuit, and the output port (such as monitor) of the intermediate subcomponent 113 is connected to the input port of the intermediate model 133; the output port of the intermediate model 133 is connected to the input port of the first scoreboard 123, and the input port of the first scoreboard 123 is connected to the output port (such as monitor) of the output component 102.

[0118] The intermediate subcomponent 113 can also be used to collect all messages before discarding the message to be discarded during the process of the circuit to be tested processing the test message; use the data information to eliminate the message to be discarded from all the messages; and input the message after eliminating the message to be discarded into the intermediate model;

[0119] The intermediate model 133 is used to simulate the function of the second sub-circuit to process the input message to obtain the remaining message;

[0120] The first scoring board 123 is used to compare the remaining messages with the actual messages to obtain the first chip verification result.

[0121] In the embodiment of the present application, the intermediate model 133 is a behavioral level model responsible for simulating the function of the second sub-circuit.

[0122] The intermediate subcomponent 113 can generate a set of data, namely, discarded data (such as medium_d_trans format data), which is the remaining message after removing the to-be-discarded message from all messages collected by the first subcircuit before discarding. The intermediate subcomponent 113 sends the discarded data to the intermediate model 133 through the monitor.

[0123] The intermediate model 133 receives the discarded data sent by the intermediate subcomponent 113 , performs the same data processing as the second subcircuit on the discarded data, and the output message is the remaining message (such as out_d_trans), and the remaining message is sent to the first scoreboard 123 .

[0124] The first scoring board 123 compares the remaining messages received from the intermediate model 133 with the actual messages received from the output component 102, such as comparing the message sequence and the message content according to the order preservation principle, to obtain a first chip verification result.

[0125] In the embodiment of the present application, the expected message (i.e., all messages before the message to be discarded is discarded) is collected by the sub-circuit of the circuit to be tested itself, and there is no need to set up an additional reference model, thereby reducing the algorithm complexity of chip verification. In addition, based on the expected message, a comparison is performed with the message actually output by the circuit to be tested to obtain the chip verification result, thereby improving the accuracy of chip verification.

[0126] In some embodiments, Figure 6 As shown, the chip verification device may further include a second reference model 105, and the comparison component 103 may further include a second scoreboard 143. The output port (such as monitor) of the input component 101 is connected to the input port of the second reference model 105, and the output port of the second reference model 105 is connected to the input port of the second scoreboard 143; the output port of the intermediate subcomponent 113 is connected to the input port of the second scoreboard 143.

[0127] In this case, the input component 101 may also be used to input a plurality of test messages into the second reference model 105;

[0128] The second reference model 105 is used to simulate the function of the first sub-circuit to process the multiple test messages, obtain the second expected message, and input the second expected message into the second scoreboard 143;

[0129] The intermediate subcomponent 113 is also used to input all messages into the second scoreboard 143;

[0130] The second scoring board 143 is used to compare the second expected message with all messages to obtain a second chip verification result.

[0131] In the embodiment of the present application, the intermediate subcomponent 113 can generate two sets of data, one set is the data after discarding (such as medium_d_trans format data); the other set is the data before discarding (such as medium_trans format data), which is all the messages collected from the first subcircuit before discarding. The intermediate subcomponent 113 sends the pre-discarding data to the second reference model 105 through the monitor. In addition, the input component 101 can input multiple test messages into the second reference model 105 through the monitor.

[0132] The second scoreboard 143 compares all messages received from the intermediate subcomponent 113 with the expected messages (i.e., the second expected messages) received from the second reference model 105 to obtain a second chip verification result, which can be used to indicate whether all messages collected by the intermediate subcomponent 113 are accurate or missing.

[0133] For example, if all messages received from the intermediate subcomponent 113 are inconsistent with the second expected message received from the second reference model 105, the second chip verification result generated by the second scoring board 143 indicates that all messages collected by the intermediate subcomponent 113 are inaccurate, which further indicates that the subsequent first chip verification result is inaccurate. If all messages received from the intermediate subcomponent 113 are consistent with the second expected message received from the second reference model 105, the second chip verification result generated by the second scoring board 143 indicates that all messages collected by the intermediate subcomponent 113 are accurate, which further indicates that the subsequent first chip verification result is accurate.

[0134] In the embodiment of the present application, by setting up the second scoring board 143, it is possible to verify whether the first chip verification result is accurate, thereby further improving the accuracy of chip verification.

[0135] In some embodiments, in order to determine whether the discarded message is a message that needs to be discarded and improve the reliability of the circuit to be tested, the intermediate subcomponent 113 can be used to detect data information using preset packet loss rules to obtain a detection result of the message to be discarded; when the detection result indicates that the behavior of discarding the message to be discarded is wrong, a prompt message is output.

[0136] In an embodiment of the present application, a user can extract a packet loss rule from the design document description and set the packet loss rule (i.e., the preset packet loss rule) in the chip verification device. The intermediate subcomponent 113 uses the preset packet loss rule to detect the data information (such as the above-mentioned drop_en signal) and writes a corresponding detector (checker). If it matches the preset packet loss rule, it is determined that the message to be discarded is a message that needs to be discarded, and the discard operation is correct; if it does not match the preset packet loss rule, it is determined that the message to be discarded is a message that does not need to be discarded, but the discard operation is wrong. At this time, the intermediate subcomponent 113 can output prompt information in the detector in the form of `uvm_error macro or other forms. The prompt information may include data information of the discarded message, etc., which is not limited to this.

[0137] With the help of prompt information, users can find the wrongly discarded messages in time, and then quickly locate the cause of the wrongly discarded messages, thereby improving the reliability of the circuit under test.

[0138] In the embodiment of the present application, the comparison component 103 may also have a data statistics function, counting the number of multiple test messages, the number of messages output by the circuit under test, and using data information to count the number of lost packets, the number of non-discarded messages, etc.

[0139] Specifically, the intermediate subcomponent 113 can use the data information of the collected messages to be discarded to determine the number of messages to be discarded, that is, the packet loss data; the first scoring board 123 can count the number of remaining messages as the number of messages output by the circuit to be tested, and count the number of actual messages as the number of non-discarded messages; the first scoring board 123 can compare the content of the message, and then deduplicate the message to obtain multiple test message numbers.

[0140] The comparison component 103 may also perform other data statistical functions, which are not limited thereto.

[0141] The technical solution provided in the embodiments of the present application has the following advantages:

[0142] 1) It is versatile and reduces the cost of use. The embodiment of the present application implements chip verification based on the Universal Verification Methodology (UVM) architecture, which can be quickly understood and used by verification engineers. The chip verification mechanism provided by the embodiment of the present application can flexibly select any verification architecture provided by the embodiment of the present application for environment construction and development of corresponding verification scenarios for all data processing modules (i.e., circuits to be tested) with packet loss according to the complexity of the actual modules.

[0143] For example, the circuit under test performs some simple data processing after discarding the message, which can be done by Figure 3a and Figure 4 Combined verification architecture; the circuit under test needs to perform a series of more complex data processing processes after discarding the message, which can be used Figure 3b and Figure 6 Combined verification architecture.

[0144] 2) Accuracy improves verification reliability. The technical solution provided in the embodiment of the present application is applicable to uncertain packet loss scenarios such as back pressure and complex scheduling, and can accurately compare the packet loss behavior of the circuit under test. The comparison includes the data content of the discarded message and the remaining message, as well as the accurate comparison check of the number of messages.

[0145] 3) Completeness. The technical solution provided in the embodiment of the present application can not only check the behavior of non-lost messages, but also effectively check the behavior of lost packets. At the same time, the technical solution provided in the embodiment of the present application is not only suitable for packet loss scenario verification, but can also be used normally for non-packet loss scenarios, and there is no need to reserve additional domain segments in the incentive for marking operations, which further improves the randomness of the incentive.

[0146] Corresponding to the above chip verification device, the embodiment of the present application also provides a chip verification method, such as Figure 7 As shown, the method comprises the following steps:

[0147] Step S701, obtaining multiple test messages, and inputting the multiple test messages into the circuit to be tested;

[0148] Step S702, generating feedback signals corresponding to a plurality of test messages according to a preset post-processing logic, and inputting the feedback signals to the circuit under test, so that the circuit under test forwards the plurality of test messages according to the feedback signals and outputs actual messages;

[0149] Step S703, collecting data information of messages to be discarded from multiple test messages during the process of the circuit under test processing the test message;

[0150] Step S704, using the data information, removing the to-be-discarded messages from the plurality of test messages to obtain the remaining messages;

[0151] Step S705, comparing the remaining message with the actual message to obtain a first chip verification result.

[0152] In the technical solution provided by the embodiment of the present application, a test message is input into the circuit to be tested for processing, and a feedback signal is generated according to a preset post-processing logic and input into the circuit to be tested. The circuit to be tested forwards multiple test messages according to the feedback signal, such as forwarding after packet loss or caching for a period of time, and inputs the actual message obtained after processing into the output component. By inputting a feedback signal into the circuit to be tested, various packet loss scenarios caused by front-stage packet loss due to back pressure, complex scheduling congestion, system anomalies, etc. can be simulated. The data information of the message to be discarded in the process of the circuit to be tested processing the test message is collected, and the message to be discarded in the multiple test messages is eliminated according to the data information. By comparing the remaining messages with the actual messages output by the circuit to be tested, the message comparison can be accurately realized, and then the chip verification under the packet loss scenario can be accurately realized.

[0153] In some embodiments, the circuit to be tested includes a first subcircuit; the first subcircuit is used to perform pre-packet loss processing and perform packet loss processing using the feedback signal. In this case, the above step S703 may include: collecting data information of the to-be-discarded message determined by the first subcircuit after processing multiple test messages.

[0154] In some embodiments, the chip verification method may further include: inputting a plurality of test messages into a first reference model, so that the first reference model simulates the function of the circuit under test to process the plurality of test messages and obtain a first expected message;

[0155] In this case, the above step S704 may include: using the data information to remove the to-be-discarded messages in the first expected messages to obtain the remaining messages.

[0156] In some embodiments, the circuit under test further includes a second subcircuit, and the second subcircuit is used to perform post-packet loss processing; the above chip verification method may also include: in the process of the circuit under test processing the test message, collecting all messages before discarding the message to be discarded;

[0157] In this case, the above step S704 may include: using data information to remove to-be-discarded messages from all messages; inputting the messages after removing the to-be-discarded messages into the intermediate model, so that the intermediate model simulates the function of the second sub-circuit to process the messages and obtain remaining messages.

[0158] In some embodiments, the chip verification method may further include:

[0159] Inputting a plurality of test messages into the second reference model so that the second reference model simulates the function of the first sub-circuit to process the plurality of test messages to obtain a second expected message;

[0160] The second expected message is compared with all messages to obtain a second chip verification result.

[0161] In some embodiments, the chip verification method may further include:

[0162] Use the preset packet loss rules to detect data information and obtain the detection results of the packets to be discarded;

[0163] When the detection result indicates that the behavior of discarding the message to be discarded is wrong, a prompt message is output.

[0164] In some embodiments, the chip verification method may further include:

[0165] The number of the multiple test messages and the number of messages output by the circuit to be tested are counted, and the number of lost packets and the number of non-discarded messages are counted using the data information.

[0166] In some embodiments, the above step S705 may include:

[0167] Perform at least one of the following comparison processes on the remaining message and the actual message to obtain the first chip verification result:

[0168] Comparison of message sequence;

[0169] Comparison and processing of message contents;

[0170] Compare the number of messages.

[0171] Corresponding to the above chip verification method, the embodiment of the present application also provides an electronic device, such as Figure 8 As shown, it includes a processor 801 , a communication interface 802 , a memory 803 and a communication bus 804 , wherein the processor 801 , the communication interface 802 , and the memory 803 communicate with each other via the communication bus 804 .

[0172] Memory 803, used for storing computer programs;

[0173] The processor 801 is used to implement any of the above chip verification methods when executing the program stored in the memory 803.

[0174] The communication bus mentioned in the above electronic device can be a Peripheral Component Interconnect (PCI) bus or an Extended Industry Standard Architecture (EISA) bus, etc. The communication bus can be divided into an address bus, a data bus, a control bus, etc. For ease of representation, only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus.

[0175] The communication interface is used for communication between the above electronic device and other devices.

[0176] The memory may include a random access memory (RAM) or a non-volatile memory (NVM), such as at least one disk memory. Optionally, the memory may also be at least one storage device located away from the aforementioned processor.

[0177] The processor can be a general-purpose processor, including a central processing unit (CPU), a network processor (NP), etc.; it can also be a digital signal processor (DSP), an application specific integrated circuit (ASIC), a field programmable gate array (FPGA) or other programmable logic devices, discrete gate or transistor logic devices, and discrete hardware components.

[0178] In another embodiment provided in the present application, a computer-readable storage medium is provided, in which a computer program is stored. When the computer program is executed by a processor, any of the above chip verification methods is implemented.

[0179] In another embodiment provided in the present application, a computer program product including instructions is also provided, which, when executed on a computer, enables the computer to execute any chip verification method in the above embodiments.

[0180] In the above embodiments, it can be implemented in whole or in part by software, hardware, firmware or any combination thereof. When implemented using software, it can be implemented in whole or in part in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded and executed on a computer, the process or function described in the embodiment of the present application is generated in whole or in part. The computer may be a general-purpose computer, a special-purpose computer, a computer network, or other programmable device. The computer instructions may be stored in a computer-readable storage medium, or transmitted from one computer-readable storage medium to another computer-readable storage medium. For example, the computer instructions may be transmitted from a website site, a computer, a server or a data center by wired (e.g., coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (e.g., infrared, wireless, microwave, etc.) mode to another website site, computer, server or data center. The computer-readable storage medium may be any available medium that a computer can access or a data storage device such as a server or a data center that includes one or more available media integrated. The available medium may be a magnetic medium (e.g., a floppy disk, a hard disk, a tape), an optical medium (e.g., a DVD), or a semiconductor medium (e.g., a solid-state drive Solid State Disk (SSD)), etc.

[0181] It should be noted that, in this article, relational terms such as first and second, etc. are only used to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply any such actual relationship or order between these entities or operations. Moreover, the terms "include", "comprise" or any other variants thereof are intended to cover non-exclusive inclusion, so that a process, method, article or device including a series of elements includes not only those elements, but also other elements not explicitly listed, or also includes elements inherent to such process, method, article or device. In the absence of further restrictions, the elements defined by the sentence "comprise a ..." do not exclude the existence of other identical elements in the process, method, article or device including the elements.

[0182] Each embodiment in this specification is described in a related manner, and the same or similar parts between the embodiments can be referred to each other, and each embodiment focuses on the differences from other embodiments. In particular, for the method, electronic device, storage medium and program product embodiments, since they are basically similar to the device embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the device embodiment.

[0183] The above description is only a preferred embodiment of the present application and is not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application are included in the protection scope of the present application.

Claims

1. A chip verification device, characterized in that: The device comprises: an input component, an output component and a comparison component; The input component is used to obtain multiple test messages and input the multiple test messages into the circuit to be tested; The output component is used to generate feedback signals corresponding to the multiple test messages according to the preset post-processing logic, and input the feedback signals to the circuit under test, so that the circuit under test forwards the multiple test messages according to the feedback signals, and inputs the actual messages obtained after processing into the output component; The comparison component is used to collect data information of the to-be-discarded messages among the multiple test messages during the process of the circuit under test processing the test message; use the data information to eliminate the to-be-discarded messages among the multiple test messages to obtain remaining messages; and compare the remaining messages with the actual messages to obtain the first chip verification result.

2. The device according to claim 1, characterized in that The circuit to be tested includes a first subcircuit; the first subcircuit is used to perform pre-packet loss processing and perform packet loss processing using the feedback signal; the comparison component also includes an intermediate subcomponent; The intermediate subcomponent is used to collect data information of the to-be-discarded messages determined after the first subcircuit processes the multiple test messages.

3. The device according to claim 2, characterized in that The apparatus further comprises a first reference model, and the comparison assembly further comprises a first scoreboard; The input component is further used to input the multiple test messages into the first reference model; The first reference model is used to simulate the function of the circuit under test to process the multiple test messages to obtain a first expected message, and input the first expected message into the first scoreboard; The intermediate subcomponent is further used to input the data information into the first scoreboard; The first scoring board is used to use the data information to eliminate the to-be-discarded messages in the first expected messages to obtain remaining messages; and compare the remaining messages with the actual messages to obtain a first chip verification result.

4. The device according to claim 2, characterized in that The circuit under test further includes a second subcircuit, and the second subcircuit is used to perform post-packet loss processing; the comparison component further includes an intermediate model and a first scoreboard; The intermediate subcomponent is further used to collect all messages before discarding the message to be discarded during the process of the circuit to be tested processing the test message; use the data information to eliminate the message to be discarded from all the messages; and input the message after eliminating the message to be discarded into the intermediate model; The intermediate model is used to simulate the function of the second sub-circuit to process the input message to obtain the remaining message; The first scoring board is used to compare the remaining message with the actual message to obtain a first chip verification result.

5. The device according to claim 4, characterized in that The apparatus further comprises a second reference model, and the comparison assembly further comprises a second scoreboard; The input component is further used to input the multiple test messages into the second reference model; The second reference model is used to simulate the function of the first sub-circuit to process the multiple test messages to obtain a second expected message, and input the second expected message into the second scoreboard; The intermediate subcomponent is further used to input all the messages into the second scoreboard; The second scoreboard is used to compare the second expected message with all the messages to obtain a second chip verification result.

6. The device according to any one of claims 1 to 5, characterized in that: The comparison assembly includes an intermediate subassembly; The intermediate subcomponent is used to detect the data information using a preset packet loss rule to obtain a detection result of the message to be discarded; when the detection result indicates that the behavior of discarding the message to be discarded is wrong, output a prompt message.

7. The device according to any one of claims 1 to 5, characterized in that: The comparison component is also used for: The number of the multiple test messages and the number of messages output by the circuit to be tested are counted, and the number of lost packets and the number of non-discarded messages are counted using the data information.

8. The device according to any one of claims 1 to 5, characterized in that: The comparison component is specifically used for: Perform at least one of the following comparison processes on the remaining message and the actual message to obtain a first chip verification result: Comparison of message sequence; Comparison and processing of message contents; Compare the number of messages.

9. A chip verification method, characterized in that: The method comprises: Acquire multiple test messages, and input the multiple test messages into the circuit to be tested; Generate feedback signals corresponding to the multiple test messages according to a preset post-processing logic, and input the feedback signals to the circuit under test, so that the circuit under test forwards the multiple test messages according to the feedback signals and outputs actual messages; In the process of the circuit under test processing the test message, collecting data information of the message to be discarded among the multiple test messages; Using the data information, removing the to-be-discarded messages from the multiple test messages to obtain remaining messages; The remaining message is compared with the actual message to obtain a first chip verification result.

10. The method according to claim 9, characterized in that The circuit to be tested includes a first subcircuit; the first subcircuit is used to perform pre-packet loss processing and perform packet loss processing using the feedback signal; The step of collecting data information of the to-be-discarded messages among the multiple test messages during the process of the circuit under test processing the test message comprises: Collect data information of the to-be-discarded messages determined after the first sub-circuit processes the multiple test messages.

11. The method according to claim 10, characterized in that The method further comprises: Inputting the multiple test messages into a first reference model, so that the first reference model simulates the function of the circuit under test to process the multiple test messages to obtain a first expected message; The step of using the data information to remove the to-be-discarded messages from the multiple test messages to obtain the remaining messages includes: The data information is used to remove the to-be-discarded messages from the first expected messages to obtain remaining messages.

12. The method according to claim 10, characterized in that The circuit to be tested further includes a second subcircuit, and the second subcircuit is used to perform post-packet loss processing; the method further includes: In the process of the circuit under test processing the test message, collecting all messages before discarding the message to be discarded; The step of using the data information to remove the to-be-discarded messages from the multiple test messages to obtain the remaining messages includes: Using the data information, eliminating the to-be-discarded messages from all the messages; The messages after the to-be-discarded messages are removed are input into the intermediate model, so that the intermediate model simulates the function of the second sub-circuit to process the messages and obtain remaining messages.

13. The method according to claim 12, characterized in that The method further comprises: Inputting the multiple test messages into a second reference model, so that the second reference model simulates the function of the first sub-circuit to process the multiple test messages to obtain a second expected message; The second expected message is compared with all the messages to obtain a second chip verification result.

14. The method according to any one of claims 9 to 13, characterized in that: The method further comprises: The data information is detected using a preset packet loss rule to obtain a detection result of the message to be discarded; When the detection result indicates that the behavior of discarding the to-be-discarded message is wrong, a prompt message is output.

15. The method according to any one of claims 9 to 13, characterized in that: The method further comprises: The number of the multiple test messages and the number of messages output by the circuit to be tested are counted, and the number of lost packets and the number of non-discarded messages are counted using the data information.

16. The method according to any one of claims 9 to 13, characterized in that: The step of comparing the remaining message with the actual message to obtain a first chip verification result includes: Perform at least one of the following comparison processes on the remaining message and the actual message to obtain a first chip verification result: Comparison of message sequence; Comparison and processing of message contents; Compare the number of messages.

17. An electronic device, characterized in that: It includes a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory communicate with each other via the communication bus; Memory, used to store computer programs; A processor, for implementing any of the methods described in claims 9-16 when executing a program stored in a memory.

18. A computer-readable storage medium, characterized in that: The computer-readable storage medium stores a computer program, and when the computer program is executed by a processor, the method according to any one of claims 9 to 16 is implemented.

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