A chip verification apparatus and method, an electronic device, and a storage medium

Abstract

Embodiments of the present application provide a chip verification device, method, electronic equipment and storage medium, which relate to the technical field of chips, and the device comprises an input component, an output component and a comparison component. The input component is configured to obtain a plurality of test messages and input the plurality of test messages into a circuit under test. The output component is configured to generate feedback signals corresponding to the plurality of test messages according to a preset post-stage processing logic, and input the feedback signals into the circuit under test, so that the circuit under test performs forwarding processing on the plurality of test messages according to the feedback signals, and inputs actual messages obtained after the processing into the output component. The comparison component is configured to collect data information of discarded messages in the plurality of test messages in a process in which the circuit under test processes the test messages, eliminate the discarded messages in the plurality of test messages by using the data information, obtain remaining messages, and compare the remaining messages with actual messages to obtain a first chip verification result. The scheme can realize chip verification in a packet loss scenario.

Description

TECHNICAL FIELD

[0001] The present application relates to the chip technical field, in particular to a chip verification device and method, electronic equipment and storage medium. BACKGROUND

[0002] In network processing chips, switch chips and other communication chips, there are a large number of data path processing logic, such as multicast path. The multicast path multicasts the message, and after multicast, the message expansion will cause the back pressure packet loss.

[0003] In chip verification, data path verification not only needs to focus on normal path to ensure normal flow, but also needs to focus on various packet loss scenarios caused by back pressure, complex scheduling congestion, system abnormalities and the like. However, the current verification environment cannot accurately perform packet loss operation, and therefore there is a certain deficiency in chip verification with similar packet loss scenarios. SUMMARY

[0004] The purpose of the embodiments of the present application is to provide a chip verification device and method, electronic equipment and storage medium to realize chip verification under packet loss scenarios. The specific technical solutions are as follows:

[0005] In a first aspect, the embodiments of the present application provide a chip verification device, which comprises an input component, an output component and a comparison component.

[0006] The input component is configured to obtain a plurality of test messages and input the plurality of test messages into a circuit under test.

[0007] The output component is configured to generate feedback signals corresponding to the plurality of test messages according to a preset post-stage processing logic, and input the feedback signals into the circuit under test, so that the circuit under test performs forwarding processing on the plurality of test messages according to the feedback signals, and inputs the actual messages obtained after processing into the output component.

[0008] The comparison component is configured to collect data information of test messages to be discarded in the plurality of test messages in the process of processing the test messages by the circuit under test, eliminate the test messages to be discarded in the plurality of test messages by using the data information to obtain remaining messages, and compare the remaining messages with the actual messages to obtain a first chip verification result.

[0009] In some embodiments, the circuit under test comprises a first sub-circuit, the first sub-circuit is configured to perform packet loss pre-processing and packet loss processing by using the feedback signals, and the comparison component further comprises an intermediate sub-component.

[0010] The intermediate sub-component is configured to collect data information of test messages to be discarded determined by the first sub-circuit after processing the plurality of test messages.

[0011] In some embodiments, the apparatus further comprises a first reference model, and the comparison component further comprises a first score board;

[0012] The input component is further configured to input the plurality of test packets into the first reference model;

[0013] The first reference model is configured to process the plurality of test packets to obtain first expected packets, and input the first expected packets into the first score board;

[0014] The intermediate sub-component is further configured to input the data information into the first score board;

[0015] The first score board is configured to remove the to-be-dropped packets from the first expected packets to obtain remaining packets, and compare the remaining packets with the actual packets to obtain a first chip verification result.

[0016] In some embodiments, the to-be-tested circuit further comprises a second sub-circuit configured to perform packet dropping post-processing, and the comparison component further comprises an intermediate model and a first score board;

[0017] The intermediate sub-component is further configured to collect all packets before the to-be-dropped packets are dropped during processing of the test packets by the to-be-tested circuit, remove the to-be-dropped packets from the all packets using the data information, and input the packets after the to-be-dropped packets are removed into the intermediate model;

[0018] The intermediate model is configured to process the input packets to obtain remaining packets;

[0019] The first score board is configured to compare the remaining packets with the actual packets to obtain a first chip verification result.

[0020] In some embodiments, the apparatus further comprises a second reference model, and the comparison component further comprises a second score board;

[0021] The input component is further configured to input the plurality of test packets into the second reference model;

[0022] The second reference model is configured to process the plurality of test packets to obtain second expected packets, and input the second expected packets into the second score board;

[0023] The intermediate sub-component is further configured to input the all packets into the second score board;

[0024] The second score board is configured to compare the second expected message with all the messages to obtain a second chip verification result.

[0025] In some embodiments, the comparison component includes an intermediate sub-component.

[0026] The intermediate sub-component is configured to detect the data information according to a preset packet loss rule to obtain a detection result of the to-be-dropped message; and output a prompt information when the detection result indicates that the behavior of dropping the to-be-dropped message is wrong.

[0027] In some embodiments, the comparison component is further configured to:

[0028] count the number of the test messages, the number of the messages output by the circuit under test, the number of the packet loss, and the number of the messages not dropped.

[0029] In some embodiments, the comparison component is specifically configured to:

[0030] perform at least one comparison processing on the remaining messages and the actual messages to obtain a first chip verification result, wherein the comparison processing includes:

[0031] comparison processing of message sequence;

[0032] comparison processing of message content;

[0033] comparison processing of message number.

[0034] In a second aspect, the embodiments of the present application provide a chip verification method, and the method includes:

[0035] acquiring a plurality of test messages and inputting the plurality of test messages into a circuit under test;

[0036] generating feedback signals corresponding to the plurality of test messages according to a preset post-processing logic, and inputting the feedback signals into the circuit under test, so that the circuit under test forwards the plurality of test messages according to the feedback signals to output actual messages;

[0037] collecting data information of to-be-dropped messages in the plurality of test messages in a process in which the circuit under test processes the test messages;

[0038] eliminating the to-be-dropped messages in the plurality of test messages by using the data information to obtain remaining messages;

[0039] comparing the remaining messages with the actual messages to obtain a first chip verification result.

[0040] In some embodiments, the circuit under test comprises a first sub-circuit; the first sub-circuit is configured to perform pre-packet loss processing and perform packet loss processing using the feedback signal.

[0041] The step of collecting data information of the to-be-discarded packets in the plurality of test packets during processing of the test packets by the circuit under test comprises:

[0042] The data information of the to-be-discarded packets determined by the first sub-circuit after processing of the plurality of test packets is collected.

[0043] In some embodiments, the method further comprises:

[0044] The plurality of test packets are input into a first reference model, so that the first reference model simulates the function of the circuit under test to process the plurality of test packets, and obtains first expected packets;

[0045] The step of discarding the to-be-discarded packets in the plurality of test packets using the data information to obtain remaining packets comprises:

[0046] The to-be-discarded packets in the first expected packets are discarded using the data information to obtain remaining packets.

[0047] In some embodiments, the circuit under test further comprises a second sub-circuit, and the second sub-circuit is configured to perform post-packet loss processing; the method further comprises:

[0048] During processing of the test packets by the circuit under test, all packets before discarding the to-be-discarded packets are collected.

[0049] The step of discarding the to-be-discarded packets in the plurality of test packets using the data information to obtain remaining packets comprises:

[0050] The to-be-discarded packets in the all packets are discarded using the data information.

[0051] The packets after discarding the to-be-discarded packets are input into an intermediate model, so that the intermediate model simulates the function of the second sub-circuit to process the packets, and obtains remaining packets.

[0052] In some embodiments, the method further comprises:

[0053] The plurality of test packets are input into a second reference model, so that the second reference model simulates the function of the first sub-circuit to process the plurality of test packets, and obtains second expected packets;

[0054] The second chip verification result is obtained by comparing the second expected packets with the all packets.

[0055] In some embodiments, the method further comprises:

[0056] detecting the data information by using a preset packet loss rule to obtain a detection result of the to-be-dropped packet;

[0057] outputting prompt information when the detection result indicates that the behavior of dropping the to-be-dropped packet is wrong.

[0058] In some embodiments, the method further comprises:

[0059] counting the number of the plurality of test packets, the number of packets output by the to-be-tested circuit, and the number of dropped packets and the number of undropped packets by using the data information.

[0060] In some embodiments, the step of comparing the remaining packets with the actual packets to obtain a first chip verification result comprises:

[0061] performing at least one comparison processing on the remaining packets and the actual packets to obtain a first chip verification result, wherein the comparison processing comprises:

[0062] comparison processing on packet sequence;

[0063] comparison processing on packet content;

[0064] comparison processing on packet number.

[0065] In a third aspect, an electronic device is provided, comprising a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory complete communication with each other through the communication bus;

[0066] the memory is configured to store a computer program;

[0067] the processor is configured to execute the program stored in the memory to implement the chip verification method described above.

[0068] In a fourth aspect, a computer readable storage medium is provided, and the computer readable storage medium stores a computer program, and the computer program is executed by a processor to implement the chip verification method described above.

[0069] In a fifth aspect, a computer program product comprising instructions is provided, and when the computer program product is executed on a computer, the computer is caused to execute the chip verification method described above.

[0070] The embodiments of the present application have the following beneficial effects:

[0071] In the technical scheme provided by the embodiment of the application, the input component inputs the test message into the to-be-tested circuit for processing, the output component generates a feedback signal according to the preset post-stage processing logic and inputs the feedback signal into the to-be-tested circuit. The to-be-tested circuit performs forwarding processing, such as packet loss or forwarding after a period of buffering, on the plurality of test messages according to the feedback signal, and inputs the actual message obtained after the processing into the output component. By inputting the feedback signal into the to-be-tested circuit through the output component, various packet loss scenarios caused by pre-stage packet loss due to back pressure, complex scheduling congestion, system abnormalities and the like can be simulated. The comparison component collects data information of the to-be-discarded message in the process of processing the test message by the to-be-tested circuit, removes the to-be-discarded message from the plurality of test messages according to the data information, and compares the remaining message with the actual message output by the to-be-tested circuit, so that the message comparison can be accurately implemented, and the chip verification under the packet loss scenario can be accurately implemented.

[0072] Of course, implementing any product or method of the present application does not necessarily require all the advantages described above to be achieved at the same time. BRIEF DESCRIPTION OF DRAWINGS

[0073] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed to be used in the embodiments or prior art description will be briefly introduced below. Obviously, the drawings in the following description only constitute some embodiments of the present application, and other embodiments can also be obtained by those skilled in the art based on these drawings.

[0074] Figure 1 The first structure schematic diagram of the chip verification device provided by the embodiment of the present application;

[0075] Figure 2 The second structure schematic diagram of the chip verification device provided by the embodiment of the present application;

[0076] Figure 3a The first structure schematic diagram of the to-be-tested circuit provided by the embodiment of the present application;

[0077] Figure 3b The second structure schematic diagram of the to-be-tested circuit provided by the embodiment of the present application;

[0078] Figure 4 The third structure schematic diagram of the chip verification device provided by the embodiment of the present application;

[0079] Figure 5 The fourth structure schematic diagram of the chip verification device provided by the embodiment of the present application;

[0080] Figure 6 The fifth structure schematic diagram of the chip verification device provided by the embodiment of the present application;

[0081] Figure 7A flowchart of a chip verification method provided by an embodiment of the present application is shown in the figure.

[0082] Figure 8 A structural diagram of an electronic device provided by an embodiment of the present application is shown in the figure. DETAILED DESCRIPTION

[0083] The technical solutions in the embodiments of the present application will be described clearly and completely below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, but not all the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art based on the present application are within the scope of protection of the present application.

[0084] For chip verification, the current verification environment cannot perform accurate packet loss operation, and therefore, there is a certain deficiency in chip verification for similar packet loss scenarios.

[0085] To solve the above problems, an embodiment of the present application provides a chip verification device, as shown in the figure. Figure 1 The device comprises an input component 101, an output component 102 and a comparison component 103.

[0086] The input component 101 is configured to acquire a plurality of test packets, input the plurality of test packets into a circuit under test, so that the circuit under test performs data path processing on the plurality of test packets, and input the processed plurality of test packets into the output component 102.

[0087] The output component 102 is configured to generate feedback signals corresponding to the plurality of test packets according to a preset post-processing logic, and input the feedback signals into the circuit under test, so that the circuit under test performs forwarding processing on the plurality of test packets according to the feedback signals, and input the actual packets obtained after the processing into the output component 102.

[0088] The comparison component 103 is configured to collect data information of discarded packets in the plurality of test packets in the process of processing the test packets by the circuit under test, eliminate the discarded packets in the plurality of test packets by using the data information to obtain remaining packets, and compare the remaining packets with the actual packets to obtain a first chip verification result.

[0089] In the technical scheme provided in the embodiments of the present application, the input component inputs test packets into the circuit under test for processing, and the output component generates feedback signals according to preset post-stage processing logic and inputs the feedback signals into the circuit under test. The circuit under test performs forwarding processing, such as packet loss or forwarding after a period of buffering, on the multiple test packets according to the feedback signals, and inputs the actual packets obtained after the processing into the output component. By inputting the feedback signals into the circuit under test through the output component, various packet loss scenarios caused by pre-stage packet loss due to back pressure, complex scheduling congestion, system abnormalities, and the like can be simulated. The comparison component collects data information of the to-be-discarded packets in the process of processing the test packets by the circuit under test, removes the to-be-discarded packets from the multiple test packets according to the data information, and compares the remaining packets with the actual packets output by the circuit under test, so that packet comparison can be accurately implemented, and chip verification in the packet loss scenario can be accurately implemented.

[0090] In addition, in the embodiments of the present application, internal information of the circuit under test is used to accurately implement packet comparison, especially comparison in the packet loss scenario, without the need to modify the test packets, for example, without the need to insert specific markers in the test packets. In this way, test packets with smaller packet length or more simulation data can be used for chip verification, and the problem of limited selection of test packets is solved.

[0091] In the embodiments of the present application, the test packet is a packet used for testing the circuit under test. The circuit under test is a design under test (DUT) and executes processing logic of a data path, such as processing logic of a multicast path.

[0092] The output port (vif) of the input component 101 is connected to the input port of the circuit under test, the output port of the circuit under test is connected to the input port (vif) of the output component 102, and the output port of the circuit under test is connected to the input port (vif) of the comparison component. The output port of the output component 102 is connected to the input port (vif) of the comparison component. For specific connection relationships, refer to the figure shown in Figure 1 .

[0093] In the chip verification process, a sequencer is started, and a virtual sequencer is used to call the sequencer in the input component 101 to distribute transaction data. The format of the transaction data can be defined as in_trans.

[0094] A driver can be arranged in the input component 101. The driver is responsible for receiving transaction data (i.e., test packets) and simulating excitation timing, and sending corresponding interface signals (such as valid & data) to the circuit under test through the output port (vif) of the input component 101. The input component 101 can be represented as IN_UVC.

[0095] The output component 102 can be used to simulate the processing logic of the post-stage circuit, such as preset post-stage processing logic. Based on the preset post-stage processing logic, a feedback signal is generated and input to the circuit under test. The feedback signal can be a back pressure signal, a congestion control signal, a signal indicating system abnormalities, etc., which can cause the circuit under test to perform uncertain packet loss processing. The output component 102 can be denoted as OUT_UVC.

[0096] The circuit under test receives the test packet input by the input component 101 and the feedback signal input by the output component 102, and performs forwarding processing (such as multicast processing) on the test packet using the feedback signal. During the forwarding processing, packets can be lost or not lost. The number of actual packets obtained after processing can be the same as the number of test packets, can be less than the number of test packets (e.g., packet loss processing is performed), or can be more than the number of test packets (e.g., multicast replication processing is performed). The circuit under test inputs the actual packets obtained after processing to the output component 102.

[0097] The comparison component 103 collects data information (out_d_trans) of the discarded packets from the circuit under test. The data information can include, but is not limited to, quintuple information, packet length, packet type, etc. The comparison component 103 compares the test packet received from the input component 101 with the data information collected from the circuit under test, deletes the test packet corresponding to the data information (i.e., the discarded packet), and then compares the remaining packet after deletion (i.e., the remaining packet) with the actual packet (act_data) received from the output component 102 to obtain the chip verification result, i.e., the first chip verification result. Here, the remaining packet after deletion is the expected remaining data after discarding, and the actual packet is the actual remaining data after discarding. The first chip verification result can be used to indicate whether the circuit under test passes the verification.

[0098] In the embodiments of the present application, the comparison component 103 can be specifically used to perform at least one of the following comparison processing on the remaining packet and the actual packet to obtain the first chip verification result:

[0099] comparison processing of packet order;

[0100] comparison processing of packet content;

[0101] comparison processing of packet number.

[0102] In special scenarios such as multicast, data information cannot completely distinguish different packets. In the embodiments of the present application, by comparing the packet order and the packet content, the problem that data information cannot distinguish different packets can be solved, and the accuracy of chip verification can be further improved.

[0103] In some embodiments, the circuit under test can include a first sub-circuit; the first sub-circuit is configured to perform pre-packet-dropping processing and packet-dropping processing using the feedback signal; the comparison component 103 can further include an intermediate sub-component 113; an input port (vif) of the intermediate sub-component 113 is connected to an output port of the first sub-circuit, as shown in Figure 2 In this case, the intermediate sub-component 113 can be configured to collect data information of the packet to be dropped determined by the first sub-circuit after processing the plurality of test packets.

[0104] In the embodiments of the present application, the intermediate sub-component 113 can sample data information of the packet to be dropped (i.e., the packet to be dropped) from the first sub-circuit, and the data information can be used to construct a drop signal (e.g., drop_en signal) corresponding to the packet to be dropped. The comparison component 103 uses the drop signal to delete the packet to be dropped.

[0105] For example, as shown in Figure 3a The circuit under test includes a pre-processing module A, a copy module B, and a cache processing module C, and the cache processing module C includes a packet-dropping processing sub-module C1 and an output processing sub-module C2. The packet-dropping processing sub-module C1 is configured to perform packet-dropping processing using the feedback signal, i.e., the pre-processing module A, the copy module B, and the packet-dropping processing sub-module C1 constitute the first sub-circuit. The intermediate sub-component 113 is connected to an output port of the packet-dropping processing sub-module C1 to accurately collect data information of the packet to be dropped, thereby deleting the packet to be dropped.

[0106] For another example, as shown in Figure 3b The circuit under test includes a pre-processing module A, a copy module B, and a cache processing module C, and the copy module B includes a packet-dropping processing sub-module B1 and an output processing sub-module B2. The packet-dropping processing sub-module B1 is configured to perform packet-dropping processing using the feedback signal, i.e., the pre-processing module A and the packet-dropping processing sub-module B1 constitute the first sub-circuit. The intermediate sub-component 113 is connected to an output port of the packet-dropping processing sub-module B1 to accurately collect data information of the packet to be dropped, thereby deleting the packet to be dropped.

[0107] In some embodiments, in order to more accurately verify packet-dropping, as shown in Figure 4As shown, the chip verification apparatus can further include a first reference model 104, and the comparison component 103 further includes a first Scoreboard (SCB) 123. A monitor can be arranged in the input component 101, and the monitor in the input component 101 is connected to an input port of the first reference model 104 as an output port, and an output port of the first reference model 104 is connected to an input port of the first SCB 123; an input port (vif) of the intermediate sub-component 113 is connected to an output port of the first sub-circuit; a monitor can be arranged in the intermediate sub-component 113, and the monitor in the intermediate sub-component 113 is connected to an input port of the first SCB 123 as an output port; a monitor can be arranged in the output component 102, and the monitor in the output component 102 is connected to an input port of the first SCB 123 as an output port.

[0108] In this case, the input component 101 can be further configured to input a plurality of test messages to the first reference model 104.

[0109] The first reference model 104 is configured to process the plurality of test messages according to a function of the circuit under test, to obtain first expected messages, and to input the first expected messages to the first SCB 123.

[0110] The intermediate sub-component 113 can be further configured to input data information to the first SCB 123.

[0111] The first SCB 123 is configured to use the data information to remove discarded messages from the first expected messages, to obtain remaining messages, and to compare the remaining messages with actual messages to obtain a first chip verification result.

[0112] In the embodiment, the input component 101 can collect data on the output port (vif) through the monitor, convert the data into in_trans format (i.e., transaction data), and send the transaction data to the first reference model 104. The first reference model 104 simulates the function of the circuit under test, and processes the transaction data (i.e., test messages) sent by the input component 101.

[0113] Taking a multicast circuit as an example, the first reference model 104 performs table lookup and replication on the test messages according to a multicast index table and a multicast replication table. The first reference model 104 can be denoted as REF_MDL. After the verification environment generates different table entries according to the table entry generation principle, one is configured to the circuit under test through a register, and the other is transmitted to the first reference model 104, and the circuit under test and the first reference model 104 perform replication functions respectively. The first reference model 104 does not consider the discard function related to the time sequence, and sends the first expected messages to the first SCB 123 in a specified format (e.g., out_trans format).

[0114] The intermediate sub-component 113 samples the data information of the packets that need to be dropped (i.e., the packets to be dropped) from the first sub-circuit. Based on this data information, a drop signal (such as the drop_en signal) corresponding to the packet to be dropped can be constructed. The drop signal is encapsulated into specific format data (such as out_d_trans format data) by the monitor and sent to the first scoring board 123. The generated drop_en signal trusts the drop behavior in the circuit under test, thereby enabling the first scoring board 123 to accurately compare the packets that have not been dropped.

[0115] The first scoring board 123 compares the first expected message (exp_data) received from the first reference model 104 with the data information (such as out_d_trans format data) received from the intermediate sub-component 113, and deletes the message marked with the drop_en signal from the first expected message. The first scoring board 123 compares the processed first expected message (i.e., the remaining message) with the actual message received from the output component 102, such as comparing the message order and message content according to the order preservation principle, to obtain the first chip verification result. If the remaining message is consistent with the actual message, it means that the circuit under test has passed the verification; if the remaining message is inconsistent with the actual message, it means that the circuit under test has failed the verification.

[0116] In this embodiment, a first reference model 104 is set to simulate the behavior of the circuit under test and obtain a first expected message, which is then compared with the message actually output by the circuit under test, thereby improving the accuracy of chip verification.

[0117] In some embodiments, the circuit under test may further include a second sub-circuit, which is used to perform post-packet loss processing, such as... Figure 3a The output processing submodule C2 and such Figure 3b The output processing submodule B2 and the buffer processing module C are included. In this case, such as Figure 5 As shown, the comparison component 103 may further include an intermediate model 133 and a first scoring board 123. The input port (vif) of the intermediate sub-component 113 is connected to the output port of the first sub-circuit, and the output port (e.g., monitor) of the intermediate sub-component 113 is connected to the input port of the intermediate model 133; the output port of the intermediate model 133 is connected to the input port of the first scoring board 123, and the input port of the first scoring board 123 is connected to the output port (e.g., monitor) of the output component 102.

[0118] Intermediate sub-component 113 can also be used to collect all messages before discarding messages during the process of the circuit under test processing test messages; use data information to remove messages to be discarded from all messages; and input the messages after removing messages to be discarded into the intermediate model.

[0119] Intermediate model 133 is used to simulate the function of the second sub-circuit to process the input message and obtain the remaining message;

[0120] The first scoring board 123 is used to compare the remaining messages with the actual messages to obtain the first chip verification result.

[0121] In this embodiment, intermediate model 133 is a behavioral-level model responsible for simulating the function of the second sub-circuit.

[0122] The intermediate sub-component 113 can generate a set of data, namely the discarded data (such as medium_d_trans format data), which consists of the remaining packets after removing the packets to be discarded from all packets collected by the first sub-circuit before discarding. The intermediate sub-component 113 sends the discarded data to the intermediate model 133 through the monitor.

[0123] The intermediate model 133 receives the discarded data sent by the intermediate sub-component 113, performs the same data processing as the second sub-circuit on the discarded data, and outputs the remaining message (such as out_d_trans), which is then sent to the first scoring board 123.

[0124] The first scoring board 123 compares the remaining messages received from the intermediate model 133 with the actual messages received from the output component 102. For example, it compares the message order and message content according to the order preservation principle to obtain the first chip verification result.

[0125] In this embodiment, the expected message (i.e., all messages before the discarded message) is collected by the sub-circuit of the circuit under test itself, eliminating the need for an additional reference model and reducing the algorithmic complexity of chip verification. Furthermore, based on the expected message, a comparison is made with the actual message output by the circuit under test to obtain the chip verification result, improving the accuracy of chip verification.

[0126] In some embodiments, such as Figure 6 As shown, the chip verification device described above may further include a second reference model 105, and the comparison component 103 may further include a second scoring board 143. The output port (e.g., monitor) of the input component 101 is connected to the input port of the second reference model 105, and the output port of the second reference model 105 is connected to the input port of the second scoring board 143; the output port of the intermediate sub-component 113 is connected to the input port of the second scoring board 143.

[0127] In this case, the input component 101 can also be used to input multiple test messages into the second reference model 105;

[0128] The second reference model 105 is configured to simulate the function of the first sub-circuit to process the plurality of test messages to obtain a second expected message, and input the second expected message into the second scoreboard 143.

[0129] The intermediate sub-assembly 113 is further configured to input all the messages into the second scoreboard 143.

[0130] The second scoreboard 143 is configured to compare the second expected message with all the messages to obtain a second chip verification result.

[0131] In the embodiment, the intermediate sub-assembly 113 can generate two groups of data, one group of data is discarded data (for example, medium_d_trans format data), and the other group of data is pre-discarded data (for example, medium_trans format data), which is all the messages collected from the first sub-circuit before being discarded. The intermediate sub-assembly 113 sends the pre-discarded data to the second reference model 105 through the monitor. In addition, the input assembly 101 can input the plurality of test messages into the second reference model 105 through the monitor.

[0132] The second scoreboard 143 compares all the messages received from the intermediate sub-assembly 113 with the expected message (i.e., the second expected message) received from the second reference model 105 to obtain the second chip verification result, which can be used to indicate whether all the messages collected by the intermediate sub-assembly 113 are accurate or missed.

[0133] For example, if all the messages received from the intermediate sub-assembly 113 are inconsistent with the second expected message received from the second reference model 105, the second chip verification result generated by the second scoreboard 143 indicates that all the messages collected by the intermediate sub-assembly 113 are inaccurate, and thus the subsequent first chip verification result is inaccurate. If all the messages received from the intermediate sub-assembly 113 are consistent with the second expected message received from the second reference model 105, the second chip verification result generated by the second scoreboard 143 indicates that all the messages collected by the intermediate sub-assembly 113 are accurate, and thus the subsequent first chip verification result is accurate.

[0134] In the embodiment, by setting the second scoreboard 143, it can be verified whether the first chip verification result is accurate, and thus the accuracy of chip verification is further improved.

[0135] In some embodiments, in order to determine whether the discarded message is a message that needs to be discarded and improve the reliability of the circuit under test, the intermediate sub-assembly 113 can be configured to detect the data information by using a preset packet loss rule to obtain a detection result of the discarded message, and output a prompt information when the detection result indicates that the behavior of discarding the discarded message is incorrect.

[0136] In the embodiment of the present application, a user can extract a packet loss rule from a design document description and set the packet loss rule (i.e., a preset packet loss rule) in a chip verification device. The intermediate subcomponent 113 detects data information (such as the above-mentioned drop_en signal) using the preset packet loss rule and writes a corresponding detector (checker). If the preset packet loss rule is matched, it is determined that the to-be-discarded packet is a packet that needs to be discarded, and the discarding operation is correct. If the preset packet loss rule is not matched, it is determined that the to-be-discarded packet is a packet that does not need to be discarded, but the discarding operation is incorrect. At this time, the intermediate subcomponent 113 can output prompt information in the form of a `uvm_error macro or other forms in the detector. The prompt information can include data information of the discarded packet, and the like, which is not limited.

[0137] Using the prompt information, a user can timely find an incorrectly discarded packet, and then quickly locate the cause of the incorrectly discarded packet, thereby improving the reliability of the circuit under test.

[0138] In the embodiment of the present application, the comparison component 103 can also have a data statistics function, which can count the number of test packets, the number of packets output by the circuit under test, and the number of packet losses and the number of non-discarded packets using data information.

[0139] Specifically, the intermediate subcomponent 113 can determine the number of to-be-discarded packets, i.e., packet loss data, using the data information of the to-be-discarded packets. The first scoreboard 123 can count the number of remaining packets as the number of packets output by the circuit under test, and count the number of actual packets as the number of non-discarded packets. The first scoreboard 123 can perform comparison processing on the content of the packet, and then perform deduplication processing on the packet to obtain the number of test packets.

[0140] The comparison component 103 can also perform other data statistics functions, which are not limited.

[0141] The technical solution provided in the embodiment of the present application has the following advantages:

[0142] 1) It has universality and reduces use cost. The embodiment of the present application implements chip verification based on a universal verification methodology (UVM) architecture, which can be quickly understood and used by verification engineers. The chip verification mechanism provided in the embodiment of the present application can be used for all data processing modules (i.e., a circuit under test) that have packet loss. According to the complexity of an actual module, any verification architecture provided in the embodiment of the present application can be flexibly selected to build an environment and develop a corresponding verification scenario.

[0143] For example, the circuit under test performs some simple data processing process after discarding a packet, and can use Figure 3a andFigure 4 The verification architecture is combined; the to-be-tested circuit still needs to perform a series of complex data processing processes after discarding the packet, and can adopt Figure 3b The verification architecture is combined. Figure 6 The verification architecture is combined.

[0144] 2) Accuracy and improved verification reliability. The technical scheme provided in the embodiment of the application is suitable for uncertain packet loss scenarios such as back pressure and complex scheduling, and can accurately compare the packet loss behavior of the to-be-tested circuit. The comparison includes accurate comparison and checking of the data content and the number of packets of the discarded packets and the remaining packets.

[0145] 3) Completeness. The technical scheme provided in the embodiment of the application can not only check the behavior of the non-lost packet, but also effectively check the behavior of the lost packet. At the same time, the technical scheme provided in the embodiment of the application is not only suitable for packet loss scenario verification, but also can be normally used for non-packet loss scenarios, and does not need to additionally leave a domain segment in the excitation for marking operation, further improving the randomness of the excitation.

[0146] Corresponding to the chip verification device described above, the embodiment of the application also provides a chip verification method. As shown in Figure 7 The method comprises the following steps:

[0147] Step S701, a plurality of test packets are obtained, and the plurality of test packets are input into the to-be-tested circuit;

[0148] Step S702, a plurality of test packets corresponding feedback signals are generated according to a preset post-processing logic, and the feedback signals are input into the to-be-tested circuit, so that the to-be-tested circuit performs forwarding processing on the plurality of test packets according to the feedback signals, and outputs actual packets;

[0149] Step S703, in the process of processing the test packets by the to-be-tested circuit, data information of the to-be-discarded packets in the plurality of test packets is collected;

[0150] Step S704, the to-be-discarded packets in the plurality of test packets are removed by using the data information, and the remaining packets are obtained;

[0151] Step S705, the remaining packets and the actual packets are compared, and a first chip verification result is obtained.

[0152] The technical scheme provided in the embodiments of the present application comprises the following steps: inputting a test packet into a to-be-tested circuit for processing, and generating a feedback signal according to a preset post-stage processing logic and inputting the feedback signal into the to-be-tested circuit; the to-be-tested circuit performs forwarding processing on the multiple test packets according to the feedback signal, such as packet loss or forwarding after a period of buffering, and inputs the actual packet obtained after processing into an output component. By inputting the feedback signal into the to-be-tested circuit, various packet loss scenarios caused by pre-stage packet loss due to back pressure, complex scheduling congestion, system abnormalities and the like can be simulated. The data information of the to-be-discarded packet in the process of processing the test packet by the to-be-tested circuit is collected, the to-be-discarded packet in the multiple test packets is removed according to the data information, and the remaining packet is compared with the actual packet output by the to-be-tested circuit, so that the packet comparison can be accurately implemented, and the chip verification under the packet loss scenario can be accurately implemented.

[0153] In some embodiments, the to-be-tested circuit comprises a first sub-circuit; the first sub-circuit is configured to perform pre-packet loss processing and packet loss processing using the feedback signal. In this case, the step S703 can comprise collecting data information of the to-be-discarded packet determined by the first sub-circuit after processing the multiple test packets.

[0154] In some embodiments, the chip verification method can further comprise: inputting the multiple test packets into a first reference model, so that the first reference model simulates the function of the to-be-tested circuit to process the multiple test packets and obtains first expected packets;

[0155] In this case, the step S704 can comprise: removing the to-be-discarded packet in the first expected packets using the data information to obtain the remaining packets.

[0156] In some embodiments, the to-be-tested circuit further comprises a second sub-circuit, and the second sub-circuit is configured to perform post-packet loss processing; the chip verification method can further comprise: collecting all packets before the to-be-discarded packet is discarded in the process of processing the test packet by the to-be-tested circuit;

[0157] In this case, the step S704 can comprise: removing the to-be-discarded packet in the all packets using the data information; and inputting the packet after removing the to-be-discarded packet into an intermediate model, so that the intermediate model simulates the function of the second sub-circuit to process the packet and obtains the remaining packets.

[0158] In some embodiments, the chip verification method can further comprise:

[0159] Inputting the multiple test packets into a second reference model, so that the second reference model simulates the function of the first sub-circuit to process the multiple test packets and obtains second expected packets;

[0160] Comparing the second expected packets with the all packets to obtain a second chip verification result.

[0161] In some embodiments, the chip verification method can further include:

[0162] The data information is detected by using the preset packet loss rule to obtain a detection result of the to-be-discarded packet.

[0163] When the detection result indicates that the behavior of discarding the to-be-discarded packet is wrong, the prompt information is output.

[0164] In some embodiments, the chip verification method can further include:

[0165] The number of the test packets, the number of the packets output by the to-be-tested circuit, the number of the packets lost, and the number of the packets not discarded are counted by using the data information.

[0166] In some embodiments, the step S705 can include:

[0167] The first chip verification result is obtained by performing at least one comparison processing on the remaining packet and the actual packet, including:

[0168] Comparison processing of the packet sequence;

[0169] Comparison processing of the packet content;

[0170] Comparison processing of the number of packets.

[0171] Corresponding to the chip verification method, the embodiments of the present application further provide an electronic device, as shown in the figure, including a processor 801, a communication interface 802, a memory 803 and a communication bus 804, wherein the processor 801, the communication interface 802 and the memory 803 complete the communication among each other through the communication bus 804. Figure 8

[0172] The memory 803 is used to store computer programs.

[0173] The processor 801 is used to execute the programs stored in the memory 803, and implement any of the above chip verification methods.

[0174] The communication bus mentioned in the above electronic device can be a peripheral component interconnect (PCI) bus or an extended industry standard architecture (EISA) bus, etc. The communication bus can be divided into address bus, data bus, control bus, etc. For the convenience of representation, only one thick line is used in the figure, but it does not mean that there is only one bus or one type of bus.

[0175] The communication interface is used for the communication between the above electronic device and other devices. ​

[0176] The memory can include a Random Access Memory (RAM) and can also include a Non-Volatile Memory (NVM), such as at least one disk memory. Optionally, the memory can also be at least one storage device located remotely from the aforementioned processor.

[0177] The processor can be a general processor, including a Central Processing Unit (CPU), a Network Processor (NP), etc.; can also be a Digital Signal Processor (DSP), an Application Specific Integrated Circuit (ASIC), a Field-Programmable Gate Array (FPGA) or other programmable logic device, a discrete gate or transistor logic device, a discrete hardware component.

[0178] In yet another embodiment provided in the present application, a computer readable storage medium is provided, and the computer readable storage medium stores a computer program. The computer program is executed by a processor to implement any of the above chip verification methods.

[0179] In yet another embodiment provided in the present application, a computer program product containing instructions, which, when run on a computer, causes the computer to execute any of the chip verification methods in the above embodiments.

[0180] In the embodiments described above, all or some of the embodiments can be implemented by software, hardware, firmware or any combination thereof. When implemented by software, all or some of the embodiments can be implemented in the form of a computer program product. The computer program product includes one or more computer instructions. When the computer program instructions are loaded into and executed by a computer, all or some of the processes or functions according to the embodiments described in the specification are generated. The computer can be a general purpose computer, a special purpose computer, a computer network, or other programmable apparatus. The computer instructions can be stored in a computer readable storage medium or transmitted from one computer readable storage medium to another computer readable storage medium, for example, the computer instructions can be transmitted from one website, computer, server or data center to another website, computer, server or data center through a wired (for example, coaxial cable, optical fiber, digital subscriber line (DSL)) or wireless (for example, infrared, wireless, microwave, etc.) manner. The computer readable storage medium can be any available medium that can be accessed by a computer or a data storage device such as a server, data center, etc. integrated with one or more available media. The available media can be a magnetic medium (for example, floppy disk, hard disk, magnetic tape), an optical medium (for example, DVD), or a semiconductor medium (for example, Solid State Disk (SSD)) and the like.

[0181] It should be noted that, in this document, the terms such as first and second are used only to distinguish one entity or operation from another entity or operation, and do not necessarily require or imply that there is any such actual relationship or order between these entities or operations. Moreover, the terms "include", "contain" or any other variants thereof are intended to cover non-exclusive inclusion, so that the process, method, article or device including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such process, method, article or device. Without more limitations, the element defined by the statement "including a" does not exclude the presence of other identical elements in the process, method, article or device including the element.

[0182] Each of the embodiments in the specification is described in a related manner, and the same or similar parts between each of the embodiments can be referred to each other. Each of the embodiments focuses on the difference from other embodiments. In particular, for the method, electronic device, storage medium and program product embodiments, since they are basically similar to the device embodiments, the description is relatively simple, and the relevant parts can be referred to the part of the description of the device embodiments.

[0183] The above merely provides the preferred embodiment of the present application, and not intended to limit the protection scope of the present application. Any modification, equivalent replacement, improvement, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.

Claims

1. A chip verification apparatus characterized by comprising: The device comprises an input component, an output component and a comparison component; The input component is configured to acquire a plurality of test packets and input the plurality of test packets into a circuit under test; The output component is configured to generate feedback signals corresponding to the plurality of test packets according to a preset post-stage processing logic, and input the feedback signals into the circuit under test, so that the circuit under test performs forwarding processing on the plurality of test packets according to the feedback signals, and inputs actual packets obtained after processing into the output component; The comparison component is configured to collect data information of discarded packets in the plurality of test packets in a process in which the circuit under test processes the test packets, eliminate the discarded packets in the plurality of test packets by using the data information to obtain remaining packets, and compare the remaining packets with the actual packets to obtain a first chip verification result.

2. The apparatus of claim 1, wherein, The circuit under test comprises a first sub-circuit, the first sub-circuit is configured to perform pre-packet loss processing and packet loss processing by using the feedback signals, and the comparison component further comprises an intermediate sub-component; The intermediate sub-component is configured to collect data information of discarded packets determined by the first sub-circuit after processing the plurality of test packets.

3. The apparatus of claim 2, wherein, The device further comprises a first reference model, and the comparison component further comprises a first score board; The input component is further configured to input the plurality of test packets into the first reference model; The first reference model is configured to simulate functions of the circuit under test to process the plurality of test packets, obtain first expected packets, and input the first expected packets into the first score board; The intermediate sub-component is further configured to input the data information into the first score board; The first score board is configured to eliminate the discarded packets in the first expected packets by using the data information to obtain remaining packets, and compare the remaining packets with the actual packets to obtain a first chip verification result.

4. The apparatus of claim 2, wherein, The circuit under test further comprises a second sub-circuit, the second sub-circuit is configured to perform post-packet loss processing, and the comparison component further comprises an intermediate model and a first score board; The intermediate sub-component is further configured to collect all packets before the discarded packets are discarded in a process in which the circuit under test processes the test packets, eliminate the discarded packets in the all packets by using the data information, and input the packets after the discarded packets are eliminated into the intermediate model; The intermediate model is configured to simulate functions of the second sub-circuit to process the input packets to obtain remaining packets; The first score board is configured to compare the remaining packets with the actual packets to obtain a first chip verification result.

5. The apparatus of claim 4, wherein, The device further comprises a second reference model, and the comparison component further comprises a second score board; The input component is further configured to input the plurality of test packets into the second reference model; The second reference model is configured to simulate functions of the first sub-circuit to process the plurality of test packets to obtain second expected packets, and input the second expected packets into the second score board; The intermediate sub-component is further configured to input the all packets into the second score board; The second score board is configured to compare the second expected message with the all messages to obtain a second chip verification result.

6. The device of any one of claims 1-5, wherein, The comparison component comprises an intermediate sub-component; The intermediate sub-component is configured to detect the data information according to a preset packet loss rule to obtain a detection result of the to-be-dropped message; and output prompt information when the detection result indicates that the behavior of dropping the to-be-dropped message is wrong.

7. The device of any one of claims 1-5, wherein, The comparison component is further configured to: count the number of the plurality of test messages, the number of messages output by the to-be-tested circuit, the number of packet losses, and the number of undropped messages according to the data information.

8. The device of any one of claims 1-5, wherein, The comparison component is specifically configured to: perform at least one of the following comparison processes on the remaining messages and the actual messages to obtain a first chip verification result: comparison of message order; comparison of message content; comparison of the number of messages.

9. A chip verification method characterized by, The method comprises: obtaining a plurality of test messages and inputting the plurality of test messages into a to-be-tested circuit; generating feedback signals corresponding to the plurality of test messages according to a preset post-processing logic, and inputting the feedback signals into the to-be-tested circuit, so that the to-be-tested circuit forwards the plurality of test messages according to the feedback signals to output actual messages; collecting data information of to-be-dropped messages in the plurality of test messages in the process of processing test messages by the to-be-tested circuit; eliminating the to-be-dropped messages in the plurality of test messages according to the data information to obtain remaining messages; comparing the remaining messages with the actual messages to obtain a first chip verification result.

10. The method of claim 9, wherein, The to-be-tested circuit comprises a first sub-circuit, and the first sub-circuit is configured to perform pre-packet loss processing and packet loss processing according to the feedback signals; The step of collecting data information of to-be-dropped messages in the plurality of test messages in the process of processing test messages by the to-be-tested circuit comprises: collecting data information of to-be-dropped messages determined by the first sub-circuit after processing the plurality of test messages.

11. The method of claim 10, wherein, The method further comprises: inputting the plurality of test messages into a first reference model, so that the first reference model simulates the function of the to-be-tested circuit to process the plurality of test messages to obtain first expected messages; The step of eliminating the to-be-dropped messages in the plurality of test messages according to the data information to obtain remaining messages comprises: eliminating the to-be-dropped messages in the first expected messages according to the data information to obtain remaining messages.

12. The method of claim 10, wherein, The to-be-tested circuit further comprises a second sub-circuit, and the second sub-circuit is configured to perform post-packet loss processing; the method further comprises: collecting all messages before the to-be-dropped messages are dropped in the process of processing test messages by the to-be-tested circuit; The step of eliminating the to-be-dropped messages in the plurality of test messages according to the data information to obtain remaining messages comprises: eliminating the to-be-dropped messages in the all messages according to the data information; inputting the messages after the to-be-dropped messages are eliminated into an intermediate model, so that the intermediate model simulates the function of the second sub-circuit to process the messages to obtain remaining messages.

13. The method of claim 12, wherein, The method further comprises: Input the plurality of test packets into a second reference model, so that the second reference model simulates the processing of the plurality of test packets by the function of the first sub-circuit to obtain second expected packets; Compare the second expected packets with the all packets to obtain a second chip verification result.

14. The method according to any one of claims 9 to 13, characterized in that, The method further comprises: Detecting the data information by using a preset packet loss rule to obtain a detection result of the to-be-dropped packets; When the detection result indicates that the behavior of dropping the to-be-dropped packets is wrong, outputting prompt information.

15. The method according to any one of claims 9-13, characterized in that, The method further comprises: Counting the number of the plurality of test packets, the number of the packets output by the to-be-tested circuit, and the number of the dropped packets and the number of the undropped packets by using the data information.

16. The method according to any one of claims 9-13, characterized in that, The step of comparing the remaining packets with the actual packets to obtain a first chip verification result comprises: Performing at least one comparison processing on the remaining packets and the actual packets to obtain a first chip verification result: Comparison processing of packet sequence; Comparison processing of packet content; Comparison processing of packet number.

17. An electronic device, comprising: The device comprises a processor, a communication interface, a memory and a communication bus, wherein the processor, the communication interface and the memory complete mutual communication through the communication bus; The memory is used for storing a computer program; The processor is used for executing the program stored on the memory to implement the method in any one of claims 9-16.

18. A computer-readable storage medium, characterized in that, The computer program stored in the computer readable storage medium is executed by the processor to implement the method in any one of claims 9-16.

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