Semiconductor structure and method for forming the same

Abstract

The present disclosure provides a semiconductor structure and a method for forming the same, the method comprising: providing a substrate, the substrate comprising an array region, a lead-out region, and a peripheral region sequentially arranged along a first direction; the array region and the lead-out region comprising a plurality of word line trenches extending along the first direction and arranged along a second direction; the first direction and the second direction intersect and are both perpendicular to a thickness direction of the substrate; forming a conductive structure in each word line trench; the top surface of the conductive structure being lower than the top surface of the peripheral region; forming a barrier layer covering at least the conductive structure and the peripheral region; performing a first etch to remove a portion of the barrier layer directly above the array region; and performing a second etch to remove the remaining barrier layer directly above the array region and a portion of the barrier layer directly above the lead-out region.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] Dynamic Random Access Memory (DRAM) is a semiconductor memory that can write and read data at high speed and at random. It is widely used in data storage devices and equipment. In the DRAM production process, to improve production efficiency and reduce production costs, the memory array and peripheral circuits are formed simultaneously on the same substrate. How to achieve effective compatibility between the memory array and peripheral circuit formation processes has become a pressing issue. Summary of the Invention

[0003] In view of this, embodiments of the present disclosure provide a semiconductor structure and a method for forming the same in order to solve at least one problem existing in the prior art.

[0004] To achieve the above objectives, the technical solution of the embodiment of the present disclosure is implemented as follows:

[0005] In a first aspect, an embodiment of the present disclosure provides a method for forming a semiconductor structure, comprising:

[0006] Providing a substrate, the substrate comprising an array region, a lead-out region, and a peripheral region sequentially arranged along a first direction; the array region and the lead-out region comprising a plurality of word line trenches extending along the first direction and arranged along a second direction; the first direction and the second direction intersecting and both being perpendicular to a thickness direction of the substrate;

[0007] forming a conductive structure in each of the word line trenches; wherein a top surface of the conductive structure is lower than a top surface of the peripheral region;

[0008] forming a barrier layer covering at least the conductive structure and the peripheral region;

[0009] Performing a first etching step to remove a portion of the barrier layer located directly above the array region;

[0010] A second etching process is performed to remove the remaining barrier layer directly above the array region and a portion of the barrier layer directly above the lead-out region.

[0011] In an optional implementation, performing the second etching includes:

[0012] The barrier layer located directly above the peripheral region is removed, and a top surface of the remaining barrier layer located directly above the lead-out region is flush with a top surface of the peripheral region.

[0013] In an optional embodiment, after the first etching is performed, the thickness of the remaining barrier layer located directly above the array region is the same as the thickness of the barrier layer located directly above the peripheral region.

[0014] In an optional embodiment, forming a barrier layer covering at least the conductive structure and the peripheral region includes:

[0015] forming a barrier layer covering the array region, the lead-out region, and the peripheral region;

[0016] The performing the first etching comprises:

[0017] removing a portion of the barrier layer on the conductive structure directly above the array region and a portion of the barrier layer directly above the array region between adjacent conductive structures, so that a top surface of the remaining barrier layer on the conductive structure directly above the array region and a top surface of the remaining barrier layer directly above the array region between adjacent conductive structures are both lower than a top surface of the barrier layer directly above the peripheral region and the lead-out region;

[0018] The performing the second etching comprises:

[0019] The remaining barrier layer on the conductive structure directly above the array area, the remaining barrier layer directly above the array area between adjacent conductive structures, part of the barrier layer directly above the lead-out area, and the barrier layer directly above the peripheral area are removed.

[0020] In an optional embodiment, the method for forming the semiconductor structure further includes:

[0021] Before performing the first etching, forming a photoresist layer covering the barrier layer;

[0022] removing a portion of the photoresist layer by a photolithography process to expose the barrier layer directly above the array region;

[0023] The performing the first etching comprises:

[0024] removing the portion of the barrier layer exposed directly above the array region;

[0025] The method for forming the semiconductor structure further includes:

[0026] After performing the first etching, the photoresist layer is removed.

[0027] In an optional embodiment, providing a substrate comprises:

[0028] providing a substrate;

[0029] Active areas arranged in an array and a first isolation structure located between the active areas are formed in the substrate of the array area, and a second isolation structure is formed in the substrate; a first portion of the second isolation structure is located in the lead-out area, and a second portion of the second isolation structure is located in the peripheral area;

[0030] The active area, the first isolation structure, and the first portion of the second isolation structure are etched along a thickness direction of the substrate to form the word line trench.

[0031] In an optional embodiment, the method for forming the semiconductor structure further includes:

[0032] Before forming the conductive structure in the word line trench, a gate dielectric layer is formed at the bottom of the word line trench.

[0033] In an optional embodiment, the method for forming the semiconductor structure further includes:

[0034] After the second etching is performed, a portion of the conductive structure located directly above the array area is removed, and the remaining conductive structure located directly above the array area and the gate dielectric layer constitute a word line structure; the conductive structure located directly above the lead-out area constitutes a word line lead-out structure; and the top surface of the word line lead-out structure is higher than the top surface of the word line structure.

[0035] In a second aspect, an embodiment of the present disclosure provides a semiconductor structure, including:

[0036] A substrate comprising an array region, a lead-out region, and a peripheral region sequentially arranged along a first direction;

[0037] A word line structure located directly above the array area; the word line structure extends along the first direction and is arranged along the second direction; the first direction and the second direction intersect and are both perpendicular to the thickness direction of the substrate;

[0038] A word line lead-out structure located directly above the lead-out region; a top surface of the word line lead-out structure being higher than a top surface of the word line structure;

[0039] A barrier layer is located directly above the word line lead-out structure; a top surface of the barrier layer is flush with a top surface of the peripheral region.

[0040] In an optional embodiment, the array area includes active areas arranged in an array and a first isolation structure located between the active areas; the substrate also includes a second isolation structure, a first portion of the second isolation structure is located in the lead-out area, and a second portion of the second isolation structure is located in the peripheral area; the top surface of the second portion is higher than the top surface of the first portion.

[0041] In the technical solution provided in the present disclosure, a portion of the barrier layer located directly above the array area is first removed by performing a first etching step, and then a second etching step is performed so that the barrier layer located directly above the array area, the barrier layer located directly above the peripheral area, and a portion of the barrier layer located directly above the lead-out area can be removed simultaneously. This allows for the formation of a word line lead-out structure having a top surface higher than that of the word line structure while avoiding the formation of a height difference between the array area and the lead-out area and the peripheral area. This ensures that the film layer formed in subsequent process steps and covering the array area, the lead-out area, and the peripheral area simultaneously has a higher flatness, which not only improves the quality of the film layer, but also improves the compatibility between the formation process of the memory array and the formation process of the peripheral circuit, thereby improving the reliability of the ultimately formed memory. BRIEF DESCRIPTION OF THE DRAWINGS

[0042] Figure 1 A schematic flow chart of a method for forming a semiconductor structure according to an embodiment of the present disclosure;

[0043] Figures 2 to 13 A schematic structural diagram of a semiconductor structure forming process according to an embodiment of the present disclosure;

[0044] Figure 14 A top view of a semiconductor structure provided in an embodiment of the present disclosure. DETAILED DESCRIPTION

[0045] Exemplary embodiments of the present disclosure will be described in more detail below with reference to the accompanying drawings. Although exemplary embodiments of the present disclosure are shown in the accompanying drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the specific embodiments described herein. Instead, these embodiments are provided to enable a more thorough understanding of the present disclosure and to fully convey the scope of the present disclosure to those skilled in the art.

[0046] In the following description, numerous specific details are provided to provide a more thorough understanding of the present disclosure. However, it will be apparent to those skilled in the art that the present disclosure can be practiced without one or more of these details. In other instances, certain technical features known in the art are not described to avoid confusion with the present disclosure; that is, all features of actual embodiments are not described herein, nor are well-known functions and structures described in detail.

[0047] In the drawings, like reference numerals refer to like elements throughout.

[0048] It should be understood that spatial relationship terms such as "under", "beneath", "below", "under", "above", "above", etc., may be used herein for convenience of description to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, the spatial relationship terms are intended to also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, then the elements or features described as "under the other elements" or "under it" or "under it" will be oriented as "on" the other elements or features. Therefore, the exemplary terms "under" and "under" can include both upper and lower orientations. The device can be oriented otherwise (rotated 90 degrees or other orientations) and the spatial description terms used herein are interpreted accordingly.

[0049] The purpose of the terms used herein is only to describe specific embodiments and is not intended to limit the present disclosure. When used herein, the singular forms "a", "an", and "the" are intended to include the plural forms, unless the context clearly indicates otherwise. It should also be understood that the terms "comprising" and / or "comprising", when used in this specification, determine the presence of the features, integers, steps, operations, elements and / or parts, but do not exclude the presence or addition of one or more other features, integers, steps, operations, elements, parts and / or groups. When used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0050] In a memory structure that includes a buried word line (BWL), a contact structure is required to lead the buried word line out. This contact structure is formed by forming a through-hole through the dielectric layer and exposing the buried word line after the memory cells in the memory array and the transistor structures in the peripheral circuits have been formed. The through-hole is then filled with a conductive material to allow the buried word line to be led out. However, because the end of the buried word line needs to be connected to the contact structure that leads out the buried word line, there is a height difference between the end of the mask word line and the rest of the mask word line. This also creates a height difference between the thin films subsequently formed on the mask word line. This height difference can adversely affect these thin films in subsequent manufacturing processes, affecting product yield.

[0051] In order to solve the above-mentioned problems, the present disclosure proposes the following embodiments.

[0052] First, the present disclosure provides a method for forming a semiconductor structure. Figure 1 A schematic diagram of a process for forming a semiconductor structure according to an embodiment of the present disclosure is shown in FIG. Figure 1As shown, the method for forming a semiconductor structure includes the following steps:

[0053] Step S10: Providing a substrate, the substrate comprising an array region, a lead-out region, and a peripheral region sequentially arranged along a first direction; the array region and the lead-out region comprising a plurality of word line trenches extending along the first direction and arranged along a second direction; the first direction and the second direction intersect and are both perpendicular to a thickness direction of the substrate;

[0054] Step S20: forming a conductive structure in each of the word line trenches; a top surface of the conductive structure is lower than a top surface of the peripheral region;

[0055] Step S30: forming a barrier layer covering at least the conductive structure and the peripheral region;

[0056] Step S40: performing a first etching to remove a portion of the barrier layer located directly above the array region;

[0057] Step S50: performing a second etching process to remove the remaining barrier layer located directly above the array region and a portion of the barrier layer located directly above the lead-out region.

[0058] Figures 2 to 13 This is a schematic diagram of the formation process of the semiconductor structure. Figure 1 and Figures 2 to 13 The method for forming the semiconductor structure provided by the embodiment of the present disclosure is described in detail.

[0059] Combined with reference Figure 2 and Figure 3 , Figure 3 for Figure 2 In the cross-sectional view along line AA', step S10 is performed: providing a substrate, the substrate including an array region a, a lead region b and a peripheral region c sequentially arranged along a first direction, the array region a and the lead region b including a plurality of word line trenches 201 extending along the first direction and arranged along a second direction.

[0060] In the embodiment of the present disclosure, the first direction and the second direction intersect and are both perpendicular to the thickness direction of the substrate. Here, the first direction may be the X direction, the second direction may be the Y direction, and the thickness direction of the substrate may be the Z direction.

[0061] In some embodiments, the specific process of providing a substrate may be: providing a substrate 101; forming an array-arranged active area 102 and a first isolation structure 103 located between the active areas 102 in the substrate 101 in the array area a, and forming a second isolation structure 104 in the substrate 101, wherein the first part 1041 of the second isolation structure is located in the lead-out area b, and the second part 1042 of the second isolation structure is located in the peripheral area c; etching the active area 102, the first isolation structure 103, and the first part 1041 of the second isolation structure along the thickness direction of the substrate to form a plurality of word line grooves 201 in the substrate.

[0062] In some specific examples, the substrate 101 can be a single-element semiconductor material substrate (for example, a silicon substrate, a germanium substrate, etc.), a compound semiconductor material substrate (for example, a germanium-silicon substrate, etc.), or a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc.

[0063] In some embodiments, the process of forming the active region 102, the first isolation structure 103, and the second isolation structure 104 in the substrate 101 may be: etching the substrate 101 to form an isolation trench, defining a region for forming the active region, and filling the isolation trench with a dielectric material to form the first isolation structure 103 and the second isolation structure 104, as shown in FIG. Figure 3 As shown, the first isolation structure 103 includes a first sub-isolation structure 1031 and a second sub-isolation structure 1032 . The size of the first sub-isolation structure 1031 in the first direction is larger than the size of the second sub-isolation structure 1032 in the first direction.

[0064] In some specific examples, the materials of the first isolation structure 103 and the second isolation structure 104 include, but are not limited to, silicon oxide.

[0065] In some specific examples, the active region formed by the isolation trench can be doped using an ion implantation process to form active regions 102. Active regions 102 extend along a third direction and are arranged in an array along the first direction and the second direction. Here, the third direction is not perpendicular to the first direction or the second direction. The portion of active region 102 directly below wordline trench 201 constitutes a channel region, and the portions on either side of the channel region in the third direction constitute a source region and a drain region, respectively.

[0066] It should be noted that in order to observe the relative positions of the active area 102 and the word line trench 201, Figure 2 This is a top view with some structures in the substrate omitted.

[0067] Combined with reference Figure 4 and Figure 5 , performing step 20 to form a conductive structure 204 in each word line trench 201 .

[0068] In some embodiments, before forming the conductive structure 204 in the word line trench 201 , the method for forming the semiconductor structure further includes: forming a gate dielectric layer 202 at the bottom of the word line trench 201 .

[0069] In some specific examples, the gate dielectric layer 202 may be formed of or include at least one of a high-k dielectric material, silicon oxide, silicon nitride, and silicon oxynitride. The high-k dielectric material may include at least one of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0070] In some embodiments, reference Figure 4 , a conductive layer 203 can be formed to fill the word line trench 201 and cover the top surfaces of the array region a, the lead region b and the peripheral region c, and then the conductive layer 203 is etched to remove part of the conductive layer 203, and a conductive layer 203 can be formed as shown in FIG. Figure 5 As shown in the conductive structure 204 , the conductive structure 204 is located directly above the array region a and the lead-out region b, and the top surface of the conductive structure 204 is lower than the top surface of the peripheral region c.

[0071] In some specific examples, the material of the conductive structure 204 can be one of a doped semiconductor material (e.g., doped silicon, doped germanium, etc.), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.), a metal material (e.g., tungsten, titanium, tantalum, etc.) and a metal semiconductor compound (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.).

[0072] Reference Figure 6 , performing step S30 to form a barrier layer 301 covering at least the conductive structure 204 and the peripheral region c.

[0073] In some specific examples, the material of the barrier layer 301 includes, but is not limited to, silicon nitride.

[0074] In some embodiments, continue to refer to Figure 6 The method for forming the semiconductor structure further includes: forming a photoresist layer 302 covering the barrier layer 301, and removing a portion of the photoresist layer 302 using a photolithography process to expose the barrier layer 301 directly above the array area a, with the remaining photoresist layer 302 covering the lead-out area b and the peripheral area c.

[0075] In some embodiments, in conjunction with reference Figure 7 and Figure 8The method for forming the semiconductor structure further includes: etching the barrier layer 301 located directly above the array region a using the photoresist layer 302 as a mask to remove the barrier layer 301 located directly above the array region a and expose the conductive structure 204 located directly above the array region a; then etching a portion of the conductive structure 204 located directly above the array region a using the remaining barrier layer 301 as a mask, wherein the remaining conductive structure 204′ located directly above the array region a and the gate dielectric layer 202 form a word line structure 205, and the remaining conductive structure located directly above the lead-out region b forms a word line lead-out structure 206.

[0076] In the embodiment of the present disclosure, the top surface of the wordline lead-out structure 206 is higher than the top surface of the wordline structure 205. When a contact structure connected to the wordline structure 205 is subsequently formed, the contact structure can be formed directly above the lead-out region b and connected to the wordline lead-out structure 206, thereby connecting to the wordline structure 205 through the wordline lead-out structure 206. Before forming the contact structure, a through-hole is first formed through the dielectric layer. The through-hole only needs to expose the wordline lead-out structure 206. This can reduce the aspect ratio of the through-hole, reduce the difficulty of etching the through-hole, and enable the bottom of the through-hole to have a larger radial dimension. In other words, a larger contact area can be provided between the contact structure and the wordline lead-out structure 206, thereby reducing the contact resistance between the contact structure and the wordline lead-out structure 206 and improving the reliability of the wordline lead-out.

[0077] In the above embodiment, if Figure 8 As shown, after the word line structure 205 and the word line lead-out structure 206 are formed, there is a remaining barrier layer 301 directly above the lead-out area b and the peripheral area c, while the barrier layer 301 directly above the array area a has been removed. The barrier layer 301 directly above the lead-out area b and the peripheral area c will form a height difference with the substrate between the two adjacent word line structures 205 located directly above the array area a, and the height difference ranges from 20nm to 25nm. In this case, when a film layer that simultaneously covers the array area a, the lead-out area b and the peripheral area c needs to be formed in a subsequent process step, a height difference may also be formed on the surface of the film layer. When the film layer needs to be polished or etched subsequently, the height difference on the surface of the film layer may cause the uniformity of the polishing or etching to be reduced, which may affect the quality of the film layer and may cause the yield of the product to be reduced.

[0078] In other embodiments, in conjunction with reference Figure 7 and Figure 9 In order to avoid the above problems, after removing the barrier layer 301 located directly above the array area a, a grinding process can be used to remove part of the barrier layer 301 located directly above the lead-out area b and the barrier layer 301 located directly above the peripheral area c.

[0079] In some specific examples, the barrier layer 301 can be polished by a chemical mechanical polishing (CMP) process to remove a portion of the barrier layer 301 located directly above the lead-out area b and the barrier layer 301 located directly above the peripheral area c, and to make the top surface of the remaining barrier layer 301 located directly above the lead-out area b flush with the top surface of the peripheral area c and the top surface of the substrate between the two adjacent conductive structures 204 located directly above the array area a, thereby avoiding a height difference between the array area a, the lead-out area b and the peripheral area c.

[0080] However, in the above embodiment, before the barrier layer 301 is ground, there is a height difference between the top surface of the barrier layer 301 located directly above the lead-out area b and the peripheral area c and the top surface of the array area a, and there is also a height difference between the top surface of the conductive structure 204 located directly above the array area a and the top surface of the array area a and the top surface of the peripheral area c. Therefore, the grinding can only stop on an uneven plane, which may reduce the reliability of the grinding process and cause damage to other structures besides the barrier layer 301.

[0081] Therefore, in the embodiments of the present disclosure, Figure 6 and Figure 10 After executing step S30, step S40 is executed to perform a first etching to remove a portion of the blocking layer 301 located directly above the array region a.

[0082] In some specific examples, after the first etching is performed, the thickness of the remaining barrier layer 301 located directly above the array region a is less than or equal to the thickness of the barrier layer 301 located directly above the peripheral region c.

[0083] In some specific examples, the first etching may be dry etching, including but not limited to plasma etching (PE), sputtering etching (SE), ion beam etching (IBE), and reactive ion etching (RIE).

[0084] In some embodiments, reference Figure 11 After performing the first etching, the photoresist layer 302 is removed.

[0085] Reference Figure 12, step S50 is performed to perform a second etching to remove the remaining barrier layer 301 directly above the array region a and a portion of the barrier layer 301 directly above the lead-out region b. Specifically, the second etching also includes removing the barrier layer 301 directly above the peripheral region c, so that the top surface of the remaining barrier layer 301 directly above the lead-out region b is flush with the top surface of the peripheral region c.

[0086] In a specific example, after performing the first etching, the thickness of the remaining barrier layer 301 located directly above the array area a is equal to the thickness of the barrier layer 301 located directly above the peripheral area c. In this case, the second etching can be a wet etching, which simultaneously removes the remaining barrier layer 301 located directly above the array area a and the barrier layer 301 located directly above the peripheral area c by controlling the etching time, and removes part of the barrier layer 301 located directly above the lead-out area b, and the amount of reduction in the thickness of the barrier layer 301 located directly above the lead-out area b is equal to the thickness of the barrier layer 301 located directly above the peripheral area c, so that the top surface of the remaining barrier layer 301 directly above the lead-out area b is flush with the top surface of the peripheral area c.

[0087] In another specific example, after the first etching, the thickness of the remaining barrier layer 301 directly above the array region a is thinner than the thickness of the barrier layer 301 directly above the peripheral region c. In this case, the second etching process can be a directional dry etching process, thereby simultaneously removing the thicker barrier layer 301 directly above the peripheral region c and the remaining thinner barrier layer 301 directly above the array region a, while preventing over-etching of the peripheral region c. The top surface of the remaining barrier layer 301 directly above the lead-out region b is flush with the top surface of the peripheral region c. Here, the dry etching process includes but is not limited to reactive ion etching.

[0088] In some embodiments, when barrier layer 301 is formed by a deposition process, barrier layer 301 simultaneously covers array region a, lead-out region b, and peripheral region c. Performing a first etch specifically includes removing portions of barrier layer 301 on conductive structures 204 directly above array region a and portions of barrier layer 301 directly above array region a between adjacent conductive structures 204, such that the top surfaces of the remaining barrier layer 301 on conductive structures 204 directly above array region a and the remaining barrier layer 301 directly above array region a between adjacent conductive structures 204 are lower than the top surfaces of barrier layer 301 directly above peripheral region c and lead-out region b. Performing a second etch specifically includes removing the remaining barrier layer 301 on conductive structures 204 directly above array region a, the remaining barrier layer 301 directly above array region a between adjacent conductive structures 204, portions of barrier layer 301 directly above lead-out region b, and the barrier layer 301 directly above peripheral region c.

[0089] In the embodiments of the present disclosure, the deposition process includes but is not limited to chemical vapor deposition (CVD), low pressure chemical vapor deposition (LPCVD), plasma enhanced chemical vapor deposition (PECVD), physical vapor deposition (PVD) and atomic layer deposition (ALD).

[0090] In some embodiments, reference Figure 13 The method for forming a semiconductor structure further includes: after performing the second etching, removing a portion of the conductive structure 204 located directly above the array area a, and the remaining conductive structure 204' located directly above the array area a and the gate dielectric layer 202 form a word line structure 205. During this process, the conductive structure located directly above the lead-out area b is covered by the remaining barrier layer 301. Therefore, when the portion of the conductive structure located directly above the array area a is removed, the conductive structure located directly above the lead-out area b is not removed and forms a word line lead-out structure 206. The top surface of the word line lead-out structure 206 is higher than the top surface of the word line structure 205.

[0091] In the embodiment of the present disclosure, a word line lead-out structure 206 connected to the word line structure 205 is formed, and the top surface of the word line lead-out structure 206 is higher than the top surface of the word line structure 205. When a contact structure connected to the word line structure 205 is subsequently formed, the contact structure can be formed directly above the lead-out region b and connected to the word line lead-out structure 206, so as to be connected to the word line structure 205 through the word line lead-out structure 206. The through hole penetrating the dielectric layer only needs to expose the word line lead-out structure 206. As a result, the aspect ratio of the through hole can be reduced, the difficulty of etching the through hole can be reduced, and the bottom of the through hole can have a larger radial dimension, that is, the contact structure and the word line lead-out structure 206 can have a larger contact area, thereby reducing the contact resistance between the contact structure and the word line lead-out structure 206 and improving the reliability of the word line lead-out.

[0092] In the embodiment of the present disclosure, a portion of the barrier layer 301 located directly above the array area a is first removed by performing a first etching step, and then a second etching step is performed so that the barrier layer 301 located directly above the array area a and the barrier layer 301 located directly above the peripheral area c can be removed simultaneously. This allows the barrier layer 301 located directly above the lead-out area b to be retained so that the conductive structure covered by the portion of the barrier layer 301 constitutes the word line lead-out structure 206, while avoiding the formation of a height difference between the array area a and the lead-out area b and the peripheral area c. As a result, the film layer formed in subsequent process steps and covering the array area a, the lead-out area b and the peripheral area c simultaneously has a higher flatness, which not only improves the quality of the film layer, but also improves the compatibility between the formation process of the memory array and the formation process of the peripheral circuit, thereby improving the reliability of the memory finally formed.

[0093] Based on a concept similar to the above-mentioned method for forming a semiconductor structure, an embodiment of the present disclosure further provides a semiconductor structure, which can be obtained by the method for forming a semiconductor structure in any of the above-mentioned embodiments. Figure 13 and Figure 14 is a schematic structural diagram of the semiconductor structure. Figure 13 for Figure 14 Cross-section along line AA'.

[0094] It should be noted that, in order to observe the relative positions of the active area 102 and the word line structure 205, Figure 14 It is a top view after omitting part of the structure in the semiconductor structure.

[0095] Combined with reference Figure 13 and Figure 14 The semiconductor structure includes: a substrate, the substrate including an array region a, a lead region b, and a peripheral region c arranged in sequence along a first direction; a word line structure 205 located directly above the array region a; the word line structure 205 extends along the first direction and is arranged along a second direction; a word line lead structure 206 located directly above the lead region b; a top surface of the word line lead structure 206 is higher than a top surface of the word line structure 205; a barrier layer 301 located directly above the word line lead structure 206; a top surface of the barrier layer 301 is flush with a top surface of the peripheral region c.

[0096] In the embodiment of the present disclosure, the first direction and the second direction intersect and are both perpendicular to the thickness direction of the substrate. Here, the first direction may be the X direction, the second direction may be the Y direction, and the thickness direction of the substrate may be the Z direction.

[0097] In some specific examples, the material of the barrier layer includes, but is not limited to, silicon nitride.

[0098] In some embodiments, the word line structure 205 includes a conductive structure 204 ′ and a gate dielectric layer 202 located directly above the array region a; and the word line lead-out structure 206 is connected to the conductive structure 204 ′ in the word line structure 205 .

[0099] In some specific examples, the material of the gate dielectric layer 202 may be at least one of a high-k dielectric material, silicon oxide, silicon nitride, and silicon oxynitride. The high-k dielectric material may include at least one of hafnium oxide, hafnium silicon oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, and lead zinc niobate.

[0100] In some specific examples, the word line lead-out structure 206 is made of the same material as the conductive structure 204' in the word line structure 205, and can be one of a doped semiconductor material (e.g., doped silicon, doped germanium, etc.), a conductive metal nitride (e.g., titanium nitride, tantalum nitride, etc.), a metal material (e.g., tungsten, titanium, tantalum, etc.), and a metal semiconductor compound (e.g., tungsten silicide, cobalt silicide, titanium silicide, etc.).

[0101] In some embodiments, array region a includes active regions 102 arranged in an array and first isolation structures 103 located between the active regions 102. The active regions 102 extend along a third direction and are arranged in an array along the first and second directions. Here, the third direction is not perpendicular to the first or second directions. The wordline structures 205 serve as gates and, together with the multiple active regions 102 arranged along the first direction, form multiple transistor structures arranged along the first direction. The portions of the active regions 102 directly below the wordline structures 205 constitute the channel regions of the transistor structures. The active regions 102 located on either side of the channel regions in the third direction respectively constitute the source and drain regions of the transistor structures.

[0102] In some embodiments, the substrate further includes a second isolation structure 104 , the first portion 1041 of the second isolation structure is located in the lead-out region b, and the second portion 1042 of the second isolation structure is located in the peripheral region c; the top surface of the second portion 1042 is higher than the top surface of the first portion 1041 .

[0103] In some embodiments, the first isolation structure 103 includes a first sub-isolation structure 1031 and a second sub-isolation structure 1032; the size of the first sub-isolation structure 1031 in the first direction is larger than the size of the second sub-isolation structure 1032 in the first direction, the first sub-isolation structure 1031 may include two dielectric material layers, and the second sub-isolation structure 1032 may include only one dielectric material layer; the size of the second isolation structure 104 in the first direction is larger than the size of the first sub-isolation structure 1031 in the first direction, and the second isolation structure 104 may include three dielectric material layers.

[0104] In some specific examples, the materials of the first isolation structure 103 and the second isolation structure 104 may be one or more dielectric materials such as silicon oxide, silicon nitride, and silicon oxynitride.

[0105] In the embodiment of the present disclosure, a word line lead-out structure 206 connected to the word line structure 205 is provided at the end thereof, and the top surface of the word line lead-out structure 206 is higher than the top surface of the word line structure 205. When a contact structure connected to the word line structure 205 is subsequently formed, the contact structure can be formed directly above the lead-out region b and connected to the word line lead-out structure 206, so as to be connected to the word line structure 205 through the word line lead-out structure 206. The through hole penetrating the dielectric layer only needs to expose the word line lead-out structure 206. Thus, the aspect ratio of the through hole can be reduced, the difficulty of etching the through hole can be reduced, and the bottom of the through hole can have a larger radial dimension, that is, the contact structure and the word line lead-out structure 206 can have a larger contact area, thereby reducing the contact resistance between the contact structure and the word line lead-out structure 206 and improving the reliability of the word line lead-out.

[0106] In the embodiment of the present disclosure, the top surface of the array area a, the top surface of the barrier layer 301 located directly above the lead-out area b, and the top surface of the peripheral area c are flush, which is conducive to the subsequent formation of other film layer structures on the semiconductor structure. It can not only improve the quality of the film layer, but also improve the compatibility of the memory array and the peripheral circuit, thereby improving the reliability of the memory finally formed.

[0107] The methods disclosed in the several method embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new method embodiments.

[0108] The features disclosed in the several device embodiments provided in this disclosure can be arbitrarily combined without conflict to obtain new device embodiments.

[0109] The above description is merely a specific embodiment of the present disclosure, but the scope of protection of the present disclosure is not limited thereto. Any changes or substitutions that can be easily conceived by a person skilled in the art within the technical scope disclosed in this disclosure should be included in the scope of protection of the present disclosure. Therefore, the scope of protection of the present disclosure should be based on the scope of protection of the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising an array region, a lead-out region, and a peripheral region sequentially arranged along a first direction; the array region and the lead-out region comprising a plurality of word line trenches extending along the first direction and arranged along a second direction; The first direction and the second direction intersect and are both perpendicular to the thickness direction of the substrate; forming a conductive structure in each of the word line trenches; The top surface of the conductive structure is lower than the top surface of the peripheral region; forming a barrier layer covering at least the conductive structure and the peripheral region; Performing a first etching step to remove a portion of the barrier layer located directly above the array region; Performing a second etching to remove the remaining barrier layer located directly above the array region and a portion of the barrier layer located directly above the lead-out region; The performing of the second etching comprises: The barrier layer located directly above the peripheral region is removed, and a top surface of the remaining barrier layer located directly above the lead-out region is flush with a top surface of the peripheral region.

2. The method for forming a semiconductor structure according to claim 1, wherein: After performing the first etching, the thickness of the remaining barrier layer located directly above the array region is less than or equal to the thickness of the barrier layer located directly above the peripheral region.

3. The method for forming a semiconductor structure according to claim 1, wherein: The forming of a barrier layer at least covering the conductive structure and the peripheral region comprises: forming a barrier layer covering the array region, the lead-out region, and the peripheral region; The performing the first etching comprises: removing a portion of the barrier layer on the conductive structure directly above the array region and a portion of the barrier layer directly above the array region between adjacent conductive structures, so that a top surface of the remaining barrier layer on the conductive structure directly above the array region and a top surface of the remaining barrier layer directly above the array region between adjacent conductive structures are both lower than a top surface of the barrier layer directly above the peripheral region and the lead-out region; The performing the second etching comprises: The remaining barrier layer on the conductive structure directly above the array area, the remaining barrier layer directly above the array area between adjacent conductive structures, part of the barrier layer directly above the lead-out area, and the barrier layer directly above the peripheral area are removed.

4. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the semiconductor structure further includes: Before performing the first etching, forming a photoresist layer covering the barrier layer; removing a portion of the photoresist layer by a photolithography process to expose the barrier layer directly above the array region; The performing the first etching comprises: removing the portion of the barrier layer exposed directly above the array region; The method for forming the semiconductor structure further includes: After performing the first etching, the photoresist layer is removed.

5. The method for forming a semiconductor structure according to claim 1, wherein: The providing of a substrate comprises: providing a substrate; Active areas arranged in an array and a first isolation structure located between the active areas are formed in the substrate of the array area, and a second isolation structure is formed in the substrate; a first portion of the second isolation structure is located in the lead-out area, and a second portion of the second isolation structure is located in the peripheral area; The active area, the first isolation structure, and the first portion of the second isolation structure are etched along a thickness direction of the substrate to form the word line trench.

6. The method for forming a semiconductor structure according to claim 1, wherein: The method for forming the semiconductor structure further includes: Before forming the conductive structure in the word line trench, a gate dielectric layer is formed at the bottom of the word line trench.

7. The method for forming a semiconductor structure according to claim 6, wherein: The method for forming the semiconductor structure further includes: After the second etching is performed, a portion of the conductive structure located directly above the array area is removed, and the remaining conductive structure located directly above the array area and the gate dielectric layer constitute a word line structure; the conductive structure located directly above the lead-out area constitutes a word line lead-out structure; and the top surface of the word line lead-out structure is higher than the top surface of the word line structure.

8. A semiconductor structure, characterized in that include: A substrate comprising an array region, a lead-out region, and a peripheral region sequentially arranged along a first direction; a word line structure located directly above the array region; The word line structure extends along the first direction and is arranged along the second direction; the first direction and the second direction intersect and are both perpendicular to the thickness direction of the substrate; A word line lead-out structure located directly above the lead-out region; a top surface of the word line lead-out structure being higher than a top surface of the word line structure; A barrier layer is located directly above the word line lead-out structure; a top surface of the barrier layer is flush with a top surface of the peripheral region; and the barrier layer is not located directly above the array region and the peripheral region.

9. The semiconductor structure according to claim 8, wherein: The array area includes active areas arranged in an array and a first isolation structure located between the active areas; the substrate also includes a second isolation structure, a first portion of the second isolation structure is located in the lead-out area, and a second portion of the second isolation structure is located in the peripheral area; the top surface of the second portion is higher than the top surface of the first portion.

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