Semiconductor structure and method of forming the same

Abstract

The present disclosure relates to the technical field of semiconductor technology, and discloses a semiconductor structure and a forming method thereof. The forming method comprises the following steps: providing a substrate, wherein the substrate comprises a base and an insulating layer, the base comprises an array area and a mark area, the array area is provided with a shallow trench isolation structure and an active area, and the insulating layer covers the base; forming a bit line contact hole; sequentially forming a first conductive layer, a second conductive layer, an etching stop layer and an insulating covering layer on a side of the insulating layer away from the base, and the first conductive layer fills the bit line contact hole; etching the insulating covering layer to form insulating parts in the array area and the mark area respectively; and etching the etching stop layer, the second conductive layer and the first conductive layer with the insulating parts as masks to form a bit line structure in the array area and a mark pattern in the mark area. The forming method disclosed by the present disclosure can reduce structural defects and improve product yield.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, and in particular to a semiconductor structure and a method for forming the same. Background Art

[0002] Dynamic Random Access Memory (DRAM) is widely used in mobile devices such as mobile phones and tablets due to its advantages such as small size, high integration, and fast transmission speed. As a core component of DRAM, the bitline structure plays a crucial role in the device's electrical performance. However, the manufacturing process of the bitline structure is prone to structural defects due to process technology, resulting in low product yield.

[0003] It should be noted that the information disclosed in the above background technology section is only used to enhance the understanding of the background of the present disclosure, and therefore may include information that does not constitute prior art known to ordinary technicians in the field. Summary of the Invention

[0004] In view of this, the present disclosure provides a semiconductor structure and a method for forming the same, which can reduce structural defects and improve product yield.

[0005] According to one aspect of the present disclosure, a method for forming a semiconductor structure is provided, comprising:

[0006] Providing a substrate, the substrate comprising a base and an insulating layer, the base comprising an array region and a marking region, the array region being provided with a shallow trench isolation structure and a plurality of active regions separated by the shallow trench isolation structure, the insulating layer covering the shallow trench isolation structure, the active regions, and the marking region;

[0007] Etching the active area and the insulating layer located on top of the active area to form a bit line contact hole;

[0008] forming a first conductive layer, a second conductive layer, an etching stop layer and an insulating cover layer in sequence on a side of the insulating layer away from the substrate, wherein the first conductive layer fills the bit line contact hole;

[0009] The insulating cover layer is etched to form insulating portions in the array region and the mark region, respectively, wherein an orthographic projection of the insulating portion in the array region on the substrate at least partially overlaps with the active region in the bit line contact hole; the etching rate of the etch stop layer is lower than the etching rate of the insulating cover layer;

[0010] The etching stop layer, the second conductive layer, and the first conductive layer are etched using the insulating portion as a mask to form a bit line structure in the array region and a mark pattern in the mark region.

[0011] In an exemplary embodiment of the present disclosure, an etching selectivity ratio between the insulating capping layer and the etching stop layer is greater than 10:1.

[0012] In an exemplary embodiment of the present disclosure, the material of the etch stop layer is undoped silicon, and the material of the insulating cap layer is silicon nitride.

[0013] In an exemplary embodiment of the present disclosure, etching the insulating cover layer to form insulating portions in the array region and the mark region respectively includes:

[0014] forming a mask layer on a surface of the insulating cover layer;

[0015] Etching the mask layer to form mask structures in the array area and the mark area, respectively, wherein an orthographic projection of the mask structure in the array area on the substrate at least partially overlaps with the active area in the bit line contact hole;

[0016] The insulating cover layer is etched using the mask layer having the mask structure as a mask to form the insulating portions in the array region and the mark region respectively.

[0017] In an exemplary embodiment of the present disclosure, etching the etch stop layer, the second conductive layer, and the first conductive layer using the insulating portion as a mask to form a bit line structure in the array area and forming a mark pattern in the mark area includes:

[0018] etching the etch stop layer using the insulating portion as a mask until the second conductive layer is exposed;

[0019] The second conductive layer and the first conductive layer are etched using the structure formed by the insulating portion and the remaining etching stop layer as a mask to form a bit line structure in the array area and a mark pattern in the mark area.

[0020] In an exemplary embodiment of the present disclosure, the forming method further includes:

[0021] The width of the insulating portion in a direction parallel to the substrate is detected, and when the width is within a first preset deviation range, the etching stop layer, the second conductive layer, and the first conductive layer are etched using the insulating portion as a mask to form a bit line structure in the array area and a mark pattern in the mark area.

[0022] In an exemplary embodiment of the present disclosure, the forming method further includes:

[0023] Detecting widths of different film layers in the bit line structure in a direction parallel to the substrate, and feeding back a detection result to an etching machine for etching the etching stop layer, the second conductive layer and the first conductive layer when a width difference of different film layers in the bit line structure in a direction parallel to the substrate exceeds a second preset deviation range.

[0024] In an exemplary embodiment of the present disclosure, the substrate further comprises a peripheral region, the peripheral region is distributed side by side with the array region and the mark region, a normal projection of the etching stop layer on the substrate covers the array region, the peripheral region and the mark region.

[0025] Before forming the insulating cover layer, the forming method further comprises:

[0026] Removing the etching stop layer in the peripheral region;

[0027] After forming the insulating cover layer, the forming method further comprises:

[0028] Etching the insulating cover layer, the second conductive layer, the first conductive layer and the insulating layer in the peripheral region to form a gate structure.

[0029] In an exemplary embodiment of the present disclosure, the forming method further comprises:

[0030] Forming an isolation layer covering the sidewall and the top of the gate structure;

[0031] Forming an insulating material layer in the peripheral region outside the gate structure and the isolation layer, a surface of the insulating material layer is flush with a surface of the isolation layer on the top of the gate structure.

[0032] According to an aspect of the present disclosure, a semiconductor structure is provided, which is formed by the forming method of any one of the above semiconductor structures.

[0033] The disclosed semiconductor structure and method for forming the same, by disposing an etch stop layer beneath the insulating cover layer, allows the etching process to terminate at the etch stop layer when etching the insulating cover layer to form the insulating portion. This process does not damage the structure of the underlying second conductive layer, thereby avoiding uneven etching losses in different regions of the second conductive layer and helping to improve the uniformity of the critical dimensions of the resulting bitline structure. During subsequent etching of the second conductive layer, the second conductive layer can be etched through using a single etching process, avoiding the loading effect and necking caused by different etching steps, helping to improve the profile of the bitline structure and further enhancing the uniformity of the bitline structure. Furthermore, because the etch stop layer has a relatively low etching rate, the insulating portion formation process does not cause significant surface damage to the etch stop layer, allowing different regions of the etch stop layer to remain relatively flat. During subsequent etching of the etch stop layer, the second conductive layer, and the first conductive layer, the film layers in the array region and the mark region can be consumed simultaneously, reducing the probability of over-etching the mark region and helping to improve product yield.

[0034] It is to be understood that the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the disclosure. BRIEF DESCRIPTION OF THE DRAWINGS

[0035] The accompanying drawings are incorporated into and constitute a part of the specification, illustrate embodiments consistent with the present disclosure, and together with the specification, are used to explain the principles of the present disclosure. Obviously, the drawings described below are only some embodiments of the present disclosure, and those skilled in the art can derive other drawings based on these drawings without inventive effort.

[0036] Figure 1 Schematic diagram of the marking area in the related art.

[0037] Figure 2 Flowchart of a method for forming a semiconductor structure in an embodiment of the present disclosure.

[0038] Figure 3 Schematic diagram of the structure of the array area after completing step S120 in the embodiment of the present disclosure.

[0039] Figure 4 Schematic diagram of the marking area in an embodiment of the present disclosure.

[0040] Figure 5 Schematic diagram of the peripheral area in an embodiment of the present disclosure.

[0041] Figure 6 FIG. 1 is a schematic diagram of the array area after step S130 is completed in an embodiment of the present disclosure.

[0042] Figure 7A schematic view of the marking region after step S130 is completed in the embodiment of the present disclosure.

[0043] Figure 8 A schematic view of the mask material layer and the second photoresist layer in the embodiment of the present disclosure.

[0044] Figure 9 A schematic view of the gate structure in the embodiment of the present disclosure.

[0045] Figure 10 A schematic view of the isolation layer and the insulating material layer in the embodiment of the present disclosure.

[0046] Figure 11 A schematic view of the array region after step S140 is completed in the embodiment of the present disclosure.

[0047] Figure 12 A schematic view of the marking region after step S140 is completed in the embodiment of the present disclosure.

[0048] Figure 13 A schematic view of the array region after step S210 is completed in the embodiment of the present disclosure.

[0049] Figure 14 A schematic view of the marking region after step S210 is completed in the embodiment of the present disclosure.

[0050] Figure 15 A schematic view of the array region after step S220 is completed in the embodiment of the present disclosure.

[0051] Figure 16 A schematic view of the marking region after step S220 is completed in the embodiment of the present disclosure.

[0052] Figure 17 A schematic view of the array region after step S150 is completed in the embodiment of the present disclosure.

[0053] Figure 18 A schematic view of the marking region after step S150 is completed in the embodiment of the present disclosure.

[0054] Figure 19 A schematic view of the array region after step S310 is completed in the embodiment of the present disclosure.

[0055] Figure 20 A schematic view of the marking region after step S310 is completed in the embodiment of the present disclosure.

[0056] Explanation of reference signs:

[0057] 10. Marking pattern; 20. Substrate; 1. Substrate; 11. Base; 111. Shallow trench isolation structure; 112. Active area; 113. Bit line contact hole; 114. First doped region; 115. Channel region; 116. Second doped region; 12. Insulating layer; 121. First insulating layer; 122. Second insulating layer; 2. First conductive layer; 3. Second conductive layer; 31. Conductive barrier layer; 32. Conductive material layer; 4. Etching stop layer; 5. Insulating cover layer; 51. Insulating portion; 6. Mask layer; 61. Mask structure; 7. Mask material layer; 8. Second photoresist layer; 100. Bit line structure; 200. Marking pattern; 300. Gate structure; 400. Isolation layer; 401. First sub-film layer; 402. Second sub-film layer; 403. Third sub-film layer; 500. Insulating material layer; A. Array region; B. Marking region; C. Peripheral region DETAILED DESCRIPTION

[0058] Example embodiments will now be described more fully with reference to the accompanying drawings. However, the example embodiments can be implemented in many forms and should not be construed as limited to the embodiments set forth herein; rather, these embodiments are provided so that this disclosure will be thorough and complete and will fully convey the concepts of the example embodiments to those skilled in the art. Like reference numerals in the figures represent identical or similar structures, and thus their detailed descriptions will be omitted. Furthermore, the figures are merely schematic illustrations of the present disclosure and are not necessarily drawn to scale.

[0059] Although relative terms such as "upper" and "lower" are used in this specification to describe the relationship of one illustrated component to another, these terms are used herein for convenience only, such as in accordance with the orientation of the illustrations in the accompanying drawings. It will be understood that if the illustrated device were flipped upside down, the component described as "upper" would become the component "lower." When a structure is referred to as "on" another structure, this may mean that the structure is integrally formed with the other structure, that the structure is "directly" disposed on the other structure, or that the structure is "indirectly" disposed on the other structure via the other structure.

[0060] The terms "a", "an", "the", "said" and "at least one" are used to indicate the presence of one or more elements / components / etc.; the terms "including" and "having" are used to express open-ended inclusion and mean that additional elements / components / etc. may be present in addition to the listed elements / components / etc.; the terms "first" and "second" etc. are used only as labels and are not intended to limit the quantity of their objects.

[0061] Typically, a marking pattern 10 is formed simultaneously during the manufacturing process of the bitline structure (BL) of a dynamic random access memory (DRAM). The main process includes: forming a conductive layer for forming the bitline structure and the marking pattern 10 and an insulating layer covering the conductive layer on a substrate 20; etching the insulating layer and the conductive layer in steps to form the bitline structure and the marking pattern 10; however, in the process of etching the insulating layer, in order to ensure that the insulating layer is completely etched through, over-etching is performed for a certain period of time. During this process, it is inevitable that some areas of the conductive layer will be damaged. This process is superimposed on the subsequent process of forming the bitline contact structure, which may lead to the problem of inconsistent key dimensions of different areas of the final bitline structure; and in the subsequent process, the conductive layer needs to be etched again to form the bitline structure. In this way, the conductive layer undergoes two etching processes, and the etching load effect and necking phenomenon are more obvious, and the uniformity of the structural profile is poor. In addition, in the subsequent process of etching the conductive layer to form the bitline structure, the etching progress of different areas may be different due to the influence of the process technology (etching load effect or plasma), and the marking area is prone to over-etching (such as Figure 1 (As shown in area a in the middle), the structural defects are more obvious and the product yield is low.

[0062] Based on this, the present disclosure provides a method for forming a semiconductor structure. Figure 2 A flow chart showing a method for forming a semiconductor structure of the present disclosure is shown in FIG. Figure 2 As shown, the forming method includes steps S110 to S150, wherein:

[0063] Step S110, providing a substrate, wherein the substrate includes a base and an insulating layer, the base including an array region and a marking region, the array region being provided with a shallow trench isolation structure and a plurality of active regions separated by the shallow trench isolation structure, the insulating layer covering the shallow trench isolation structure, the active regions, and the marking region;

[0064] Step S120, etching the active area and the insulating layer located on top of the active area to form a bit line contact hole;

[0065] Step S130, forming a first conductive layer, a second conductive layer, an etch stop layer, and an insulating cover layer in sequence on a side of the insulating layer away from the substrate, wherein the first conductive layer fills the bit line contact hole;

[0066] Step S140, etching the insulating cover layer to form insulating portions in the array region and the mark region, respectively, wherein an orthographic projection of the insulating portion in the array region on the substrate at least partially overlaps with the active region in the bit line contact hole; the etching rate of the etch stop layer is lower than the etching rate of the insulating cover layer;

[0067] In step S150 , the etching stop layer, the second conductive layer, and the first conductive layer are etched using the insulating portion as a mask to form a bit line structure in the array region and a mark pattern in the mark region.

[0068] The disclosed method for forming a semiconductor structure, by disposing an etch stop layer beneath the insulating cover layer, allows the etching process to terminate at the etch stop layer when etching the insulating cover layer to form the insulating portion. This process does not damage the structure of the underlying second conductive layer, thereby avoiding uneven etching losses in different regions of the second conductive layer and helping to improve the uniformity of the critical dimensions of the resulting bitline structure. During subsequent etching of the second conductive layer, the second conductive layer can be etched through using a single etching process, avoiding the loading effect and necking caused by different etching steps, helping to improve the profile of the bitline structure and further enhancing the uniformity of the bitline structure. Furthermore, because the etch stop layer has a relatively low etching rate, the insulating portion formation process does not cause significant surface damage to the etch stop layer, allowing different regions of the etch stop layer to remain relatively flat. During subsequent etching of the etch stop layer, the second conductive layer, and the first conductive layer, the film layers in the array region and the mark region can be consumed simultaneously, reducing the probability of over-etching the mark region and helping to improve product yield.

[0069] The following is a detailed description of the steps and details of the method for forming a semiconductor structure disclosed herein:

[0070] like Figure 2 As shown, in step S110, a substrate is provided, wherein the substrate includes a base and an insulating layer, the base includes an array area and a marking area, a shallow trench isolation structure and a plurality of active areas separated by the shallow trench isolation structure are provided in the array area, and the insulating layer covers the shallow trench isolation structure, the active area and the marking area.

[0071] like Figure 3 and Figure 4 As shown, the substrate 11 can be a flat plate structure, which can be rectangular, circular, elliptical, polygonal or irregular in shape, and its material can be a semiconductor material, for example, its material can be silicon, but is not limited to silicon or other semiconductor materials. No special limitation is made to the shape and material of the substrate 11.

[0072] In some embodiments of the present disclosure, please continue to refer to Figure 3 and Figure 4 As shown, the substrate 11 may include an array area A and a marking area B. The marking area B may be located on the periphery of the array area A, and the marking area B may surround the outer periphery of the array area A. For example, the array area A may be a circular area, a rectangular area, or an irregular pattern area. Of course, it may also be an area of ​​other shapes, which is not particularly limited here. The marking area B may be an annular area and may surround the outer periphery of the array area A. It may be a circular area, a rectangular area, or an annular area of ​​other shapes, which are not listed here one by one. The array area A can be used to form a capacitor array, a transistor array, a word line structure and a bit line structure connecting transistors and capacitors, and the marking area B can be used to form a marking pattern, which can be used as a position mark during the process.

[0073] In some embodiments of the present disclosure, the substrate 11 may be a silicon substrate, and a shallow trench isolation structure 111 is formed within the array region A of the substrate 11. The shallow trench isolation structure 111 can be formed by forming a trench in the substrate 11 and then filling the trench with an isolation material layer. The material of the shallow trench isolation structure 111 may include silicon nitride or silicon oxide, etc., which are not particularly limited here. The cross-sectional shape of the shallow trench isolation structure 111 can be set according to actual needs. The shallow trench isolation structure 111 can separate a plurality of active areas 112 on the substrate 11.

[0074] In an exemplary embodiment of the present disclosure, Figure 5 As shown, the substrate 11 may further include a peripheral region C, which may be arranged side by side with the array region A and the marking region B. For example, the peripheral region C may be arranged adjacent to the array region A, surrounding the outer periphery of the array region A, and the marking region B may be located on a side of the peripheral region C away from the array region A. The peripheral region C may be used to form word line contact plugs and peripheral transistors. In some embodiments of the present disclosure, the peripheral region C may include a first doped region 114, a channel region 115, and a second doped region 116, which are arranged adjacent to each other in sequence.

[0075] The insulating layer 12 can conformally cover the surface of the substrate 11. It can be a thin film formed on the substrate 11 or a coating formed on the substrate 11. The specific form of the insulating layer 12 is not specifically limited herein. For example, the insulating layer 12 can be formed on the surface of the substrate 11 by chemical vapor deposition, physical vapor deposition or atomic layer deposition. Of course, the insulating layer 12 can also be formed by other methods. The formation method of the insulating layer 12 is not specifically limited herein. The insulating layer 12 can be a single-layer film structure or a composite film structure composed of multiple film layers. The specific form of the insulating layer 12 is not specifically limited herein. In some embodiments of the present disclosure, the insulating layer 12 may include a first insulating layer 121 and a second insulating layer 122, wherein the first insulating layer 121 may cover the surface of the shallow trench isolation structure 111, each active area 112 and the marking area B, and the second insulating layer 122 may cover the surface of the first insulating layer 121, and the end of the second insulating layer 122 is flush with the end of the first insulating layer 121. The first insulating layer 121 and the second insulating layer 122 are made of different materials. For example, the first insulating layer 121 may be made of silicon oxide, and the second insulating layer 122 may be made of silicon nitride.

[0076] like Figure 2 As shown, in step S120 , the active area 112 and the insulating layer 12 located on the top of the active area 112 are etched to form a bit line contact hole 113 .

[0077] A photoresist layer can be formed on the surface of the insulating layer 12 by spin coating or other methods. The material of the photoresist layer can be either positive or negative photoresist, without particular limitation herein. The photoresist layer is exposed using a mask, the pattern of which can match the desired pattern of the bitline contact holes 113. The exposed photoresist layer can then be developed to form a plurality of spaced-apart developed areas, each of which can expose the surface of the insulating layer 12. The developed areas can be circular or rectangular in shape parallel to the substrate 11, with their orthographic projections on the substrate 11 at least partially overlapping with the active area 112.

[0078] The active area 112 and the insulating layer 12 located on top of the active area 112 can be etched in each developing area by an isotropic etching process. In this process, the insulating layer 12 can be penetrated and the height of the top of the active area 112 opposite the developing area can be reduced. The hole segment formed by the recessed portion in the active area 112 after etching and the through hole in the insulating layer 12 corresponding to the recessed portion can be used as the bit line contact hole 113. The structure after completing step S120 in the embodiment of the present disclosure is as follows: Figure 3 shown.

[0079] like Figure 2As shown, in step S130 , a first conductive layer 2 , a second conductive layer 3 , an etching stop layer 4 and an insulating cover layer 5 are sequentially formed on a side of the insulating layer 12 away from the substrate 11 , and the first conductive layer 2 fills the bit line contact hole 113 .

[0080] See Figure 6 and Figure 7 As shown, the first conductive layer 2, the second conductive layer 3, the etch stop layer 4, and the insulating cover layer 5 can be stacked and distributed in sequence along a direction perpendicular to the substrate 11. In some embodiments of the present disclosure, the material of the first conductive layer 2 can be doped polysilicon, and the first conductive layer 2 can be formed on the surface of the insulating layer 12 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. During this process, the first conductive layer 2 can cover the entire surface of the insulating layer 12 and can fill the bit line contact holes 113.

[0081] The second conductive layer 3 can be a single film layer or a multi-layer film layer, which is not specifically limited here. Optionally, the second conductive layer 3 can be a composite film layer structure composed of multiple film layers. For example, the second conductive layer 3 can include a conductive barrier layer 31 and a conductive material layer 32, wherein the conductive barrier layer 31 covers the entire surface of the first conductive layer 2, and the conductive material layer 32 is located on the surface of the conductive barrier layer 31; the material of the conductive barrier layer 31 can be titanium nitride, and the material of the conductive material layer 32 can be tungsten. The conductive barrier layer 31 can prevent the metal ions in the conductive material layer 32 from diffusing into the first conductive layer 2, which helps to improve the stability of the device; at the same time, the resistance of the conductive material layer 32 is relatively small, which helps to improve the conductive performance.

[0082] In some embodiments of the present disclosure, the material of the etch stop layer 4 may be an insulating material. For example, the material of the etch stop layer 4 is undoped silicon, for example, it may be undoped single crystal silicon or undoped polycrystalline silicon. Compared with doped silicon, undoped silicon can reduce the resistance and parasitic capacitance of the subsequent bit line structure. The thickness of the etch stop layer 4 may be less than the thickness of the insulating cover layer 5, and its thickness may be greater than one-fifteenth of the thickness of the insulating cover layer 5. The etch stop layer 4 may be formed on the surface of the second conductive layer 3 by chemical vapor deposition, physical vapor deposition or atomic layer deposition. Of course, the etch stop layer 4 may also be formed by other methods. The formation method of the etch stop layer 4 is not specifically limited here. It should be noted that during the manufacturing process, for the convenience of the process, the etch stop layer 4 can be spread over the surface of the second conductive layer 3, that is, the orthographic projection of the etch stop layer 4 on the substrate 11 covers the array area A, the peripheral area C and the mark area B.

[0083] In some embodiments of the present disclosure, to prevent the provision of the etch stop layer 4 from affecting the electrical performance of transistors subsequently formed in the peripheral region C, the etch stop layer 4 located in the peripheral region C may be removed by a dry etching process before forming the insulating cap layer 5. For example, a first photoresist layer may be formed on the surface of the etch stop layer 4 by spin coating or other methods. The first photoresist layer may be made of a photoresist. The first photoresist layer is exposed and developed to form a developed region. The orthographic projection of the developed region on the substrate 11 at least partially overlaps with the peripheral region C. The etch stop layer 4 is dry-etched in the developed region to remove the etch stop layer 4 located in the peripheral region C. During this process, the etching gas employed has an etching rate with respect to the second conductive layer 3 that is much lower than its etching rate with respect to the etch stop layer 4 to avoid damaging the underlying second conductive layer 3 during the removal of the etch stop layer 4. For example, when the etch stop layer 4 is made of undoped silicon and the film layer of the second conductive layer 3 adjacent to the etch stop layer 4 is made of tungsten, a gas containing hydrogen bromide may be used to etch the etch stop layer 4 to remove the etch stop layer 4 located in the peripheral region C.

[0084] After removing the etch stop layer 4 located in the peripheral region C, the first photoresist layer may be removed and an insulating cover layer 5 may be formed. The insulating cover layer 5 may cover the surface of the remaining etch stop layer 4 and the surface of the second conductive layer 3 in the peripheral region C that is not covered by the etch stop layer 4. In some embodiments of the present disclosure, the insulating cover layer 5 may be made of silicon nitride and may be formed by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. Of course, the insulating cover layer 5 may also be formed by other methods, and the method for forming the insulating cover layer 5 is not particularly limited herein.

[0085] In some embodiments of the present disclosure, after forming the insulating cover layer 5, the forming method of the present disclosure may further include:

[0086] In step S1301 , the insulating cover layer 5 , the second conductive layer 3 , the first conductive layer 2 , and the insulating layer 12 located in the peripheral region C are etched to form a gate structure.

[0087] A mask material layer 7 may be formed on the surface of the insulating cover layer 5 by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. The material of the mask material layer 7 may include a spin-on hard mask (SOH). Subsequently, a photoresist material layer may be formed on the surface of the mask material layer 7 by spin coating or other methods. The photoresist material layer may be exposed and developed to form a second photoresist layer 8, such as Figure 8 As shown, the orthographic projection of the second photoresist layer 8 on the substrate 11 can cover the array area A, the mark area B and the channel area of ​​the peripheral area C.

[0088] like Figure 9As shown, the mask material layer 7 not covered by the second photoresist layer 8 and the insulating cover layer 5, the second conductive layer 3, the first conductive layer 2, and the insulating layer 12 directly below the mask material layer 7 can be etched to form a gate structure 300 in the peripheral region C. It should be noted that after the gate structure 300 is formed, the second photoresist layer 8 can be removed by ashing or other processes to expose the top of the gate structure 300 and the insulating cover layer 5.

[0089] In some embodiments of the present disclosure, the forming method of the present disclosure may further include step S1302 and step S1303, wherein:

[0090] In step S1302 , an isolation layer 400 is formed to cover the sidewalls and top of the gate structure 300 .

[0091] The material of the isolation layer 400 may be an insulating material, and the isolation layer 400 may be used to insulate and protect the surface of the gate structure 300 to reduce the risk of short circuit or coupling between the gate structure 300 and other surrounding structures. The isolation layer 400 may be a composite film structure composed of multiple layers of thin films. For example, the isolation layer 400 may include a first sub-film layer 401, a second sub-film layer 402, and a third sub-film layer 403. The first sub-film layer 401, the second sub-film layer 402, and the third sub-film layer 403 may sequentially conformally cover the sidewalls and top of the gate structure 300, that is, the first sub-film layer 401 may conformally cover the sidewalls and surface of the gate structure 300, and the second sub-film layer 402 may be located between the first sub-film layer 401 and the third sub-film layer 403. The material of the first sub-film layer 401 can be the same as the material of the third sub-film layer 403, and the material of the second sub-film layer 402 can be different from the material of the first sub-film layer 401. For example, the material of the first sub-film layer 401 and the material of the third sub-film layer 403 can both be silicon nitride, and the material of the second sub-film layer 402 can be silicon oxide.

[0092] In step S1303 , an insulating material layer 500 is formed in the peripheral region C outside the gate structure 300 and the isolation layer 400 . The surface of the insulating material layer 500 is flush with the surface of the isolation layer 400 on top of the gate structure 300 .

[0093] like Figure 10As shown, an insulating material can be deposited on the surface of the structure formed by the substrate 1, the gate structure 300, and the isolation layer 400 exposed in the peripheral area C by chemical vapor deposition, physical vapor deposition, or atomic layer deposition. The insulating material can at least fill the height difference between the surface of the isolation layer 400 on the top of the gate structure 300 and the surface of the substrate 1; then, the surface of the insulating material can be modified by back etching or grinding so that the surface of the remaining insulating material is flush with the surface of the isolation layer 400 on the top of the gate structure 300, and the remaining insulating material can be used as the insulating material layer 500.

[0094] In some embodiments of the present disclosure, step S140 may be performed after forming the insulating material layer 500 .

[0095] like Figure 2 As shown, in step S140, the insulating cover layer 5 is etched to form insulating portions 51 in the array area A and the mark area B, respectively. The positive projection of the insulating portion 51 in the array area A on the substrate 11 at least partially overlaps with the active area 112 in the bit line contact hole 113. The etching rate of the etching stop layer 4 is less than the etching rate of the insulating cover layer 5.

[0096] like Figure 11 and Figure 12 As shown, in the process of etching to form the insulating portion 51, the etching endpoint can be stopped on the etching stop layer 4, without causing damage to the structure of the second conductive layer 3 below, thereby avoiding the problem of uneven etching loss in different areas of the second conductive layer 3, and helping to improve the uniformity of the key dimensions of the finally formed bit line structure 100.

[0097] In some embodiments of the present disclosure, the etching selectivity ratio between the insulating cover layer 5 and the etch stop layer 4 is greater than 10:1. Because the etching rate of the etch stop layer 4 is relatively low, the surface of the etch stop layer 4 is not significantly damaged during the formation of the insulating portion 51. Different regions of the etch stop layer 4 remain relatively flat. During the subsequent etching of the etch stop layer 4, the second conductive layer 3, and the first conductive layer 2, the film layers of the array region A and the marking region B are simultaneously consumed, reducing the probability of over-etching the marking region B and helping to improve product yield.

[0098] In an exemplary embodiment of the present disclosure, the insulating cover layer 5 is etched to form insulating portions 51 in the array region A and the mark region B (i.e., step S140), including steps S210 to S230, wherein:

[0099] In step S210 , a mask layer 6 is formed on the surface of the insulating cover layer 5 .

[0100] A mask layer 6 can be formed on the surface of the insulating cover layer 5 by chemical vapor deposition, physical vapor deposition or atomic layer deposition. The mask layer 6 can be a multi-layer film structure or a single-layer film structure. Its material can be at least one of a carbon film layer, SiO2, SiN, polysilicon and SiCN. Of course, it can also be other materials, which are not listed here one by one.

[0101] In some embodiments, the mask layer 6 may be a multilayer, which may include a silicon oxynitride layer and a carbon film layer. The carbon film layer may be first formed on the surface of the insulating cover layer 5, and then the silicon oxynitride layer may be formed on the surface of the carbon film layer.

[0102] In step S220 , the mask layer 6 is etched to form mask structures 61 in the array area A and the mark area B, respectively. The orthographic projection of the mask structure 61 in the array area A on the substrate 11 at least partially overlaps with the active area 112 in the bit line contact hole 113 .

[0103] The number of the mask structures 61 can be multiple, and the multiple mask structures 61 can be distributed at intervals; Figure 15 As shown, the orthographic projection of a portion of the mask structure 61 on the substrate 11 is located in the array area A, and the orthographic projection of the portion of the mask structure 61 on the substrate 11 at least partially overlaps with the active area 112 in the bit line contact hole 113; Figure 16 As shown, the orthographic projection of another portion of the mask structure 61 on the substrate 11 is located within the marking area B.

[0104] In step S230 , the insulating cover layer 5 is etched using the mask layer 6 having the mask structure 61 as a mask to form the insulating portion 51 in the array region A and the mark region B, respectively.

[0105] The insulating cover layer 5 can be etched by a dry etching process using the mask layer 6 as a mask to form a plurality of insulating portions 51. The etching gas for the dry etching can be set according to the materials of the insulating cover layer 5 and the etching stop layer 4 below the insulating cover layer 5 to ensure that the etching selectivity of the etching gas for the insulating cover layer 5 is much greater than its etching selectivity for the etching stop layer 4. For example, when the material of the insulating cover layer 5 is silicon nitride and the material of the etching stop layer 4 is undoped silicon, the etching gas can be a mixture of CH2FCHF2, oxygen and argon.

[0106] like Figure 2 As shown, in step S150 , the etching stop layer 4 , the second conductive layer 3 and the first conductive layer 2 are etched using the insulating portion 51 as a mask to form a bit line structure 100 in the array region A and a mark pattern 200 in the mark region B.

[0107] Each insulating portion 51 can be used as a mask to etch the etching stop layer 4, the first conductive layer 2, and the second conductive layer 3 thereunder, thereby forming a bit line structure 100 and a marking pattern 200. In the present disclosure, after the etching stop layer 4, the second conductive layer 3, and the first conductive layer 2 are etched, the insulating portion 51 located in the array region A and the remaining etching stop layer 4, the second conductive layer 3, and the first conductive layer 2 thereunder together constitute the bit line structure 100; the insulating portion 51 located in the marking region B and the remaining etching stop layer 4, the second conductive layer 3, and the first conductive layer 2 thereunder together constitute the marking pattern 200. In the embodiment of the present disclosure, the structure of the array region after completing step S150 is as follows: Figure 17 After completing step S150, the structure of the marking area is as shown in FIG. Figure 18 shown.

[0108] In an exemplary embodiment of the present disclosure, etching the etch stop layer 4, the second conductive layer 3, and the first conductive layer 2 using the insulating portion 51 as a mask to form the bit line structure 100 in the array region A and forming the mark pattern 200 in the mark region B (i.e., step S150) includes steps S310 and S320, wherein:

[0109] In step S310 , the etching stop layer 4 is etched using the insulating portion 51 as a mask until the second conductive layer 3 is exposed.

[0110] In some embodiments of the present disclosure, after the insulating portion 51 is formed, the mask layer 6 can be removed to expose the top of the insulating portion 51, and then the etching stop layer 4 can be dry-etched using the insulating portion 51 as a mask to remove the etching stop layer 4 in the area not covered by the insulating portion 51; in this process, the etching gas can be set according to the specific materials of the etching stop layer 4, the insulating portion 51, and the top film layer in the second conductive layer 3 below, so as to ensure that the damage to the surface of the second conductive layer 3 is minimized as much as possible without destroying the shape and size of the insulating portion 51. For example, when the material of the insulating portion 51 is silicon nitride, the material of the etching stop layer 4 is undoped silicon, and the material of the top film layer in the second conductive layer 3 is tungsten, the etching gas can be a mixed gas including hydrogen bromide. In the embodiment of the present disclosure, the structure of the array area after completing step S310 is as follows: Figure 19 After completing step S310, the structure of the marking area is as shown in FIG. Figure 20 shown.

[0111] In step S320 , the second conductive layer 3 and the first conductive layer 2 are etched using the structure formed by the insulating portion 51 and the remaining etching stop layer 4 as a mask to form a bit line structure 100 in the array area A and a mark pattern 200 in the mark area B.

[0112] The insulating portion 51 and the remaining etching stop layer 4 thereunder can be used together as a mask to perform dry etching on the second conductive layer 3 and the first conductive layer 2. During this process, since the second conductive layer 3 has not been etched before, the second conductive layer 3 can be etched through through a single etching process, thereby avoiding the load effect and necking phenomenon caused by different etching times, helping to improve the profile of the bit line structure 100 and further improving the uniformity of the bit line structure 100.

[0113] In an exemplary embodiment of the present disclosure, the forming method of the present disclosure may further include:

[0114] In step S160, the width of the insulating portion 51 in a direction parallel to the substrate 11 is detected, and when the width is within a first preset deviation range, the etching stop layer 4, the second conductive layer 3 and the first conductive layer 2 are etched using the insulating portion 51 as a mask to form a bit line structure 100 in the array area A and a marking pattern 200 in the marking area B.

[0115] For example, after forming the insulating portion 51 and before etching the etch stop layer 4, the width of the insulating portion 51 in a direction parallel to the substrate 11 can be detected by critical dimension (CD) detection, and the detected width values ​​of each insulating portion 51 can be compared. When the difference in the width values ​​of each insulating portion 51 is within a first preset deviation range, it is determined that the etching process of the insulating portion 51 meets the process standard, and the next etching step can be performed (for example, etching the etch stop layer 4, the second conductive layer 3, and the first conductive layer 2 using the insulating portion 51 as a mask). The first preset deviation range can be 0 nm to 5 nm. That is, when the absolute value of the difference in the width of the two insulating portions 51 with the largest size difference among the insulating portions 51 is within 5 nm (inclusive), it can be considered that the width of the insulating portion 51 in a direction parallel to the substrate 11 is within the first preset deviation range.

[0116] It should be noted that when the difference in the width values ​​of each insulating portion 51 is outside the first preset deviation range, it is determined that the etching process of the insulating portion 51 does not meet the process standard, and the detection result can be fed back to the etching machine; so as to adjust the process parameters of the etching process for forming the insulating portion 51 according to the detection result; after the process parameters are adjusted, the above process can be repeated and a new insulating portion 51 can be formed until the width of the formed insulating portion 51 in the direction parallel to the substrate 11 is within the first preset deviation range, and then the next process is continued (i.e., executing step S150).

[0117] In an exemplary embodiment of the present disclosure, the forming method of the present disclosure may further include:

[0118] In step S170, the widths of different film layers in the bit line structure 100 in a direction parallel to the substrate 11 are detected, and when the width difference of different film layers in the bit line structure 100 in a direction parallel to the substrate 11 exceeds a second preset deviation range, the detection result is fed back to the etching machine used to etch the etching stop layer 4, the second conductive layer 3 and the first conductive layer 2.

[0119] After forming the bit line structure 100 and the mark pattern 200, the widths of the etch stop layer 4, the first conductive layer 2, and the second conductive layer 3 in a direction parallel to the substrate 11 can be measured by optical critical dimension (OCD) measurement, and the detected widths of the various film layers can be compared. When the difference in the widths of the different film layers is within a second preset deviation range, it can be determined that the etching process of the etch stop layer 4, the second conductive layer 3, and the first conductive layer 2 meets the process standard. The second preset deviation range can be 0 nm to 8 nm. That is, when the absolute value of the difference in the widths of the two film layers with the largest size difference among the different film layer structures is within 8 nm (inclusive), it can be considered that the widths of the etch stop layer 4, the first conductive layer 2, and the second conductive layer 3 in a direction parallel to the substrate 11 are within the second preset deviation range.

[0120] It should be noted that when the difference in the width values ​​of the etch stop layer 4, the first conductive layer 2, and the second conductive layer 3 is outside the second preset deviation range, it is determined that the etching process of the etch stop layer 4, the first conductive layer 2, and the second conductive layer 3 does not meet the process standards. The test results can be fed back to the etching machine to adjust the process parameters used for etching the etch stop layer 4, the first conductive layer 2, and the second conductive layer 3 based on the test results, thereby facilitating more precise control of the profile of the bit line structure 100. At the same time, because the profile of the bit line structure 100 is precisely controlled through the two-step closed-loop test (CD test and OCD test), the probability of dimensional anomalies in the bit line structure 100 is reduced, which helps to increase the process window for the subsequent formation of the capacitor hole for the capacitor plug, thereby reducing the process difficulty.

[0121] It should be noted that although the steps of the method for forming a semiconductor structure in the present disclosure are described in a specific order in the accompanying drawings, this does not require or imply that the steps must be performed in this specific order, or that all steps must be performed to achieve the desired results. Additionally or alternatively, certain steps may be omitted, multiple steps may be combined into one step, and / or one step may be decomposed into multiple steps.

[0122] The embodiments of the present disclosure further provide a semiconductor structure, which can be formed by the method for forming a semiconductor structure of any of the above embodiments.

[0123] The specific details and manufacturing processes of each part of the above-mentioned semiconductor structure have been described in detail in the corresponding method for forming the semiconductor structure, and therefore, they will not be repeated here.

[0124] For example, the semiconductor structure may be a dynamic random access memory (DRAM), a static random access memory (SRAM), etc. Of course, it may also be other storage devices, which are not listed here one by one.

[0125] Other embodiments of the present disclosure will readily occur to those skilled in the art after considering the specification and practicing the invention disclosed herein. This disclosure is intended to cover any variations, uses, or adaptations of the present disclosure that follow the general principles of the present disclosure and include common knowledge or customary techniques in the art not disclosed herein. The description and examples are to be considered as exemplary only, with the true scope and spirit of the present disclosure being indicated by the appended claims.

Claims

1. A method for forming a semiconductor structure, characterized in that: include: Providing a substrate, the substrate comprising a base and an insulating layer, the base comprising an array region and a marking region, the array region being provided with a shallow trench isolation structure and a plurality of active regions separated by the shallow trench isolation structure, the insulating layer covering the shallow trench isolation structure, the active regions, and the marking region; Etching the active area and the insulating layer located on top of the active area to form a bit line contact hole; forming a first conductive layer, a second conductive layer, an etching stop layer and an insulating cover layer in sequence on a side of the insulating layer away from the substrate, wherein the first conductive layer fills the bit line contact hole; Etching the insulating cover layer to form insulating portions in the array region and the mark region, respectively, wherein an orthographic projection of the insulating portion in the array region on the substrate at least partially overlaps with the active region in the bit line contact hole; The etching rate of the etching stop layer is lower than the etching rate of the insulating cover layer; Etching the etch stop layer, the second conductive layer, and the first conductive layer using the insulating portion as a mask to form a bit line structure in the array region and a mark pattern in the mark region; Wherein, the material of the etching stop layer is undoped silicon, and the material of the insulating cover layer is silicon nitride.

2. The forming method according to claim 1, wherein: An etching selectivity ratio between the insulating cover layer and the etching stop layer is greater than 10:

1.

3. The forming method according to any one of claims 1 to 2, characterized in that: The etching of the insulating cover layer to form insulating portions in the array area and the mark area respectively includes: forming a mask layer on a surface of the insulating cover layer; Etching the mask layer to form mask structures in the array area and the mark area, respectively, wherein an orthographic projection of the mask structure in the array area on the substrate at least partially overlaps with the active area in the bit line contact hole; The insulating cover layer is etched using the mask layer having the mask structure as a mask to form the insulating portions in the array region and the mark region respectively.

4. The forming method according to any one of claims 1 to 2, characterized in that: The etching stop layer, the second conductive layer, and the first conductive layer are etched using the insulating portion as a mask to form a bit line structure in the array area and a mark pattern in the mark area, comprising: etching the etch stop layer using the insulating portion as a mask until the second conductive layer is exposed; The second conductive layer and the first conductive layer are etched using the structure formed by the insulating portion and the remaining etching stop layer as a mask to form a bit line structure in the array area and a mark pattern in the mark area.

5. The forming method according to any one of claims 1 to 2, characterized in that: The forming method further comprises: The width of the insulating portion in a direction parallel to the substrate is detected, and when the width is within a first preset deviation range, the etching stop layer, the second conductive layer, and the first conductive layer are etched using the insulating portion as a mask to form a bit line structure in the array area and a mark pattern in the mark area.

6. The forming method according to any one of claims 1 to 2, characterized in that: The forming method further comprises: The widths of different film layers in the bit line structure in a direction parallel to the substrate are detected, and when the difference in the widths of different film layers in the bit line structure in a direction parallel to the substrate exceeds a second preset deviation range, the detection results are fed back to an etching machine used to etch the etching stop layer, the second conductive layer, and the first conductive layer.

7. The forming method according to any one of claims 1 to 2, characterized in that: The substrate further includes a peripheral area, the peripheral area is distributed side by side with the array area and the mark area, and the orthographic projection of the etch stop layer on the substrate covers the array area, the peripheral area and the mark area; Before forming the insulating cover layer, the forming method further includes: removing the etching stop layer located in the peripheral area; After forming the insulating cover layer, the forming method further includes: The insulating cover layer, the second conductive layer, the first conductive layer, and the insulating layer located in the peripheral region are etched to form a gate structure.

8. The forming method according to claim 7, wherein: The forming method further comprises: forming an isolation layer covering the sidewalls and top of the gate structure; An insulating material layer is formed in the peripheral region outside the gate structure and the isolation layer, and a surface of the insulating material layer is flush with a surface of the isolation layer located on top of the gate structure.

9. A semiconductor structure, characterized in that The semiconductor structure is formed by the method for forming a semiconductor structure according to any one of claims 1 to 8.

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