Memory device and method of making the same

Abstract

The application belongs to the technical field of semiconductor, and particularly relates to a storage device and a manufacturing method thereof. The storage device comprises a reading transistor and a writing transistor. The reading transistor comprises a first gate, a first gate dielectric layer, a first channel, a first drain and a first source. The first channel is formed at least in a partial region of a side wall of a receiving hole. The first drain and the first source are both connected with the first channel. The first gate dielectric layer covers at least the first channel. The first gate is formed in the receiving hole and located at a side of the first gate dielectric layer away from the first channel. The writing transistor comprises a second channel and a second source. The second channel is at least partially located in the receiving hole. The second source is connected with the second channel. The channels of the reading transistor and the writing transistor are in the same receiving hole. Compared with a storage unit connected with a thin film transistor using two horizontal channels in the same plane, the storage unit occupies a smaller area, and the integration density of the transistor is improved.

Description

Technical Field

[0001] This application belongs to the field of semiconductor technology, and specifically relates to a memory device and its manufacturing method. Background Technology

[0002] A typical Dynamic Random Access Memory (DRAM) cell consists of a MOS (Metal Oxide Semiconductor) transistor with its drain connected to a capacitor. This type of cell requires constant refreshing of the capacitor's charge to prevent data loss, and during reading, the charge in the capacitor must be released, and then rewritten, resulting in high power consumption. Furthermore, the large area occupied by the capacitor makes miniaturization a significant challenge.

[0003] A dual-transistor capacitorless dynamic random access memory (2T0C) uses two MOS transistors as storage cells, with the drain of one transistor connected to the gate of the other. It uses the gate capacitance to store charge and changes the transconductance of the transistor to store information.

[0004] Existing dynamic random access memory based on 2T0C memory cells generally uses two horizontally channeled thin film transistors (TFTs) connected on the same plane, which occupies a large area and has a low integration density. Summary of the Invention

[0005] The purpose of this application is to provide a storage device and a method for manufacturing the same, so as to reduce the area occupied by the storage cell and increase the integration density of the dynamic random access memory.

[0006] To achieve the above objectives, this application provides a memory cell, including a substrate and at least one memory device layer disposed on the substrate, the memory device layer comprising:

[0007] The insulating layer includes a first insulating layer and a second insulating layer stacked vertically.

[0008] At least one memory cell, the memory cell including a read transistor and a write transistor, the read transistor including a first gate, a first gate dielectric layer, a first channel, a first drain and a first source, a receiving hole is provided on the side of the first insulating layer near the second insulating layer, the first channel is formed at least in a portion of the sidewall of the receiving hole, the first drain and the first source are disposed outside the receiving hole at a distance, the first drain is located on the side of the first source away from the second insulating layer, the first drain and the first source are both connected to the first channel, the first gate dielectric layer at least covers the first channel, and the first gate is formed in the receiving hole and located on the side of the first gate dielectric layer away from the first channel;

[0009] The write transistor includes a second gate, a second gate dielectric layer, a second channel, and a second source. The second channel is at least partially located within the accommodating via. The drain of the second channel is connected to the first gate. The second source is connected to the second channel. The second gate is formed on the side of the second channel away from the first gate dielectric layer. The second gate dielectric layer is formed between the second gate and the second channel.

[0010] Optionally, the upper surface of the first gate near the second insulating layer is located between the upper surface of the first insulating layer near the second insulating layer and the lower surface of the first source away from the second insulating layer.

[0011] Optionally, the orthographic projection of the receiving hole on the substrate is located within the orthographic projection of the first drain on the substrate, the orthographic projection of the receiving hole on the substrate is located within the orthographic projection of the first source on the substrate, and the orthographic projection of the receiving hole on the substrate is located within the orthographic projection of the second source on the substrate, the first channel surrounds the first gate, the second gate is at least partially located in the receiving hole, and at least a portion of the second channel surrounds the portion of the second gate located in the receiving hole.

[0012] Optionally, the storage device layer includes a first channel layer and an isolation portion. The first channel layer is formed on the entire sidewall of the receiving hole. The first channel layer includes a first channel and an extension portion. The surface of the first source electrode near the second insulating layer is the upper surface of the first source electrode. The first channel is located on the side of the upper surface of the first source electrode away from the second insulating layer. The extension portion is located on the side of the upper surface of the first source electrode near the second insulating layer. The upper surface of the extension portion near the second insulating layer is flush with or spaced from the upper surface of the first insulating layer near the second insulating layer. The isolation portion is formed between the extension portion and the second channel.

[0013] Optionally, the memory cell further includes a dielectric portion formed within the receiving aperture and located on the side of the first gate near the second insulating layer. The dielectric portion has a first via, and the second channel passes through the first via and connects to the first gate; and / or

[0014] The first gate dielectric layer also covers the extension, and the isolation portion includes the portion of the extension covered by the first gate dielectric layer;

[0015] Wherein, when the isolation portion includes the dielectric portion and the portion of the first gate dielectric layer covering the extension portion, the dielectric portion is located on the side of the first gate dielectric layer away from the first channel layer.

[0016] Optionally, the material of the dielectric portion includes a low dielectric constant material.

[0017] Optionally, the first through hole and the receiving hole are coaxially arranged.

[0018] Optionally, the aperture of the first via at the end furthest from the first gate is greater than or equal to the aperture of the first via at the end closest to the first gate, and the aperture of the first via at the end closest to the first gate is greater than or equal to 20 nanometers; and / or

[0019] The inner diameter of the accommodating hole is 50 nanometers to 500 nanometers.

[0020] Optionally, the storage device layer includes a first channel layer formed on the sidewall of the receiving hole. The first channel layer includes a first channel and an extension. The surface of the first source electrode near the second insulating layer is the upper surface of the first source electrode. The first channel is located on the side of the upper surface of the first source electrode away from the second insulating layer. The extension is located on the side of the upper surface of the first source electrode near the second insulating layer. There is a predetermined distance between the upper surface of the extension near the second insulating layer and the upper surface of the first insulating layer near the second insulating layer. In the depth direction of the receiving hole, the second channel and the first channel layer are spaced apart.

[0021] Optionally, the first gate dielectric layer covers the first channel and the bottom of the receiving hole, the receiving hole extending to the first drain near the upper surface of the second insulating layer, or the receiving hole extending into the first drain, or the receiving hole penetrating the first drain.

[0022] Optionally, the memory device layer further includes a first signal line, a second signal line, a third signal line, and a fourth signal line. The first signal line and the second signal line are both located in the first insulating layer and extend in different directions. The first signal line is connected to the first drain, the second signal line is connected to the first source, the fourth signal line is located in the second insulating layer, the third signal line and the fourth signal line extend in different directions, the third signal line is connected to the second source, and the fourth signal line is connected to the second gate.

[0023] Optionally, the first signal line and the first drain are disposed on the same layer, the second signal line and the first source are disposed on the same layer, and the fourth signal line and the second gate are disposed on the same layer or the fourth signal line is disposed on the side of the second gate away from the first gate.

[0024] Optionally, the fourth signal line and the second gate are disposed on the same layer, and the fourth signal line is a stacked structure. The stacked structure includes a second gate material layer in contact with the second gate dielectric layer and a conductor layer located on the side of the second gate material layer away from the second gate dielectric layer.

[0025] Optionally, the third signal line includes a first branch line, wherein the first branch line, the second source, and the second channel are disposed on the same layer and connected; and / or

[0026] The third signal line includes a second branch line, which is disposed on the side of the second insulating layer away from the first insulating layer, and the second branch line is connected to the second source electrode through a second via.

[0027] Optionally, the material of the second channel includes an oxide semiconductor, and the material of the second branch line includes tungsten, molybdenum, titanium nitride, doped polycrystalline silicon, or doped monocrystalline silicon.

[0028] This application also provides a method for manufacturing a storage device, including:

[0029] A stacked structure is formed on one side of a substrate. The stacked structure includes a first insulating layer and a first lead layer and a second lead layer spaced apart within the first insulating layer. The second lead layer is located on the side of the first lead layer away from the substrate. The first lead layer includes a first drain, and the second lead layer includes a first source.

[0030] An accommodating hole is formed on the side of the stacked structure away from the substrate;

[0031] A first channel is formed in at least a portion of the sidewall of the receiving hole, the first channel connecting the first drain and the first source;

[0032] A first gate dielectric layer is formed that at least covers the first channel;

[0033] A first gate is formed on the side of the first gate dielectric layer away from the first channel within the accommodating hole;

[0034] A second channel and a second source are formed on the side of the first gate away from the substrate, and the second channel is at least partially located in the accommodating hole;

[0035] A second gate dielectric layer and a second gate are sequentially formed on the side of the second channel away from the substrate. The first gate, the first channel, the first drain, and the first source constitute a read transistor, and the second gate, the second channel, and the second source constitute a write transistor.

[0036] A second insulating layer is formed that at least covers the second gate and the second source.

[0037] Optionally, forming the first channel at least in a portion of the sidewall of the receiving hole includes:

[0038] A first channel material layer is formed at least on the inner wall of the accommodating hole;

[0039] The first channel material layer is etched using a dry etching method to remove at least a portion of the first channel material layer at the bottom of the receiving hole, forming a first channel layer covering the sidewall of the receiving hole. The upper surface of the first channel layer near the second insulating layer is flush with or spaced from the upper surface of the first insulating layer near the second insulating layer. The first channel layer includes the first channel.

[0040] Optionally, before forming the second gate dielectric layer, the method for fabricating the storage device includes:

[0041] A dielectric layer is formed within the accommodating aperture and on the side of the first gate away from the substrate;

[0042] The dielectric layer is dry-etched to form a first via on the dielectric layer, forming a dielectric portion that at least covers the portion of the first gate dielectric layer located within the accommodating via, and the first via exposes the first gate.

[0043] The second channel is formed, and the second channel passes through the first via and is connected to the first gate.

[0044] Optionally, the second channel material layer is fabricated using an atomic layer deposition process.

[0045] Optionally, forming a connected second channel and a second source on the side of the first gate away from the substrate includes:

[0046] A second channel material layer is formed on the side of the first gate away from the substrate;

[0047] The second channel material layer is etched to form the second channel and the second source electrode.

[0048] Optionally, forming a stacked structure on one side of the substrate includes:

[0049] A first insulating material layer, a first lead layer, a second insulating material layer, a second lead layer, and a third insulating material layer are stacked sequentially on the substrate. The first lead layer includes a first signal line connected to the first drain, and the second lead layer includes a second signal line connected to the first source. The first signal line and the second signal line extend in different directions.

[0050] The etching of the second channel material layer to form the second channel and the second source includes: forming a first branch line connected to the second source; and / or, after forming a second insulating layer that at least covers the second gate and the second source, the method of fabricating the memory device includes: forming a second branch line on the side of the second insulating layer away from the substrate, the second branch line being connected to the second source through a second via, the first branch line and / or the second branch line constituting a third signal line;

[0051] The step of sequentially forming a second gate dielectric layer and a second gate on the side of the second channel away from the substrate includes:

[0052] A second gate dielectric layer is formed that at least covers the second channel;

[0053] A second gate and a fourth signal line are formed in connection. The second gate is located on the side of the second gate dielectric layer away from the substrate. The fourth signal line and the third signal line extend in different directions.

[0054] Optionally, the orthographic projection of the accommodating hole on the substrate is located within the orthographic projection of the first drain electrode on the substrate, the orthographic projection of the accommodating hole on the substrate is located within the orthographic projection of the first source electrode on the substrate, and the orthographic projection of the accommodating hole on the substrate is located within the orthographic projection of the second source electrode on the substrate. The accommodating hole is formed by dry etching and penetrates the first drain electrode.

[0055] The storage device and its manufacturing method disclosed in this application have the following beneficial effects:

[0056] In this application, the storage device includes a substrate and at least one storage device layer disposed on the substrate. The storage device layer includes an insulating layer and at least one storage cell. The storage cell includes a read transistor and a write transistor. In the read transistor: a first channel is formed at least in a portion of the sidewall of a accommodating aperture in the first insulating layer; a first gate dielectric layer at least covers the first channel; and a first gate is formed within the accommodating aperture and located on the side of the first gate dielectric layer away from the first channel. In the write transistor: a second channel is at least partially located within the accommodating aperture. By configuring the first and second channels, the read transistor and the write transistor are formed as stacked vertical channel transistors, and the channels of the read transistor and the write transistor are in the same accommodating aperture. Compared with storage cells connected using two horizontal channels on the same plane, this reduces the storage cell area and increases the transistor integration density.

[0057] Other features and advantages of this application will become apparent from the following detailed description, or may be learned in part from practice of this application.

[0058] It should be understood that the above general description and the following detailed description are exemplary and explanatory only, and are not intended to limit this disclosure. Attached Figure Description

[0059] The accompanying drawings, which are incorporated in and form part of this specification, illustrate embodiments consistent with this application and, together with the description, serve to explain the principles of this application. It is obvious that the drawings described below are merely some embodiments of this application, and those skilled in the art can obtain other drawings based on these drawings without any inventive effort.

[0060] Figure 1 This is a top view of the storage device in an embodiment of this application.

[0061] Figure 2 yes Figure 1 A schematic diagram of the X-direction cross-section of the storage device.

[0062] Figure 3 yes Figure 1 A schematic diagram of the Y-direction cross-section of the storage device.

[0063] Figure 4 This is a schematic cross-sectional view of a storage device with a medium section in the X direction, as shown in the embodiments of this application.

[0064] Figure 5 This is a schematic diagram of the circuit structure of the storage unit in an embodiment of this application.

[0065] Figure 6 This is a schematic diagram of the circuit structure of the storage device in an embodiment of this application.

[0066] Figure 7 This is a flowchart of a method for manufacturing a storage device according to an embodiment of this application.

[0067] Figure 8 This is a schematic cross-sectional view of the accommodating hole formed in the X direction in an embodiment of this application.

[0068] Figure 9 This is a schematic cross-sectional view of the first channel layer formed in an embodiment of this application.

[0069] Figure 10 This is a schematic cross-sectional view of the first gate formed in the X direction in an embodiment of this application.

[0070] Figure 11 This is a schematic cross-sectional view of the Y-direction forming the first gate in an embodiment of this application.

[0071] Figure 12 This is a schematic cross-sectional view of the second channel formed in the X direction in an embodiment of this application.

[0072] Figure 13 This is a schematic diagram of the Y-direction cross-section forming the second channel in an embodiment of this application.

[0073] Figure 14 This is a schematic cross-sectional view of the X-direction forming the fourth signal line in an embodiment of this application.

[0074] Figure 15 This is a schematic diagram of the Y-direction cross-section of the fourth signal line formed in an embodiment of this application.

[0075] Figure 16 This is a schematic cross-sectional view of the medium section formed in the embodiment of this application.

[0076] Explanation of reference numerals in the attached figures:

[0077] 100. Substrate;

[0078] 210. First insulating layer; 211. Receiving hole; 220. Second insulating layer;

[0079] 311, First drain; 312, First signal line; 321, First source; 322, Second signal line; 331, Second branch line; 341, Conductor layer;

[0080] 410. First trench layer; 411. First trench; 412. Extension; 421. Second trench; 422. Second source electrode; 423. First branch line;

[0081] 511, First gate dielectric layer; 521, Second gate dielectric layer;

[0082] 611, First gate; 621, Second gate material layer;

[0083] 710. Medium section; 711. First via;

[0084] 10. Read transistor; 20. Write transistor. Detailed Implementation

[0085] Exemplary embodiments will now be described more fully with reference to the accompanying drawings. However, these exemplary embodiments can be implemented in many forms and should not be construed as limited to the examples set forth herein; rather, these embodiments are provided to make this application more comprehensive and complete, and to fully convey the concept of the exemplary embodiments to those skilled in the art.

[0086] Furthermore, the described features, structures, or characteristics can be combined in any suitable manner in one or more embodiments. Numerous specific details are provided in the following description to give a thorough understanding of embodiments of this application. However, those skilled in the art will recognize that the technical solutions of this application can be practiced without one or more of the specific details, or other methods, components, apparatuses, steps, etc., can be employed. In other instances, well-known methods, apparatuses, implementations, or operations are not shown or described in detail to avoid obscuring various aspects of this application.

[0087] The present application will now be described in further detail with reference to the accompanying drawings and specific embodiments. It should be noted that the technical features involved in the various embodiments described below can be combined with each other as long as they do not conflict with each other. The embodiments described below with reference to the accompanying drawings are exemplary and intended to explain the present application, and should not be construed as limiting the present application.

[0088] See Figures 1 to 3 As shown, in this embodiment, the storage device includes a substrate 100 and at least one memory device layer disposed on the substrate 100. The substrate 100 can be any substrate known to those skilled in the art for supporting semiconductor integrated circuits; for example, it can be an insulating substrate, a semiconductor substrate, or a composite substrate, and this application does not impose any limitations. It is understood that the substrate 100 can be removed after the memory device layer is fabricated. After the memory device layer is fabricated and the substrate 100 is removed, it is bonded to other substrates with its top or bottom surface. These other substrates are, for example, peripheral substrates containing peripheral devices, temporary support substrates, or substrates with other devices disposed on them. This application does not specifically limit the relationship between the substrate 100 and the memory device layer.

[0089] The storage device layer includes an insulating layer and at least one storage cell. Figure 2 and Figure 3(Only one memory cell is shown). The insulating layer includes a first insulating layer 210 and a second insulating layer 220 stacked vertically, the vertical direction being perpendicular or approximately perpendicular to the substrate 100. The memory cell includes a read transistor 10 and a write transistor 20.

[0090] The read transistor 10 includes a first gate 611, a first gate dielectric layer 511, a first channel 411, a first drain 311, and a first source 321. A receiving hole 211 is provided on the side of the first insulating layer 210 near the second insulating layer 220, and the first channel 411 is formed at least in a portion of the sidewall of the receiving hole 211. The first drain 311 and the first source 321 are spaced apart outside the receiving hole 211, with the first drain 311 located on the side of the first source 321 away from the second insulating layer 220, i.e., the first drain 311 is closer to the substrate 100 than the first source 321. Both the first drain 311 and the first source 321 are connected to the first channel 411. The first gate dielectric layer 511 at least covers the first channel 411, and the first gate 611 is formed within the receiving hole 211 and located on the side of the first gate dielectric layer 511 away from the first channel 411.

[0091] The write transistor 20 includes a second gate, a second gate dielectric layer 521, a second channel 421, and a second source 422. The second channel 421 is at least partially located within the accommodating via 211. The drain terminal of the second channel 421 is connected to the first gate 611. The second source 422 is located outside the accommodating via 211 and is connected to the second channel 421. The second gate is formed on the side of the second channel 421 away from the first gate dielectric layer 511. The second gate dielectric layer 521 is formed between the second gate and the second channel 421.

[0092] Existing dynamic random access memory based on 2T0C memory cells generally uses two horizontally channeled thin-film transistors connected on the same plane, which occupies a large area and has a low storage density.

[0093] In this embodiment, the storage device includes a substrate 100 and at least one storage device layer disposed on the substrate 100. When the storage device layer is multilayered, the multilayer storage device layers are vertically stacked on the substrate 100. The storage device layer includes an insulating layer and at least one storage cell. The storage cell includes a read transistor 10 and a write transistor 20. In the read transistor 10: a first channel 411 is formed at least in a portion of the sidewall of the accommodating hole 211 in the first insulating layer 210; a first gate dielectric layer 511 at least covers the first channel 411; and a first gate 611 is formed within the accommodating hole 211 and located on the side of the first gate dielectric layer 511 away from the first channel 411. In the write transistor 20: a second channel 421 is at least partially located within the accommodating hole 211. With the configuration of the first channel 411 and the second channel 421, the read transistor 10 and the write transistor 20 are formed as stacked vertical channel transistors, and the channels of the read transistor 10 and the write transistor 20 are in the same receiving hole 211. Compared with the memory cell connected by two horizontal channels on the same plane, the memory cell area is reduced and the transistor integration density is improved.

[0094] See Figures 2 to 3 As shown, the upper surface of the first gate 611 is lower than the upper surface of the first insulating layer 210 and higher than the lower surface of the first source 321. The upper surface of the first gate 611 may be planar or approximately planar.

[0095] The upper surface of the first gate 611 is higher than the lower surface of the first source 321, which can ensure the control capability of the first gate 611 over the first channel 411 and improve the read margin; the upper surface of the first gate 611 is lower than the upper surface of the first insulating layer 210, which ensures that there is space in the upper part of the accommodating hole 211 to accommodate the write transistor 20.

[0096] Preferably, the upper surface of the first gate 611 is slightly higher than the upper surface of the first source 321, which can maximize the control capability of the first gate 611 over the first channel 411, while ensuring that there is more space above the accommodating hole 211 to accommodate the write transistor 20.

[0097] See Figures 1 to 3 As shown, the orthographic projection of the accommodating hole 211 on the substrate 100 is located within the orthographic projection of the first drain 311 on the substrate 100; the orthographic projection of the accommodating hole 211 on the substrate 100 is located within the orthographic projection of the first source 321 on the substrate 100; the orthographic projection of the accommodating hole 211 on the substrate 100 is located within the orthographic projection of the second source 422 on the substrate 100.

[0098] A first channel 411 is disposed in a portion of the sidewall of the receiving hole 211, and the first channel 411 surrounds the first gate 611. The second gate is at least partially located within the receiving hole 211, and at least a portion of the second channel 421 surrounds the portion of the second gate located within the receiving hole 211. That is, a portion of the second channel 421 is located between the second gate and the first gate 611, and a portion of the second channel 421 is located between the second gate and the receiving hole 211. The receiving hole 211 may be a circular hole, and the portions of the first gate 611 and the second gate located within the receiving hole 211 may be cylindrical.

[0099] It should be noted that the first channel 411 may be provided in a part of the side wall of the receiving hole 211, but is not limited thereto. The first channel 411 may also be provided in part at the bottom of the receiving hole 211, depending on the specific situation.

[0100] The first channel 411 surrounds the first gate 611, and at least a portion of the second channel 421 surrounds the second gate located in the accommodating hole 211. That is, both the read transistor 10 and the write transistor 20 are channel-all-around transistors. When occupying the same area on the substrate, the vertical channel-all-around transistor has a larger channel width than the horizontally arranged planar transistor, which improves the read margin. Moreover, the channel length can be changed by adjusting the vertical extension length of the source-drain channel to reduce charge leakage, which is beneficial to improving the performance of the memory device.

[0101] See Figures 1 to 3 As shown, the storage device layer includes a first channel layer 410 and an isolation portion. The first channel layer 410 is formed on the sidewall of the receiving hole 211, and includes a first channel 411 and an extension 412. The surface of the first source 321 near the second insulating layer 220 is the upper surface of the first source 321. The first channel 411 is located on the side of the upper surface of the first source 321 away from the second insulating layer 220, and the extension 412 is located on the side of the upper surface of the first source 321 near the second insulating layer 220. The upper surface of the extension 412 near the second insulating layer 220 is flush with or spaced from the upper surface of the first insulating layer 210 near the second insulating layer 220, that is, the first channel layer 410 covers the entire sidewall of the receiving hole 211, or the upper surface of the first channel layer 410 is slightly lower than the upper surface of the first insulating layer 210. The isolation portion is formed between the extension 412 and the second channel 421.

[0102] The first channel layer 410 is formed on the entire sidewall of the receiving hole 211. When fabricating the first channel layer 410, a first channel material layer can be formed on the inner wall of the receiving hole 211 and the upper surface of the first insulating layer 210. Then, the first channel material layer on the upper surface of the first insulating layer 210 and the bottom of the receiving hole 211 is etched away to form the first channel layer 410. Compared with the scheme where the first channel layer 410 is formed in a part of the sidewall of the receiving hole 211, the fabrication process of the first channel layer 410 is simpler and can reduce the manufacturing cost of the storage device. In other embodiments, when fabricating the first channel layer 410, a first channel material layer can be formed on the inner wall of the receiving hole 211 and the upper surface of the first insulating layer 210. A sacrificial material layer is prepared to at least cover the portion of the first channel material layer located at the bottom of the receiving hole 211. Then, the first channel material layer located on the upper surface of the first insulating layer 210 is etched away to form the first channel layer 410. The first channel layer 410 also includes the portion located at the bottom of the receiving hole 211, which may be determined depending on the circumstances.

[0103] When etching away the upper surface of the first insulating layer 210 and the first channel material at the bottom of the receiving hole 211, the first channel material layer can be partially over-etched, so that the upper surface of the extension 412 near the second insulating layer 220 and the upper surface of the first insulating layer 210 near the second insulating layer 220 are separated. That is, the upper surface of the first channel layer 410 is slightly lower than the upper surface of the first insulating layer 210. This can ensure that the removal of the upper surface of the first insulating layer 210 and the first channel material at the bottom of the receiving hole 211 is carried out while reducing the requirements for etching process precision.

[0104] An isolation section is formed between the extension 412 and the second channel 421. See also Figure 2 and Figure 3 As shown, the first gate dielectric layer 511 can cover the bottom of the first channel layer 410 and the receiving hole 211, and the isolation portion includes the portion of the extension 412 covered by the first gate dielectric layer 511.

[0105] In other embodiments, see Figure 4 As shown, the isolation portion includes a dielectric portion 710, which is formed within a receiving aperture 211 and located on the side of the first gate 611 near the second insulating layer 220. The dielectric portion 710 has a first via 711 that exposes a portion of the upper surface of the first gate 611. A second channel 421 passes through the first via 711 and connects to the first gate 611, meaning the dielectric portion 710 is located between the second channel 421 and the first channel layer 410. For example, the diameter of the end of the first via 711 away from the first gate 611 is greater than or equal to the diameter of the end of the first via 711 near the first gate 611.

[0106] The inner diameter of the accommodating aperture 211 is 50 nm to 500 nm. If the inner diameter of the accommodating aperture 211 is less than 50 nm, it increases the difficulty of fabricating the accommodating aperture 211 and is not conducive to filling the various film layers of the read transistor 10 and write transistor 20 and the dielectric portion 710 (if any) inside the aperture; if the inner diameter of the accommodating aperture 211 is greater than 500 nm, it occupies a large area, which is not conducive to improving the storage density.

[0107] The aperture of the first via 711 near the first gate 611 is greater than or equal to 20 nanometers. When the aperture of the first via 711 near the first gate 611 is less than 20 nanometers: the contact area between the first gate 611 and the second channel 421 is too small, resulting in a large impedance during the writing and erasing process via the write transistor 20; during the fabrication of the second channel 421, the reliability of the connection between the second channel 421 and the first gate 611 is reduced due to the limitation of film deposition uniformity.

[0108] It is understandable that when the inner diameter of the accommodating hole 211 is less than 50 nanometers and the memory cell also includes a dielectric section 710 and the second channel 421 is connected to the first gate 611 via the first via 711 in the dielectric section 710, the manufacturing process is difficult, including but not limited to the increased requirements for uniformity of deposition and etching during the preparation of the dielectric section 710.

[0109] Since the first channel layer 410 is formed on the entire sidewall of the receiving hole 211, the second channel 421 is at least partially located within the receiving hole 211. The portion of the second channel 421 located within the receiving hole 211 is surrounded by the first channel layer 410, and the second channel 421 and the first channel layer 410 overlap in the vertical direction. A dielectric portion 710 is provided between the second channel 421 and the first channel layer 410, which can reduce the parasitic capacitance between the second channel 421 and the first channel layer 410, and reduce crosstalk between the first channel layer 410 and the write transistor 20.

[0110] It should be understood that the isolation portion includes the portion of the first gate dielectric layer 511 covering the extension portion 412, or the isolation portion includes the portion of the first gate dielectric layer 511 covering the extension portion 412 and the dielectric portion 710, but is not limited thereto. The isolation portion may also include the dielectric portion 710 but not the portion of the first gate dielectric layer 511 covering the extension portion 412. That is, when the isolation portion includes the dielectric portion 710, the first gate dielectric layer 511 may not cover the portion of the extension portion 412, depending on the specific circumstances.

[0111] See Figure 4 As shown, the first through hole 711 and the receiving hole 211 are coaxially arranged.

[0112] The first via 711 and the receiving hole 211 are coaxially arranged so that the second channel 421 and the first channel layer 410 are evenly spaced, which can further reduce the parasitic capacitance between the two channels.

[0113] In some embodiments, the material of the dielectric portion 710 includes a low dielectric constant material.

[0114] The dielectric section 710 is made of a low dielectric constant material, which further reduces the parasitic capacitance between the two channels.

[0115] In this embodiment, the first channel layer 410 is formed on the entire sidewall of the receiving hole 211 to simplify the fabrication process of the first channel layer 410. In some embodiments, when the upper surface of the first insulating layer 210 and the first channel material layer at the bottom of the receiving hole 211 are etched away to form the first channel layer 410, the portion of the first channel layer 410 located at the opening of the receiving hole 211, that is, the portion of the first channel layer 410 located at the upper end of the sidewall of the receiving hole 211, can be etched away by a predetermined amount. For example, a protective material layer is used to fill a portion of the depth of the receiving hole 211, and then the predetermined amount of the first channel material layer not covered by the protective material layer is etched away. The protective material layer is then removed, thereby allowing the first channel layer 410 to be formed in a portion of the sidewall of the receiving hole 211. In the depth direction of the receiving hole 211, the second channel 421 and the first channel layer 410 are spaced apart.

[0116] The second channel 421 and the first channel layer 410 are spaced apart in the depth direction of the accommodating via 211, which can reduce the parasitic capacitance between the two channel layers and reduce the mutual interference between the read transistor 10 and the write transistor 20. At the same time, the process of fabricating the dielectric section 710 can be omitted, thereby reducing the manufacturing cost of the storage device.

[0117] See Figures 1 to 3 As shown, the first gate dielectric layer 511 covers the bottom of the first channel layer 410 and the receiving hole 211, and the receiving hole 211 penetrates the first drain 311.

[0118] It should be noted that the receiving hole 211 can penetrate the first drain electrode 311, but it is not limited to this. The receiving hole 211 can also extend to the upper surface of the first drain electrode 311 near the second insulating layer 220 or extend into the first drain electrode 311, depending on the specific situation.

[0119] When the receiving hole 211 extends to the upper surface of the first drain 311 or into the first drain 311, the bottom surface of the receiving hole 211 can be covered by the first channel layer 410, so that the first channel layer 410 and the first drain 311 have a sufficiently large contact surface. The receiving hole 211 penetrates the first drain 311, and the first channel layer 410 can be formed only on the sidewall of the receiving hole 211, making the manufacturing process of the first channel layer 410 simpler. When the accommodating hole 211 penetrates the first drain 311 and the first channel layer 410 is formed on the sidewall of the accommodating hole 211 but not on the bottom surface of the accommodating hole 211, the first gate dielectric layer 511 covers the bottom surface of the accommodating hole 211 and the first gate 611 is formed on the surface of the first gate dielectric layer 511 away from the bottom surface of the accommodating hole 211. Compared to the first gate dielectric layer 511 not covering the bottom surface of the accommodating hole 211 and the first gate 611 being formed on the surface of the first insulating layer 210 located on the bottom surface of the accommodating hole 211, the first gate 611 is easier to fabricate.

[0120] See Figures 1 to 3 As shown, the memory device layer also includes a first signal line 312, a second signal line 322, a third signal line, and a fourth signal line. The first signal line 312 and the second signal line 322 are both located in the first insulating layer 210 and extend in different directions. For example, the first signal line 312 may extend along the X direction, and the second signal line 322 may extend along the Y direction, wherein the X and Y directions form an angle, such as a right angle or an acute angle, which is not limited to this. The first signal line 312 is connected to the first drain 311, and the second signal line 322 is connected to the first source 321.

[0121] The fourth signal line is located within the second insulating layer 220, and the third and fourth signal lines extend in different directions. For example, the fourth signal line is located within the second insulating layer 220 if at least one side is covered by the second insulating layer 220; that is, the fourth signal line can be covered by one side or three sides of the second insulating layer 220. The third and fourth signal lines extend in different directions, for example, the third signal line can extend along the X direction, and the fourth signal line can extend along the Y direction, wherein the X and Y directions form an angle, such as a right angle or an acute angle, which is not limited to this. The third signal line is connected to the second source 422, and the fourth signal line is connected to the second gate.

[0122] like Figure 6As shown, in the storage device layer, the storage devices are typically arranged in a matrix. Exemplarily, a first signal line 312 and a second signal line 322, connected to the same storage cell, are respectively connected to a row of storage cells and a column of storage cells in the matrix. A third signal line and a fourth signal line are also connected to a row of storage cells and a column of storage cells in the matrix. By making the extension directions of the first signal line 312 and the second signal line 322 different, and the extension directions of the third signal line and the fourth signal line different, and through the intersection of the first signal line 312 and the second signal line 322, and the intersection of the third signal line and the fourth signal line, the storage cell is located at the intersection point where the first to fourth signal lines connect. This allows selection of the storage cell for read and write functions. The first signal line 312 can be parallel to one of the third and fourth signal lines, and the second signal line 322 can be parallel to the other of the third and fourth signal lines. However, the invention is not limited to this; it is sufficient that the extension directions of the first signal line 312 and the second signal line 322, and the third signal line and the fourth signal line are different.

[0123] See Figures 1 to 3 As shown, the first signal line 312 and the first drain 311 are arranged on the same layer, the second signal line 322 and the first source 321 are arranged on the same layer, and the fourth signal line is arranged on the same layer as the second gate.

[0124] It should be noted that the first signal line 312 and the first drain 311 can be arranged on the same layer, that is, the first signal line 312 and the first drain 311 are integrally connected and manufactured using the same material in the same process. However, this is not limited to this; the first signal line 312 and the first drain 311 can also be manufactured using different materials and different processes, depending on the specific circumstances. Similarly, the second signal line 322 and the first source 321 can be arranged on the same layer, that is, the second signal line 322 and the first source 321 are integrally connected and manufactured using the same material in the same process. However, this is not limited to this; the second signal line 322 and the first source 321 can also be manufactured using different materials and different processes. The fourth signal line and the second gate are arranged on the same layer, that is, the fourth signal line and the second gate are integrally connected and manufactured using the same material in the same process. However, this is not limited to this; the fourth signal line and the second gate can also be manufactured using different materials and different processes, depending on the specific circumstances.

[0125] The first signal line 312 is disposed on the same layer as the first drain 311, the second signal line 322 is disposed on the same layer as the first source 321, and the fourth signal line is disposed on the same layer as the second gate, which can reduce the manufacturing cost of the memory device.

[0126] It should be noted that the fourth signal line can also be located on the side of the second gate away from the first gate 611, and connected directly to the second gate or through a via. The present invention does not specifically limit the connection method between the fourth signal line and the second gate.

[0127] It is understandable that, in order to simultaneously obtain a write transistor 20 that meets electrical characteristic requirements and a fourth signal line with low impedance, the fourth signal line and the second gate fabricated in the same layer can be multilayered, such as... Figure 2 , 3 As shown, the fourth signal line and the second gate fabricated in the same layer include a stacked structure. The stacked structure includes a second gate material layer 621 on the side close to the second gate dielectric layer 521, and a conductor layer 341 on the side away from the second gate dielectric layer 521. The second gate material layer 621 is, for example, an oxide semiconductor or titanium nitride. The oxide semiconductor includes, for example, indium oxide, zinc oxide, gallium oxide, indium gallium zinc oxide, etc. The conductor layer 341 is made of, for example, tungsten, molybdenum, titanium nitride, doped polycrystalline silicon, doped monocrystalline silicon, etc. The materials of the second gate material layer 621 and the conductor layer 341 can be the same or different, depending on the specific situation. By configuring the second gate material layer 621 to meet the electrical characteristic requirements of the write transistor 20 and configuring the conductor layer 341 to be a high conductivity material, the fabrication cost of the fourth signal line and the second gate can be reduced while ensuring that the write transistor 20 meets the electrical characteristic requirements and the fourth signal line has low impedance.

[0128] Figure 2 , 3 The stacked structure shown in the embodiment includes two layers: a second gate material layer 621 and a conductor layer 341. In other embodiments, the stacked structure may include multiple layers. There may also be other conductive layers between the second gate material layer 621 and the conductor layer 341. There may also be other conductive layers on the side of the conductor layer 341 away from the second gate material layer 621. The second gate material layer 621 and the conductor layer 341 may also be multilayer structures. The present invention does not specifically limit the number of layers in the stacked structure.

[0129] See Figures 1 to 3 As shown, the third signal line includes a first branch line 423, which, along with the second source 422 and the second channel 421, is disposed on the same layer and connected. The third signal line may also include a second branch line 331, which is disposed on the side of the second insulating layer 220 away from the first insulating layer 210, and is connected to the second source 422 through a second via.

[0130] It should be noted that when the storage device layer includes the second branch line 331, a third insulating layer may be provided on the side of the second insulating layer 220 away from the first insulating layer 210 to cover the second branch line 331. The third signal line may include one of the first branch line 423 and the second branch line 331, or may include both the first branch line 423 and the second branch line 331.

[0131] The first branch line 423, the second source 422, and the second channel 421 are arranged on the same layer, which can reduce the manufacturing cost of the storage device. Simultaneously, using the same material as the second channel 421 to fabricate the first branch line 423 eliminates the need for separate fabrication of the first branch line 423, further reducing the manufacturing cost of the storage device. When the impedance of the first branch line 423 is high, it is detrimental to signal transmission. Fabricating the second branch line 331 on the side of the second insulating layer 220 away from the first insulating layer 210 can reduce the impedance between the second sources 422 of two adjacent storage cells, thereby reducing signal delay on the third signal line.

[0132] The material of the second channel 421 includes oxide semiconductors. Thin-film transistors made of oxide semiconductors have extremely low off-state currents, which can significantly reduce leakage current when used in 2TOC dynamic random access memory. It should be understood that the first channel 411 and the second channel 421 can be made of oxide semiconductor materials, such as indium oxide, zinc oxide, gallium oxide, indium gallium zinc oxide, etc., but are not limited to these. The first channel 411 and the second channel 421 can also be made of other metal oxides or semiconductor materials, depending on the specific circumstances.

[0133] When the material of the second channel 421 is an oxide semiconductor, the second branch line 331 is made of materials with good conductivity such as tungsten, molybdenum, titanium nitride, doped polycrystalline silicon or doped single-crystal silicon, which can reduce the impedance between the second source 422 of two adjacent memory cells and reduce the signal attenuation on the third signal line.

[0134] Furthermore, the insulating layer can be made of commonly used insulating materials in the art, such as silicon oxide and silicon nitride. The insulating layer preferably includes a low dielectric constant material or includes air gaps to reduce crosstalk between wiring or devices. It should be understood that the insulating layer can be any common insulating dielectric material in the art, and this application is not limited thereto. The material used to make the insulating layer can be the same as or different from the material used to make the dielectric portion 710. The gate dielectric layer can be made of a high dielectric constant material or other materials commonly used in the art for gate dielectric layers, such as hafnium dioxide, silicon dioxide, and aluminum oxide.

[0135] The first gate 611 can be made of a conductive material capable of storing charge, such as doped polycrystalline silicon, but this application is not limited to this; tungsten, doped single-crystal silicon, molybdenum, or titanium nitride can also be used, as long as the material of the first gate 611 can achieve charge storage. The material of the second gate material layer 621 includes oxide semiconductor or titanium nitride, and can be the same as or different from the material of the first gate 611. The materials of the first drain 311, the first source 321, and the conductor layer 341 can be the same as or different from the materials of the second branch line 331.

[0136] See Figures 2 to 6As shown, the first signal line 312 can be used as the read word line RWL, the second signal line 322 can be used as the read bit line RBL, the third signal line can be used as the write bit line WBL, and the fourth signal line can be used as the write word line WWL. It is understood that the connection relationships between the write word line WWL, the write bit line WBL, and the write transistor 20 are interchangeable, as are the connection relationships between the read word line RWL, the read bit line RBL, and the read transistor 10. Furthermore, the operation methods for the write word line WWL, the write bit line WBL, the read word line RWL, and the read bit line RBL during storage operations are also changed accordingly. This invention does not impose specific limitations on these methods.

[0137] The memory cell alters the charge in the gate capacitance of the read transistor 10 by writing to the write transistor 20, thereby affecting the resistance state between the source and drain of the read transistor 10, and thus distinguishing between "0" and "1". It is understood that in this embodiment, the gate capacitance of the read transistor 10 is... Figure 5 Storage node A in the middle.

[0138] The specific storage principle of the storage unit is as follows:

[0139] During the writing of a "1", the write word line WWL applies a positive voltage (greater than the threshold voltage Vth) to the gate of the write transistor 20, causing the write transistor 20 to turn on. The write bit line WBL applies a positive voltage to the source of the write transistor 20, affecting the gate capacitance of the read transistor 10 (i.e., Figure 5 Inject charge into memory node A. After charge injection, remove the gate and source voltages of write transistor 20, and retain the "1" state;

[0140] During the process of reading "1", the read word line RWL is connected to the source of the read transistor 10 with a read voltage. Since there is a certain charge in the gate capacitor, the read transistor 10 is in a low resistance state. The read bit line RBL receives a large current, which can be amplified and identified by the external circuit to complete the process of reading "1".

[0141] During the writing of a "0", the write word line WWL applies a positive voltage (greater than the threshold voltage Vth) to the gate electrode of the write transistor 20, turning it on. The write bit line WBL applies a negative voltage to the source of the write transistor 20 to draw charge from the gate capacitance (i.e., the storage node) of the read transistor 10. After the charge is drawn, the gate and source voltages of the write transistor 20 are removed, preserving the "0" state.

[0142] During the process of reading "0", the read word line RWL is connected to the source of the read transistor 10 with a read voltage. Since there is no charge in the gate capacitor, the read transistor 10 is in a high resistance state. The read bit line RBL receives a small current, which can be amplified and identified by the external circuit to complete the reading of "0".

[0143] This application also provides a method for manufacturing a storage device, used to manufacture the storage device disclosed above. See also Figure 7 As shown, see Figures 7 to 15 As shown, the method for manufacturing the storage device includes:

[0144] S100: A stacked structure is formed on one side of the substrate 100. The stacked structure includes a first insulating layer 210 and a first lead layer and a second lead layer spaced apart within the first insulating layer 210. The second lead layer is located on the side of the first lead layer away from the substrate 100. The first lead layer includes a first drain 311 and the second lead layer includes a first source 321.

[0145] S200: An accommodating hole 211 is formed on the side of the stacked structure away from the substrate 100;

[0146] S300: At least a portion of the sidewall of the receiving hole 211 is formed with a first channel 411, the first channel 411 connecting the first drain 311 and the first source 321;

[0147] S400: Form a first gate dielectric layer 511 that at least covers the first channel 411;

[0148] S500: A first gate 611 is formed on the side of the first gate dielectric layer 511 in the accommodating hole 211 away from the first channel 411;

[0149] S600: A second channel 421 and a second source 422 are formed on the side of the first gate 611 away from the substrate 100, and the second channel 421 is at least partially located in the accommodating hole 211;

[0150] S700: A second gate dielectric layer 521 and a second gate are sequentially formed on the side of the second channel 421 away from the substrate 100. The first gate 611, the first channel 411, the first drain 311 and the first source 321 constitute a read transistor 10. The second gate, the second channel 421 and the second source 422 constitute a write transistor 20.

[0151] S800: A second insulating layer 220 is formed that at least covers the second gate and the second source 422.

[0152] In this embodiment, the first channel 411 and the first gate 611 of the read transistor 10, and the second channel 421 and the second gate of the write transistor 20 are formed in the same accommodating hole 211, forming a stacked vertical channel dual transistor memory cell. Compared with a memory cell using two horizontal channels connected on the same plane, the memory cell area is reduced and the transistor integration density is improved.

[0153] In some embodiments, when forming the stacked structure in step S100, a first insulating material layer, a first lead layer, a second insulating material layer, a second lead layer, and a third insulating material layer may be formed sequentially on the substrate 100. The first lead layer further includes a first signal line 312 connected to the first drain 311, and the second lead layer further includes a second signal line 322 connected to the first source 321. The first signal line 312 and the second signal line 322 extend in different directions. For example, the first signal line 312 may extend along the X direction, and the second signal line 322 may extend along the Y direction.

[0154] The first signal line 312 is arranged on the same layer as the first drain 311, and the second signal line 322 is arranged on the same layer as the first source 321, which can reduce the manufacturing cost of the storage device.

[0155] In some embodiments, the orthographic projection of the accommodating via 211 onto the substrate 100 lies within the orthographic projection of the first drain 311 onto the substrate 100; the orthographic projection of the accommodating via 211 onto the substrate 100 lies within the orthographic projection of the first source 321 onto the substrate 100; and the orthographic projection of the accommodating via 211 onto the substrate 100 lies within the orthographic projection of the second source 422 onto the substrate 100. The accommodating via 211 is formed by dry etching and penetrates the first drain 311.

[0156] The accommodating aperture 211 penetrates the first drain 311, allowing the subsequently formed first gate 611 to overlap more with the drain end of the first channel 411 in the depth direction of the accommodating aperture 211, thereby improving the control capability of the first gate 611 over the first channel 411 and increasing the read margin. The first channel 411 can be formed only on the sidewall of the accommodating aperture 211, making the fabrication process of the first channel 411 simpler.

[0157] In some embodiments, forming a first channel 411 at least in a portion of the sidewall of the receiving hole 211 includes:

[0158] At least a first channel material layer is formed on the inner wall of the receiving hole 211;

[0159] The first channel material layer is etched by dry etching to remove at least a portion of the first channel material layer at the bottom of the receiving hole 211, forming a first channel layer 410 covering the sidewall of the receiving hole 211. The upper surface of the first channel layer 410 near the second insulating layer 220 is flush with or spaced from the upper surface of the first insulating layer 210 near the second insulating layer 220. The first channel layer 410 includes the first channel 411.

[0160] The first channel layer 410 is formed on the entire sidewall of the receiving hole 211. Compared with the scheme where the first channel layer 410 is formed on a portion of the sidewall of the receiving hole 211, the manufacturing process of the first channel layer 410 is simpler and can reduce the manufacturing cost of the storage device.

[0161] Accordingly, in step S400, forming a first gate dielectric layer 511 that at least covers the first channel 411 includes forming a first gate dielectric material layer that covers the first channel layer 410, the first gate dielectric material layer including the first gate dielectric layer 511.

[0162] In some embodiments, in step S500, forming a first gate 611 on the side of the first gate dielectric layer 511 in the accommodating hole 211 away from the first channel 411 includes: depositing a first gate material layer to fill the accommodating hole 211 formed in step S400, and then etching back to form the first gate 611. Preferably, the top surface of the first gate 611 is slightly higher than the upper surface of the first source 321, which allows the subsequently formed first gate 611 to overlap more with the source end of the first channel 411 in the depth direction of the accommodating hole 211, thereby improving the control capability of the first gate 611 over the first channel 411 and improving the read margin.

[0163] In some embodiments, in step S600, forming a connected second channel 421 and a second source 422 on the side of the first gate 611 away from the substrate 100 includes: Figure 12 As shown, in the receiving hole 211 formed in step S500, a second channel material layer is deposited, and then as follows... Figure 13 As shown, a patterned second channel material layer is formed to create a second channel 421 and a second source electrode 422.

[0164] In some embodiments, when patterning the second channel material layer, the etching stops in the first gate dielectric material layer to ensure that the second channel material layer is cut off during patterning to avoid short circuits; preferably, the etching stops in the first insulating layer 210 to further reduce the difficulty of controlling the etching process during patterning.

[0165] In some embodiments, see Figure 16 As shown, the first gate dielectric layer 511 covers the first channel layer 410. Before forming the second gate dielectric layer 521, the method for fabricating the memory device includes:

[0166] A dielectric layer is formed within the accommodating aperture 211 and on the side of the first gate 611 away from the substrate 100;

[0167] A first via 711 is formed on the dielectric layer by dry etching, forming a dielectric portion 710 that at least covers the portion of the first gate dielectric layer 511 located inside the accommodating via 211. The first via 711 exposes a portion of the upper surface of the first gate 611.

[0168] A second channel 421 is formed, which passes through the first via 711 and connects to the first gate 611.

[0169] Given a fixed inner diameter of the accommodating via 211, the inner diameter of the first via 711 is related to the radial thickness of the dielectric portion 710. The preferred method for fabricating the dielectric layer is a deposition process with good step coverage, such as ALD (Atomic Layer Deposition), which ensures high uniformity of the dielectric layer thickness on the deposition surface. By controlling the deposition thickness of the dielectric layer, the inner diameter of the first via 711 is controlled. This prevents the inner diameter of the first via 711 from being too small, which would make the manufacturing process difficult when the second channel 421 connects to the first gate 611 via the first via 711 in the dielectric portion 710. Conversely, preventing the inner diameter of the first via 711 from being too large would result in an excessively close distance between the two channels and an increase in parasitic capacitance.

[0170] Since the first channel layer 410 is formed on the entire sidewall of the receiving hole 211, the second channel 421 is at least partially located within the receiving hole 211, and the portion of the second channel 421 located within the receiving hole 211 is located within the first channel layer 410. The second channel 421 and the first channel layer 410 overlap in the vertical direction. The dielectric portion 710 provided between the second channel 421 and the first channel layer 410 can reduce the parasitic capacitance between the two channel layers and decrease the mutual interference between the read transistor 10 and the write transistor 20.

[0171] For example, the aperture of the first via 711 at the end furthest from the first gate 611 is greater than or equal to the aperture of the first via 711 at the end closest to the first gate 611, to facilitate the filling of the second channel material layer. The aperture of the first via 711 at the end closest to the first gate 611 is greater than or equal to 20 nanometers. The second channel material layer is fabricated using an atomic layer deposition process.

[0172] Since the second channel 421 passes through the first via 711 and is connected to the first gate 611, the material layer of the second channel is made by atomic layer deposition process. The film layer formed by atomic layer deposition process has good coverage of the steps, which can improve the yield of the memory device.

[0173] In some embodiments, forming a connected second channel 421 and a second source 422 on the side of the first gate 611 away from the substrate 100 includes:

[0174] A second channel material layer is formed on the side of the first gate 611 away from the substrate 100;

[0175] The second channel material layer is etched to form the second channel 421 and the second source electrode 422.

[0176] The second source 422 and the second channel 421 are arranged on the same layer, which can reduce the manufacturing cost of the storage device.

[0177] In some embodiments, etching the second channel material layer to form the second channel 421 and the second source 422 includes:

[0178] A first branch line 423 is formed and connected to the second source 422, and the first branch line 423 constitutes the third signal line.

[0179] The second channel 421, the second source 422, and the first branch line 423 are arranged on the same layer, which can reduce the manufacturing cost of the storage device.

[0180] In some embodiments, forming a second gate dielectric layer 521 and a second gate sequentially on the side of the second channel 421 away from the substrate 100 includes:

[0181] A second gate dielectric layer 521 is formed that at least covers the second channel 421;

[0182] A second gate and a fourth signal line are formed in connection. The second gate is located on the side of the second gate dielectric layer 521 away from the substrate 100. The fourth signal line and the third signal line extend in different directions.

[0183] The first signal line 312 and the second signal line 322 extend in different directions, and the fourth signal line and the third signal line extend in different directions. Through the intersection of the first signal line 312 and the second signal line 322, and the intersection of the third signal line and the fourth signal line, the storage unit is located at the intersection point where the first to fourth signal lines are connected, which can realize the function of selecting the storage unit for reading and writing.

[0184] In some embodiments, the material of the second channel 421 includes an oxide semiconductor, such as indium oxide, zinc oxide, or gallium oxide. After forming a second insulating layer 220 that at least covers the second gate and the second source 422, a method for fabricating the memory device includes:

[0185] A second branch line 331 is formed on the side of the second insulating layer 220 away from the substrate 100. The second branch line 331 is connected to the second source electrode 422 through a second via. The first branch line 423 and / or the second branch line 331 constitute a third signal line. The material of the second branch line 331 includes tungsten, molybdenum, titanium nitride, doped polycrystalline silicon, or doped monocrystalline silicon.

[0186] When the material of the second channel 421 is an oxide semiconductor, the second branch line 331 is made of materials with good conductivity such as tungsten, molybdenum, titanium nitride, doped polycrystalline silicon or doped single-crystal silicon, which can reduce the impedance of the third signal line and reduce the signal delay on the third signal line.

[0187] The terms "first," "second," etc., are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the number of technical features indicated. Therefore, a feature defined with "first," "second," etc., may explicitly or implicitly include one or more of that feature. In the description of this application, "multiple" means two or more, unless otherwise explicitly specified.

[0188] In this application, unless otherwise expressly specified and limited, the terms "assembly," "connection," etc., should be interpreted broadly. For example, they can refer to a fixed connection, a detachable connection, or an integral part; they can refer to a mechanical connection or an electrical connection; they can refer to a direct connection or an indirect connection through an intermediate medium; they can refer to the internal communication of two components or the interaction between two components. Those skilled in the art can understand the specific meaning of the above terms in this application according to the specific circumstances.

[0189] In the description of this specification, references to terms such as "some embodiments," "exemplarily," etc., indicate that a specific feature, structure, material, or characteristic described in connection with that embodiment or example is included in at least one embodiment or example of this application. The illustrative expressions of the above terms in this specification do not necessarily refer to the same embodiment or example. Furthermore, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. Moreover, without contradiction, those skilled in the art can combine and integrate the different embodiments or examples described in this specification, as well as the features of different embodiments or examples.

[0190] Although embodiments of this application have been shown and described above, it is understood that the above embodiments are exemplary and should not be construed as limiting this application. Those skilled in the art can make changes, modifications, substitutions and variations to the above embodiments within the scope of this application. Therefore, any changes or modifications made in accordance with the claims and description of this application should fall within the scope of this patent application.

Claims

1. A memory device, comprising: The memory device layer includes: An insulating layer including a first insulating layer and a second insulating layer vertically stacked; At least one memory cell, the memory cell including a read transistor and a write transistor, the read transistor including a first gate, a first gate dielectric layer, a first channel, a first drain and a first source, the first insulating layer being provided with a receiving hole on a side close to the second insulating layer, the first channel being formed at least in a partial region of a sidewall of the receiving hole, the first drain and the first source being provided at intervals outside the receiving hole, the first drain being located on a side of the first source away from the second insulating layer, the first drain and the first source being connected to the first channel, the first gate dielectric layer covering at least the first channel, the first gate being formed in the receiving hole and located on a side of the first gate dielectric layer away from the first channel; The write transistor includes a second gate, a second gate dielectric layer, a second channel and a second source, the second channel being located at least partially in the receiving hole, a drain end of the second channel being connected to the first gate, the second source being connected to the second channel, the second gate being formed on a side of the second channel away from the first gate dielectric layer, the second gate dielectric layer being formed between the second gate and the second channel.

2. The memory device of claim 1, wherein, The first gate close to the upper surface of the second insulating layer is located between the first insulating layer close to the upper surface of the second insulating layer and the lower surface of the first source away from the second insulating layer.

3. The memory device of claim 2, wherein, A normal projection of the receiving hole on the substrate is located within a normal projection of the first drain on the substrate, a normal projection of the receiving hole on the substrate is located within a normal projection of the first source on the substrate, and a normal projection of the receiving hole on the substrate is located within a normal projection of the second source on the substrate, the first channel surrounds the first gate, the second gate is at least partially located in the receiving hole, and at least a part of the second channel surrounds the second gate in the part of the receiving hole.

4. The storage device according to one of claims 1 to 3, characterized in that The memory device layer includes a first channel layer and an isolation portion, the first channel layer being formed on a sidewall of the receiving hole, the first channel layer including the first channel and an extension portion, an upper surface of the first source close to the second insulating layer being an upper surface of the first source, the first channel being located on a side of the upper surface of the first source away from the second insulating layer, the extension portion being located on a side of the upper surface of the first source close to the second insulating layer, an upper surface of the extension portion close to the second insulating layer being flush with or spaced apart from an upper surface of the first insulating layer close to the second insulating layer, the isolation portion being formed between the extension portion and the second channel.

5. The memory device of claim 4, wherein, The isolation portion includes a dielectric portion, the dielectric portion being formed in the receiving hole and located on a side of the first gate close to the second insulating layer, the dielectric portion having a first via hole, the second channel passing through the first via hole to be connected to the first gate; and / or The first gate dielectric layer also covers the extension, and the isolation portion includes a portion of the first gate dielectric layer covering the extension; The isolation portion includes the dielectric portion and the portion of the first gate dielectric layer covering the extension, and the dielectric portion is located on a side of the first gate dielectric layer away from the first channel layer.

6. The memory device of claim 5, wherein, The material of the dielectric portion includes a low dielectric constant material.

7. The memory device of claim 5, wherein, The first via and the accommodating hole are coaxially arranged.

8. The memory device of claim 5, wherein, The aperture of the first via away from the first gate is greater than or equal to the aperture of the first via close to the first gate, and the aperture of the first via close to the first gate is greater than or equal to 20 nanometers; and / or The inner diameter of the accommodating hole is 50 nanometers to 500 nanometers.

9. The memory device of claim 3, wherein, The memory device layer includes a first channel layer, the first channel layer is formed on the sidewall of the accommodating hole, the first channel layer includes the first channel and an extension, the upper surface of the first source electrode close to the surface of the second insulating layer is an upper surface of the first source electrode, the first channel is located on a side of the upper surface of the first source electrode away from the second insulating layer, the extension is located on a side of the upper surface of the first source electrode close to the second insulating layer, the upper surface of the extension close to the second insulating layer has a predetermined distance from the upper surface of the first insulating layer close to the second insulating layer, and the second channel and the first channel layer form a gap in the depth direction of the accommodating hole.

10. The memory device of claim 3, wherein, The first gate dielectric layer covers the first channel and the bottom of the accommodating hole, the accommodating hole extends to the upper surface of the first drain electrode close to the second insulating layer, or the accommodating hole extends into the first drain electrode, or the accommodating hole penetrates through the first drain electrode.

11. The memory device of claim 1, wherein, The memory device layer further includes a first signal line, a second signal line, a third signal line, and a fourth signal line, the first signal line and the second signal line are both located in the first insulating layer and have different extension directions, the first signal line is connected with the first drain electrode, the second signal line is connected with the first source electrode, the fourth signal line is located in the second insulating layer, the third signal line and the fourth signal line have different extension directions, the third signal line is connected with the second source electrode, and the fourth signal line is connected with the second gate electrode.

12. The memory device of claim 11, wherein, The first signal line and the first drain electrode are arranged in the same layer, the second signal line and the first source electrode are arranged in the same layer, and the fourth signal line and the second gate electrode are arranged in the same layer or the fourth signal line is arranged on a side of the second gate electrode away from the first gate electrode.

13. The memory device of claim 12, wherein, The fourth signal line and the second gate electrode are arranged in the same layer, the fourth signal line has a laminated structure, the laminated structure includes a second gate electrode material layer in contact with the second gate dielectric layer, and a conductor layer located on a side of the second gate electrode material layer away from the second gate dielectric layer.

14. The memory device of claim 11, wherein, The third signal line includes a first branch line, the first branch line, the second source electrode, and the second channel are arranged in the same layer and connected; and / or The third signal line comprises a second branch line, the second branch line is arranged on the side of the second insulating layer away from the first insulating layer, and the second branch line is connected with the second source electrode through a second via hole.

15. The memory device of claim 14, wherein, The material of the second channel comprises an oxide semiconductor, and the material of the second branch line comprises tungsten, molybdenum, titanium nitride, doped polysilicon or doped monocrystalline silicon.

16. A method of fabricating a memory device, comprising: Comprise: A stack structure is formed on one side of a substrate, the stack structure comprises a first insulating layer and a first lead layer and a second lead layer which are arranged in the first insulating layer in a spaced manner, the second lead layer is located on the side of the first lead layer away from the substrate, the first lead layer comprises a first drain electrode, and the second lead layer comprises a first source electrode; A containing hole is formed on the side of the stack structure away from the substrate; A first channel is formed at least in a partial region of a sidewall of the containing hole, the first channel connects the first drain electrode and the first source electrode; A first gate dielectric layer covering at least the first channel is formed; A first gate electrode is formed on the side of the first gate dielectric layer in the containing hole away from the first channel; A second channel and a second source electrode connected with each other are formed on the side of the first gate electrode away from the substrate, and the second channel is at least partially located in the containing hole; A second gate dielectric layer and a second gate electrode are sequentially formed on the side of the second channel away from the substrate, the first gate electrode, the first channel, the first drain electrode and the first source electrode constitute a read transistor, and the second gate electrode, the second channel and the second source electrode constitute a write transistor; A second insulating layer covering at least the second gate electrode and the second source electrode is formed.

17. The method according to claim 16, wherein The first channel formed at least in a partial region of a sidewall of the containing hole comprises: A first channel material layer is formed at least on an inner wall of the containing hole; The first channel material layer is etched by a dry etching method to remove at least part of the first channel material layer at the bottom of the containing hole, so as to form a first channel layer covering the sidewall of the containing hole, the first channel layer is flush with or forms a spacing with the upper surface of the first insulating layer close to the upper surface of the second insulating layer, and the first channel layer comprises the first channel.

18. The method according to claim 17, wherein The first gate dielectric layer covers at least the first channel layer, and before the second gate dielectric layer is formed, the manufacturing method of the storage device comprises: A dielectric layer is formed in the containing hole and on the side of the first gate electrode away from the substrate; A first via hole is formed on the dielectric layer by dry etching the dielectric layer, so as to form a dielectric part covering at least the part of the first gate dielectric layer in the containing hole, and the first via hole exposes the first gate electrode; The second channel is formed so as to be connected with the first gate electrode through the first via hole.

19. The method according to claim 18, wherein The second channel material layer is manufactured by an atomic layer deposition process.

20. The method according to claim 16, wherein The second channel and the second source electrode connected with each other on the side of the first gate electrode away from the substrate comprise: A second channel material layer is formed on the side of the first gate electrode away from the substrate; The second channel material layer is etched to form the second channel and the second source electrode.

21. The method according to claim 20, wherein The stack structure formed on one side of a substrate comprises: The first insulating material layer, the first lead layer, the second insulating material layer, the second lead layer and the third insulating material layer are sequentially stacked on the substrate, the first lead layer comprises a first signal line connected with the first drain electrode, the second lead layer comprises a second signal line connected with the first source electrode, and the first signal line and the second signal line extend in different directions; The etching of the second channel material layer to form the second channel and the second source electrode comprises forming a first branch line connected with the second source electrode; and / or, after the forming of the second insulating layer covering at least the second gate electrode and the second source electrode, the manufacturing method of the storage device comprises forming a second branch line on a side of the second insulating layer away from the substrate, the second branch line being connected with the second source electrode through a second via, and the first branch line and / or the second branch line forming a third signal line; The sequentially forming of the second gate dielectric layer and the second gate electrode on a side of the second channel away from the substrate comprises: forming the second gate dielectric layer covering at least the second channel; forming the second gate electrode and a fourth signal line connected with each other, the second gate electrode being located on a side of the second gate dielectric layer away from the substrate, and the fourth signal line and the third signal line extending in different directions.

22. The method according to claim 16, wherein The normal projection of the accommodating hole on the substrate is located within the normal projection of the first drain electrode on the substrate, the normal projection of the accommodating hole on the substrate is located within the normal projection of the first source electrode on the substrate, and the normal projection of the accommodating hole on the substrate is located within the normal projection of the second source electrode on the substrate, the accommodating hole is formed by dry etching, and the accommodating hole penetrates the first drain electrode.

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