Plasma doping of gap fill material

Abstract

The invention relates to plasma doping of gap fill materials. In various processes for forming electronic devices using spin-on dielectric materials, the properties of the spin-on dielectric materials may be enhanced by curing these materials using plasma doping. For example, the hardness and Young's modulus of the cured material may be increased. Other properties may be enhanced. The plasma doping that cures the spin-on dielectric material uses a mechanism as a combination of a plasma ion implant and high energy radiation associated with the ionized species. In addition, physical properties of the spin-on dielectric material may be modified along the length of the spin-on dielectric material by selecting an implant energy and a dopant dose of a particular dopant used corresponding to a change in selection with respect to the length.

Description

[0001] Information about divisional applications

[0002] This application is a divisional application of the invention patent application with application date of December 28, 2020, application number 202011582142.5, and invention name “Plasma doping of gap filling materials”.

[0003] Priority application

[0004] This application claims the benefit of priority to U.S. Provisional Application Serial No. 62 / 955,814, filed on December 31, 2019, which is incorporated herein by reference in its entirety. Technical Field

[0005] Embodiments of the present invention generally relate to the fabrication of electronic devices and fabricated electronic devices, and more particularly, to electronic devices and forming electronic devices using plasma doping. Background Art

[0006] Memory devices are typically provided as internal semiconductor integrated circuits in computers or other electronic devices. There are many different types of memory, including volatile and non-volatile memory. Volatile memory requires power to maintain its data, and includes random access memory (RAM), dynamic random access memory (DRAM), or synchronous dynamic random access memory (SDRAM), etc. Non-volatile memory can retain stored data when not powered, and includes flash memory, read-only memory (ROM), electrically erasable programmable ROM (EEPROM), erasable programmable ROM (EPROM), resistance variable memory (such as phase change random access memory (PCRAM)), resistive random access memory (RRAM), magnetoresistive random access memory (MRAM), or three-dimensional (3D) XPoint TM Memory, etc. 3D X-Point memory is a non-volatile memory (NVM) technology with a stackable cross-grid data access array, where bit storage is based on changes in bulk resistance.

[0007] Flash memory is used in various electronic applications as non-volatile memory. Flash memory devices typically include one or more groups of single transistor, floating gate, or charge trap memory cells that allow high memory density, high reliability, and low power consumption. Two common types of flash memory array architectures include NAND and NOR architectures, which are named after the logical form in which the basic memory cell configuration of each is arranged. The memory cells of the memory array are typically arranged in a matrix. In an example, the gate of each floating gate memory cell in a row of the array is coupled to an access line (e.g., a word line). In a NOR architecture, the drain of each memory cell in a column of the array is coupled to a data line (e.g., a bit line). In a NAND architecture, the drain of each memory cell in a string of the array is coupled in series (source to drain) between a source line and a bit line. Summary of the invention

[0008] One embodiment of the present invention provides a method comprising: forming a spin-on dielectric as a dielectric providing electrical isolation in an electronic device; and curing the spin-on dielectric by plasma doping (PLAD) the spin-on dielectric.

[0009] Another embodiment of the present invention provides a method comprising: forming a carbon-rich spin-on dielectric (C-SOD) as a dielectric providing electrical isolation in an electronic device; and curing the C-SOD by subjecting the C-SOD to a combination of a plasma ion implant providing a photon energy greater than 10 eV and a species of the plasma ion implant.

[0010] Yet another embodiment of the present invention provides a memory device comprising: a three-dimensional memory array; and a dielectric film that provides electrical isolation in the memory array, the dielectric film comprising a spin-on dielectric (SOD) as a dielectric between stacks of memory cells of the memory array, wherein the SOD comprises carbon and plasma implanted ions. BRIEF DESCRIPTION OF THE DRAWINGS

[0011] The drawings, which are not necessarily drawn to scale, generally illustrate the various embodiments discussed herein by way of example and not by way of limitation.

[0012] Figure 1 is a block diagram representing an arrangement of a vertical 3D stack of X-Point memory devices according to various embodiments.

[0013] Figure 2 is a representation of a portion of two stacks in a 3D X-Point device with the two stacks separated and covered by a dielectric gap filler in accordance with various embodiments.

[0014] Figure 3is another representation of a portion of two stacks in a 3D X-Point device having two stacks separated and covered by a dielectric gap filler in accordance with various embodiments.

[0015] Figure 4 is a representation of a portion of multiple stacks in a 3D X-Point device having multiple stacks separated and covered from each other by dielectric gap fillers according to various embodiments.

[0016] Figure 5 is a representation of an apparatus for plasma doping of wafers according to various embodiments.

[0017] Figure 6 A table showing experimental results of solidifying C-SOD using conventional methods and different PLAD methods according to various embodiments.

[0018] Figure 7 A table showing experimental results of solidifying C-SOD using conventional methods and different PLAD methods according to various embodiments.

[0019] Figure 8 A table showing density distribution from X-ray reflectometry (XRR) measurements on SiOC SOD according to various embodiments.

[0020] Figures 9A to 9C Three cases associated with parameter sets for PLAD of C-SOD according to various embodiments are shown.

[0021] Fig.10 Stopping and Range of Ions in Material (SRIM) simulations of He concentration distribution according to various embodiments are shown.

[0022] Fig.11 is a flow chart of features of an example method of making a dielectric film in an electronic device according to various embodiments.

[0023] Fig.12 is a flow chart of features of an embodiment of an example method of making a dielectric film in an electronic device according to various embodiments.

[0024] Fig.13 A block diagram of an example system including a memory structured with a three-dimensional memory array such that a dielectric film in the memory array includes a PLAD-cured SOD is shown in accordance with various embodiments. DETAILED DESCRIPTION

[0025] The following detailed description refers to the accompanying drawings that illustrate various embodiments that may be implemented. These embodiments are described in sufficient detail to enable those of ordinary skill in the art to practice these and other embodiments. Other embodiments may be utilized, and structural, logical, mechanical, and electrical changes may be made to these embodiments. The various embodiments are not necessarily mutually exclusive, as some embodiments may be combined with one or more other embodiments to form new embodiments. Therefore, the following detailed description should not be understood in a limiting sense.

[0026] Spin coating deposition in electronic device manufacturing is a process of applying a material to a wafer, wherein the material is initially dispensed on the wafer in liquid form and the wafer is rotated to achieve uniform distribution of the material and then the material solidifies by low temperature (e.g., <200° C.) bisque firing. Spin coating materials are used as dielectric gap fillers for narrow and high aspect ratio trench filling in both shallow trench isolation (STI) and pre-metal dielectric application in electronic devices due to their good gap filling properties. For example, in several three-dimensional (3D) memories, there are columns of selectable memory cells, where there are gaps between the columns that electrically isolate the individual columns in the columns when manufactured, although in some architectures, conductive plate-like structures may connect portions of some of the columns based on the corresponding architecture. The gap is filled with a dielectric material, wherein this dielectric material is called a dielectric gap filler or gap filler. The spin-on dielectric (SOD) of the gap filler may include materials such as silicates, siloxanes, silazanes, or silsesquioxanes. SOD also includes spin-on glass (SOG) and spin-on dielectric polymers. For example, the cross-point (X-Point) memory device uses a carbon-rich spin-on dielectric (C-SOD) film to fill the gaps between the stacks at the access lines WL such as word lines and at the data lines BL such as bit lines to eliminate the gaps for better filling. This C-SOD film can provide sufficient density at low temperatures. For the purpose of this description, a low carbon (C atomic %) SOD is a SOD with a C content of 10 to 30%, and a carbon-rich SOD is a SOD with a C content of 30 to 60%. The content is in atomic percentage, where C% is the atomic percentage of carbon content, which can be detected by X-ray photoelectron spectroscopy (XPS). For example, in a SiOC composition, the atomic percentages of C, Si, and O add up to a total of 100%.

[0027] An organic low-k dielectric C-SOD material for X-Point WL or BL trench filling includes SiO xAdd about 50% carbon (C) plus porosity (silsesquioxane derivative). Low-k dielectrics are dielectrics with a dielectric constant lower than that of SiO2 (k<3.9), and high-k dielectrics are dielectrics with a dielectric constant greater than that of SiO2 (k>3.9). Organic SODs (C-based) can have k values ​​ranging from 2.65 to 3.1, while C-free inorganic SODs have k values ​​ranging from 5.6 to 7.9. C-SOD films can vary depending on the percentage of carbon, the stoichiometry of silicon oxide, and porosity.

[0028] In addition, SOD filler materials have demonstrated tunable thermal conductivity, where this thermal conductivity is approximately 0.14 Wm -1 K -1 1.3Wm for SiOC2 -1 K -1 Compared with conventional SiO x This relatively low thermal conductivity of the SOD filler material compared to fillers such as tetraethyl orthosilicate (TEOS) reduces thermal crosstalk (TD) problems during cell operation by providing a balanced thermal barrier among nearest neighbor cells. Tunability can be provided by selection of materials and processing parameters.

[0029] However, the deposited or thermally cured SOD (e.g., C-SOD having about 50% carbon together with SiO x , where x>1) will typically present integration challenges in terms of chemical mechanical polishing (CMP) and etching during device processing. The challenges include weak mechanical strength with a modulus of approximately 6 GPa. Adhesion and bonding failures, such as CMP cracks (cracks are materials that break during the CMP process, which may include sharp-pointed geometries), have been observed. In addition, the deposited or thermally cured SOD is typically susceptible to chemical attack and has poor selectivity with respect to carbon, which makes it susceptible to post-processing, such as post-processing resulting in porous materials. Curing is a process during which a chemical reaction such as polymerization or a physical action such as evaporation occurs to produce a harder, tougher or more stable bond (or substance). In polymer chemistry and process design, curing is a chemical process that produces toughening or hardening of a polymer material by cross-linking of polymer chains. Cross-linking is the bonding of a polymer chain to another polymer chain. In addition, during CMP, there is a large amount or direct adhesion failure in the C-SOD stack treated with tetramethylamide hydroxide (TMAH).

[0030] Another challenge is the alignment mark damage at the CMP location. Due to the surface topography, the bottom filling problem of the C-SOD filling after the alignment mark is more serious. The C-SOD filler can be lower than the alignment mark of the array height. The alignment mark surface topography of the feature width can cause the C-SOD bottom filling. For the C-SOD film treated with TMAH and ultraviolet (UV), the bottom filling is worse.

[0031] In addition to process issues, C-SOD films are generally considered to be the root cause of reduced cell programming window and performance degradation. Hydrogen (H), moisture or steam poisoning on the phase change (PM) region is considered to be the mechanism for these process issues. As an example, the PM region, which may be implemented as a chalcogenide-based phase change region, may be arranged as a memory element of a phase change memory (PCM) device; and other memory storage technologies such as variable resistance memory technology may have memory elements (sometimes again including chalcogenide materials) that may be subject to such damage or degradation.

[0032] The mitigation of integration problems can be achieved by improving the physical stability of C-SOD including mechanical strength and adhesion and the chemical stability including dry or wet etching properties. Curing in a current furnace at 200°C in a N2 environment for two hours, the total process time can be greater than an hour at a processing rate of more than 3 minutes / wafer. This furnace curing can provide appropriate crosslinking in the case of H2O removal (dehydration). However, this curing results in the material having insufficient mechanical strength, a Young's modulus of 6GPa. In addition, furnace curing has low throughput (T-put) and high cost. In contrast, in the most known method for ultraviolet (UV) curing under non-oxidizing and oxidizing conditions, a process time of 4 minutes / wafer is achieved. UV curing provides enhanced crosslinking under a mechanical strength improved to a Young's modulus of about 7.5GPa. This may still be insufficient mechanical strength. UV curing has low T-put and high tool integration cost.

[0033] In various embodiments, a method for enhancing the mechanical properties and selective densification of organosilicate SOD materials by plasma doping (PLAD) process is provided. As an example, SOD materials can be formed into array gap filling materials, although other applications are considered. Selective densification can be realized as the selectivity of surface densification relative to body densification. PLAD process is an implantation process different from conventional beamline implantation. SOG or SOD curing can be improved by implantation in post-coating or bisque firing treatment to improve its mechanical strength and modulate its chemical composition, thereby providing a balanced Si / C / O ratio. Mechanical strength can be exhibited by its Young's modulus (E) and hardness (H). Improving the ratio of mechanical strength and balancing components can provide the successful integration of SOD gap fillers in any memory device with respect to mitigating process-related challenges such as CMP and etching. In addition, improving mechanical strength and balancing cost ratio can restore the cycle performance of device units, thereby providing enhanced reliability or durability, improving PM film quality and durability by removing hydrides.

[0034] The PLAD process taught herein can provide high throughput, low cost, low temperature, such as room temperature (RT), processing, and can be used for solidifying C-SOD by the mechanism of the combination of plasma ion implant and high energy radiation associated with the species of the ion dopant used. This method using the PLAD process provides a novel way of cross-linking C-SOD film to improve mechanical, electrical and chemical properties. The selective modification of the surface relative to the body can be implemented by tuning implant energy and ion density in the PLAD process.

[0035] Helium (He) can be used as an implant in the PLAD process to solidify the SOD film. Treatment is provided using He plasma under soft x-ray radiation. Extended ultraviolet (EUV) radiation spectrum provides much higher photon energy 40.81eV (for He II) and 21.22eV (for He I) than the normal UV radiation and photon energy of other plasmas less than 10eV. He I and He II refer to two different ionization states of He. Using higher photon energy will significantly improve C-SOD and unit film properties. At the same time, in-situ He plasma low-energy ion bombardment enhances C-SOD solidification and further improves C-SOD film properties.

[0036] C-SOD curing by PLAD shows significant C-SOD improvements, including much higher near-surface mechanical strength (hardness and Young's modulus), tunable electrical properties, and enhanced chemical and thermal stability, with less volume shrinkage. Based on these property improvements, the current problems of CMP and dry etching processes are minimized and greatly improved.

[0037] Curing SOD by He PLAD can facilitate H removal by high energy radiation to improve cell reliability / durability. This PLAD process can provide significantly higher T-put and low cost because the associated process time is only 1 minute compared to more than three minutes to several hours using conventional processes. Curing by PLAD is not limited to helium implants, but is also applicable to other PLAD implants, including H, nitrogen (N), boron (B), diborane (B2H6), fluoride (F), boron trifluoride (BF3), C, germanium (Ge), etc., such as Figure 6 is shown in Table 640.

[0038] As taught herein, curing SOD by PLAD is not limited to one type of SOD, such as C-SOD, but is also applicable to other SOD materials, including SOG materials and polymers used in shallow trench isolation (STI) gap fill. These materials include, for example, but not limited to, organic SODs and photoimageable SODs with different carbon contents from about 10% to 60% by atomic percentage. SODs cured by PLAD are suitable for DRAM structures with low-k SOD fillers and NAND large area gap (LAG) filler films, including photodefinable UV sensitive gap fillers.

[0039] The PLAD curing of SOD can be applied before or after the CMP planarization of SOD according to the integrated flow in the manufacture of integrated circuits. PLAD can be implemented without any additional integrated changes or architectural changes in the process. The PLAD treatment of SOD gap filling material can be performed as a low temperature process that makes the integration in the low thermal budget memory device feasible. In addition, the PLAD process of SOD gap filling material can be tuned by ion density (dose), bias energy and exposure time. The tunable process can include selecting dose, bias energy or exposure time to modify the physical properties of the formed SOD gap filling material. Selection can be made according to the functional relationship or table relationship between the process parameters and the physical properties of the SOD gap filling material about the length of the formed SOD gap filling material.

[0040] Figure 1 1 is a block diagram representing an arrangement 100 of a vertical 3D stack of X-Point memory devices. X-Point memory devices are non-volatile memories with relatively high endurance because they are not significantly affected by the number of write cycles performed. X-Point memory devices have several columns of thin memory regions, where the thin regions are stacked to provide an increased density of memory cells. Arrangement 100 has a cross-point structure with vertical electrodes connecting sub-microscopic columns. Individual memory cells 105 can be addressed by selecting a top electrode 115 and a bottom electrode 110 coupled to the individual memory cells 105. As shown in FIG. Figure 1 , top electrode 115 is an electrode coupled to more than one memory cell, where the memory cells are coupled to different bottom electrodes. Thus, each memory cell can be addressed by activating one assigned top electrode and one assigned bottom electrode. Each memory cell can store a single bit of data. Arrangement 100 shows a column of two memory cells in a stack, where the top electrode of a memory cell, such as top electrode 115, is the bottom electrode of the memory cell at the top of the stack of two memory cells.

[0041] Each memory cell, such as memory cell 105, may be coupled to one of its assigned electrodes via a selector 120. The selector 120 may be implemented without transistors to enable its associated memory cell to be written or read. The selector 120 may be arranged as a bidirectional threshold switch (OTS). An OTS is a two-terminal symmetrical voltage-sensitive switching device. An OTC may be implemented as a glass switch that returns to a relatively high resistance state after transitioning from a relatively high resistance state to a conductive state in response to the current through the switch dropping below a holding current value.

[0042] In arrangement 100, there are gaps between the columns of stacked memory cells, which are presented for ease of discussion. During the manufacturing process, these gaps can be filled with dielectric gap fillers using SODs. Several SODs can be used, including (but not limited to) SOG. The SOD can be a PLAD cured SOD.

[0043] Figure 2 2 is a representation 200 of a portion of two stacks 201-1 and 201-2 in a 3D X-Point device, wherein the two stacks 201-1 and 201-2 are separated and covered by a dielectric gap filler 202. Each of the stacks is structured in the same manner. The dielectric gap filler 202 may be a PLAD cured SOD. Several SODs may be used, including but not limited to SOG. The dielectric gap filler 202 may be used for array trenches in a 3D X-Point device. The stack 201-1 and thus the stack 201-2 may further include a stack in Figure 2 The segments on the part shown in .

[0044] The stack 201-1 and thus the stack 201-2 are a type of stack including a PM region 205 and a selector device (SD) 220. The stack 201-1 may be arranged vertically on the bottom with an access line 210 such as a word line, wherein a bottom electrode 212 is on the access line 210, an SD 220 is on the bottom electrode 212, and an intermediate electrode 214 is on the SD 220. The PM region 205 is arranged above the intermediate electrode 214 and separated from the intermediate electrode 214 by a thin film region 204. The PM may be a chalcogenide-based PM. Another thin film region 206 may be disposed on the PM region 205, wherein a top electrode 215 is disposed on the thin film region 206. A hard mask (HM) 218 ​​may optionally be disposed above the top electrode 215, wherein the HM 218 may typically be silicon nitride. The stack 201-1 may include a first sealing region 216 and a second sealing region 217. The bottom electrode, the middle electrode, and the top electrode may be implemented using different electrode materials or the same material. The electrode material may include, but is not limited to, carbon. The sheets 204 and 206 may include tungsten. The first sealing region 216 may be silicon nitride 216, and the second sealing region 217 may be silicon nitride. Other dielectric sealing materials may be used.

[0045] Figure 3 300 is a representation of a portion of two stacks 301-1 and 301-2 in a 3D X-Point device, where the two stacks 301-1 and 301-2 are separated and covered by a dielectric gap filler 302. Each of the stacks is structured in the same manner. The dielectric gap filler 302 may be a PLAD cured SOD. Several SODs may be used, including but not limited to SOG. The dielectric gap filler 302 may be used for array trenches in a 3D X-Point device. The stack 301-1 and thus the stack 301-2 may further include a stack in Figure 3 The segments on the part shown in .

[0046] Stack 301-1 and thus stack 301-2 are a type of stack including SD 320 in which there is no PM region. Stack 301-1 may be arranged vertically on the bottom with access line 310, such as a word line, wherein bottom electrode 312 is on access line 310, SD 320 is on bottom electrode 312, and top electrode 315 is on SD 320. HM 318 may optionally be disposed on top electrode 315, wherein HM 318 may typically be silicon nitride. Stack 301-1 may include a first sealing region 316 and a second sealing region 317. The bottom electrode and the top electrode may be implemented using different electrode materials or the same material. The electrode material may include, but is not limited to, carbon. The first sealing region 316 may be silicon nitride 316, and the second sealing region 317 may be silicon nitride. Other dielectric sealing materials may be used.

[0047] Figure 4 401 - 7 in a 3D X-Point device, wherein the multiple stacks are separated from each other and covered by dielectric gap fillers 402. Each of the stacks is structured in the same manner. The dielectric gap filler 402 may be a PLAD cured SOD. Several SODs may be used, including but not limited to SOG. The dielectric gap filler 402 may be used for array trenches in a 3D X-Point device. Although seven stacks are shown, a 3D X-Point may have more or less than seven stacks.

[0048] The stack 401-1 and thus other stacks of 3D X-Point devices may be similar to Figure 2 4. The stack 401-1 may be structured like the stack 201-1 of FIG. 4. The stack 401-1 includes a PM region 405 and a SD 420. The stack 401-1 may be arranged vertically on the bottom with an access line 410, such as a word line, wherein a bottom electrode 412 is on the access line 410, a SD 420 is on the bottom electrode 412, and a middle electrode 414 is on the SD 420. The PM region 405 is arranged above the middle electrode 414 and separated from the middle electrode 414 by a thin sheet region 404. The PM region 405 may be a chalcogenide-based PM. Another thin sheet region 406 may be disposed on the PM region 405, wherein a top electrode 415 is disposed on the thin sheet region 406. A HM structured as regions 419 and 418 may optionally be disposed above the top electrode 415, wherein the HM may typically be silicon nitride. The stack 201-1 may include a sealing region 417. The bottom, middle, and top electrodes may be implemented using different electrode materials or the same material. The electrode material may include, but is not limited to, carbon. Sheets 404 and 406 may include tungsten. Sealing region 417 may be a nitride region. Other dielectric sealing materials may be used.

[0049] although Figures 1 to 4For demonstrating the implementation of PLAD-cured SOD as a dielectric gap filler in a 3D X-Point device, PLAD-cured SOD can be implemented as a dielectric that provides electrical isolation in several other electronic devices. For example, PLAD-cured SOD can be used in DRAM memory and NAND-type memory. In the 3D memory array of SRAM device, low-k SOD can be used to provide electrical isolation. In NAND-type memory array, PLAD-cured SOD can be implemented as SOG disposed in an area with a high aspect ratio. In NAND-type memory array, PLAD-cured SOD can be implemented as SOG disposed in an area with a low aspect ratio. Low aspect ratio structure has a height to width (h / w) ratio less than 10 / 1, and high aspect ratio structure has an h / w ratio greater than 10 / 1. In order to be used in DRAM devices, NAND-type memory devices and other electronic devices, PLAD-cured SODs other than PLAD-cured SOG can be used, such as PLAD-cured carbon-rich SODs.

[0050] Figure 5 5 is a representation of an apparatus 500 for plasma doping of a wafer 503. The apparatus 500 includes a chamber 530 having a showerhead 534 coupled to a gas line 532. Precursors flow into the chamber 530 through the gas line 532 and the showerhead 534. The apparatus 500 includes a radio frequency (RF) generator 536 for forming a plasma 538 above the wafer 503 mounted on a platform that may be configured as a heater 535. The heater may be coupled to a negative potential source 537. Excess gas from the process may be pumped out of the chamber 530 through an exhaust or exit port 538.

[0051] When the RF generator 536 coupled to the showerhead 534 is turned on, the RF power ionizes the dopant gas flowing from the gas line 532 through the showerhead 534. The positive ions are attracted to the negative potential provided by the negative potential source 537 and are accelerated toward the wafer 503. The RF signal is used to dissociate the dopant molecules ionized in the plasma. These ions are accelerated by the negative bias potential provided by the negative potential source 537. The RF generator 536 can provide pulsed plasma doping in the PLAD process. This type of doping can provide high dose, low energy doping, which can be used for ultra-shallow junctions, such as 10 16 cm -2 The PLAD process can provide conformal doping for 3D structures as a non-line-of-sight process applicable to a variety of structures, such as (but not limited to) deep trench sidewalls and FinFet structures. Apparatus 500 can be used for PLAD curing of SOD materials in a wide variety of electronic devices.

[0052] In various embodiments, SOD can be cured using PLAD (herein referred to as He PLAD) with He as dopant ion. He PLAD can be implemented in different formats with respect to one or more of dose, implant energy, pressure, temperature and exposure time. Consider He PLAD radiation under different circumstances. The low pressure of 4mTorr (the pressure of the most known conventional method) can provide radiation from soft X-ray to EUV with violet-blue plasma daughter. The high pressure of 10mTorr (it is 2.5 times higher than 4mTorr) can provide far infrared (IR) radiation with reddish plasma. The low energy of 100V (it is 80 times lower than the most known conventional method energy of 8KV operation) can contribute to "radiation dominant" process. The combination of PLAD and the radiation provided by using He can be changed in the PLAD energy range between 8kV and 100V to find out the optimal process conditions. He II provides a photon energy of 40.81 eV, which is in the soft X-ray range, and He I provides a photon energy of 21.22 eV (He I), which is in the EUV range.

[0053] For example, H + He + Low dose implantation of energetic light ions can be used to improve crosslinking of organosiloxanes, forming Si-O-Si bonds of organosiloxanes to improve mechanical strength. The implanted ions cause homolytic bond cleavage, allowing -Si-O-Si- crosslinks to form. Homolytic bond cleavage is the chemical bond dissociation of a molecule, where each of the fragments retains one of the originally bonded electrons. It is expected that the lighter the ions used, such as H + He + , the stronger the effect. It should be noted that, in contrast, it can be seen that the oxygen-based plasma is damaging the C-SOD and in some cases can remove most of the carbon from the SOD by oxidation. It can also be seen that this oxidizing condition is damaging the chalcogenide memory cell and the sealing dielectric layer. Using the oxygen-based plasma also makes the C-SOD more porous so that it will serve as a reservoir for etch contaminants, post-CMP slurry particles, or aqueous solutions.

[0054] Figure 6 Table 640 showing experimental results of using conventional methods and different PLAD methods to solidify C-SOD. Only furnace process does not use implant tool or implant species. Using BL as the implant tool identification uses the process of implanted beam line. Implant species are defined by the type, implant energy and dosage of dopant. For example, F8k3E15 of line 7 of beamline implant tool is an implant species of fluoride with a dosage of 3E15 under implant energy 8KeV. Group 642 is He PLAD result, which is clearly the best result of the group about hardness and Young's modulus. PLAD process can be extended to Ge, B, C, F and other dopants.

[0055] Figure 7 Table 740 showing the experimental results of using conventional methods and different PLAD methods to solidify C-SOD. UV BKM refers to the best known method for UV treatment. The values ​​of hardness and Young's modulus are averaged at about 250nm, and the values ​​in brackets are surfaces within 20nm. The dry etching rate is in the PMME layer. High energy (8keV) He PLAD can make C-SOD too hard so that the etching rate is about 0, and also has degraded electrical properties. Low energy (E) and very low energy (VLE) He PLAD processes that can be defined as between 1kV and 250V have shown most improvements. Note that ultra-low energy is defined as 250eV and lower. These improvements include better near-surface hardness or Young's modulus properties, better electrical properties, reduced etching rates and acceptable volume shrinkage. These improvements compared to only furnace and UV treatment can provide better near-surface mechanical strength to improve CMP and dry etching problems, and maintain a body region with good chemical or thermal stability.

[0056] Figure 8 Table 840 of density distribution from X-ray reflectometry (XRR) measurement of SiOC SOD is shown. Such measurement provides information for tuning SOD. Tuning can be performed by selecting parameters from the parameter set for the PLAD solidification of SOD. Tuning by using the selected parameter set can be based on the surface modification of the SOD film associated with different parameter sets to body modification. In table 840, G1 to G7 are parameter sets of He PLAD, wherein each set comprises the parameters of implant energy, dosage, time and pressure. In table 840, POR means recording process and p is density. The region of SOD from 0 to 1nm of the vertical end of SOD above substrate and relative to substrate is surface region, and the region from 1 to 4nm of the vertical end is near surface region, and the region exceeding 4nm of the vertical end is the body region of SOD.

[0057] He PLAD using set G1 or set G2 results in the volume of SiOC being densified by He PLAD with the parameters of the corresponding set. He PLAD using the parameters of any of sets G4, G5, G6 and G7 results in the surface of SiOC being densified by HePLAD for the corresponding set, with the bulk remaining in a non-densified state. He PLAD using the parameters of set G3 is a critical result between the sets of the two groups.

[0058] Figures 9A to 9C Showcase and e.g. Figure 8 Table 840 shows three scenarios associated with the parameter set of the PLAD of the C-SOC. Fig. 9AA high energy implant 944 is shown in which the surface region (0-1 nm) and near-surface region (1-4 nm) are softened, while the bulk region is densified. Fig. 9B A low energy, high dose implant 946 is shown in which the surface region (0 to 1 nm), near-surface region (1 to 4 nm), and bulk region undergo virtually no change. Fig. 9C Low and intermediate energy implants 948 are shown in which the surface region (0-1 nm) and near-surface region (1-4 nm) are densified, while the bulk region is not densified.

[0059] Fig.10 1047 shows the He concentration versus depth of a C-SOD with a surface region for CMP. The parameter set (also referred to as a recipe) for He PLAD of the C-SOD in the simulation is a He dopant species for a dose of 1E16 at an implant energy of 1 KeV, the recipe being Fig.10 In addition, He concentration measurement by secondary ion mass spectrometry (SIMS) and nuclear reaction analysis (NRA) can be performed directly at the wafer level of the final product and can be completely non-destructive. The non-destructive process does not include cross-sectioning, assembly, or sample preparation. After removal (e.g., by CMP or direct energy beam (DEB)), He concentrations can be as high as 1E21 / cm 3 According to the X-Point process flow, the top surface of the C-SOD area treated with He-PLAD can be removed by CMP planarization by about 200 to

[0060] Fig.11 1 is a flow chart of features of an embodiment of an example method 1100 for preparing a dielectric film in an electronic device. At 1110, a spin-on dielectric is formed as a dielectric that provides electrical isolation in an electronic device. The spin-on dielectric may be formed as one of several different materials. The spin-on dielectric may be provided as a spin-on glass. The spin-on dielectric may be a carbon-containing spin-on dielectric. The spin-on dielectric may be a carbon-rich spin-on dielectric. The spin-on dielectric may include, but is not limited to, one or more of the following: an organic spin-on dielectric, an organic SOD having different carbon contents from about 10% to 60% by atomic percentage, and a photoimageable SOD.

[0061] At 1120, in manufacturing an electronic device, the spin-on dielectric is cured by plasma doping the spin-on dielectric. The PLAD process may be implemented as an oxygen-free PLAD process. The PLAD process may be implemented using one or more dopant species. PLAD may be implemented using a dopant that is an oxygen-free dopant. PLAD may include doping with helium. The PLAD may include, but is not limited to, doping with one or more of the following: hydrogen, nitrogen, boron, diborane, fluoride, boron trifluoride, carbon, and germanium. The PLAD may include using a dopant that provides a photon energy greater than 10 eV.

[0062] Variations of method 1100 or methods similar to method 1100 may include several different embodiments, which may be combined depending on the application of such methods or the architecture or process flow of the integrated circuit in which such methods are implemented. Such methods may include selectively modifying the physical properties of the spin-on dielectric by applying implant energy and implant dose at levels selected according to the relationship between the implant energy or implant dose and the length of the spin-on dielectric. Selectively modifying the spin-on dielectric of the dielectric gap filler by tuning the implant energy and implant dose may allow the formation of Si-O-Si cross-linked structures. The modification of the physical properties of the SOD may include modification of one or more of thermal properties, optical properties, chemical properties, electrical properties, and mechanical properties. Selectively modifying the spin-on dielectric may include modifying the surface area of ​​the spin-on dielectric relative to the body area of ​​the spin-on dielectric or modifying the body area of ​​the spin-on dielectric relative to the surface area of ​​the spin-on dielectric. Modifying the spin-on dielectric may include densifying the surface area while the body area remains undensified or softening the surface area while the body area is densified. Optical properties such as, but not limited to, refractive index and absorption coefficient can be modified along the length of the spin-on dielectric. Selectively modifying the spin-on dielectric can include using implant energies ranging from 100 eV to 10 KeV. Additionally, carbon-free SODs or inorganic SODs having a dielectric constant in the range of from about 5.6 to about 7.6 can be densified by PLAD curing.

[0063] A variation of method 1100 or a method similar to method 1100 may include subjecting the spin-on dielectric to a chemical mechanical polishing (CMP) process after curing. After curing, the spin-on dielectric may have a Young's modulus of more than 10 GPa provided by the curing for performing the CMP. After curing, the spin-on dielectric may be subjected to dry etching.

[0064] Fig.1212 is a flow chart of features of an embodiment of an example method 1200 of preparing a dielectric film in an electronic device. At 1210, a carbon rich spin-on dielectric (C-SOD) is formed as a dielectric that provides electrical isolation in an electronic device. The C-SOD may be a photo-definable UV sensitive gap filler. The UV sensitive gap filler is a material that is sensitive to UV light, such as, but not limited to, a photoresist material. At 1220, the C-SOD is cured by subjecting the C-SOD to a plasma ion implant that provides a photon energy greater than 10 eV and a combination of species of the plasma ion implant. The selected ion implant dose of the species and implant energy may be selected to provide mechanical strengths such as film hardness and Young's modulus that assist in integrating the film into an electronic device. The species may include one or more of the following: helium, hydrogen, nitrogen, boron, diborane, fluoride, boron trifluoride, carbon, and germanium.

[0065] Variations of method 1200 or methods similar to method 1200 may include several different embodiments, which may be combined depending on the application of such methods and / or the architecture or process flow of the integrated circuit for which such methods are implemented. Such methods may include subjecting the C-SOD to a plasma ion implant and a combination of species of the plasma ion implant for one minute or less. Subjecting the C-SOD to a plasma ion implant and a combination of species of the plasma ion implant at room temperature.

[0066] Variations of method 1200 or methods similar to method 1200 may include selectively modifying the physical properties of the C-SOD by applying implant energy and implant dosage at a level selected according to the relationship between the implant energy or implant dosage and the length of the C-SOD. The physical properties of the C-SOD may include the modification of one or more of thermal properties, optical properties, chemical properties, electrical properties, and mechanical properties. Selectively modifying the C-SOD may include densifying the surface region while the body region remains non-densified or softening the surface region while the body region is densified. The physical properties may include the optical properties of the C-SOD modified along the length of the C-SOD.

[0067] In various embodiments, a memory device may include: a three-dimensional memory array; and a dielectric film providing electrical isolation in the memory array, wherein the dielectric film includes a spin-on dielectric (SOD) as a dielectric between stacks of memory cells of the memory array, wherein the SOD includes carbon and plasma implanted ions. The SOD including carbon and plasma implanted ions may be implemented by several different material compositions. For example, the SOD may be a carbon-rich SOD. The plasma implanted ions may include, but are not limited to, one or more of the following: helium, hydrogen, nitrogen, boron, diborane, fluoride, boron trifluoride, carbon, and germanium.

[0068] The variation of such memory device may include several different embodiments that may depend on the application of such memory device or the architecture combination of memory device. Such memory device may include a SOD with a physical property that changes vertically along the SOD. The physical property that changes may be density. Other physical properties of the SOD that may change are one or more of thermal properties, optical properties, chemical properties, electrical properties, and mechanical properties. In addition, the SOD may have a porosity in the range of from about 10% to about 50%, wherein the pore size is between about 0.6nm and 0.7nm.

[0069] Variations of such memory devices may include a three-dimensional memory array structured as a chalcogenide-based phase change memory array. The three-dimensional memory array structure may include an OTS selector device located between the access line and the data line in the stack. In the three-dimensional memory array structure, the SOD including carbon and plasma implanted ions may have a tuned thermal conductivity provided by PLAD curing between array cells, with a balanced thermal barrier among the nearest neighbor cells. The three-dimensional memory array may be a DRAM memory array, and the SOD may be a low-k SOD. The three-dimensional memory array may be a NAND-type memory array in which the SOD is disposed in a region with a high aspect ratio. The three-dimensional memory array may be a NAND-type memory array in which the SOD is disposed in a region with a low aspect ratio.

[0070] Fig.13 A block diagram of an embodiment of an example system 1300 is shown, the example system 1300 includes a memory 1363, the memory 1363 is structured to have a three-dimensional memory array so that the dielectric film that provides electrical isolation in the memory array includes SOD as a dielectric between stacks of memory cells of the memory array. The SOD can be structured to include carbon and plasma implanted ions from PLAD curing of the SOD. PLAD curing of the SOD can be implemented according to various embodiments discussed herein.

[0071] The system 1300 may include a controller 1362 operably coupled to a memory 1363. The system 1300 may also include an electronic device 1367 and a peripheral device 1369. One or more of the controller 1362, the memory 1363, the electronic device 1367, or the peripheral device 1369 may be in the form of one or more ICs.

[0072] The bus 1366 provides electrical conductivity between and / or among the various components of the system 1300. In an embodiment, the bus 1366 may include an address bus, a data bus, and a control bus that are each independently configured. In an alternative embodiment, the bus 1366 may use common conductive lines to provide one or more of address, data, or control, the use of which is regulated by the controller 1362. The bus 1366 may operate as a network communication structure. The controller 1362 may be in the form of one or more processors.

[0073] The electronic device 1367 may include additional memory. The memory in the system 1300 may be configured as one or more types of memory, such as, but not limited to, X-Point memory devices, NAND memory devices, DRAM, static random access memory (SRAM), synchronous dynamic random access memory (SDRAM), synchronous graphics random access memory (SGRAM), double data rate dynamic ram (DDR), double data rate SDRAM, magnetic-based memory, and other types of memory.

[0074] Peripheral devices 1369 may include displays, imaging devices, printing devices, wireless devices, additional storage memory, and control devices that may operate in conjunction with controller 1362. In various embodiments, system 1300 includes, but is not limited to, fiber optic systems or devices, optoelectronic systems or devices, optical systems or devices, imaging systems or devices, and information handling systems or devices, such as wireless devices, radio systems or devices, telecommunication systems or devices, and computers.

[0075] Following are example embodiments of systems and methods according to the teachings herein.

[0076] Example method 1 may include: forming a spin-on dielectric as a dielectric that provides electrical isolation in an electronic device; and curing the spin-on dielectric by plasma doping (PLAD) the spin-on dielectric.

[0077] Example method 2 may include the features of example method 1 and may include: the spin-on dielectric is spin-on glass.

[0078] Example method 3 may include features of any of the preceding example methods and may include selectively modifying a physical property of the spin-on dielectric by applying implant energy and implant dose at levels selected based on a relationship of implant energy or implant dose to a length of the spin-on dielectric.

[0079] Example method 4 may include features of example method 3 and any of the foregoing example methods and may include: selectively modifying the spin-on dielectric includes modifying a surface area of ​​the spin-on dielectric relative to a bulk area of ​​the spin-on dielectric or modifying a bulk area of ​​the spin-on dielectric relative to a surface area of ​​the spin-on dielectric.

[0080] Example method 5 may include features of example method 4 and any of the preceding example methods and may include modifying the spin-on dielectric including densifying a surface region while the bulk region remains undensified or softening the surface region while the bulk region is densified.

[0081] Example method 6 may include the features of example method 3 and any of the preceding example methods and may include selectively modifying the spin-on dielectric including using an implant energy ranging from 100 eV to 10 KeV.

[0082] Example method 7 may include features of any of the preceding example methods and may include that the PLAD includes using a dopant that provides a photon energy greater than 10 eV.

[0083] Example method 8 may include features of any of the preceding example methods and may include that the PLAD includes doping with helium.

[0084] Example method 9 may include features of any of the preceding example methods and may include that the PLAD includes doping with one or more of: hydrogen, nitrogen, boron, diborane, fluoride, boron trifluoride, carbon, and germanium.

[0085] Example method 10 may include features of any of the foregoing example methods and may include the spin-on dielectric including one or more of an organic spin-on dielectric and a photoimageable spin-on dielectric having varying carbon contents from approximately 10% to 60% by atomic percent.

[0086] Example method 11 may include features of any of the preceding example methods and may include subjecting the spin-on dielectric to a chemical mechanical polishing (CMP) process after curing.

[0087] Example method 12 may include the features of claim 11 and any of the preceding example methods and may include: after curing the spin-on dielectric having a Young's modulus provided by the curing exceeding 10 GPa for performing the CMP.

[0088] Example method 13 may include features of any of the preceding example methods and may include subjecting the spin-on dielectric to a dry etch after curing.

[0089] Example method 14 may include: forming a carbon-rich spin-on dielectric (C-SOD) as a dielectric that provides electrical isolation in an electronic device; and curing the C-SOD by subjecting the C-SOD to a combination of a plasma ion implant providing a photon energy greater than 10 eV and a species of the plasma ion implant.

[0090] Example method 15 may include the features of claim 14 and may include subjecting the C-SOD to the combination for one minute or less.

[0091] Example method 16 may include the features of any of claims 14 and 15 and may include subjecting the C-SOD to the combination at room temperature.

[0092] Example method 17 may include features of any of the aforementioned example methods 14 to 16 and may include selectively modifying a physical property of the C-SOD by applying implant energy and implant dose at levels selected based on the relationship of implant energy or implant dose to the length of the C-SOD.

[0093] Example method 18 may include features of claim 17 and any of the foregoing example methods 14-16 and may include selectively modifying the C-SOD to include densifying a surface region while the bulk region remains undensified or softening the surface region while densifying the bulk region.

[0094] Example method 19 may include the features of claim 17 and any of the foregoing example methods 14-16 and 18 and may include that the physical property includes an optical property of the C-SOD modified along the length of the C-SOD.

[0095] Example method 20 may include features of any of the foregoing example methods 14-19 and may include that the species includes one or more of: helium, hydrogen, nitrogen, boron, diborane, fluorides, boron trifluoride, carbon, and germanium.

[0096] An example memory device 1 may include: a three-dimensional memory array; and a dielectric film that provides electrical isolation in the memory array, the dielectric film comprising a spin-on dielectric (SOD) as a dielectric between stacks of memory cells of the memory array, wherein the SOD comprises carbon and plasma implanted ions.

[0097] Example memory device 2 may include features of example memory device 1 and may include that the SOD is a carbon-rich SOD.

[0098] Example memory device 3 may include features of any of the foregoing example memory devices and may include that the SOD has a physical property that varies vertically along the SOD.

[0099] Example memory device 4 may include features of example memory device 3 and any of the preceding example memory devices and may include that the physical property is density.

[0100] Example memory device 5 can include features of any of the foregoing example memory devices and can include that the plasma implanted ions include one or more of: helium, hydrogen, nitrogen, boron, diborane, fluorides, boron trifluoride, carbon, and germanium.

[0101] Example memory device 6 may include features of any of the foregoing example memory devices and may include that the three-dimensional memory array is a chalcogenide-based phase change memory array.

[0102] Example memory device 7 may include features of any of the foregoing example memory devices and may include: the three-dimensional memory array is a dynamic random access memory (DRAM) memory array, and the SOD is a low-k SOD.

[0103] The example memory device 8 may include features of any of the foregoing example memory devices and may include: the three-dimensional memory array is a NAND-type memory array, wherein the SOD is disposed in a region with a high aspect ratio.

[0104] Example memory device 9 may include features of any of the foregoing example memory devices and may include: the three-dimensional memory array is a NAND-type memory array, wherein the SOD is disposed in a region having a low aspect ratio.

[0105] The example memory device 10 can include features of any of the foregoing example memory devices and can include: the SOD having a porosity ranging from about 10% to about 50%, with a pore size between about 0.6 nm and 0.7 nm.

[0106] In example memory device 11, any of the memory devices of example memory devices 1-10 may include a memory device incorporated into an electronic system further including a host processor and a communication bus extending between the host processor and the memory device.

[0107] In example memory device 12, any of the memory devices of example memory devices 1-11 may be modified to include any structure presented in another example memory device 1-11.

[0108] In example memory device 13, any of the apparatus of any of the memory devices of example memory devices 1-12 may further include a machine-readable storage device configured to store instructions as a physical state, wherein the instructions may be used to perform one or more operations of the apparatus.

[0109] In example memory device 14 , any of example memory devices 1 - 13 may be adapted and operated to perform operations according to any of the methods of example methods 1 - 20 below.

[0110] As taught herein, for example, H + 、He + Low dose implantation of He and other high energy light ions can be used to improve the crosslinking of organosiloxanes to improve mechanical strength. The crosslinking can include forming Si-O-Si bonds. Such techniques using He PLAD processes can increase hardness by more than 22 times and increase Young's modulus by more than 10 times. The implanted ions cause homolytic bond rupture, allowing -Si-O-Si- crosslinking to form, and therefore allowing mechanical properties to be enhanced. These increased mechanical properties include hardness, Young's modulus, increase and densification. The lighter the ions used, the stronger the effect.

[0111] Solidifying the SOD region by PLAD can be used to selectively densify the surface or body of the gap filler film by tuning the ion dose and energy. The tuning can be provided by selecting PLAD process parameters (e.g., implant energy and ion dose) that match the desired density modification of the SOD region. In addition to the density modification, other physical properties of the SOD region can be modified along the length of the SOD region.

[0112] The He PLAD process is a high throughput, low cost, low temperature process that can be used to cure C-SOD films by a combination of high energy radiation and plasma ion implantation. He and species other than He can be used to cure SOD in structures when forming electronic devices, wherein the structures can have a wide variety of aspect ratios, depths, and functions.

[0113] In addition, PLAD curing is not limited to a specific type of SOD (e.g., C-SOD), but is also applicable to any other SOD or SOG material and polymer used in STI gap fillers. Other SOD materials may include organic SODs and photoimageable SODs with different carbon contents ranging from about 10% to 60% atomic percentage, and others. PLAD curing is applicable to 3D X-Point memory devices due to its applicability to a range of SOD materials and structures. DRAM devices include NAND devices using low-k SOD fillers, NAND memories include NAND devices with larger area gap filler films, and other electronic devices.

[0114] Although specific embodiments have been illustrated and described herein, it will be appreciated by those skilled in the art that any arrangement calculated to achieve the same purpose may replace the specific embodiments shown. Various embodiments use permutations and / or combinations of the embodiments described herein. The above description is intended to be illustrative rather than restrictive, and the words or terms used herein are for descriptive purposes. In addition, in the foregoing specific embodiments, it can be seen that some features are grouped together in a single embodiment for the purpose of simplifying the present invention. A person skilled in the art will understand the combination of the above embodiments with other embodiments after studying the above description.

Claims

1. A memory device, comprising: Three-dimensional memory array; and A dielectric film provides electrical isolation in the memory array, the dielectric film comprising a spin-on dielectric SOD as a dielectric between stacks of memory cells of the memory array, wherein the SOD comprises carbon and plasma implanted ions, the SOD having a carbon content that varies along the length of the SOD.

2. The memory device of claim 1, wherein the SOD is a carbon-rich SOD. 3 . The memory device of claim 1 , wherein the SOD has a physical property that changes vertically along the SOD. The memory device of claim 3 , wherein the physical property is density.

5. The memory device of claim 1, wherein the plasma implanted ions include one or more of: helium, hydrogen, nitrogen, boron, diborane, fluorides, boron trifluoride, carbon, and germanium.

6. The memory device of claim 1, wherein the three-dimensional memory array is a chalcogenide-based phase change memory array.

7. The memory device of claim 1, wherein the three-dimensional memory array is a dynamic random access memory (DRAM) memory array and the SOD is a low-k SOD.

8. The memory device of claim 1, wherein the three-dimensional memory array is a NAND-type memory array, wherein the SOD is disposed in a region having a high aspect ratio.

9. The memory device of claim 1, wherein the three-dimensional memory array is a NAND-type memory array, wherein the SOD is disposed in a region having a low aspect ratio.

10. The memory device of claim 1, wherein the SOD has a porosity ranging from about 10% to about 50%, with a pore size between about 0.6 nm and 0.7 nm.

11. An electronic device comprising: integrated circuit; as well as A spin-on dielectric SOD that provides electrical isolation in the integrated circuit, wherein the SOD comprises carbon and plasma implanted ions, the SOD having a carbon content that varies along the length of the SOD and one or more additional properties that vary with the length of the SOD.

12. The electronic device of claim 11, wherein the one or more additional properties that vary with the length include properties based on a dose of the plasma implanted ions.

13. The electronic device of claim 11, wherein the SOD comprises spin-on-glass.

14. The electronic device of claim 11, wherein the plasma implanted ions include one or more of: nitrogen, boron, diborane, fluoride, boron trifluoride, carbon, or germanium.

15. The electronic device of claim 11, wherein the SOD comprises one or more of an organic spin-on dielectric or a photoimageable spin-on dielectric having varying carbon contents from about 10% to 60% by atomic percent.

16. The electronic device of claim 11, wherein the SOD comprises a carbon-rich spin-on dielectric (C-SOD).

17. The electronic device of claim 16, wherein the C-SOD comprises SiOx, where x>1, plus about 50% carbon plus porosity.

18. The electronic device of claim 11, wherein the integrated circuit is a three-dimensional cross-point memory device.

19. The electronic device of claim 11, wherein the SOD comprises a densified surface region and a non-densified body region.

20. The electronic device of claim 11, wherein the SOD is a gap filler in a memory array gap between columns of stacked memory cells in a memory device.

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